]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/gpu/drm/i915/i915_drv.c
drm/i915: Include a generation number in the device info
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
5669fcac 30#include <linux/device.h>
1da177e4
LT
31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
35
79e53945 36#include <linux/console.h>
354ff967 37#include "drm_crtc_helper.h"
79e53945 38
d6073d77 39static int i915_modeset = -1;
79e53945
JB
40module_param_named(modeset, i915_modeset, int, 0400);
41
42unsigned int i915_fbpercrtc = 0;
43module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
1da177e4 44
652c393a
JB
45unsigned int i915_powersave = 1;
46module_param_named(powersave, i915_powersave, int, 0400);
47
33814341
JB
48unsigned int i915_lvds_downclock = 0;
49module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
50
112b715e 51static struct drm_driver driver;
1f7a6e37 52extern int intel_agp_enabled;
112b715e 53
cfdf1fa2 54#define INTEL_VGA_DEVICE(id, info) { \
49ae35f2
KH
55 .class = PCI_CLASS_DISPLAY_VGA << 8, \
56 .class_mask = 0xffff00, \
57 .vendor = 0x8086, \
58 .device = id, \
59 .subvendor = PCI_ANY_ID, \
60 .subdevice = PCI_ANY_ID, \
cfdf1fa2
KH
61 .driver_data = (unsigned long) info }
62
9a7e8492 63static const struct intel_device_info intel_i830_info = {
c96c3a8c 64 .gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
65};
66
9a7e8492 67static const struct intel_device_info intel_845g_info = {
c96c3a8c 68 .gen = 2, .is_i8xx = 1,
cfdf1fa2
KH
69};
70
9a7e8492 71static const struct intel_device_info intel_i85x_info = {
c96c3a8c 72 .gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
5ce8ba7c 73 .cursor_needs_physical = 1,
cfdf1fa2
KH
74};
75
9a7e8492 76static const struct intel_device_info intel_i865g_info = {
c96c3a8c 77 .gen = 2, .is_i8xx = 1,
cfdf1fa2
KH
78};
79
9a7e8492 80static const struct intel_device_info intel_i915g_info = {
c96c3a8c 81 .gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
cfdf1fa2 82};
9a7e8492 83static const struct intel_device_info intel_i915gm_info = {
c96c3a8c 84 .gen = 3, .is_i9xx = 1, .is_mobile = 1,
b295d1b6 85 .cursor_needs_physical = 1,
cfdf1fa2 86};
9a7e8492 87static const struct intel_device_info intel_i945g_info = {
c96c3a8c 88 .gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
cfdf1fa2 89};
9a7e8492 90static const struct intel_device_info intel_i945gm_info = {
c96c3a8c 91 .gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
b295d1b6 92 .has_hotplug = 1, .cursor_needs_physical = 1,
cfdf1fa2
KH
93};
94
9a7e8492 95static const struct intel_device_info intel_i965g_info = {
c96c3a8c
CW
96 .gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1,
97 .has_hotplug = 1,
cfdf1fa2
KH
98};
99
9a7e8492 100static const struct intel_device_info intel_i965gm_info = {
c96c3a8c
CW
101 .gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
102 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
cfdf1fa2
KH
103};
104
9a7e8492 105static const struct intel_device_info intel_g33_info = {
c96c3a8c
CW
106 .gen = 3, .is_g33 = 1, .is_i9xx = 1,
107 .need_gfx_hws = 1, .has_hotplug = 1,
cfdf1fa2
KH
108};
109
9a7e8492 110static const struct intel_device_info intel_g45_info = {
c96c3a8c
CW
111 .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
112 .has_pipe_cxsr = 1, .has_hotplug = 1,
cfdf1fa2
KH
113};
114
9a7e8492 115static const struct intel_device_info intel_gm45_info = {
c96c3a8c 116 .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,
cfdf1fa2 117 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
c96c3a8c 118 .has_pipe_cxsr = 1, .has_hotplug = 1,
cfdf1fa2
KH
119};
120
9a7e8492 121static const struct intel_device_info intel_pineview_info = {
c96c3a8c
CW
122 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
123 .need_gfx_hws = 1, .has_hotplug = 1,
cfdf1fa2
KH
124};
125
9a7e8492 126static const struct intel_device_info intel_ironlake_d_info = {
c96c3a8c
CW
127 .gen = 5, .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1,
128 .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
cfdf1fa2
KH
129};
130
9a7e8492 131static const struct intel_device_info intel_ironlake_m_info = {
c96c3a8c
CW
132 .gen = 5, .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
133 .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
cfdf1fa2
KH
134};
135
9a7e8492 136static const struct intel_device_info intel_sandybridge_d_info = {
c96c3a8c
CW
137 .gen = 6, .is_i965g = 1, .is_i9xx = 1,
138 .need_gfx_hws = 1, .has_hotplug = 1,
f6e450a6
EA
139};
140
9a7e8492 141static const struct intel_device_info intel_sandybridge_m_info = {
c96c3a8c
CW
142 .gen = 6, .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1,
143 .need_gfx_hws = 1, .has_hotplug = 1,
a13e4093
EA
144};
145
6103da0d
CW
146static const struct pci_device_id pciidlist[] = { /* aka */
147 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
148 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
149 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
5ce8ba7c 150 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
6103da0d
CW
151 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
152 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
153 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
154 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
155 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
156 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
157 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
158 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
159 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
160 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
161 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
162 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
163 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
164 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
165 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
166 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
167 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
168 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
169 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
170 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
171 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
172 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
cfdf1fa2
KH
173 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
174 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
175 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
176 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
f6e450a6 177 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
a13e4093 178 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
4fefe435 179 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
49ae35f2 180 {0, 0, 0}
1da177e4
LT
181};
182
79e53945
JB
183#if defined(CONFIG_DRM_I915_KMS)
184MODULE_DEVICE_TABLE(pci, pciidlist);
185#endif
186
3bad0781
ZW
187#define INTEL_PCH_DEVICE_ID_MASK 0xff00
188#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
189
190void intel_detect_pch (struct drm_device *dev)
191{
192 struct drm_i915_private *dev_priv = dev->dev_private;
193 struct pci_dev *pch;
194
195 /*
196 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
197 * make graphics device passthrough work easy for VMM, that only
198 * need to expose ISA bridge to let driver know the real hardware
199 * underneath. This is a requirement from virtualization team.
200 */
201 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
202 if (pch) {
203 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
204 int id;
205 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
206
207 if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
208 dev_priv->pch_type = PCH_CPT;
209 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
210 }
211 }
212 pci_dev_put(pch);
213 }
214}
215
84b79f8d 216static int i915_drm_freeze(struct drm_device *dev)
ba8bbcf6 217{
61caf87c
RW
218 struct drm_i915_private *dev_priv = dev->dev_private;
219
ba8bbcf6 220 pci_save_state(dev->pdev);
ba8bbcf6 221
5669fcac 222 /* If KMS is active, we do the leavevt stuff here */
226485e9 223 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
84b79f8d
RW
224 int error = i915_gem_idle(dev);
225 if (error) {
226485e9 226 dev_err(&dev->pdev->dev,
84b79f8d
RW
227 "GEM idle failed, resume might fail\n");
228 return error;
229 }
226485e9 230 drm_irq_uninstall(dev);
5669fcac
JB
231 }
232
9e06dd39
JB
233 i915_save_state(dev);
234
3b1c1c11 235 intel_opregion_free(dev, 1);
8ee1c3db 236
84b79f8d
RW
237 /* Modeset on resume, not lid events */
238 dev_priv->modeset_on_lid = 0;
61caf87c
RW
239
240 return 0;
84b79f8d
RW
241}
242
6a9ee8af 243int i915_suspend(struct drm_device *dev, pm_message_t state)
84b79f8d
RW
244{
245 int error;
246
247 if (!dev || !dev->dev_private) {
248 DRM_ERROR("dev: %p\n", dev);
249 DRM_ERROR("DRM not initialized, aborting suspend.\n");
250 return -ENODEV;
251 }
252
253 if (state.event == PM_EVENT_PRETHAW)
254 return 0;
255
256 error = i915_drm_freeze(dev);
257 if (error)
258 return error;
259
b932ccb5
DA
260 if (state.event == PM_EVENT_SUSPEND) {
261 /* Shut down the device */
262 pci_disable_device(dev->pdev);
263 pci_set_power_state(dev->pdev, PCI_D3hot);
264 }
ba8bbcf6
JB
265
266 return 0;
267}
268
84b79f8d 269static int i915_drm_thaw(struct drm_device *dev)
ba8bbcf6 270{
5669fcac 271 struct drm_i915_private *dev_priv = dev->dev_private;
84b79f8d 272 int error = 0;
8ee1c3db 273
61caf87c
RW
274 i915_restore_state(dev);
275
276 intel_opregion_init(dev, 1);
277
5669fcac
JB
278 /* KMS EnterVT equivalent */
279 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
280 mutex_lock(&dev->struct_mutex);
281 dev_priv->mm.suspended = 0;
282
84b79f8d 283 error = i915_gem_init_ringbuffer(dev);
5669fcac 284 mutex_unlock(&dev->struct_mutex);
226485e9
JB
285
286 drm_irq_install(dev);
84b79f8d 287
354ff967
ZY
288 /* Resume the modeset for every activated CRTC */
289 drm_helper_resume_force_mode(dev);
290 }
5669fcac 291
c9354c85 292 dev_priv->modeset_on_lid = 0;
06891e27 293
84b79f8d
RW
294 return error;
295}
296
6a9ee8af 297int i915_resume(struct drm_device *dev)
84b79f8d
RW
298{
299 if (pci_enable_device(dev->pdev))
300 return -EIO;
301
302 pci_set_master(dev->pdev);
303
84b79f8d 304 return i915_drm_thaw(dev);
ba8bbcf6
JB
305}
306
11ed50ec
BG
307/**
308 * i965_reset - reset chip after a hang
309 * @dev: drm device to reset
310 * @flags: reset domains
311 *
312 * Reset the chip. Useful if a hang is detected. Returns zero on successful
313 * reset or otherwise an error code.
314 *
315 * Procedure is fairly simple:
316 * - reset the chip using the reset reg
317 * - re-init context state
318 * - re-init hardware status page
319 * - re-init ring buffer
320 * - re-init interrupt state
321 * - re-init display
322 */
323int i965_reset(struct drm_device *dev, u8 flags)
324{
325 drm_i915_private_t *dev_priv = dev->dev_private;
326 unsigned long timeout;
327 u8 gdrst;
328 /*
329 * We really should only reset the display subsystem if we actually
330 * need to
331 */
332 bool need_display = true;
333
334 mutex_lock(&dev->struct_mutex);
335
336 /*
337 * Clear request list
338 */
b09a1fec 339 i915_gem_retire_requests(dev);
11ed50ec
BG
340
341 if (need_display)
342 i915_save_display(dev);
343
344 if (IS_I965G(dev) || IS_G4X(dev)) {
345 /*
346 * Set the domains we want to reset, then the reset bit (bit 0).
347 * Clear the reset bit after a while and wait for hardware status
348 * bit (bit 1) to be set
349 */
350 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
351 pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0));
352 udelay(50);
353 pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe);
354
355 /* ...we don't want to loop forever though, 500ms should be plenty */
356 timeout = jiffies + msecs_to_jiffies(500);
357 do {
358 udelay(100);
359 pci_read_config_byte(dev->pdev, GDRST, &gdrst);
360 } while ((gdrst & 0x1) && time_after(timeout, jiffies));
361
362 if (gdrst & 0x1) {
363 WARN(true, "i915: Failed to reset chip\n");
364 mutex_unlock(&dev->struct_mutex);
365 return -EIO;
366 }
367 } else {
368 DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
f953c935 369 mutex_unlock(&dev->struct_mutex);
11ed50ec
BG
370 return -ENODEV;
371 }
372
373 /* Ok, now get things going again... */
374
375 /*
376 * Everything depends on having the GTT running, so we need to start
377 * there. Fortunately we don't need to do this unless we reset the
378 * chip at a PCI level.
379 *
380 * Next we need to restore the context, but we don't use those
381 * yet either...
382 *
383 * Ring buffer needs to be re-initialized in the KMS case, or if X
384 * was running at the time of the reset (i.e. we weren't VT
385 * switched away).
386 */
387 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
8187a2b7
ZN
388 !dev_priv->mm.suspended) {
389 struct intel_ring_buffer *ring = &dev_priv->render_ring;
11ed50ec 390 dev_priv->mm.suspended = 0;
8187a2b7 391 ring->init(dev, ring);
11ed50ec
BG
392 mutex_unlock(&dev->struct_mutex);
393 drm_irq_uninstall(dev);
394 drm_irq_install(dev);
395 mutex_lock(&dev->struct_mutex);
396 }
397
398 /*
399 * Display needs restore too...
400 */
401 if (need_display)
402 i915_restore_display(dev);
403
404 mutex_unlock(&dev->struct_mutex);
405 return 0;
406}
407
408
112b715e
KH
409static int __devinit
410i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
411{
dcdb1674 412 return drm_get_pci_dev(pdev, ent, &driver);
112b715e
KH
413}
414
415static void
416i915_pci_remove(struct pci_dev *pdev)
417{
418 struct drm_device *dev = pci_get_drvdata(pdev);
419
420 drm_put_dev(dev);
421}
422
84b79f8d 423static int i915_pm_suspend(struct device *dev)
112b715e 424{
84b79f8d
RW
425 struct pci_dev *pdev = to_pci_dev(dev);
426 struct drm_device *drm_dev = pci_get_drvdata(pdev);
427 int error;
112b715e 428
84b79f8d
RW
429 if (!drm_dev || !drm_dev->dev_private) {
430 dev_err(dev, "DRM not initialized, aborting suspend.\n");
431 return -ENODEV;
432 }
112b715e 433
84b79f8d
RW
434 error = i915_drm_freeze(drm_dev);
435 if (error)
436 return error;
112b715e 437
84b79f8d
RW
438 pci_disable_device(pdev);
439 pci_set_power_state(pdev, PCI_D3hot);
cbda12d7 440
84b79f8d 441 return 0;
cbda12d7
ZW
442}
443
84b79f8d 444static int i915_pm_resume(struct device *dev)
cbda12d7 445{
84b79f8d
RW
446 struct pci_dev *pdev = to_pci_dev(dev);
447 struct drm_device *drm_dev = pci_get_drvdata(pdev);
448
449 return i915_resume(drm_dev);
cbda12d7
ZW
450}
451
84b79f8d 452static int i915_pm_freeze(struct device *dev)
cbda12d7 453{
84b79f8d
RW
454 struct pci_dev *pdev = to_pci_dev(dev);
455 struct drm_device *drm_dev = pci_get_drvdata(pdev);
456
457 if (!drm_dev || !drm_dev->dev_private) {
458 dev_err(dev, "DRM not initialized, aborting suspend.\n");
459 return -ENODEV;
460 }
461
462 return i915_drm_freeze(drm_dev);
cbda12d7
ZW
463}
464
84b79f8d 465static int i915_pm_thaw(struct device *dev)
cbda12d7 466{
84b79f8d
RW
467 struct pci_dev *pdev = to_pci_dev(dev);
468 struct drm_device *drm_dev = pci_get_drvdata(pdev);
469
470 return i915_drm_thaw(drm_dev);
cbda12d7
ZW
471}
472
84b79f8d 473static int i915_pm_poweroff(struct device *dev)
cbda12d7 474{
84b79f8d
RW
475 struct pci_dev *pdev = to_pci_dev(dev);
476 struct drm_device *drm_dev = pci_get_drvdata(pdev);
84b79f8d 477
61caf87c 478 return i915_drm_freeze(drm_dev);
cbda12d7
ZW
479}
480
b4b78d12 481static const struct dev_pm_ops i915_pm_ops = {
cbda12d7
ZW
482 .suspend = i915_pm_suspend,
483 .resume = i915_pm_resume,
484 .freeze = i915_pm_freeze,
485 .thaw = i915_pm_thaw,
486 .poweroff = i915_pm_poweroff,
84b79f8d 487 .restore = i915_pm_resume,
cbda12d7
ZW
488};
489
de151cf6
JB
490static struct vm_operations_struct i915_gem_vm_ops = {
491 .fault = i915_gem_fault,
ab00b3e5
JB
492 .open = drm_gem_vm_open,
493 .close = drm_gem_vm_close,
de151cf6
JB
494};
495
1da177e4 496static struct drm_driver driver = {
792d2b9a
DA
497 /* don't use mtrr's here, the Xserver or user space app should
498 * deal with them for intel hardware.
499 */
673a394b
EA
500 .driver_features =
501 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
502 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
22eae947 503 .load = i915_driver_load,
ba8bbcf6 504 .unload = i915_driver_unload,
673a394b 505 .open = i915_driver_open,
22eae947
DA
506 .lastclose = i915_driver_lastclose,
507 .preclose = i915_driver_preclose,
673a394b 508 .postclose = i915_driver_postclose,
d8e29209
RW
509
510 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
511 .suspend = i915_suspend,
512 .resume = i915_resume,
513
cda17380 514 .device_is_agp = i915_driver_device_is_agp,
0a3e67a4
JB
515 .enable_vblank = i915_enable_vblank,
516 .disable_vblank = i915_disable_vblank,
1da177e4
LT
517 .irq_preinstall = i915_driver_irq_preinstall,
518 .irq_postinstall = i915_driver_irq_postinstall,
519 .irq_uninstall = i915_driver_irq_uninstall,
520 .irq_handler = i915_driver_irq_handler,
521 .reclaim_buffers = drm_core_reclaim_buffers,
522 .get_map_ofs = drm_core_get_map_ofs,
523 .get_reg_ofs = drm_core_get_reg_ofs,
7c1c2871
DA
524 .master_create = i915_master_create,
525 .master_destroy = i915_master_destroy,
955b12de 526#if defined(CONFIG_DEBUG_FS)
27c202ad
BG
527 .debugfs_init = i915_debugfs_init,
528 .debugfs_cleanup = i915_debugfs_cleanup,
955b12de 529#endif
673a394b
EA
530 .gem_init_object = i915_gem_init_object,
531 .gem_free_object = i915_gem_free_object,
de151cf6 532 .gem_vm_ops = &i915_gem_vm_ops,
1da177e4
LT
533 .ioctls = i915_ioctls,
534 .fops = {
b5e89ed5
DA
535 .owner = THIS_MODULE,
536 .open = drm_open,
537 .release = drm_release,
ed8b6704 538 .unlocked_ioctl = drm_ioctl,
de151cf6 539 .mmap = drm_gem_mmap,
b5e89ed5
DA
540 .poll = drm_poll,
541 .fasync = drm_fasync,
c9a9c5e0 542 .read = drm_read,
8ca7c1df 543#ifdef CONFIG_COMPAT
b5e89ed5 544 .compat_ioctl = i915_compat_ioctl,
8ca7c1df 545#endif
22eae947
DA
546 },
547
1da177e4 548 .pci_driver = {
22eae947
DA
549 .name = DRIVER_NAME,
550 .id_table = pciidlist,
112b715e
KH
551 .probe = i915_pci_probe,
552 .remove = i915_pci_remove,
cbda12d7 553 .driver.pm = &i915_pm_ops,
22eae947 554 },
bc5f4523 555
22eae947
DA
556 .name = DRIVER_NAME,
557 .desc = DRIVER_DESC,
558 .date = DRIVER_DATE,
559 .major = DRIVER_MAJOR,
560 .minor = DRIVER_MINOR,
561 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4
LT
562};
563
564static int __init i915_init(void)
565{
1f7a6e37
ZW
566 if (!intel_agp_enabled) {
567 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
568 return -ENODEV;
569 }
570
1da177e4 571 driver.num_ioctls = i915_max_ioctl;
79e53945 572
31169714
CW
573 i915_gem_shrinker_init();
574
79e53945
JB
575 /*
576 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
577 * explicitly disabled with the module pararmeter.
578 *
579 * Otherwise, just follow the parameter (defaulting to off).
580 *
581 * Allow optional vga_text_mode_force boot option to override
582 * the default behavior.
583 */
584#if defined(CONFIG_DRM_I915_KMS)
585 if (i915_modeset != 0)
586 driver.driver_features |= DRIVER_MODESET;
587#endif
588 if (i915_modeset == 1)
589 driver.driver_features |= DRIVER_MODESET;
590
591#ifdef CONFIG_VGA_CONSOLE
592 if (vgacon_text_force() && i915_modeset == -1)
593 driver.driver_features &= ~DRIVER_MODESET;
594#endif
595
f97108d1
JB
596 if (!(driver.driver_features & DRIVER_MODESET)) {
597 driver.suspend = i915_suspend;
598 driver.resume = i915_resume;
599 }
600
1da177e4
LT
601 return drm_init(&driver);
602}
603
604static void __exit i915_exit(void)
605{
31169714 606 i915_gem_shrinker_exit();
1da177e4
LT
607 drm_exit(&driver);
608}
609
610module_init(i915_init);
611module_exit(i915_exit);
612
b5e89ed5
DA
613MODULE_AUTHOR(DRIVER_AUTHOR);
614MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 615MODULE_LICENSE("GPL and additional rights");