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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[net-next-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
CommitLineData
1da177e4
LT		 1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4
LT		 28
29#include "drmP.h"
30#include "drm.h"
79e53945 31#include "drm_crtc_helper.h"
785b93ef 32#include "drm_fb_helper.h"
79e53945 33#include "intel_drv.h"
1da177e4
LT		 34#include "i915_drm.h"
35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
28d52043 37#include <linux/vgaarb.h>
c4804411
ZW		 38#include <linux/acpi.h>
39#include <linux/pnp.h>
6a9ee8af 40#include <linux/vga_switcheroo.h>
5a0e3ad6 41#include <linux/slab.h>
1da177e4 42
398c9cb2
KP		 43/**
44 * Sets up the hardware status page for devices that need a physical address
45 * in the register.
46 */
3043c60c 47static int i915_init_phys_hws(struct drm_device *dev)
398c9cb2
KP		 48{
49 drm_i915_private_t *dev_priv = dev->dev_private;
50 /* Program Hardware Status Page */
51 dev_priv->status_page_dmah =
e6be8d9d 52 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
398c9cb2
KP		 53
54 if (!dev_priv->status_page_dmah) {
55 DRM_ERROR("Can not allocate hardware status page\n");
56 return -ENOMEM;
57 }
8187a2b7
ZN		 58 dev_priv->render_ring.status_page.page_addr
59 = dev_priv->status_page_dmah->vaddr;
398c9cb2
KP		 60 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
61
8187a2b7 62 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
398c9cb2 63
9b974cc1
ZW		 64 if (IS_I965G(dev))
65 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
66 0xf0;
67
398c9cb2 68 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
8a4c47f3 69 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
398c9cb2
KP		 70 return 0;
71}
72
73/**
74 * Frees the hardware status page, whether it's a physical address or a virtual
75 * address set up by the X Server.
76 */
3043c60c 77static void i915_free_hws(struct drm_device *dev)
398c9cb2
KP		 78{
79 drm_i915_private_t *dev_priv = dev->dev_private;
80 if (dev_priv->status_page_dmah) {
81 drm_pci_free(dev, dev_priv->status_page_dmah);
82 dev_priv->status_page_dmah = NULL;
83 }
84
852835f3
ZN		 85 if (dev_priv->render_ring.status_page.gfx_addr) {
86 dev_priv->render_ring.status_page.gfx_addr = 0;
398c9cb2
KP		 87 drm_core_ioremapfree(&dev_priv->hws_map, dev);
88 }
89
90 /* Need to rewrite hardware status page */
91 I915_WRITE(HWS_PGA, 0x1ffff000);
92}
93
84b1fd10 94void i915_kernel_lost_context(struct drm_device * dev)
1da177e4
LT		 95{
96 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 97 struct drm_i915_master_private *master_priv;
8187a2b7 98 struct intel_ring_buffer *ring = &dev_priv->render_ring;
1da177e4 99
79e53945
JB		 100 /*
101 * We should never lose context on the ring with modesetting
102 * as we don't expose it to userspace
103 */
104 if (drm_core_check_feature(dev, DRIVER_MODESET))
105 return;
106
585fb111
JB		 107 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
108 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
1da177e4
LT		 109 ring->space = ring->head - (ring->tail + 8);
110 if (ring->space < 0)
8187a2b7 111 ring->space += ring->size;
1da177e4 112
7c1c2871
DA		 113 if (!dev->primary->master)
114 return;
115
116 master_priv = dev->primary->master->driver_priv;
117 if (ring->head == ring->tail && master_priv->sarea_priv)
118 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
1da177e4
LT		 119}
120
84b1fd10 121static int i915_dma_cleanup(struct drm_device * dev)
1da177e4 122{
ba8bbcf6 123 drm_i915_private_t *dev_priv = dev->dev_private;
1da177e4
LT		 124 /* Make sure interrupts are disabled here because the uninstall ioctl
125 * may not have been called from userspace and after dev_private
126 * is freed, it's too late.
127 */
ed4cb414 128 if (dev->irq_enabled)
b5e89ed5 129 drm_irq_uninstall(dev);
1da177e4 130
8187a2b7 131 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 132 if (HAS_BSD(dev))
133 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
dc7a9319 134
398c9cb2
KP		 135 /* Clear the HWS virtual address at teardown */
136 if (I915_NEED_GFX_HWS(dev))
137 i915_free_hws(dev);
1da177e4
LT		 138
139 return 0;
140}
141
ba8bbcf6 142static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
1da177e4 143{
ba8bbcf6 144 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 145 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 146
3a03ac1a
DA		 147 master_priv->sarea = drm_getsarea(dev);
148 if (master_priv->sarea) {
149 master_priv->sarea_priv = (drm_i915_sarea_t *)
150 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
151 } else {
8a4c47f3 152 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
3a03ac1a
DA		 153 }
154
673a394b 155 if (init->ring_size != 0) {
8187a2b7 156 if (dev_priv->render_ring.gem_object != NULL) {
673a394b
EA		 157 i915_dma_cleanup(dev);
158 DRM_ERROR("Client tried to initialize ringbuffer in "
159 "GEM mode\n");
160 return -EINVAL;
161 }
1da177e4 162
8187a2b7 163 dev_priv->render_ring.size = init->ring_size;
1da177e4 164
d3301d86
EA		 165 dev_priv->render_ring.map.offset = init->ring_start;
166 dev_priv->render_ring.map.size = init->ring_size;
167 dev_priv->render_ring.map.type = 0;
168 dev_priv->render_ring.map.flags = 0;
169 dev_priv->render_ring.map.mtrr = 0;
1da177e4 170
d3301d86 171 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
673a394b 172
d3301d86 173 if (dev_priv->render_ring.map.handle == NULL) {
673a394b
EA		 174 i915_dma_cleanup(dev);
175 DRM_ERROR("can not ioremap virtual address for"
176 " ring buffer\n");
177 return -ENOMEM;
178 }
1da177e4
LT		 179 }
180
d3301d86 181 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
1da177e4 182
a6b54f3f 183 dev_priv->cpp = init->cpp;
1da177e4
LT		 184 dev_priv->back_offset = init->back_offset;
185 dev_priv->front_offset = init->front_offset;
186 dev_priv->current_page = 0;
7c1c2871
DA		 187 if (master_priv->sarea_priv)
188 master_priv->sarea_priv->pf_current_page = 0;
1da177e4 189
1da177e4
LT		 190 /* Allow hardware batchbuffers unless told otherwise.
191 */
192 dev_priv->allow_batchbuffer = 1;
193
1da177e4
LT		 194 return 0;
195}
196
84b1fd10 197static int i915_dma_resume(struct drm_device * dev)
1da177e4
LT		 198{
199 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
200
8187a2b7 201 struct intel_ring_buffer *ring;
8a4c47f3 202 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 203
8187a2b7
ZN		 204 ring = &dev_priv->render_ring;
205
206 if (ring->map.handle == NULL) {
1da177e4
LT		 207 DRM_ERROR("can not ioremap virtual address for"
208 " ring buffer\n");
20caafa6 209 return -ENOMEM;
1da177e4
LT		 210 }
211
212 /* Program Hardware Status Page */
8187a2b7 213 if (!ring->status_page.page_addr) {
1da177e4 214 DRM_ERROR("Can not find hardware status page\n");
20caafa6 215 return -EINVAL;
1da177e4 216 }
8a4c47f3 217 DRM_DEBUG_DRIVER("hw status page @ %p\n",
8187a2b7
ZN		 218 ring->status_page.page_addr);
219 if (ring->status_page.gfx_addr != 0)
220 ring->setup_status_page(dev, ring);
dc7a9319 221 else
585fb111 222 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
8187a2b7 223
8a4c47f3 224 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
1da177e4
LT		 225
226 return 0;
227}
228
c153f45f
EA		 229static int i915_dma_init(struct drm_device *dev, void *data,
230 struct drm_file *file_priv)
1da177e4 231{
c153f45f 232 drm_i915_init_t *init = data;
1da177e4
LT		 233 int retcode = 0;
234
c153f45f 235 switch (init->func) {
1da177e4 236 case I915_INIT_DMA:
ba8bbcf6 237 retcode = i915_initialize(dev, init);
1da177e4
LT		 238 break;
239 case I915_CLEANUP_DMA:
240 retcode = i915_dma_cleanup(dev);
241 break;
242 case I915_RESUME_DMA:
0d6aa60b 243 retcode = i915_dma_resume(dev);
1da177e4
LT		 244 break;
245 default:
20caafa6 246 retcode = -EINVAL;
1da177e4
LT		 247 break;
248 }
249
250 return retcode;
251}
252
253/* Implement basically the same security restrictions as hardware does
254 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
255 *
256 * Most of the calculations below involve calculating the size of a
257 * particular instruction. It's important to get the size right as
258 * that tells us where the next instruction to check is. Any illegal
259 * instruction detected will be given a size of zero, which is a
260 * signal to abort the rest of the buffer.
261 */
262static int do_validate_cmd(int cmd)
263{
264 switch (((cmd >> 29) & 0x7)) {
265 case 0x0:
266 switch ((cmd >> 23) & 0x3f) {
267 case 0x0:
268 return 1; /* MI_NOOP */
269 case 0x4:
270 return 1; /* MI_FLUSH */
271 default:
272 return 0; /* disallow everything else */
273 }
274 break;
275 case 0x1:
276 return 0; /* reserved */
277 case 0x2:
278 return (cmd & 0xff) + 2; /* 2d commands */
279 case 0x3:
280 if (((cmd >> 24) & 0x1f) <= 0x18)
281 return 1;
282
283 switch ((cmd >> 24) & 0x1f) {
284 case 0x1c:
285 return 1;
286 case 0x1d:
b5e89ed5 287 switch ((cmd >> 16) & 0xff) {
1da177e4
LT		 288 case 0x3:
289 return (cmd & 0x1f) + 2;
290 case 0x4:
291 return (cmd & 0xf) + 2;
292 default:
293 return (cmd & 0xffff) + 2;
294 }
295 case 0x1e:
296 if (cmd & (1 << 23))
297 return (cmd & 0xffff) + 1;
298 else
299 return 1;
300 case 0x1f:
301 if ((cmd & (1 << 23)) == 0) /* inline vertices */
302 return (cmd & 0x1ffff) + 2;
303 else if (cmd & (1 << 17)) /* indirect random */
304 if ((cmd & 0xffff) == 0)
305 return 0; /* unknown length, too hard */
306 else
307 return (((cmd & 0xffff) + 1) / 2) + 1;
308 else
309 return 2; /* indirect sequential */
310 default:
311 return 0;
312 }
313 default:
314 return 0;
315 }
316
317 return 0;
318}
319
320static int validate_cmd(int cmd)
321{
322 int ret = do_validate_cmd(cmd);
323
bc5f4523 324/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
1da177e4
LT		 325
326 return ret;
327}
328
201361a5 329static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
1da177e4
LT		 330{
331 drm_i915_private_t *dev_priv = dev->dev_private;
332 int i;
1da177e4 333
8187a2b7 334 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
20caafa6 335 return -EINVAL;
de227f5f 336
c29b669c 337 BEGIN_LP_RING((dwords+1)&~1);
de227f5f 338
1da177e4
LT		 339 for (i = 0; i < dwords;) {
340 int cmd, sz;
341
201361a5 342 cmd = buffer[i];
1da177e4 343
1da177e4 344 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
20caafa6 345 return -EINVAL;
1da177e4 346
1da177e4
LT		 347 OUT_RING(cmd);
348
349 while (++i, --sz) {
201361a5 350 OUT_RING(buffer[i]);
1da177e4 351 }
1da177e4
LT		 352 }
353
de227f5f
DA		 354 if (dwords & 1)
355 OUT_RING(0);
356
357 ADVANCE_LP_RING();
358
1da177e4
LT		 359 return 0;
360}
361
673a394b
EA		 362int
363i915_emit_box(struct drm_device *dev,
201361a5 364 struct drm_clip_rect *boxes,
673a394b 365 int i, int DR1, int DR4)
1da177e4 366{
201361a5 367 struct drm_clip_rect box = boxes[i];
1da177e4 368
1da177e4
LT		 369 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
370 DRM_ERROR("Bad box %d,%d..%d,%d\n",
371 box.x1, box.y1, box.x2, box.y2);
20caafa6 372 return -EINVAL;
1da177e4
LT		 373 }
374
c29b669c
AH		 375 if (IS_I965G(dev)) {
376 BEGIN_LP_RING(4);
377 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
378 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
78eca43d 379 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
c29b669c
AH		 380 OUT_RING(DR4);
381 ADVANCE_LP_RING();
382 } else {
383 BEGIN_LP_RING(6);
384 OUT_RING(GFX_OP_DRAWRECT_INFO);
385 OUT_RING(DR1);
386 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
387 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
388 OUT_RING(DR4);
389 OUT_RING(0);
390 ADVANCE_LP_RING();
391 }
1da177e4
LT		 392
393 return 0;
394}
395
c29b669c
AH		 396/* XXX: Emitting the counter should really be moved to part of the IRQ
397 * emit. For now, do it in both places:
398 */
399
84b1fd10 400static void i915_emit_breadcrumb(struct drm_device *dev)
de227f5f
DA		 401{
402 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 403 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
de227f5f 404
c99b058f 405 dev_priv->counter++;
af6061af 406 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 407 dev_priv->counter = 0;
7c1c2871
DA		 408 if (master_priv->sarea_priv)
409 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
de227f5f
DA		 410
411 BEGIN_LP_RING(4);
585fb111 412 OUT_RING(MI_STORE_DWORD_INDEX);
0baf823a 413 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
de227f5f
DA		 414 OUT_RING(dev_priv->counter);
415 OUT_RING(0);
416 ADVANCE_LP_RING();
417}
418
84b1fd10 419static int i915_dispatch_cmdbuffer(struct drm_device * dev,
201361a5
EA		 420 drm_i915_cmdbuffer_t *cmd,
421 struct drm_clip_rect *cliprects,
422 void *cmdbuf)
1da177e4
LT		 423{
424 int nbox = cmd->num_cliprects;
425 int i = 0, count, ret;
426
427 if (cmd->sz & 0x3) {
428 DRM_ERROR("alignment");
20caafa6 429 return -EINVAL;
1da177e4
LT		 430 }
431
432 i915_kernel_lost_context(dev);
433
434 count = nbox ? nbox : 1;
435
436 for (i = 0; i < count; i++) {
437 if (i < nbox) {
201361a5 438 ret = i915_emit_box(dev, cliprects, i,
1da177e4
LT		 439 cmd->DR1, cmd->DR4);
440 if (ret)
441 return ret;
442 }
443
201361a5 444 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
1da177e4
LT		 445 if (ret)
446 return ret;
447 }
448
de227f5f 449 i915_emit_breadcrumb(dev);
1da177e4
LT		 450 return 0;
451}
452
84b1fd10 453static int i915_dispatch_batchbuffer(struct drm_device * dev,
201361a5
EA		 454 drm_i915_batchbuffer_t * batch,
455 struct drm_clip_rect *cliprects)
1da177e4 456{
1da177e4
LT		 457 int nbox = batch->num_cliprects;
458 int i = 0, count;
1da177e4
LT		 459
460 if ((batch->start | batch->used) & 0x7) {
461 DRM_ERROR("alignment");
20caafa6 462 return -EINVAL;
1da177e4
LT		 463 }
464
465 i915_kernel_lost_context(dev);
466
467 count = nbox ? nbox : 1;
468
469 for (i = 0; i < count; i++) {
470 if (i < nbox) {
201361a5 471 int ret = i915_emit_box(dev, cliprects, i,
1da177e4
LT		 472 batch->DR1, batch->DR4);
473 if (ret)
474 return ret;
475 }
476
0790d5e1 477 if (!IS_I830(dev) && !IS_845G(dev)) {
1da177e4 478 BEGIN_LP_RING(2);
21f16289
DA		 479 if (IS_I965G(dev)) {
480 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
481 OUT_RING(batch->start);
482 } else {
483 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
484 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
485 }
1da177e4
LT		 486 ADVANCE_LP_RING();
487 } else {
488 BEGIN_LP_RING(4);
489 OUT_RING(MI_BATCH_BUFFER);
490 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
491 OUT_RING(batch->start + batch->used - 4);
492 OUT_RING(0);
493 ADVANCE_LP_RING();
494 }
495 }
496
de227f5f 497 i915_emit_breadcrumb(dev);
1da177e4
LT		 498
499 return 0;
500}
501
af6061af 502static int i915_dispatch_flip(struct drm_device * dev)
1da177e4
LT		 503{
504 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871
DA		 505 struct drm_i915_master_private *master_priv =
506 dev->primary->master->driver_priv;
1da177e4 507
7c1c2871 508 if (!master_priv->sarea_priv)
c99b058f
KH		 509 return -EINVAL;
510
8a4c47f3 511 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
be25ed9c 512 __func__,
513 dev_priv->current_page,
514 master_priv->sarea_priv->pf_current_page);
1da177e4 515
af6061af
DA		 516 i915_kernel_lost_context(dev);
517
518 BEGIN_LP_RING(2);
585fb111 519 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
af6061af
DA		 520 OUT_RING(0);
521 ADVANCE_LP_RING();
1da177e4 522
af6061af
DA		 523 BEGIN_LP_RING(6);
524 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
525 OUT_RING(0);
526 if (dev_priv->current_page == 0) {
527 OUT_RING(dev_priv->back_offset);
528 dev_priv->current_page = 1;
1da177e4 529 } else {
af6061af
DA		 530 OUT_RING(dev_priv->front_offset);
531 dev_priv->current_page = 0;
1da177e4 532 }
af6061af
DA		 533 OUT_RING(0);
534 ADVANCE_LP_RING();
1da177e4 535
af6061af
DA		 536 BEGIN_LP_RING(2);
537 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
538 OUT_RING(0);
539 ADVANCE_LP_RING();
1da177e4 540
7c1c2871 541 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
1da177e4
LT		 542
543 BEGIN_LP_RING(4);
585fb111 544 OUT_RING(MI_STORE_DWORD_INDEX);
0baf823a 545 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
af6061af
DA		 546 OUT_RING(dev_priv->counter);
547 OUT_RING(0);
1da177e4
LT		 548 ADVANCE_LP_RING();
549
7c1c2871 550 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
af6061af 551 return 0;
1da177e4
LT		 552}
553
84b1fd10 554static int i915_quiescent(struct drm_device * dev)
1da177e4
LT		 555{
556 drm_i915_private_t *dev_priv = dev->dev_private;
557
558 i915_kernel_lost_context(dev);
8187a2b7
ZN		 559 return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
560 dev_priv->render_ring.size - 8);
1da177e4
LT		 561}
562
c153f45f
EA		 563static int i915_flush_ioctl(struct drm_device *dev, void *data,
564 struct drm_file *file_priv)
1da177e4 565{
546b0974
EA		 566 int ret;
567
568 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 569
546b0974
EA		 570 mutex_lock(&dev->struct_mutex);
571 ret = i915_quiescent(dev);
572 mutex_unlock(&dev->struct_mutex);
573
574 return ret;
1da177e4
LT		 575}
576
c153f45f
EA		 577static int i915_batchbuffer(struct drm_device *dev, void *data,
578 struct drm_file *file_priv)
1da177e4 579{
1da177e4 580 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 581 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 582 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 583 master_priv->sarea_priv;
c153f45f 584 drm_i915_batchbuffer_t *batch = data;
1da177e4 585 int ret;
201361a5 586 struct drm_clip_rect *cliprects = NULL;
1da177e4
LT		 587
588 if (!dev_priv->allow_batchbuffer) {
589 DRM_ERROR("Batchbuffer ioctl disabled\n");
20caafa6 590 return -EINVAL;
1da177e4
LT		 591 }
592
8a4c47f3 593 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
be25ed9c 594 batch->start, batch->used, batch->num_cliprects);
1da177e4 595
546b0974 596 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 597
201361a5
EA		 598 if (batch->num_cliprects < 0)
599 return -EINVAL;
600
601 if (batch->num_cliprects) {
9a298b2a
EA		 602 cliprects = kcalloc(batch->num_cliprects,
603 sizeof(struct drm_clip_rect),
604 GFP_KERNEL);
201361a5
EA		 605 if (cliprects == NULL)
606 return -ENOMEM;
607
608 ret = copy_from_user(cliprects, batch->cliprects,
609 batch->num_cliprects *
610 sizeof(struct drm_clip_rect));
611 if (ret != 0)
612 goto fail_free;
613 }
1da177e4 614
546b0974 615 mutex_lock(&dev->struct_mutex);
201361a5 616 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
546b0974 617 mutex_unlock(&dev->struct_mutex);
1da177e4 618
c99b058f 619 if (sarea_priv)
0baf823a 620 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5
EA		 621
622fail_free:
9a298b2a 623 kfree(cliprects);
201361a5 624
1da177e4
LT		 625 return ret;
626}
627
c153f45f
EA		 628static int i915_cmdbuffer(struct drm_device *dev, void *data,
629 struct drm_file *file_priv)
1da177e4 630{
1da177e4 631 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 632 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 633 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
7c1c2871 634 master_priv->sarea_priv;
c153f45f 635 drm_i915_cmdbuffer_t *cmdbuf = data;
201361a5
EA		 636 struct drm_clip_rect *cliprects = NULL;
637 void *batch_data;
1da177e4
LT		 638 int ret;
639
8a4c47f3 640 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
be25ed9c 641 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
1da177e4 642
546b0974 643 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 644
201361a5
EA		 645 if (cmdbuf->num_cliprects < 0)
646 return -EINVAL;
647
9a298b2a 648 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
201361a5
EA		 649 if (batch_data == NULL)
650 return -ENOMEM;
651
652 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
653 if (ret != 0)
654 goto fail_batch_free;
655
656 if (cmdbuf->num_cliprects) {
9a298b2a
EA		 657 cliprects = kcalloc(cmdbuf->num_cliprects,
658 sizeof(struct drm_clip_rect), GFP_KERNEL);
a40e8d31
OA		 659 if (cliprects == NULL) {
660 ret = -ENOMEM;
201361a5 661 goto fail_batch_free;
a40e8d31 662 }
201361a5
EA		 663
664 ret = copy_from_user(cliprects, cmdbuf->cliprects,
665 cmdbuf->num_cliprects *
666 sizeof(struct drm_clip_rect));
667 if (ret != 0)
668 goto fail_clip_free;
1da177e4
LT		 669 }
670
546b0974 671 mutex_lock(&dev->struct_mutex);
201361a5 672 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
546b0974 673 mutex_unlock(&dev->struct_mutex);
1da177e4
LT		 674 if (ret) {
675 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
355d7f37 676 goto fail_clip_free;
1da177e4
LT		 677 }
678
c99b058f 679 if (sarea_priv)
0baf823a 680 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
201361a5 681
201361a5 682fail_clip_free:
9a298b2a 683 kfree(cliprects);
355d7f37 684fail_batch_free:
9a298b2a 685 kfree(batch_data);
201361a5
EA		 686
687 return ret;
1da177e4
LT		 688}
689
c153f45f
EA		 690static int i915_flip_bufs(struct drm_device *dev, void *data,
691 struct drm_file *file_priv)
1da177e4 692{
546b0974
EA		 693 int ret;
694
8a4c47f3 695 DRM_DEBUG_DRIVER("%s\n", __func__);
1da177e4 696
546b0974 697 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1da177e4 698
546b0974
EA		 699 mutex_lock(&dev->struct_mutex);
700 ret = i915_dispatch_flip(dev);
701 mutex_unlock(&dev->struct_mutex);
702
703 return ret;
1da177e4
LT		 704}
705
c153f45f
EA		 706static int i915_getparam(struct drm_device *dev, void *data,
707 struct drm_file *file_priv)
1da177e4 708{
1da177e4 709 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 710 drm_i915_getparam_t *param = data;
1da177e4
LT		 711 int value;
712
713 if (!dev_priv) {
3e684eae 714 DRM_ERROR("called with no initialization\n");
20caafa6 715 return -EINVAL;
1da177e4
LT		 716 }
717
c153f45f 718 switch (param->param) {
1da177e4 719 case I915_PARAM_IRQ_ACTIVE:
0a3e67a4 720 value = dev->pdev->irq ? 1 : 0;
1da177e4
LT		 721 break;
722 case I915_PARAM_ALLOW_BATCHBUFFER:
723 value = dev_priv->allow_batchbuffer ? 1 : 0;
724 break;
0d6aa60b
DA		 725 case I915_PARAM_LAST_DISPATCH:
726 value = READ_BREADCRUMB(dev_priv);
727 break;
ed4c9c4a
KH		 728 case I915_PARAM_CHIPSET_ID:
729 value = dev->pci_device;
730 break;
673a394b 731 case I915_PARAM_HAS_GEM:
ac5c4e76 732 value = dev_priv->has_gem;
673a394b 733 break;
0f973f27
JB		 734 case I915_PARAM_NUM_FENCES_AVAIL:
735 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
736 break;
02e792fb
DV		 737 case I915_PARAM_HAS_OVERLAY:
738 value = dev_priv->overlay ? 1 : 0;
739 break;
e9560f7c
JB		 740 case I915_PARAM_HAS_PAGEFLIPPING:
741 value = 1;
742 break;
76446cac
JB		 743 case I915_PARAM_HAS_EXECBUF2:
744 /* depends on GEM */
745 value = dev_priv->has_gem;
746 break;
e3a815fc
ZN		 747 case I915_PARAM_HAS_BSD:
748 value = HAS_BSD(dev);
749 break;
1da177e4 750 default:
8a4c47f3 751 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
76446cac 752 param->param);
20caafa6 753 return -EINVAL;
1da177e4
LT		 754 }
755
c153f45f 756 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1da177e4 757 DRM_ERROR("DRM_COPY_TO_USER failed\n");
20caafa6 758 return -EFAULT;
1da177e4
LT		 759 }
760
761 return 0;
762}
763
c153f45f
EA		 764static int i915_setparam(struct drm_device *dev, void *data,
765 struct drm_file *file_priv)
1da177e4 766{
1da177e4 767 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 768 drm_i915_setparam_t *param = data;
1da177e4
LT		 769
770 if (!dev_priv) {
3e684eae 771 DRM_ERROR("called with no initialization\n");
20caafa6 772 return -EINVAL;
1da177e4
LT		 773 }
774
c153f45f 775 switch (param->param) {
1da177e4 776 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1da177e4
LT		 777 break;
778 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
c153f45f 779 dev_priv->tex_lru_log_granularity = param->value;
1da177e4
LT		 780 break;
781 case I915_SETPARAM_ALLOW_BATCHBUFFER:
c153f45f 782 dev_priv->allow_batchbuffer = param->value;
1da177e4 783 break;
0f973f27
JB		 784 case I915_SETPARAM_NUM_USED_FENCES:
785 if (param->value > dev_priv->num_fence_regs ||
786 param->value < 0)
787 return -EINVAL;
788 /* Userspace can use first N regs */
789 dev_priv->fence_reg_start = param->value;
790 break;
1da177e4 791 default:
8a4c47f3 792 DRM_DEBUG_DRIVER("unknown parameter %d\n",
be25ed9c 793 param->param);
20caafa6 794 return -EINVAL;
1da177e4
LT		 795 }
796
797 return 0;
798}
799
c153f45f
EA		 800static int i915_set_status_page(struct drm_device *dev, void *data,
801 struct drm_file *file_priv)
dc7a9319 802{
dc7a9319 803 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 804 drm_i915_hws_addr_t *hws = data;
8187a2b7 805 struct intel_ring_buffer *ring = &dev_priv->render_ring;
b39d50e5
ZW		 806
807 if (!I915_NEED_GFX_HWS(dev))
808 return -EINVAL;
dc7a9319
WZ		 809
810 if (!dev_priv) {
3e684eae 811 DRM_ERROR("called with no initialization\n");
20caafa6 812 return -EINVAL;
dc7a9319 813 }
dc7a9319 814
79e53945
JB		 815 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
816 WARN(1, "tried to set status page when mode setting active\n");
817 return 0;
818 }
819
8a4c47f3 820 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
c153f45f 821
8187a2b7 822 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
dc7a9319 823
8b409580 824 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
dc7a9319
WZ		 825 dev_priv->hws_map.size = 4*1024;
826 dev_priv->hws_map.type = 0;
827 dev_priv->hws_map.flags = 0;
828 dev_priv->hws_map.mtrr = 0;
829
dd0910b3 830 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
dc7a9319 831 if (dev_priv->hws_map.handle == NULL) {
dc7a9319 832 i915_dma_cleanup(dev);
e20f9c64 833 ring->status_page.gfx_addr = 0;
dc7a9319
WZ		 834 DRM_ERROR("can not ioremap virtual address for"
835 " G33 hw status page\n");
20caafa6 836 return -ENOMEM;
dc7a9319 837 }
8187a2b7
ZN		 838 ring->status_page.page_addr = dev_priv->hws_map.handle;
839 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
840 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
dc7a9319 841
8a4c47f3 842 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
e20f9c64 843 ring->status_page.gfx_addr);
8a4c47f3 844 DRM_DEBUG_DRIVER("load hws at %p\n",
e20f9c64 845 ring->status_page.page_addr);
dc7a9319
WZ		 846 return 0;
847}
848
ec2a4c3f
DA		 849static int i915_get_bridge_dev(struct drm_device *dev)
850{
851 struct drm_i915_private *dev_priv = dev->dev_private;
852
853 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
854 if (!dev_priv->bridge_dev) {
855 DRM_ERROR("bridge device not found\n");
856 return -1;
857 }
858 return 0;
859}
860
c4804411
ZW		 861#define MCHBAR_I915 0x44
862#define MCHBAR_I965 0x48
863#define MCHBAR_SIZE (4*4096)
864
865#define DEVEN_REG 0x54
866#define DEVEN_MCHBAR_EN (1 << 28)
867
868/* Allocate space for the MCH regs if needed, return nonzero on error */
869static int
870intel_alloc_mchbar_resource(struct drm_device *dev)
871{
872 drm_i915_private_t *dev_priv = dev->dev_private;
873 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
874 u32 temp_lo, temp_hi = 0;
875 u64 mchbar_addr;
876 int ret = 0;
877
878 if (IS_I965G(dev))
879 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
880 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
881 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
882
883 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
884#ifdef CONFIG_PNP
885 if (mchbar_addr &&
886 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
887 ret = 0;
888 goto out;
889 }
890#endif
891
892 /* Get some space for it */
893 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
894 MCHBAR_SIZE, MCHBAR_SIZE,
895 PCIBIOS_MIN_MEM,
896 0, pcibios_align_resource,
897 dev_priv->bridge_dev);
898 if (ret) {
899 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
900 dev_priv->mch_res.start = 0;
901 goto out;
902 }
903
904 if (IS_I965G(dev))
905 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
906 upper_32_bits(dev_priv->mch_res.start));
907
908 pci_write_config_dword(dev_priv->bridge_dev, reg,
909 lower_32_bits(dev_priv->mch_res.start));
910out:
911 return ret;
912}
913
914/* Setup MCHBAR if possible, return true if we should disable it again */
915static void
916intel_setup_mchbar(struct drm_device *dev)
917{
918 drm_i915_private_t *dev_priv = dev->dev_private;
919 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
920 u32 temp;
921 bool enabled;
922
923 dev_priv->mchbar_need_disable = false;
924
925 if (IS_I915G(dev) || IS_I915GM(dev)) {
926 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
927 enabled = !!(temp & DEVEN_MCHBAR_EN);
928 } else {
929 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
930 enabled = temp & 1;
931 }
932
933 /* If it's already enabled, don't have to do anything */
934 if (enabled)
935 return;
936
937 if (intel_alloc_mchbar_resource(dev))
938 return;
939
940 dev_priv->mchbar_need_disable = true;
941
942 /* Space is allocated or reserved, so enable it. */
943 if (IS_I915G(dev) || IS_I915GM(dev)) {
944 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
945 temp | DEVEN_MCHBAR_EN);
946 } else {
947 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
948 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
949 }
950}
951
952static void
953intel_teardown_mchbar(struct drm_device *dev)
954{
955 drm_i915_private_t *dev_priv = dev->dev_private;
956 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
957 u32 temp;
958
959 if (dev_priv->mchbar_need_disable) {
960 if (IS_I915G(dev) || IS_I915GM(dev)) {
961 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
962 temp &= ~DEVEN_MCHBAR_EN;
963 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
964 } else {
965 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
966 temp &= ~1;
967 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
968 }
969 }
970
971 if (dev_priv->mch_res.start)
972 release_resource(&dev_priv->mch_res);
973}
974
79e53945
JB		 975/**
976 * i915_probe_agp - get AGP bootup configuration
977 * @pdev: PCI device
978 * @aperture_size: returns AGP aperture configured size
979 * @preallocated_size: returns size of BIOS preallocated AGP space
980 *
981 * Since Intel integrated graphics are UMA, the BIOS has to set aside
982 * some RAM for the framebuffer at early boot. This code figures out
983 * how much was set aside so we can use it for our own purposes.
984 */
2a34f5e6 985static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
80824003
JB		 986 uint32_t *preallocated_size,
987 uint32_t *start)
79e53945 988{
ec2a4c3f 989 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 990 u16 tmp = 0;
991 unsigned long overhead;
241fa85b 992 unsigned long stolen;
79e53945 993
79e53945 994 /* Get the fb aperture size and "stolen" memory amount. */
ec2a4c3f 995 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
79e53945
JB		 996
997 *aperture_size = 1024 * 1024;
998 *preallocated_size = 1024 * 1024;
999
60fd99e3 1000 switch (dev->pdev->device) {
79e53945
JB		 1001 case PCI_DEVICE_ID_INTEL_82830_CGC:
1002 case PCI_DEVICE_ID_INTEL_82845G_IG:
1003 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1004 case PCI_DEVICE_ID_INTEL_82865_IG:
1005 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1006 *aperture_size *= 64;
1007 else
1008 *aperture_size *= 128;
1009 break;
1010 default:
1011 /* 9xx supports large sizes, just look at the length */
60fd99e3 1012 *aperture_size = pci_resource_len(dev->pdev, 2);
79e53945
JB		 1013 break;
1014 }
1015
1016 /*
1017 * Some of the preallocated space is taken by the GTT
1018 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1019 */
bad720ff 1020 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
60fd99e3
EA		 1021 overhead = 4096;
1022 else
1023 overhead = (*aperture_size / 1024) + 4096;
1024
14bc490b
ZW		 1025 if (IS_GEN6(dev)) {
1026 /* SNB has memory control reg at 0x50.w */
1027 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1028
1029 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1030 case INTEL_855_GMCH_GMS_DISABLED:
1031 DRM_ERROR("video memory is disabled\n");
1032 return -1;
1033 case SNB_GMCH_GMS_STOLEN_32M:
1034 stolen = 32 * 1024 * 1024;
1035 break;
1036 case SNB_GMCH_GMS_STOLEN_64M:
bad720ff 1037 stolen = 64 * 1024 * 1024;
14bc490b
ZW		 1038 break;
1039 case SNB_GMCH_GMS_STOLEN_96M:
1040 stolen = 96 * 1024 * 1024;
1041 break;
1042 case SNB_GMCH_GMS_STOLEN_128M:
1043 stolen = 128 * 1024 * 1024;
1044 break;
1045 case SNB_GMCH_GMS_STOLEN_160M:
1046 stolen = 160 * 1024 * 1024;
1047 break;
1048 case SNB_GMCH_GMS_STOLEN_192M:
1049 stolen = 192 * 1024 * 1024;
1050 break;
1051 case SNB_GMCH_GMS_STOLEN_224M:
1052 stolen = 224 * 1024 * 1024;
1053 break;
1054 case SNB_GMCH_GMS_STOLEN_256M:
1055 stolen = 256 * 1024 * 1024;
1056 break;
1057 case SNB_GMCH_GMS_STOLEN_288M:
1058 stolen = 288 * 1024 * 1024;
1059 break;
1060 case SNB_GMCH_GMS_STOLEN_320M:
1061 stolen = 320 * 1024 * 1024;
1062 break;
1063 case SNB_GMCH_GMS_STOLEN_352M:
1064 stolen = 352 * 1024 * 1024;
1065 break;
1066 case SNB_GMCH_GMS_STOLEN_384M:
1067 stolen = 384 * 1024 * 1024;
1068 break;
1069 case SNB_GMCH_GMS_STOLEN_416M:
1070 stolen = 416 * 1024 * 1024;
1071 break;
1072 case SNB_GMCH_GMS_STOLEN_448M:
1073 stolen = 448 * 1024 * 1024;
1074 break;
1075 case SNB_GMCH_GMS_STOLEN_480M:
1076 stolen = 480 * 1024 * 1024;
1077 break;
1078 case SNB_GMCH_GMS_STOLEN_512M:
1079 stolen = 512 * 1024 * 1024;
1080 break;
1081 default:
1082 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1083 tmp & SNB_GMCH_GMS_STOLEN_MASK);
1084 return -1;
1085 }
1086 } else {
1087 switch (tmp & INTEL_GMCH_GMS_MASK) {
1088 case INTEL_855_GMCH_GMS_DISABLED:
bad720ff
EA		 1089 DRM_ERROR("video memory is disabled\n");
1090 return -1;
14bc490b
ZW		 1091 case INTEL_855_GMCH_GMS_STOLEN_1M:
1092 stolen = 1 * 1024 * 1024;
1093 break;
1094 case INTEL_855_GMCH_GMS_STOLEN_4M:
1095 stolen = 4 * 1024 * 1024;
1096 break;
1097 case INTEL_855_GMCH_GMS_STOLEN_8M:
1098 stolen = 8 * 1024 * 1024;
1099 break;
1100 case INTEL_855_GMCH_GMS_STOLEN_16M:
1101 stolen = 16 * 1024 * 1024;
1102 break;
1103 case INTEL_855_GMCH_GMS_STOLEN_32M:
1104 stolen = 32 * 1024 * 1024;
1105 break;
1106 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1107 stolen = 48 * 1024 * 1024;
1108 break;
1109 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1110 stolen = 64 * 1024 * 1024;
1111 break;
1112 case INTEL_GMCH_GMS_STOLEN_128M:
1113 stolen = 128 * 1024 * 1024;
1114 break;
1115 case INTEL_GMCH_GMS_STOLEN_256M:
1116 stolen = 256 * 1024 * 1024;
1117 break;
1118 case INTEL_GMCH_GMS_STOLEN_96M:
1119 stolen = 96 * 1024 * 1024;
1120 break;
1121 case INTEL_GMCH_GMS_STOLEN_160M:
1122 stolen = 160 * 1024 * 1024;
1123 break;
1124 case INTEL_GMCH_GMS_STOLEN_224M:
1125 stolen = 224 * 1024 * 1024;
1126 break;
1127 case INTEL_GMCH_GMS_STOLEN_352M:
1128 stolen = 352 * 1024 * 1024;
1129 break;
1130 default:
1131 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1132 tmp & INTEL_GMCH_GMS_MASK);
1133 return -1;
bad720ff 1134 }
79e53945 1135 }
14bc490b 1136
241fa85b 1137 *preallocated_size = stolen - overhead;
80824003 1138 *start = overhead;
79e53945
JB		 1139
1140 return 0;
1141}
1142
80824003
JB		 1143#define PTE_ADDRESS_MASK 0xfffff000
1144#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1145#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1146#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1147#define PTE_MAPPING_TYPE_CACHED (3 << 1)
1148#define PTE_MAPPING_TYPE_MASK (3 << 1)
1149#define PTE_VALID (1 << 0)
1150
1151/**
1152 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1153 * @dev: drm device
1154 * @gtt_addr: address to translate
1155 *
1156 * Some chip functions require allocations from stolen space but need the
1157 * physical address of the memory in question. We use this routine
1158 * to get a physical address suitable for register programming from a given
1159 * GTT address.
1160 */
1161static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1162 unsigned long gtt_addr)
1163{
1164 unsigned long *gtt;
1165 unsigned long entry, phys;
1166 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1167 int gtt_offset, gtt_size;
1168
1169 if (IS_I965G(dev)) {
bad720ff 1170 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
80824003
JB		 1171 gtt_offset = 2*1024*1024;
1172 gtt_size = 2*1024*1024;
1173 } else {
1174 gtt_offset = 512*1024;
1175 gtt_size = 512*1024;
1176 }
1177 } else {
1178 gtt_bar = 3;
1179 gtt_offset = 0;
1180 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1181 }
1182
1183 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1184 gtt_size);
1185 if (!gtt) {
1186 DRM_ERROR("ioremap of GTT failed\n");
1187 return 0;
1188 }
1189
1190 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1191
44d98a61 1192 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
80824003
JB		 1193
1194 /* Mask out these reserved bits on this hardware. */
1195 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1196 IS_I945G(dev) || IS_I945GM(dev)) {
1197 entry &= ~PTE_ADDRESS_MASK_HIGH;
1198 }
1199
1200 /* If it's not a mapping type we know, then bail. */
1201 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1202 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1203 iounmap(gtt);
1204 return 0;
1205 }
1206
1207 if (!(entry & PTE_VALID)) {
1208 DRM_ERROR("bad GTT entry in stolen space\n");
1209 iounmap(gtt);
1210 return 0;
1211 }
1212
1213 iounmap(gtt);
1214
1215 phys =(entry & PTE_ADDRESS_MASK) |
1216 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1217
44d98a61 1218 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
80824003
JB		 1219
1220 return phys;
1221}
1222
1223static void i915_warn_stolen(struct drm_device *dev)
1224{
1225 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1226 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1227}
1228
1229static void i915_setup_compression(struct drm_device *dev, int size)
1230{
1231 struct drm_i915_private *dev_priv = dev->dev_private;
1232 struct drm_mm_node *compressed_fb, *compressed_llb;
29bd0ae2
AM		 1233 unsigned long cfb_base;
1234 unsigned long ll_base = 0;
80824003
JB		 1235
1236 /* Leave 1M for line length buffer & misc. */
1237 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1238 if (!compressed_fb) {
b5e50c3f 1239 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1240 i915_warn_stolen(dev);
1241 return;
1242 }
1243
1244 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1245 if (!compressed_fb) {
1246 i915_warn_stolen(dev);
b5e50c3f 1247 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1248 return;
1249 }
1250
74dff282
JB		 1251 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1252 if (!cfb_base) {
1253 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1254 drm_mm_put_block(compressed_fb);
80824003
JB		 1255 }
1256
74dff282
JB		 1257 if (!IS_GM45(dev)) {
1258 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1259 4096, 0);
1260 if (!compressed_llb) {
1261 i915_warn_stolen(dev);
1262 return;
1263 }
1264
1265 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1266 if (!compressed_llb) {
1267 i915_warn_stolen(dev);
1268 return;
1269 }
1270
1271 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1272 if (!ll_base) {
1273 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1274 drm_mm_put_block(compressed_fb);
1275 drm_mm_put_block(compressed_llb);
1276 }
80824003
JB		 1277 }
1278
1279 dev_priv->cfb_size = size;
1280
ee5382ae 1281 intel_disable_fbc(dev);
20bf377e
JB		 1282 dev_priv->compressed_fb = compressed_fb;
1283
74dff282 1284 if (IS_GM45(dev)) {
74dff282
JB		 1285 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1286 } else {
74dff282
JB		 1287 I915_WRITE(FBC_CFB_BASE, cfb_base);
1288 I915_WRITE(FBC_LL_BASE, ll_base);
20bf377e 1289 dev_priv->compressed_llb = compressed_llb;
80824003
JB		 1290 }
1291
80824003
JB		 1292 DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1293 ll_base, size >> 20);
80824003
JB		 1294}
1295
20bf377e
JB		 1296static void i915_cleanup_compression(struct drm_device *dev)
1297{
1298 struct drm_i915_private *dev_priv = dev->dev_private;
1299
1300 drm_mm_put_block(dev_priv->compressed_fb);
1301 if (!IS_GM45(dev))
1302 drm_mm_put_block(dev_priv->compressed_llb);
1303}
1304
28d52043
DA		 1305/* true = enable decode, false = disable decoder */
1306static unsigned int i915_vga_set_decode(void *cookie, bool state)
1307{
1308 struct drm_device *dev = cookie;
1309
1310 intel_modeset_vga_set_state(dev, state);
1311 if (state)
1312 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1313 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1314 else
1315 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1316}
1317
6a9ee8af
DA		 1318static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1319{
1320 struct drm_device *dev = pci_get_drvdata(pdev);
1321 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1322 if (state == VGA_SWITCHEROO_ON) {
fbf81762 1323 printk(KERN_INFO "i915: switched on\n");
6a9ee8af
DA		 1324 /* i915 resume handler doesn't set to D0 */
1325 pci_set_power_state(dev->pdev, PCI_D0);
1326 i915_resume(dev);
fbf81762 1327 drm_kms_helper_poll_enable(dev);
6a9ee8af
DA		 1328 } else {
1329 printk(KERN_ERR "i915: switched off\n");
fbf81762 1330 drm_kms_helper_poll_disable(dev);
6a9ee8af
DA		 1331 i915_suspend(dev, pmm);
1332 }
1333}
1334
1335static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1336{
1337 struct drm_device *dev = pci_get_drvdata(pdev);
1338 bool can_switch;
1339
1340 spin_lock(&dev->count_lock);
1341 can_switch = (dev->open_count == 0);
1342 spin_unlock(&dev->count_lock);
1343 return can_switch;
1344}
1345
2a34f5e6 1346static int i915_load_modeset_init(struct drm_device *dev,
80824003 1347 unsigned long prealloc_start,
2a34f5e6
EA		 1348 unsigned long prealloc_size,
1349 unsigned long agp_size)
79e53945
JB		 1350{
1351 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 1352 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1353 int ret = 0;
1354
1355 dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1356 0xff000000;
1357
79e53945
JB		 1358 /* Basic memrange allocator for stolen space (aka vram) */
1359 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
80824003 1360 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
79e53945 1361
11ed50ec
BG		 1362 /* We're off and running w/KMS */
1363 dev_priv->mm.suspended = 0;
79e53945 1364
13f4c435
EA		 1365 /* Let GEM Manage from end of prealloc space to end of aperture.
1366 *
1367 * However, leave one page at the end still bound to the scratch page.
1368 * There are a number of places where the hardware apparently
1369 * prefetches past the end of the object, and we've seen multiple
1370 * hangs with the GPU head pointer stuck in a batchbuffer bound
1371 * at the last page of the aperture. One page should be enough to
1372 * keep any prefetching inside of the aperture.
1373 */
1374 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
79e53945 1375
11ed50ec 1376 mutex_lock(&dev->struct_mutex);
79e53945 1377 ret = i915_gem_init_ringbuffer(dev);
11ed50ec 1378 mutex_unlock(&dev->struct_mutex);
79e53945 1379 if (ret)
b8da7de5 1380 goto out;
79e53945 1381
80824003 1382 /* Try to set up FBC with a reasonable compressed buffer size */
9216d44d 1383 if (I915_HAS_FBC(dev) && i915_powersave) {
80824003
JB		 1384 int cfb_size;
1385
1386 /* Try to get an 8M buffer... */
1387 if (prealloc_size > (9*1024*1024))
1388 cfb_size = 8*1024*1024;
1389 else /* fall back to 7/8 of the stolen space */
1390 cfb_size = prealloc_size * 7 / 8;
1391 i915_setup_compression(dev, cfb_size);
1392 }
1393
79e53945
JB		 1394 /* Allow hardware batchbuffers unless told otherwise.
1395 */
1396 dev_priv->allow_batchbuffer = 1;
1397
1398 ret = intel_init_bios(dev);
1399 if (ret)
1400 DRM_INFO("failed to find VBIOS tables\n");
1401
28d52043
DA		 1402 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1403 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1404 if (ret)
1405 goto destroy_ringbuffer;
1406
6a9ee8af
DA		 1407 ret = vga_switcheroo_register_client(dev->pdev,
1408 i915_switcheroo_set_state,
1409 i915_switcheroo_can_switch);
1410 if (ret)
1411 goto destroy_ringbuffer;
1412
b01f2c3a
JB		 1413 intel_modeset_init(dev);
1414
79e53945
JB		 1415 ret = drm_irq_install(dev);
1416 if (ret)
1417 goto destroy_ringbuffer;
1418
79e53945
JB		 1419 /* Always safe in the mode setting case. */
1420 /* FIXME: do pre/post-mode set stuff in core KMS code */
1421 dev->vblank_disable_allowed = 1;
1422
1423 /*
1424 * Initialize the hardware status page IRQ location.
1425 */
1426
1427 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1428
38651674 1429 intel_fbdev_init(dev);
eb1f8e4f 1430 drm_kms_helper_poll_init(dev);
79e53945
JB		 1431 return 0;
1432
79e53945 1433destroy_ringbuffer:
21099537 1434 mutex_lock(&dev->struct_mutex);
79e53945 1435 i915_gem_cleanup_ringbuffer(dev);
21099537 1436 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1437out:
1438 return ret;
1439}
1440
7c1c2871
DA		 1441int i915_master_create(struct drm_device *dev, struct drm_master *master)
1442{
1443 struct drm_i915_master_private *master_priv;
1444
9a298b2a 1445 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
7c1c2871
DA		 1446 if (!master_priv)
1447 return -ENOMEM;
1448
1449 master->driver_priv = master_priv;
1450 return 0;
1451}
1452
1453void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1454{
1455 struct drm_i915_master_private *master_priv = master->driver_priv;
1456
1457 if (!master_priv)
1458 return;
1459
9a298b2a 1460 kfree(master_priv);
7c1c2871
DA		 1461
1462 master->driver_priv = NULL;
1463}
1464
7648fa99 1465static void i915_pineview_get_mem_freq(struct drm_device *dev)
7662c8bd
SL		 1466{
1467 drm_i915_private_t *dev_priv = dev->dev_private;
1468 u32 tmp;
1469
7662c8bd
SL		 1470 tmp = I915_READ(CLKCFG);
1471
1472 switch (tmp & CLKCFG_FSB_MASK) {
1473 case CLKCFG_FSB_533:
1474 dev_priv->fsb_freq = 533; /* 133*4 */
1475 break;
1476 case CLKCFG_FSB_800:
1477 dev_priv->fsb_freq = 800; /* 200*4 */
1478 break;
1479 case CLKCFG_FSB_667:
1480 dev_priv->fsb_freq = 667; /* 167*4 */
1481 break;
1482 case CLKCFG_FSB_400:
1483 dev_priv->fsb_freq = 400; /* 100*4 */
1484 break;
1485 }
1486
1487 switch (tmp & CLKCFG_MEM_MASK) {
1488 case CLKCFG_MEM_533:
1489 dev_priv->mem_freq = 533;
1490 break;
1491 case CLKCFG_MEM_667:
1492 dev_priv->mem_freq = 667;
1493 break;
1494 case CLKCFG_MEM_800:
1495 dev_priv->mem_freq = 800;
1496 break;
1497 }
95534263
LP		 1498
1499 /* detect pineview DDR3 setting */
1500 tmp = I915_READ(CSHRDDR3CTL);
1501 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
7662c8bd
SL		 1502}
1503
7648fa99
JB		 1504static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1505{
1506 drm_i915_private_t *dev_priv = dev->dev_private;
1507 u16 ddrpll, csipll;
1508
1509 ddrpll = I915_READ16(DDRMPLL1);
1510 csipll = I915_READ16(CSIPLL0);
1511
1512 switch (ddrpll & 0xff) {
1513 case 0xc:
1514 dev_priv->mem_freq = 800;
1515 break;
1516 case 0x10:
1517 dev_priv->mem_freq = 1066;
1518 break;
1519 case 0x14:
1520 dev_priv->mem_freq = 1333;
1521 break;
1522 case 0x18:
1523 dev_priv->mem_freq = 1600;
1524 break;
1525 default:
1526 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1527 ddrpll & 0xff);
1528 dev_priv->mem_freq = 0;
1529 break;
1530 }
1531
1532 dev_priv->r_t = dev_priv->mem_freq;
1533
1534 switch (csipll & 0x3ff) {
1535 case 0x00c:
1536 dev_priv->fsb_freq = 3200;
1537 break;
1538 case 0x00e:
1539 dev_priv->fsb_freq = 3733;
1540 break;
1541 case 0x010:
1542 dev_priv->fsb_freq = 4266;
1543 break;
1544 case 0x012:
1545 dev_priv->fsb_freq = 4800;
1546 break;
1547 case 0x014:
1548 dev_priv->fsb_freq = 5333;
1549 break;
1550 case 0x016:
1551 dev_priv->fsb_freq = 5866;
1552 break;
1553 case 0x018:
1554 dev_priv->fsb_freq = 6400;
1555 break;
1556 default:
1557 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1558 csipll & 0x3ff);
1559 dev_priv->fsb_freq = 0;
1560 break;
1561 }
1562
1563 if (dev_priv->fsb_freq == 3200) {
1564 dev_priv->c_m = 0;
1565 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1566 dev_priv->c_m = 1;
1567 } else {
1568 dev_priv->c_m = 2;
1569 }
1570}
1571
1572struct v_table {
1573 u8 vid;
1574 unsigned long vd; /* in .1 mil */
1575 unsigned long vm; /* in .1 mil */
1576 u8 pvid;
1577};
1578
1579static struct v_table v_table[] = {
1580 { 0, 16125, 15000, 0x7f, },
1581 { 1, 16000, 14875, 0x7e, },
1582 { 2, 15875, 14750, 0x7d, },
1583 { 3, 15750, 14625, 0x7c, },
1584 { 4, 15625, 14500, 0x7b, },
1585 { 5, 15500, 14375, 0x7a, },
1586 { 6, 15375, 14250, 0x79, },
1587 { 7, 15250, 14125, 0x78, },
1588 { 8, 15125, 14000, 0x77, },
1589 { 9, 15000, 13875, 0x76, },
1590 { 10, 14875, 13750, 0x75, },
1591 { 11, 14750, 13625, 0x74, },
1592 { 12, 14625, 13500, 0x73, },
1593 { 13, 14500, 13375, 0x72, },
1594 { 14, 14375, 13250, 0x71, },
1595 { 15, 14250, 13125, 0x70, },
1596 { 16, 14125, 13000, 0x6f, },
1597 { 17, 14000, 12875, 0x6e, },
1598 { 18, 13875, 12750, 0x6d, },
1599 { 19, 13750, 12625, 0x6c, },
1600 { 20, 13625, 12500, 0x6b, },
1601 { 21, 13500, 12375, 0x6a, },
1602 { 22, 13375, 12250, 0x69, },
1603 { 23, 13250, 12125, 0x68, },
1604 { 24, 13125, 12000, 0x67, },
1605 { 25, 13000, 11875, 0x66, },
1606 { 26, 12875, 11750, 0x65, },
1607 { 27, 12750, 11625, 0x64, },
1608 { 28, 12625, 11500, 0x63, },
1609 { 29, 12500, 11375, 0x62, },
1610 { 30, 12375, 11250, 0x61, },
1611 { 31, 12250, 11125, 0x60, },
1612 { 32, 12125, 11000, 0x5f, },
1613 { 33, 12000, 10875, 0x5e, },
1614 { 34, 11875, 10750, 0x5d, },
1615 { 35, 11750, 10625, 0x5c, },
1616 { 36, 11625, 10500, 0x5b, },
1617 { 37, 11500, 10375, 0x5a, },
1618 { 38, 11375, 10250, 0x59, },
1619 { 39, 11250, 10125, 0x58, },
1620 { 40, 11125, 10000, 0x57, },
1621 { 41, 11000, 9875, 0x56, },
1622 { 42, 10875, 9750, 0x55, },
1623 { 43, 10750, 9625, 0x54, },
1624 { 44, 10625, 9500, 0x53, },
1625 { 45, 10500, 9375, 0x52, },
1626 { 46, 10375, 9250, 0x51, },
1627 { 47, 10250, 9125, 0x50, },
1628 { 48, 10125, 9000, 0x4f, },
1629 { 49, 10000, 8875, 0x4e, },
1630 { 50, 9875, 8750, 0x4d, },
1631 { 51, 9750, 8625, 0x4c, },
1632 { 52, 9625, 8500, 0x4b, },
1633 { 53, 9500, 8375, 0x4a, },
1634 { 54, 9375, 8250, 0x49, },
1635 { 55, 9250, 8125, 0x48, },
1636 { 56, 9125, 8000, 0x47, },
1637 { 57, 9000, 7875, 0x46, },
1638 { 58, 8875, 7750, 0x45, },
1639 { 59, 8750, 7625, 0x44, },
1640 { 60, 8625, 7500, 0x43, },
1641 { 61, 8500, 7375, 0x42, },
1642 { 62, 8375, 7250, 0x41, },
1643 { 63, 8250, 7125, 0x40, },
1644 { 64, 8125, 7000, 0x3f, },
1645 { 65, 8000, 6875, 0x3e, },
1646 { 66, 7875, 6750, 0x3d, },
1647 { 67, 7750, 6625, 0x3c, },
1648 { 68, 7625, 6500, 0x3b, },
1649 { 69, 7500, 6375, 0x3a, },
1650 { 70, 7375, 6250, 0x39, },
1651 { 71, 7250, 6125, 0x38, },
1652 { 72, 7125, 6000, 0x37, },
1653 { 73, 7000, 5875, 0x36, },
1654 { 74, 6875, 5750, 0x35, },
1655 { 75, 6750, 5625, 0x34, },
1656 { 76, 6625, 5500, 0x33, },
1657 { 77, 6500, 5375, 0x32, },
1658 { 78, 6375, 5250, 0x31, },
1659 { 79, 6250, 5125, 0x30, },
1660 { 80, 6125, 5000, 0x2f, },
1661 { 81, 6000, 4875, 0x2e, },
1662 { 82, 5875, 4750, 0x2d, },
1663 { 83, 5750, 4625, 0x2c, },
1664 { 84, 5625, 4500, 0x2b, },
1665 { 85, 5500, 4375, 0x2a, },
1666 { 86, 5375, 4250, 0x29, },
1667 { 87, 5250, 4125, 0x28, },
1668 { 88, 5125, 4000, 0x27, },
1669 { 89, 5000, 3875, 0x26, },
1670 { 90, 4875, 3750, 0x25, },
1671 { 91, 4750, 3625, 0x24, },
1672 { 92, 4625, 3500, 0x23, },
1673 { 93, 4500, 3375, 0x22, },
1674 { 94, 4375, 3250, 0x21, },
1675 { 95, 4250, 3125, 0x20, },
1676 { 96, 4125, 3000, 0x1f, },
1677 { 97, 4125, 3000, 0x1e, },
1678 { 98, 4125, 3000, 0x1d, },
1679 { 99, 4125, 3000, 0x1c, },
1680 { 100, 4125, 3000, 0x1b, },
1681 { 101, 4125, 3000, 0x1a, },
1682 { 102, 4125, 3000, 0x19, },
1683 { 103, 4125, 3000, 0x18, },
1684 { 104, 4125, 3000, 0x17, },
1685 { 105, 4125, 3000, 0x16, },
1686 { 106, 4125, 3000, 0x15, },
1687 { 107, 4125, 3000, 0x14, },
1688 { 108, 4125, 3000, 0x13, },
1689 { 109, 4125, 3000, 0x12, },
1690 { 110, 4125, 3000, 0x11, },
1691 { 111, 4125, 3000, 0x10, },
1692 { 112, 4125, 3000, 0x0f, },
1693 { 113, 4125, 3000, 0x0e, },
1694 { 114, 4125, 3000, 0x0d, },
1695 { 115, 4125, 3000, 0x0c, },
1696 { 116, 4125, 3000, 0x0b, },
1697 { 117, 4125, 3000, 0x0a, },
1698 { 118, 4125, 3000, 0x09, },
1699 { 119, 4125, 3000, 0x08, },
1700 { 120, 1125, 0, 0x07, },
1701 { 121, 1000, 0, 0x06, },
1702 { 122, 875, 0, 0x05, },
1703 { 123, 750, 0, 0x04, },
1704 { 124, 625, 0, 0x03, },
1705 { 125, 500, 0, 0x02, },
1706 { 126, 375, 0, 0x01, },
1707 { 127, 0, 0, 0x00, },
1708};
1709
1710struct cparams {
1711 int i;
1712 int t;
1713 int m;
1714 int c;
1715};
1716
1717static struct cparams cparams[] = {
1718 { 1, 1333, 301, 28664 },
1719 { 1, 1066, 294, 24460 },
1720 { 1, 800, 294, 25192 },
1721 { 0, 1333, 276, 27605 },
1722 { 0, 1066, 276, 27605 },
1723 { 0, 800, 231, 23784 },
1724};
1725
1726unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1727{
1728 u64 total_count, diff, ret;
1729 u32 count1, count2, count3, m = 0, c = 0;
1730 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1731 int i;
1732
1733 diff1 = now - dev_priv->last_time1;
1734
1735 count1 = I915_READ(DMIEC);
1736 count2 = I915_READ(DDREC);
1737 count3 = I915_READ(CSIEC);
1738
1739 total_count = count1 + count2 + count3;
1740
1741 /* FIXME: handle per-counter overflow */
1742 if (total_count < dev_priv->last_count1) {
1743 diff = ~0UL - dev_priv->last_count1;
1744 diff += total_count;
1745 } else {
1746 diff = total_count - dev_priv->last_count1;
1747 }
1748
1749 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1750 if (cparams[i].i == dev_priv->c_m &&
1751 cparams[i].t == dev_priv->r_t) {
1752 m = cparams[i].m;
1753 c = cparams[i].c;
1754 break;
1755 }
1756 }
1757
1758 div_u64(diff, diff1);
1759 ret = ((m * diff) + c);
1760 div_u64(ret, 10);
1761
1762 dev_priv->last_count1 = total_count;
1763 dev_priv->last_time1 = now;
1764
1765 return ret;
1766}
1767
1768unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1769{
1770 unsigned long m, x, b;
1771 u32 tsfs;
1772
1773 tsfs = I915_READ(TSFS);
1774
1775 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1776 x = I915_READ8(TR1);
1777
1778 b = tsfs & TSFS_INTR_MASK;
1779
1780 return ((m * x) / 127) - b;
1781}
1782
1783static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1784{
1785 unsigned long val = 0;
1786 int i;
1787
1788 for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1789 if (v_table[i].pvid == pxvid) {
1790 if (IS_MOBILE(dev_priv->dev))
1791 val = v_table[i].vm;
1792 else
1793 val = v_table[i].vd;
1794 }
1795 }
1796
1797 return val;
1798}
1799
1800void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1801{
1802 struct timespec now, diff1;
1803 u64 diff;
1804 unsigned long diffms;
1805 u32 count;
1806
1807 getrawmonotonic(&now);
1808 diff1 = timespec_sub(now, dev_priv->last_time2);
1809
1810 /* Don't divide by 0 */
1811 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1812 if (!diffms)
1813 return;
1814
1815 count = I915_READ(GFXEC);
1816
1817 if (count < dev_priv->last_count2) {
1818 diff = ~0UL - dev_priv->last_count2;
1819 diff += count;
1820 } else {
1821 diff = count - dev_priv->last_count2;
1822 }
1823
1824 dev_priv->last_count2 = count;
1825 dev_priv->last_time2 = now;
1826
1827 /* More magic constants... */
1828 diff = diff * 1181;
1829 div_u64(diff, diffms * 10);
1830 dev_priv->gfx_power = diff;
1831}
1832
1833unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1834{
1835 unsigned long t, corr, state1, corr2, state2;
1836 u32 pxvid, ext_v;
1837
1838 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1839 pxvid = (pxvid >> 24) & 0x7f;
1840 ext_v = pvid_to_extvid(dev_priv, pxvid);
1841
1842 state1 = ext_v;
1843
1844 t = i915_mch_val(dev_priv);
1845
1846 /* Revel in the empirically derived constants */
1847
1848 /* Correction factor in 1/100000 units */
1849 if (t > 80)
1850 corr = ((t * 2349) + 135940);
1851 else if (t >= 50)
1852 corr = ((t * 964) + 29317);
1853 else /* < 50 */
1854 corr = ((t * 301) + 1004);
1855
1856 corr = corr * ((150142 * state1) / 10000 - 78642);
1857 corr /= 100000;
1858 corr2 = (corr * dev_priv->corr);
1859
1860 state2 = (corr2 * state1) / 10000;
1861 state2 /= 100; /* convert to mW */
1862
1863 i915_update_gfx_val(dev_priv);
1864
1865 return dev_priv->gfx_power + state2;
1866}
1867
1868/* Global for IPS driver to get at the current i915 device */
1869static struct drm_i915_private *i915_mch_dev;
1870/*
1871 * Lock protecting IPS related data structures
1872 * - i915_mch_dev
1873 * - dev_priv->max_delay
1874 * - dev_priv->min_delay
1875 * - dev_priv->fmax
1876 * - dev_priv->gpu_busy
1877 */
1878DEFINE_SPINLOCK(mchdev_lock);
1879
1880/**
1881 * i915_read_mch_val - return value for IPS use
1882 *
1883 * Calculate and return a value for the IPS driver to use when deciding whether
1884 * we have thermal and power headroom to increase CPU or GPU power budget.
1885 */
1886unsigned long i915_read_mch_val(void)
1887{
1888 struct drm_i915_private *dev_priv;
1889 unsigned long chipset_val, graphics_val, ret = 0;
1890
1891 spin_lock(&mchdev_lock);
1892 if (!i915_mch_dev)
1893 goto out_unlock;
1894 dev_priv = i915_mch_dev;
1895
1896 chipset_val = i915_chipset_val(dev_priv);
1897 graphics_val = i915_gfx_val(dev_priv);
1898
1899 ret = chipset_val + graphics_val;
1900
1901out_unlock:
1902 spin_unlock(&mchdev_lock);
1903
1904 return ret;
1905}
1906EXPORT_SYMBOL_GPL(i915_read_mch_val);
1907
1908/**
1909 * i915_gpu_raise - raise GPU frequency limit
1910 *
1911 * Raise the limit; IPS indicates we have thermal headroom.
1912 */
1913bool i915_gpu_raise(void)
1914{
1915 struct drm_i915_private *dev_priv;
1916 bool ret = true;
1917
1918 spin_lock(&mchdev_lock);
1919 if (!i915_mch_dev) {
1920 ret = false;
1921 goto out_unlock;
1922 }
1923 dev_priv = i915_mch_dev;
1924
1925 if (dev_priv->max_delay > dev_priv->fmax)
1926 dev_priv->max_delay--;
1927
1928out_unlock:
1929 spin_unlock(&mchdev_lock);
1930
1931 return ret;
1932}
1933EXPORT_SYMBOL_GPL(i915_gpu_raise);
1934
1935/**
1936 * i915_gpu_lower - lower GPU frequency limit
1937 *
1938 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1939 * frequency maximum.
1940 */
1941bool i915_gpu_lower(void)
1942{
1943 struct drm_i915_private *dev_priv;
1944 bool ret = true;
1945
1946 spin_lock(&mchdev_lock);
1947 if (!i915_mch_dev) {
1948 ret = false;
1949 goto out_unlock;
1950 }
1951 dev_priv = i915_mch_dev;
1952
1953 if (dev_priv->max_delay < dev_priv->min_delay)
1954 dev_priv->max_delay++;
1955
1956out_unlock:
1957 spin_unlock(&mchdev_lock);
1958
1959 return ret;
1960}
1961EXPORT_SYMBOL_GPL(i915_gpu_lower);
1962
1963/**
1964 * i915_gpu_busy - indicate GPU business to IPS
1965 *
1966 * Tell the IPS driver whether or not the GPU is busy.
1967 */
1968bool i915_gpu_busy(void)
1969{
1970 struct drm_i915_private *dev_priv;
1971 bool ret = false;
1972
1973 spin_lock(&mchdev_lock);
1974 if (!i915_mch_dev)
1975 goto out_unlock;
1976 dev_priv = i915_mch_dev;
1977
1978 ret = dev_priv->busy;
1979
1980out_unlock:
1981 spin_unlock(&mchdev_lock);
1982
1983 return ret;
1984}
1985EXPORT_SYMBOL_GPL(i915_gpu_busy);
1986
1987/**
1988 * i915_gpu_turbo_disable - disable graphics turbo
1989 *
1990 * Disable graphics turbo by resetting the max frequency and setting the
1991 * current frequency to the default.
1992 */
1993bool i915_gpu_turbo_disable(void)
1994{
1995 struct drm_i915_private *dev_priv;
1996 bool ret = true;
1997
1998 spin_lock(&mchdev_lock);
1999 if (!i915_mch_dev) {
2000 ret = false;
2001 goto out_unlock;
2002 }
2003 dev_priv = i915_mch_dev;
2004
2005 dev_priv->max_delay = dev_priv->fstart;
2006
2007 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2008 ret = false;
2009
2010out_unlock:
2011 spin_unlock(&mchdev_lock);
2012
2013 return ret;
2014}
2015EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2016
79e53945
JB		 2017/**
2018 * i915_driver_load - setup chip and create an initial config
2019 * @dev: DRM device
2020 * @flags: startup flags
2021 *
2022 * The driver load routine has to do several things:
2023 * - drive output discovery via intel_modeset_init()
2024 * - initialize the memory manager
2025 * - allocate initial config memory
2026 * - setup the DRM framebuffer with the allocated memory
2027 */
84b1fd10 2028int i915_driver_load(struct drm_device *dev, unsigned long flags)
22eae947 2029{
ea059a1e 2030 struct drm_i915_private *dev_priv;
d883f7f1 2031 resource_size_t base, size;
cfdf1fa2 2032 int ret = 0, mmio_bar;
80824003 2033 uint32_t agp_size, prealloc_size, prealloc_start;
22eae947
DA		 2034 /* i915 has 4 more counters */
2035 dev->counters += 4;
2036 dev->types[6] = _DRM_STAT_IRQ;
2037 dev->types[7] = _DRM_STAT_PRIMARY;
2038 dev->types[8] = _DRM_STAT_SECONDARY;
2039 dev->types[9] = _DRM_STAT_DMA;
2040
9a298b2a 2041 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
ba8bbcf6
JB		 2042 if (dev_priv == NULL)
2043 return -ENOMEM;
2044
ba8bbcf6 2045 dev->dev_private = (void *)dev_priv;
673a394b 2046 dev_priv->dev = dev;
cfdf1fa2 2047 dev_priv->info = (struct intel_device_info *) flags;
ba8bbcf6
JB		 2048
2049 /* Add register map (needed for suspend/resume) */
cfdf1fa2 2050 mmio_bar = IS_I9XX(dev) ? 0 : 1;
ba8bbcf6
JB		 2051 base = drm_get_resource_start(dev, mmio_bar);
2052 size = drm_get_resource_len(dev, mmio_bar);
2053
ec2a4c3f
DA		 2054 if (i915_get_bridge_dev(dev)) {
2055 ret = -EIO;
2056 goto free_priv;
2057 }
2058
3043c60c 2059 dev_priv->regs = ioremap(base, size);
79e53945
JB		 2060 if (!dev_priv->regs) {
2061 DRM_ERROR("failed to map registers\n");
2062 ret = -EIO;
ec2a4c3f 2063 goto put_bridge;
79e53945 2064 }
ed4cb414 2065
ab657db1
EA		 2066 dev_priv->mm.gtt_mapping =
2067 io_mapping_create_wc(dev->agp->base,
2068 dev->agp->agp_info.aper_size * 1024*1024);
6644107d
VP		 2069 if (dev_priv->mm.gtt_mapping == NULL) {
2070 ret = -EIO;
2071 goto out_rmmap;
2072 }
2073
ab657db1
EA		 2074 /* Set up a WC MTRR for non-PAT systems. This is more common than
2075 * one would think, because the kernel disables PAT on first
2076 * generation Core chips because WC PAT gets overridden by a UC
2077 * MTRR if present. Even if a UC MTRR isn't present.
2078 */
2079 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2080 dev->agp->agp_info.aper_size *
2081 1024 * 1024,
2082 MTRR_TYPE_WRCOMB, 1);
2083 if (dev_priv->mm.gtt_mtrr < 0) {
040aefa2 2084 DRM_INFO("MTRR allocation failed. Graphics "
ab657db1
EA		 2085 "performance may suffer.\n");
2086 }
2087
80824003 2088 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2a34f5e6
EA		 2089 if (ret)
2090 goto out_iomapfree;
2091
aed5f1dc 2092 dev_priv->wq = create_singlethread_workqueue("i915");
9c9fe1f8
EA		 2093 if (dev_priv->wq == NULL) {
2094 DRM_ERROR("Failed to create our workqueue.\n");
2095 ret = -ENOMEM;
2096 goto out_iomapfree;
2097 }
2098
ac5c4e76
DA		 2099 /* enable GEM by default */
2100 dev_priv->has_gem = 1;
ac5c4e76 2101
2a34f5e6
EA		 2102 if (prealloc_size > agp_size * 3 / 4) {
2103 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2104 "memory stolen.\n",
2105 prealloc_size / 1024, agp_size / 1024);
2106 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2107 "updating the BIOS to fix).\n");
2108 dev_priv->has_gem = 0;
2109 }
2110
79a78dd6
CW		 2111 if (dev_priv->has_gem == 0 &&
2112 drm_core_check_feature(dev, DRIVER_MODESET)) {
2113 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2114 ret = -ENODEV;
2115 goto out_iomapfree;
2116 }
2117
9880b7a5 2118 dev->driver->get_vblank_counter = i915_get_vblank_counter;
42c2798b 2119 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
bad720ff 2120 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
42c2798b 2121 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
9880b7a5 2122 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
42c2798b 2123 }
9880b7a5 2124
c4804411
ZW		 2125 /* Try to make sure MCHBAR is enabled before poking at it */
2126 intel_setup_mchbar(dev);
2127
673a394b
EA		 2128 i915_gem_load(dev);
2129
398c9cb2
KP		 2130 /* Init HWS */
2131 if (!I915_NEED_GFX_HWS(dev)) {
2132 ret = i915_init_phys_hws(dev);
2133 if (ret != 0)
9c9fe1f8 2134 goto out_workqueue_free;
398c9cb2 2135 }
ed4cb414 2136
7648fa99
JB		 2137 if (IS_PINEVIEW(dev))
2138 i915_pineview_get_mem_freq(dev);
2139 else if (IS_IRONLAKE(dev))
2140 i915_ironlake_get_mem_freq(dev);
7662c8bd 2141
ed4cb414
EA		 2142 /* On the 945G/GM, the chipset reports the MSI capability on the
2143 * integrated graphics even though the support isn't actually there
2144 * according to the published specs. It doesn't appear to function
2145 * correctly in testing on 945G.
2146 * This may be a side effect of MSI having been made available for PEG
2147 * and the registers being closely associated.
d1ed629f
KP		 2148 *
2149 * According to chipset errata, on the 965GM, MSI interrupts may
b60678a7
KP		 2150 * be lost or delayed, but we use them anyways to avoid
2151 * stuck interrupts on some machines.
ed4cb414 2152 */
b60678a7 2153 if (!IS_I945G(dev) && !IS_I945GM(dev))
d3e74d02 2154 pci_enable_msi(dev->pdev);
ed4cb414
EA		 2155
2156 spin_lock_init(&dev_priv->user_irq_lock);
63eeaf38 2157 spin_lock_init(&dev_priv->error_lock);
9d34e5db 2158 dev_priv->trace_irq_seqno = 0;
ed4cb414 2159
52440211
KP		 2160 ret = drm_vblank_init(dev, I915_NUM_PIPE);
2161
2162 if (ret) {
2163 (void) i915_driver_unload(dev);
2164 return ret;
2165 }
2166
11ed50ec
BG		 2167 /* Start out suspended */
2168 dev_priv->mm.suspended = 1;
2169
3bad0781
ZW		 2170 intel_detect_pch(dev);
2171
79e53945 2172 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
80824003
JB		 2173 ret = i915_load_modeset_init(dev, prealloc_start,
2174 prealloc_size, agp_size);
79e53945
JB		 2175 if (ret < 0) {
2176 DRM_ERROR("failed to init modeset\n");
9c9fe1f8 2177 goto out_workqueue_free;
79e53945
JB		 2178 }
2179 }
2180
74a365b3 2181 /* Must be done after probing outputs */
01c66889 2182 intel_opregion_init(dev, 0);
74a365b3 2183
f65d9421
BG		 2184 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2185 (unsigned long) dev);
7648fa99
JB		 2186
2187 spin_lock(&mchdev_lock);
2188 i915_mch_dev = dev_priv;
2189 dev_priv->mchdev_lock = &mchdev_lock;
2190 spin_unlock(&mchdev_lock);
2191
79e53945
JB		 2192 return 0;
2193
9c9fe1f8
EA		 2194out_workqueue_free:
2195 destroy_workqueue(dev_priv->wq);
6644107d
VP		 2196out_iomapfree:
2197 io_mapping_free(dev_priv->mm.gtt_mapping);
79e53945
JB		 2198out_rmmap:
2199 iounmap(dev_priv->regs);
ec2a4c3f
DA		 2200put_bridge:
2201 pci_dev_put(dev_priv->bridge_dev);
79e53945 2202free_priv:
9a298b2a 2203 kfree(dev_priv);
ba8bbcf6
JB		 2204 return ret;
2205}
2206
2207int i915_driver_unload(struct drm_device *dev)
2208{
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210
9df30794
CW		 2211 i915_destroy_error_state(dev);
2212
7648fa99
JB		 2213 spin_lock(&mchdev_lock);
2214 i915_mch_dev = NULL;
2215 spin_unlock(&mchdev_lock);
2216
9c9fe1f8 2217 destroy_workqueue(dev_priv->wq);
f65d9421 2218 del_timer_sync(&dev_priv->hangcheck_timer);
9c9fe1f8 2219
ab657db1
EA		 2220 io_mapping_free(dev_priv->mm.gtt_mapping);
2221 if (dev_priv->mm.gtt_mtrr >= 0) {
2222 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2223 dev->agp->agp_info.aper_size * 1024 * 1024);
2224 dev_priv->mm.gtt_mtrr = -1;
2225 }
2226
79e53945 2227 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
3d8620cc
JB		 2228 intel_modeset_cleanup(dev);
2229
6363ee6f
ZY		 2230 /*
2231 * free the memory space allocated for the child device
2232 * config parsed from VBT
2233 */
2234 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2235 kfree(dev_priv->child_dev);
2236 dev_priv->child_dev = NULL;
2237 dev_priv->child_dev_num = 0;
2238 }
79e53945 2239 drm_irq_uninstall(dev);
6a9ee8af 2240 vga_switcheroo_unregister_client(dev->pdev);
28d52043 2241 vga_client_register(dev->pdev, NULL, NULL, NULL);
79e53945
JB		 2242 }
2243
ed4cb414
EA		 2244 if (dev->pdev->msi_enabled)
2245 pci_disable_msi(dev->pdev);
2246
3043c60c
EA		 2247 if (dev_priv->regs != NULL)
2248 iounmap(dev_priv->regs);
ba8bbcf6 2249
01c66889 2250 intel_opregion_free(dev, 0);
8ee1c3db 2251
79e53945 2252 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
71acb5eb
DA		 2253 i915_gem_free_all_phys_object(dev);
2254
79e53945
JB		 2255 mutex_lock(&dev->struct_mutex);
2256 i915_gem_cleanup_ringbuffer(dev);
2257 mutex_unlock(&dev->struct_mutex);
20bf377e
JB		 2258 if (I915_HAS_FBC(dev) && i915_powersave)
2259 i915_cleanup_compression(dev);
79e53945
JB		 2260 drm_mm_takedown(&dev_priv->vram);
2261 i915_gem_lastclose(dev);
02e792fb
DV		 2262
2263 intel_cleanup_overlay(dev);
79e53945
JB		 2264 }
2265
c4804411
ZW		 2266 intel_teardown_mchbar(dev);
2267
ec2a4c3f 2268 pci_dev_put(dev_priv->bridge_dev);
9a298b2a 2269 kfree(dev->dev_private);
ba8bbcf6 2270
22eae947
DA		 2271 return 0;
2272}
2273
673a394b
EA		 2274int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2275{
2276 struct drm_i915_file_private *i915_file_priv;
2277
8a4c47f3 2278 DRM_DEBUG_DRIVER("\n");
673a394b 2279 i915_file_priv = (struct drm_i915_file_private *)
9a298b2a 2280 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
673a394b
EA		 2281
2282 if (!i915_file_priv)
2283 return -ENOMEM;
2284
2285 file_priv->driver_priv = i915_file_priv;
2286
b962442e 2287 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
673a394b
EA		 2288
2289 return 0;
2290}
2291
79e53945
JB		 2292/**
2293 * i915_driver_lastclose - clean up after all DRM clients have exited
2294 * @dev: DRM device
2295 *
2296 * Take care of cleaning up after all DRM clients have exited. In the
2297 * mode setting case, we want to restore the kernel's initial mode (just
2298 * in case the last client left us in a bad state).
2299 *
2300 * Additionally, in the non-mode setting case, we'll tear down the AGP
2301 * and DMA structures, since the kernel won't be using them, and clea
2302 * up any GEM state.
2303 */
84b1fd10 2304void i915_driver_lastclose(struct drm_device * dev)
1da177e4 2305{
ba8bbcf6
JB		 2306 drm_i915_private_t *dev_priv = dev->dev_private;
2307
79e53945 2308 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
785b93ef 2309 drm_fb_helper_restore();
6a9ee8af 2310 vga_switcheroo_process_delayed_switch();
144a75fa 2311 return;
79e53945 2312 }
144a75fa 2313
673a394b
EA		 2314 i915_gem_lastclose(dev);
2315
ba8bbcf6 2316 if (dev_priv->agp_heap)
b5e89ed5 2317 i915_mem_takedown(&(dev_priv->agp_heap));
ba8bbcf6 2318
b5e89ed5 2319 i915_dma_cleanup(dev);
1da177e4
LT		 2320}
2321
6c340eac 2322void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1da177e4 2323{
ba8bbcf6 2324 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 2325 i915_gem_release(dev, file_priv);
79e53945
JB		 2326 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2327 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1da177e4
LT		 2328}
2329
673a394b
EA		 2330void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2331{
2332 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2333
9a298b2a 2334 kfree(i915_file_priv);
673a394b
EA		 2335}
2336
c153f45f
EA		 2337struct drm_ioctl_desc i915_ioctls[] = {
2338 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2339 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2340 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
2341 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2342 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2343 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2344 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
2345 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2346 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2347 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
2348 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2349 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2350 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2351 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2352 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
2353 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
4b408939 2354 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
f05dd2f0
EA		 2355 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2356 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2357 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2358 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2359 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2360 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2361 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2362 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2363 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2364 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2365 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2366 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2367 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2368 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2369 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2370 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2371 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2372 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2373 DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2374 DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2375 DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2376 DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2377 DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
c94f7029
DA		 2378};
2379
2380int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
cda17380
DA		 2381
2382/**
2383 * Determine if the device really is AGP or not.
2384 *
2385 * All Intel graphics chipsets are treated as AGP, even if they are really
2386 * PCI-e.
2387 *
2388 * \param dev The device to be tested.
2389 *
2390 * \returns
2391 * A value of 1 is always retured to indictate every i9x5 is AGP.
2392 */
84b1fd10 2393int i915_driver_device_is_agp(struct drm_device * dev)
cda17380
DA		 2394{
2395 return 1;
2396}
Clone of davem's net-next-2.6 tree