[net-next-2.6.git] / drivers / gpu / drm / i915 / dvo_tfp410.c

/*
 * Copyright © 2007 Dave Mueller
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Dave Mueller <dave.mueller@gmx.ch>
 *
 */

#include "dvo.h"

/* register definitions according to the TFP410 data sheet */
#define TFP410_VID		0x014C
#define TFP410_DID		0x0410

#define TFP410_VID_LO		0x00
#define TFP410_VID_HI		0x01
#define TFP410_DID_LO		0x02
#define TFP410_DID_HI		0x03
#define TFP410_REV		0x04

#define TFP410_CTL_1		0x08
#define TFP410_CTL_1_TDIS	(1<<6)
#define TFP410_CTL_1_VEN	(1<<5)
#define TFP410_CTL_1_HEN	(1<<4)
#define TFP410_CTL_1_DSEL	(1<<3)
#define TFP410_CTL_1_BSEL	(1<<2)
#define TFP410_CTL_1_EDGE	(1<<1)
#define TFP410_CTL_1_PD		(1<<0)

#define TFP410_CTL_2		0x09
#define TFP410_CTL_2_VLOW	(1<<7)
#define TFP410_CTL_2_MSEL_MASK	(0x7<<4)
#define TFP410_CTL_2_MSEL	(1<<4)
#define TFP410_CTL_2_TSEL	(1<<3)
#define TFP410_CTL_2_RSEN	(1<<2)
#define TFP410_CTL_2_HTPLG	(1<<1)
#define TFP410_CTL_2_MDI	(1<<0)

#define TFP410_CTL_3		0x0A
#define TFP410_CTL_3_DK_MASK 	(0x7<<5)
#define TFP410_CTL_3_DK		(1<<5)
#define TFP410_CTL_3_DKEN	(1<<4)
#define TFP410_CTL_3_CTL_MASK	(0x7<<1)
#define TFP410_CTL_3_CTL	(1<<1)

#define TFP410_USERCFG		0x0B

#define TFP410_DE_DLY		0x32

#define TFP410_DE_CTL		0x33
#define TFP410_DE_CTL_DEGEN	(1<<6)
#define TFP410_DE_CTL_VSPOL	(1<<5)
#define TFP410_DE_CTL_HSPOL	(1<<4)
#define TFP410_DE_CTL_DEDLY8	(1<<0)

#define TFP410_DE_TOP		0x34

#define TFP410_DE_CNT_LO	0x36
#define TFP410_DE_CNT_HI	0x37

#define TFP410_DE_LIN_LO	0x38
#define TFP410_DE_LIN_HI	0x39

#define TFP410_H_RES_LO		0x3A
#define TFP410_H_RES_HI		0x3B

#define TFP410_V_RES_LO		0x3C
#define TFP410_V_RES_HI		0x3D

struct tfp410_priv {
	bool quiet;
};

static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
{
	struct tfp410_priv *tfp = dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
	u8 out_buf[2];
	u8 in_buf[2];

	struct i2c_msg msgs[] = {
		{
			.addr = dvo->slave_addr,
			.flags = 0,
			.len = 1,
			.buf = out_buf,
		},
		{
			.addr = dvo->slave_addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = in_buf,
		}
	};

	out_buf[0] = addr;
	out_buf[1] = 0;

	if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
		*ch = in_buf[0];
		return true;
	};

	if (!tfp->quiet) {
		DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
			  addr, i2cbus->adapter.name, dvo->slave_addr);
	}
	return false;
}

static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
{
	struct tfp410_priv *tfp = dvo->dev_priv;
	struct i2c_adapter *adapter = dvo->i2c_bus;
	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
	uint8_t out_buf[2];
	struct i2c_msg msg = {
		.addr = dvo->slave_addr,
		.flags = 0,
		.len = 2,
		.buf = out_buf,
	};

	out_buf[0] = addr;
	out_buf[1] = ch;

	if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
		return true;

	if (!tfp->quiet) {
		DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
			  addr, i2cbus->adapter.name, dvo->slave_addr);
	}

	return false;
}

static int tfp410_getid(struct intel_dvo_device *dvo, int addr)
{
	uint8_t ch1, ch2;

	if (tfp410_readb(dvo, addr+0, &ch1) &&
	    tfp410_readb(dvo, addr+1, &ch2))
		return ((ch2 << 8) & 0xFF00) | (ch1 & 0x00FF);

	return -1;
}

/* Ti TFP410 driver for chip on i2c bus */
static bool tfp410_init(struct intel_dvo_device *dvo,
			struct i2c_adapter *adapter)
{
	/* this will detect the tfp410 chip on the specified i2c bus */
	struct tfp410_priv *tfp;
	int id;

	tfp = kzalloc(sizeof(struct tfp410_priv), GFP_KERNEL);
	if (tfp == NULL)
		return false;

	dvo->i2c_bus = adapter;
	dvo->dev_priv = tfp;
	tfp->quiet = true;

	if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
		DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
				"Slave %d.\n",
			  id, adapter->name, dvo->slave_addr);
		goto out;
	}

	if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
		DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
				"Slave %d.\n",
			  id, adapter->name, dvo->slave_addr);
		goto out;
	}
	tfp->quiet = false;
	return true;
out:
	kfree(tfp);
	return false;
}

static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo)
{
	enum drm_connector_status ret = connector_status_disconnected;
	uint8_t ctl2;

	if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {
		if (ctl2 & TFP410_CTL_2_RSEN)
			ret = connector_status_connected;
		else
			ret = connector_status_disconnected;
	}

	return ret;
}

static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo,
					      struct drm_display_mode *mode)
{
	return MODE_OK;
}

static void tfp410_mode_set(struct intel_dvo_device *dvo,
			    struct drm_display_mode *mode,
			    struct drm_display_mode *adjusted_mode)
{
    /* As long as the basics are set up, since we don't have clock dependencies
     * in the mode setup, we can just leave the registers alone and everything
     * will work fine.
     */
    /* don't do much */
    return;
}

/* set the tfp410 power state */
static void tfp410_dpms(struct intel_dvo_device *dvo, int mode)
{
	uint8_t ctl1;

	if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))
		return;

	if (mode == DRM_MODE_DPMS_ON)
		ctl1 |= TFP410_CTL_1_PD;
	else
		ctl1 &= ~TFP410_CTL_1_PD;

	tfp410_writeb(dvo, TFP410_CTL_1, ctl1);
}

static void tfp410_dump_regs(struct intel_dvo_device *dvo)
{
	uint8_t val, val2;

	tfp410_readb(dvo, TFP410_REV, &val);
	DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_CTL_1, &val);
	DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_CTL_2, &val);
	DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_CTL_3, &val);
	DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_USERCFG, &val);
	DRM_LOG_KMS("TFP410_USERCFG: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_DE_DLY, &val);
	DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_DE_CTL, &val);
	DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_DE_TOP, &val);
	DRM_LOG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
	tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
	tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
	DRM_LOG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
	tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
	tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
	DRM_LOG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
	tfp410_readb(dvo, TFP410_H_RES_LO, &val);
	tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
	DRM_LOG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
	tfp410_readb(dvo, TFP410_V_RES_LO, &val);
	tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
	DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
}

static void tfp410_destroy(struct intel_dvo_device *dvo)
{
	struct tfp410_priv *tfp = dvo->dev_priv;

	if (tfp) {
		kfree(tfp);
		dvo->dev_priv = NULL;
	}
}

struct intel_dvo_dev_ops tfp410_ops = {
	.init = tfp410_init,
	.detect = tfp410_detect,
	.mode_valid = tfp410_mode_valid,
	.mode_set = tfp410_mode_set,
	.dpms = tfp410_dpms,
	.dump_regs = tfp410_dump_regs,
	.destroy = tfp410_destroy,
};
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright © 2007 Dave Mueller
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Dave Mueller <dave.mueller@gmx.ch>
	25	*
	26	*/
	27
	28	#include "dvo.h"
	29
	30	/* register definitions according to the TFP410 data sheet */
	31	#define TFP410_VID 0x014C
	32	#define TFP410_DID 0x0410
	33
	34	#define TFP410_VID_LO 0x00
	35	#define TFP410_VID_HI 0x01
	36	#define TFP410_DID_LO 0x02
	37	#define TFP410_DID_HI 0x03
	38	#define TFP410_REV 0x04
	39
	40	#define TFP410_CTL_1 0x08
	41	#define TFP410_CTL_1_TDIS (1<<6)
	42	#define TFP410_CTL_1_VEN (1<<5)
	43	#define TFP410_CTL_1_HEN (1<<4)
	44	#define TFP410_CTL_1_DSEL (1<<3)
	45	#define TFP410_CTL_1_BSEL (1<<2)
	46	#define TFP410_CTL_1_EDGE (1<<1)
	47	#define TFP410_CTL_1_PD (1<<0)
	48
	49	#define TFP410_CTL_2 0x09
	50	#define TFP410_CTL_2_VLOW (1<<7)
	51	#define TFP410_CTL_2_MSEL_MASK (0x7<<4)
	52	#define TFP410_CTL_2_MSEL (1<<4)
	53	#define TFP410_CTL_2_TSEL (1<<3)
	54	#define TFP410_CTL_2_RSEN (1<<2)
	55	#define TFP410_CTL_2_HTPLG (1<<1)
	56	#define TFP410_CTL_2_MDI (1<<0)
	57
	58	#define TFP410_CTL_3 0x0A
	59	#define TFP410_CTL_3_DK_MASK (0x7<<5)
	60	#define TFP410_CTL_3_DK (1<<5)
	61	#define TFP410_CTL_3_DKEN (1<<4)
	62	#define TFP410_CTL_3_CTL_MASK (0x7<<1)
	63	#define TFP410_CTL_3_CTL (1<<1)
	64
65	#define TFP410_USERCFG 0x0B
66
67	#define TFP410_DE_DLY 0x32
68
69	#define TFP410_DE_CTL 0x33
70	#define TFP410_DE_CTL_DEGEN (1<<6)
71	#define TFP410_DE_CTL_VSPOL (1<<5)
72	#define TFP410_DE_CTL_HSPOL (1<<4)
73	#define TFP410_DE_CTL_DEDLY8 (1<<0)
74
75	#define TFP410_DE_TOP 0x34
76
77	#define TFP410_DE_CNT_LO 0x36
78	#define TFP410_DE_CNT_HI 0x37
79
80	#define TFP410_DE_LIN_LO 0x38
81	#define TFP410_DE_LIN_HI 0x39
82
83	#define TFP410_H_RES_LO 0x3A
84	#define TFP410_H_RES_HI 0x3B
85
86	#define TFP410_V_RES_LO 0x3C
87	#define TFP410_V_RES_HI 0x3D
88
79e53945 JB	89	struct tfp410_priv {
79e53945 JB	90	bool quiet;
79e53945 JB	91	};
	92
	93	static bool tfp410_readb(struct intel_dvo_device dvo, int addr, uint8_t ch)
	94	{
	95	struct tfp410_priv *tfp = dvo->dev_priv;
f9c10a9b KP	96	struct i2c_adapter *adapter = dvo->i2c_bus;
f9c10a9b KP	97	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
79e53945 JB	98	u8 out_buf[2];
	99	u8 in_buf[2];
	100
	101	struct i2c_msg msgs[] = {
	102	{
f9c10a9b	103	.addr = dvo->slave_addr,
79e53945 JB	104	.flags = 0,
	105	.len = 1,
	106	.buf = out_buf,
	107	},
	108	{
f9c10a9b	109	.addr = dvo->slave_addr,
79e53945 JB	110	.flags = I2C_M_RD,
	111	.len = 1,
	112	.buf = in_buf,
	113	}
	114	};
	115
	116	out_buf[0] = addr;
	117	out_buf[1] = 0;
	118
	119	if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
	120	*ch = in_buf[0];
	121	return true;
	122	};
	123
	124	if (!tfp->quiet) {
d0c3b04a	125	DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
f9c10a9b	126	addr, i2cbus->adapter.name, dvo->slave_addr);
79e53945 JB	127	}
	128	return false;
	129	}
	130
	131	static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
	132	{
	133	struct tfp410_priv *tfp = dvo->dev_priv;
f9c10a9b KP	134	struct i2c_adapter *adapter = dvo->i2c_bus;
f9c10a9b KP	135	struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
79e53945 JB	136	uint8_t out_buf[2];
79e53945 JB	137	struct i2c_msg msg = {
f9c10a9b	138	.addr = dvo->slave_addr,
79e53945 JB	139	.flags = 0,
	140	.len = 2,
	141	.buf = out_buf,
	142	};
	143
	144	out_buf[0] = addr;
	145	out_buf[1] = ch;
	146
	147	if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
	148	return true;
	149
	150	if (!tfp->quiet) {
d0c3b04a	151	DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
f9c10a9b	152	addr, i2cbus->adapter.name, dvo->slave_addr);
79e53945 JB	153	}
	154
	155	return false;
	156	}
	157
	158	static int tfp410_getid(struct intel_dvo_device *dvo, int addr)
	159	{
	160	uint8_t ch1, ch2;
	161
	162	if (tfp410_readb(dvo, addr+0, &ch1) &&
	163	tfp410_readb(dvo, addr+1, &ch2))
	164	return ((ch2 << 8) & 0xFF00) \| (ch1 & 0x00FF);
	165
	166	return -1;
	167	}
	168
	169	/* Ti TFP410 driver for chip on i2c bus */
	170	static bool tfp410_init(struct intel_dvo_device *dvo,
f9c10a9b	171	struct i2c_adapter *adapter)
79e53945 JB	172	{
	173	/* this will detect the tfp410 chip on the specified i2c bus */
	174	struct tfp410_priv *tfp;
	175	int id;
	176
	177	tfp = kzalloc(sizeof(struct tfp410_priv), GFP_KERNEL);
	178	if (tfp == NULL)
	179	return false;
	180
f9c10a9b	181	dvo->i2c_bus = adapter;
79e53945 JB	182	dvo->dev_priv = tfp;
	183	tfp->quiet = true;
	184
	185	if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
d0c3b04a ZY	186	DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
d0c3b04a ZY	187	"Slave %d.\n",
f9c10a9b	188	id, adapter->name, dvo->slave_addr);
79e53945 JB	189	goto out;
	190	}
	191
	192	if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
d0c3b04a ZY	193	DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
d0c3b04a ZY	194	"Slave %d.\n",
f9c10a9b	195	id, adapter->name, dvo->slave_addr);
79e53945 JB	196	goto out;
	197	}
	198	tfp->quiet = false;
	199	return true;
	200	out:
	201	kfree(tfp);
	202	return false;
	203	}
	204
	205	static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo)
	206	{
	207	enum drm_connector_status ret = connector_status_disconnected;
	208	uint8_t ctl2;
	209
	210	if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {
f458823b	211	if (ctl2 & TFP410_CTL_2_RSEN)
79e53945 JB	212	ret = connector_status_connected;
	213	else
	214	ret = connector_status_disconnected;
	215	}
	216
	217	return ret;
	218	}
	219
	220	static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo,
	221	struct drm_display_mode *mode)
	222	{
	223	return MODE_OK;
	224	}
	225
	226	static void tfp410_mode_set(struct intel_dvo_device *dvo,
	227	struct drm_display_mode *mode,
	228	struct drm_display_mode *adjusted_mode)
	229	{
	230	/* As long as the basics are set up, since we don't have clock dependencies
	231	* in the mode setup, we can just leave the registers alone and everything
	232	* will work fine.
	233	*/
	234	/* don't do much */
	235	return;
	236	}
	237
	238	/* set the tfp410 power state */
	239	static void tfp410_dpms(struct intel_dvo_device *dvo, int mode)
	240	{
	241	uint8_t ctl1;
	242
	243	if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))
	244	return;
	245
	246	if (mode == DRM_MODE_DPMS_ON)
	247	ctl1 \|= TFP410_CTL_1_PD;
	248	else
	249	ctl1 &= ~TFP410_CTL_1_PD;
	250
	251	tfp410_writeb(dvo, TFP410_CTL_1, ctl1);
	252	}
	253
	254	static void tfp410_dump_regs(struct intel_dvo_device *dvo)
	255	{
	256	uint8_t val, val2;
	257
	258	tfp410_readb(dvo, TFP410_REV, &val);
d0c3b04a	259	DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val);
79e53945	260	tfp410_readb(dvo, TFP410_CTL_1, &val);
d0c3b04a	261	DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val);
79e53945	262	tfp410_readb(dvo, TFP410_CTL_2, &val);
d0c3b04a	263	DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val);
79e53945	264	tfp410_readb(dvo, TFP410_CTL_3, &val);
d0c3b04a	265	DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val);
79e53945	266	tfp410_readb(dvo, TFP410_USERCFG, &val);
d0c3b04a	267	DRM_LOG_KMS("TFP410_USERCFG: 0x%02X\n", val);
79e53945	268	tfp410_readb(dvo, TFP410_DE_DLY, &val);
d0c3b04a	269	DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
79e53945	270	tfp410_readb(dvo, TFP410_DE_CTL, &val);
d0c3b04a	271	DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
79e53945	272	tfp410_readb(dvo, TFP410_DE_TOP, &val);
d0c3b04a	273	DRM_LOG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
79e53945 JB	274	tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
79e53945 JB	275	tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
d0c3b04a	276	DRM_LOG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
79e53945 JB	277	tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
79e53945 JB	278	tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
d0c3b04a	279	DRM_LOG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
79e53945 JB	280	tfp410_readb(dvo, TFP410_H_RES_LO, &val);
79e53945 JB	281	tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
d0c3b04a	282	DRM_LOG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
79e53945 JB	283	tfp410_readb(dvo, TFP410_V_RES_LO, &val);
79e53945 JB	284	tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
d0c3b04a	285	DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
79e53945 JB	286	}
79e53945 JB	287
79e53945 JB	288	static void tfp410_destroy(struct intel_dvo_device *dvo)
	289	{
	290	struct tfp410_priv *tfp = dvo->dev_priv;
	291
	292	if (tfp) {
	293	kfree(tfp);
	294	dvo->dev_priv = NULL;
	295	}
	296	}
	297
	298	struct intel_dvo_dev_ops tfp410_ops = {
	299	.init = tfp410_init,
	300	.detect = tfp410_detect,
	301	.mode_valid = tfp410_mode_valid,
	302	.mode_set = tfp410_mode_set,
	303	.dpms = tfp410_dpms,
	304	.dump_regs = tfp410_dump_regs,
79e53945 JB	305	.destroy = tfp410_destroy,
79e53945 JB	306	};