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ed568912 KH |
1 | /* -*- c-basic-offset: 8 -*- |
2 | * | |
3 | * fw-ohci.c - Driver for OHCI 1394 boards | |
4 | * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/poll.h> | |
cf3e72fd AM |
28 | #include <linux/dma-mapping.h> |
29 | ||
ed568912 KH |
30 | #include <asm/uaccess.h> |
31 | #include <asm/semaphore.h> | |
32 | ||
33 | #include "fw-transaction.h" | |
34 | #include "fw-ohci.h" | |
35 | ||
36 | #define descriptor_output_more 0 | |
37 | #define descriptor_output_last (1 << 12) | |
38 | #define descriptor_input_more (2 << 12) | |
39 | #define descriptor_input_last (3 << 12) | |
40 | #define descriptor_status (1 << 11) | |
41 | #define descriptor_key_immediate (2 << 8) | |
42 | #define descriptor_ping (1 << 7) | |
43 | #define descriptor_yy (1 << 6) | |
44 | #define descriptor_no_irq (0 << 4) | |
45 | #define descriptor_irq_error (1 << 4) | |
46 | #define descriptor_irq_always (3 << 4) | |
47 | #define descriptor_branch_always (3 << 2) | |
48 | ||
49 | struct descriptor { | |
50 | __le16 req_count; | |
51 | __le16 control; | |
52 | __le32 data_address; | |
53 | __le32 branch_address; | |
54 | __le16 res_count; | |
55 | __le16 transfer_status; | |
56 | } __attribute__((aligned(16))); | |
57 | ||
58 | struct ar_context { | |
59 | struct fw_ohci *ohci; | |
60 | struct descriptor descriptor; | |
61 | __le32 buffer[512]; | |
62 | dma_addr_t descriptor_bus; | |
63 | dma_addr_t buffer_bus; | |
64 | ||
65 | u32 command_ptr; | |
66 | u32 control_set; | |
67 | u32 control_clear; | |
68 | ||
69 | struct tasklet_struct tasklet; | |
70 | }; | |
71 | ||
72 | struct at_context { | |
73 | struct fw_ohci *ohci; | |
74 | dma_addr_t descriptor_bus; | |
75 | dma_addr_t buffer_bus; | |
76 | ||
77 | struct list_head list; | |
78 | ||
79 | struct { | |
80 | struct descriptor more; | |
81 | __le32 header[4]; | |
82 | struct descriptor last; | |
83 | } d; | |
84 | ||
85 | u32 command_ptr; | |
86 | u32 control_set; | |
87 | u32 control_clear; | |
88 | ||
89 | struct tasklet_struct tasklet; | |
90 | }; | |
91 | ||
92 | #define it_header_sy(v) ((v) << 0) | |
93 | #define it_header_tcode(v) ((v) << 4) | |
94 | #define it_header_channel(v) ((v) << 8) | |
95 | #define it_header_tag(v) ((v) << 14) | |
96 | #define it_header_speed(v) ((v) << 16) | |
97 | #define it_header_data_length(v) ((v) << 16) | |
98 | ||
99 | struct iso_context { | |
100 | struct fw_iso_context base; | |
101 | struct tasklet_struct tasklet; | |
102 | u32 control_set; | |
103 | u32 control_clear; | |
104 | u32 command_ptr; | |
105 | u32 context_match; | |
106 | ||
107 | struct descriptor *buffer; | |
108 | dma_addr_t buffer_bus; | |
109 | struct descriptor *head_descriptor; | |
110 | struct descriptor *tail_descriptor; | |
111 | struct descriptor *tail_descriptor_last; | |
112 | struct descriptor *prev_descriptor; | |
113 | }; | |
114 | ||
115 | #define CONFIG_ROM_SIZE 1024 | |
116 | ||
117 | struct fw_ohci { | |
118 | struct fw_card card; | |
119 | ||
120 | __iomem char *registers; | |
121 | dma_addr_t self_id_bus; | |
122 | __le32 *self_id_cpu; | |
123 | struct tasklet_struct bus_reset_tasklet; | |
124 | int generation; | |
125 | int request_generation; | |
126 | ||
127 | /* Spinlock for accessing fw_ohci data. Never call out of | |
128 | * this driver with this lock held. */ | |
129 | spinlock_t lock; | |
130 | u32 self_id_buffer[512]; | |
131 | ||
132 | /* Config rom buffers */ | |
133 | __be32 *config_rom; | |
134 | dma_addr_t config_rom_bus; | |
135 | __be32 *next_config_rom; | |
136 | dma_addr_t next_config_rom_bus; | |
137 | u32 next_header; | |
138 | ||
139 | struct ar_context ar_request_ctx; | |
140 | struct ar_context ar_response_ctx; | |
141 | struct at_context at_request_ctx; | |
142 | struct at_context at_response_ctx; | |
143 | ||
144 | u32 it_context_mask; | |
145 | struct iso_context *it_context_list; | |
146 | u32 ir_context_mask; | |
147 | struct iso_context *ir_context_list; | |
148 | }; | |
149 | ||
95688e97 | 150 | static inline struct fw_ohci *fw_ohci(struct fw_card *card) |
ed568912 KH |
151 | { |
152 | return container_of(card, struct fw_ohci, card); | |
153 | } | |
154 | ||
155 | #define CONTEXT_CYCLE_MATCH_ENABLE 0x80000000 | |
156 | ||
157 | #define CONTEXT_RUN 0x8000 | |
158 | #define CONTEXT_WAKE 0x1000 | |
159 | #define CONTEXT_DEAD 0x0800 | |
160 | #define CONTEXT_ACTIVE 0x0400 | |
161 | ||
162 | #define OHCI1394_MAX_AT_REQ_RETRIES 0x2 | |
163 | #define OHCI1394_MAX_AT_RESP_RETRIES 0x2 | |
164 | #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 | |
165 | ||
166 | #define FW_OHCI_MAJOR 240 | |
167 | #define OHCI1394_REGISTER_SIZE 0x800 | |
168 | #define OHCI_LOOP_COUNT 500 | |
169 | #define OHCI1394_PCI_HCI_Control 0x40 | |
170 | #define SELF_ID_BUF_SIZE 0x800 | |
171 | ||
ed568912 KH |
172 | static char ohci_driver_name[] = KBUILD_MODNAME; |
173 | ||
95688e97 | 174 | static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) |
ed568912 KH |
175 | { |
176 | writel(data, ohci->registers + offset); | |
177 | } | |
178 | ||
95688e97 | 179 | static inline u32 reg_read(const struct fw_ohci *ohci, int offset) |
ed568912 KH |
180 | { |
181 | return readl(ohci->registers + offset); | |
182 | } | |
183 | ||
95688e97 | 184 | static inline void flush_writes(const struct fw_ohci *ohci) |
ed568912 KH |
185 | { |
186 | /* Do a dummy read to flush writes. */ | |
187 | reg_read(ohci, OHCI1394_Version); | |
188 | } | |
189 | ||
190 | static int | |
191 | ohci_update_phy_reg(struct fw_card *card, int addr, | |
192 | int clear_bits, int set_bits) | |
193 | { | |
194 | struct fw_ohci *ohci = fw_ohci(card); | |
195 | u32 val, old; | |
196 | ||
197 | reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); | |
198 | msleep(2); | |
199 | val = reg_read(ohci, OHCI1394_PhyControl); | |
200 | if ((val & OHCI1394_PhyControl_ReadDone) == 0) { | |
201 | fw_error("failed to set phy reg bits.\n"); | |
202 | return -EBUSY; | |
203 | } | |
204 | ||
205 | old = OHCI1394_PhyControl_ReadData(val); | |
206 | old = (old & ~clear_bits) | set_bits; | |
207 | reg_write(ohci, OHCI1394_PhyControl, | |
208 | OHCI1394_PhyControl_Write(addr, old)); | |
209 | ||
210 | return 0; | |
211 | } | |
212 | ||
213 | static void ar_context_run(struct ar_context *ctx) | |
214 | { | |
215 | reg_write(ctx->ohci, ctx->command_ptr, ctx->descriptor_bus | 1); | |
216 | reg_write(ctx->ohci, ctx->control_set, CONTEXT_RUN); | |
217 | flush_writes(ctx->ohci); | |
218 | } | |
219 | ||
220 | static void ar_context_tasklet(unsigned long data) | |
221 | { | |
222 | struct ar_context *ctx = (struct ar_context *)data; | |
223 | struct fw_ohci *ohci = ctx->ohci; | |
224 | u32 status; | |
225 | int length, speed, ack, timestamp, tcode; | |
226 | ||
227 | /* FIXME: What to do about evt_* errors? */ | |
228 | length = le16_to_cpu(ctx->descriptor.req_count) - | |
229 | le16_to_cpu(ctx->descriptor.res_count) - 4; | |
230 | status = le32_to_cpu(ctx->buffer[length / 4]); | |
231 | ack = ((status >> 16) & 0x1f) - 16; | |
232 | speed = (status >> 21) & 0x7; | |
233 | timestamp = status & 0xffff; | |
234 | ||
235 | ctx->buffer[0] = le32_to_cpu(ctx->buffer[0]); | |
236 | ctx->buffer[1] = le32_to_cpu(ctx->buffer[1]); | |
237 | ctx->buffer[2] = le32_to_cpu(ctx->buffer[2]); | |
238 | ||
239 | tcode = (ctx->buffer[0] >> 4) & 0x0f; | |
240 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
241 | ctx->buffer[3] = le32_to_cpu(ctx->buffer[3]); | |
242 | ||
243 | /* The OHCI bus reset handler synthesizes a phy packet with | |
244 | * the new generation number when a bus reset happens (see | |
245 | * section 8.4.2.3). This helps us determine when a request | |
246 | * was received and make sure we send the response in the same | |
247 | * generation. We only need this for requests; for responses | |
248 | * we use the unique tlabel for finding the matching | |
249 | * request. */ | |
250 | ||
251 | if (ack + 16 == 0x09) | |
252 | ohci->request_generation = (ctx->buffer[2] >> 16) & 0xff; | |
253 | else if (ctx == &ohci->ar_request_ctx) | |
254 | fw_core_handle_request(&ohci->card, speed, ack, timestamp, | |
255 | ohci->request_generation, | |
256 | length, ctx->buffer); | |
257 | else | |
258 | fw_core_handle_response(&ohci->card, speed, ack, timestamp, | |
259 | length, ctx->buffer); | |
260 | ||
261 | ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus); | |
262 | ctx->descriptor.req_count = cpu_to_le16(sizeof ctx->buffer); | |
263 | ctx->descriptor.res_count = cpu_to_le16(sizeof ctx->buffer); | |
264 | ||
265 | dma_sync_single_for_device(ohci->card.device, ctx->descriptor_bus, | |
266 | sizeof ctx->descriptor_bus, DMA_TO_DEVICE); | |
267 | ||
268 | /* FIXME: We stop and restart the ar context here, what if we | |
269 | * stop while a receive is in progress? Maybe we could just | |
270 | * loop the context back to itself and use it in buffer fill | |
271 | * mode as intended... */ | |
272 | ||
273 | reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN); | |
274 | ar_context_run(ctx); | |
275 | } | |
276 | ||
277 | static int | |
278 | ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 control_set) | |
279 | { | |
280 | ctx->descriptor_bus = | |
281 | dma_map_single(ohci->card.device, &ctx->descriptor, | |
282 | sizeof ctx->descriptor, DMA_TO_DEVICE); | |
283 | if (ctx->descriptor_bus == 0) | |
284 | return -ENOMEM; | |
285 | ||
286 | if (ctx->descriptor_bus & 0xf) | |
fcf7770a AM |
287 | fw_notify("descriptor not 16-byte aligned: 0x%08lx\n", |
288 | (unsigned long)ctx->descriptor_bus); | |
ed568912 KH |
289 | |
290 | ctx->buffer_bus = | |
291 | dma_map_single(ohci->card.device, ctx->buffer, | |
292 | sizeof ctx->buffer, DMA_FROM_DEVICE); | |
293 | ||
294 | if (ctx->buffer_bus == 0) { | |
295 | dma_unmap_single(ohci->card.device, ctx->descriptor_bus, | |
296 | sizeof ctx->descriptor, DMA_TO_DEVICE); | |
297 | return -ENOMEM; | |
298 | } | |
299 | ||
300 | memset(&ctx->descriptor, 0, sizeof ctx->descriptor); | |
301 | ctx->descriptor.control = cpu_to_le16(descriptor_input_more | | |
302 | descriptor_status | | |
303 | descriptor_branch_always); | |
304 | ctx->descriptor.req_count = cpu_to_le16(sizeof ctx->buffer); | |
305 | ctx->descriptor.data_address = cpu_to_le32(ctx->buffer_bus); | |
306 | ctx->descriptor.res_count = cpu_to_le16(sizeof ctx->buffer); | |
307 | ||
308 | ctx->control_set = control_set; | |
309 | ctx->control_clear = control_set + 4; | |
310 | ctx->command_ptr = control_set + 12; | |
311 | ctx->ohci = ohci; | |
312 | ||
313 | tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx); | |
314 | ||
315 | ar_context_run(ctx); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static void | |
321 | do_packet_callbacks(struct fw_ohci *ohci, struct list_head *list) | |
322 | { | |
323 | struct fw_packet *p, *next; | |
324 | ||
325 | list_for_each_entry_safe(p, next, list, link) | |
326 | p->callback(p, &ohci->card, p->status); | |
327 | } | |
328 | ||
329 | static void | |
330 | complete_transmission(struct fw_packet *packet, | |
331 | int status, struct list_head *list) | |
332 | { | |
333 | list_move_tail(&packet->link, list); | |
334 | packet->status = status; | |
335 | } | |
336 | ||
337 | /* This function prepares the first packet in the context queue for | |
338 | * transmission. Must always be called with the ochi->lock held to | |
339 | * ensure proper generation handling and locking around packet queue | |
340 | * manipulation. */ | |
341 | static void | |
342 | at_context_setup_packet(struct at_context *ctx, struct list_head *list) | |
343 | { | |
344 | struct fw_packet *packet; | |
345 | struct fw_ohci *ohci = ctx->ohci; | |
346 | int z, tcode; | |
347 | ||
348 | packet = fw_packet(ctx->list.next); | |
349 | ||
350 | memset(&ctx->d, 0, sizeof ctx->d); | |
351 | if (packet->payload_length > 0) { | |
352 | packet->payload_bus = dma_map_single(ohci->card.device, | |
353 | packet->payload, | |
354 | packet->payload_length, | |
355 | DMA_TO_DEVICE); | |
356 | if (packet->payload_bus == 0) { | |
357 | complete_transmission(packet, -ENOMEM, list); | |
358 | return; | |
359 | } | |
360 | ||
361 | ctx->d.more.control = | |
362 | cpu_to_le16(descriptor_output_more | | |
363 | descriptor_key_immediate); | |
364 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
365 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
366 | ctx->d.last.control = | |
367 | cpu_to_le16(descriptor_output_last | | |
368 | descriptor_irq_always | | |
369 | descriptor_branch_always); | |
370 | ctx->d.last.req_count = cpu_to_le16(packet->payload_length); | |
371 | ctx->d.last.data_address = cpu_to_le32(packet->payload_bus); | |
372 | z = 3; | |
373 | } else { | |
374 | ctx->d.more.control = | |
375 | cpu_to_le16(descriptor_output_last | | |
376 | descriptor_key_immediate | | |
377 | descriptor_irq_always | | |
378 | descriptor_branch_always); | |
379 | ctx->d.more.req_count = cpu_to_le16(packet->header_length); | |
380 | ctx->d.more.res_count = cpu_to_le16(packet->timestamp); | |
381 | z = 2; | |
382 | } | |
383 | ||
384 | /* The DMA format for asyncronous link packets is different | |
385 | * from the IEEE1394 layout, so shift the fields around | |
386 | * accordingly. If header_length is 8, it's a PHY packet, to | |
387 | * which we need to prepend an extra quadlet. */ | |
388 | if (packet->header_length > 8) { | |
389 | ctx->d.header[0] = cpu_to_le32((packet->header[0] & 0xffff) | | |
390 | (packet->speed << 16)); | |
391 | ctx->d.header[1] = cpu_to_le32((packet->header[1] & 0xffff) | | |
392 | (packet->header[0] & 0xffff0000)); | |
393 | ctx->d.header[2] = cpu_to_le32(packet->header[2]); | |
394 | ||
395 | tcode = (packet->header[0] >> 4) & 0x0f; | |
396 | if (TCODE_IS_BLOCK_PACKET(tcode)) | |
397 | ctx->d.header[3] = cpu_to_le32(packet->header[3]); | |
398 | else | |
399 | ctx->d.header[3] = packet->header[3]; | |
400 | } else { | |
401 | ctx->d.header[0] = | |
402 | cpu_to_le32((OHCI1394_phy_tcode << 4) | | |
403 | (packet->speed << 16)); | |
404 | ctx->d.header[1] = cpu_to_le32(packet->header[0]); | |
405 | ctx->d.header[2] = cpu_to_le32(packet->header[1]); | |
406 | ctx->d.more.req_count = cpu_to_le16(12); | |
407 | } | |
408 | ||
409 | /* FIXME: Document how the locking works. */ | |
410 | if (ohci->generation == packet->generation) { | |
411 | reg_write(ctx->ohci, ctx->command_ptr, | |
412 | ctx->descriptor_bus | z); | |
413 | reg_write(ctx->ohci, ctx->control_set, | |
414 | CONTEXT_RUN | CONTEXT_WAKE); | |
415 | } else { | |
416 | /* We dont return error codes from this function; all | |
417 | * transmission errors are reported through the | |
418 | * callback. */ | |
419 | complete_transmission(packet, -ESTALE, list); | |
420 | } | |
421 | } | |
422 | ||
423 | static void at_context_stop(struct at_context *ctx) | |
424 | { | |
425 | u32 reg; | |
426 | ||
427 | reg_write(ctx->ohci, ctx->control_clear, CONTEXT_RUN); | |
428 | ||
429 | reg = reg_read(ctx->ohci, ctx->control_set); | |
430 | if (reg & CONTEXT_ACTIVE) | |
431 | fw_notify("Tried to stop context, but it is still active " | |
432 | "(0x%08x).\n", reg); | |
433 | } | |
434 | ||
435 | static void at_context_tasklet(unsigned long data) | |
436 | { | |
437 | struct at_context *ctx = (struct at_context *)data; | |
438 | struct fw_ohci *ohci = ctx->ohci; | |
439 | struct fw_packet *packet; | |
440 | LIST_HEAD(list); | |
441 | unsigned long flags; | |
442 | int evt; | |
443 | ||
444 | spin_lock_irqsave(&ohci->lock, flags); | |
445 | ||
446 | packet = fw_packet(ctx->list.next); | |
447 | ||
448 | at_context_stop(ctx); | |
449 | ||
450 | if (packet->payload_length > 0) { | |
451 | dma_unmap_single(ohci->card.device, packet->payload_bus, | |
452 | packet->payload_length, DMA_TO_DEVICE); | |
453 | evt = le16_to_cpu(ctx->d.last.transfer_status) & 0x1f; | |
454 | packet->timestamp = le16_to_cpu(ctx->d.last.res_count); | |
455 | } | |
456 | else { | |
457 | evt = le16_to_cpu(ctx->d.more.transfer_status) & 0x1f; | |
458 | packet->timestamp = le16_to_cpu(ctx->d.more.res_count); | |
459 | } | |
460 | ||
461 | if (evt < 16) { | |
462 | switch (evt) { | |
463 | case OHCI1394_evt_timeout: | |
464 | /* Async response transmit timed out. */ | |
465 | complete_transmission(packet, -ETIMEDOUT, &list); | |
466 | break; | |
467 | ||
468 | case OHCI1394_evt_flushed: | |
469 | /* The packet was flushed should give same | |
470 | * error as when we try to use a stale | |
471 | * generation count. */ | |
472 | complete_transmission(packet, -ESTALE, &list); | |
473 | break; | |
474 | ||
475 | case OHCI1394_evt_missing_ack: | |
476 | /* This would be a higher level software | |
477 | * error, it is using a valid (current) | |
478 | * generation count, but the node is not on | |
479 | * the bus. */ | |
480 | complete_transmission(packet, -ENODEV, &list); | |
481 | break; | |
482 | ||
483 | default: | |
484 | complete_transmission(packet, -EIO, &list); | |
485 | break; | |
486 | } | |
487 | } else | |
488 | complete_transmission(packet, evt - 16, &list); | |
489 | ||
490 | /* If more packets are queued, set up the next one. */ | |
491 | if (!list_empty(&ctx->list)) | |
492 | at_context_setup_packet(ctx, &list); | |
493 | ||
494 | spin_unlock_irqrestore(&ohci->lock, flags); | |
495 | ||
496 | do_packet_callbacks(ohci, &list); | |
497 | } | |
498 | ||
499 | static int | |
500 | at_context_init(struct at_context *ctx, struct fw_ohci *ohci, u32 control_set) | |
501 | { | |
502 | INIT_LIST_HEAD(&ctx->list); | |
503 | ||
504 | ctx->descriptor_bus = | |
505 | dma_map_single(ohci->card.device, &ctx->d, | |
506 | sizeof ctx->d, DMA_TO_DEVICE); | |
507 | if (ctx->descriptor_bus == 0) | |
508 | return -ENOMEM; | |
509 | ||
510 | ctx->control_set = control_set; | |
511 | ctx->control_clear = control_set + 4; | |
512 | ctx->command_ptr = control_set + 12; | |
513 | ctx->ohci = ohci; | |
514 | ||
515 | tasklet_init(&ctx->tasklet, at_context_tasklet, (unsigned long)ctx); | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
520 | static void | |
521 | at_context_transmit(struct at_context *ctx, struct fw_packet *packet) | |
522 | { | |
523 | LIST_HEAD(list); | |
524 | unsigned long flags; | |
525 | int was_empty; | |
526 | ||
527 | spin_lock_irqsave(&ctx->ohci->lock, flags); | |
528 | ||
529 | was_empty = list_empty(&ctx->list); | |
530 | list_add_tail(&packet->link, &ctx->list); | |
531 | if (was_empty) | |
532 | at_context_setup_packet(ctx, &list); | |
533 | ||
534 | spin_unlock_irqrestore(&ctx->ohci->lock, flags); | |
535 | ||
536 | do_packet_callbacks(ctx->ohci, &list); | |
537 | } | |
538 | ||
539 | static void bus_reset_tasklet(unsigned long data) | |
540 | { | |
541 | struct fw_ohci *ohci = (struct fw_ohci *)data; | |
542 | int self_id_count, i, j, reg, node_id; | |
543 | int generation, new_generation; | |
544 | unsigned long flags; | |
545 | ||
546 | reg = reg_read(ohci, OHCI1394_NodeID); | |
547 | if (!(reg & OHCI1394_NodeID_idValid)) { | |
548 | fw_error("node ID not valid, new bus reset in progress\n"); | |
549 | return; | |
550 | } | |
551 | node_id = reg & 0xffff; | |
552 | ||
553 | /* The count in the SelfIDCount register is the number of | |
554 | * bytes in the self ID receive buffer. Since we also receive | |
555 | * the inverted quadlets and a header quadlet, we shift one | |
556 | * bit extra to get the actual number of self IDs. */ | |
557 | ||
558 | self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff; | |
559 | generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff; | |
560 | ||
561 | for (i = 1, j = 0; j < self_id_count; i += 2, j++) { | |
562 | if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) | |
563 | fw_error("inconsistent self IDs\n"); | |
564 | ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]); | |
565 | } | |
566 | ||
567 | /* Check the consistency of the self IDs we just read. The | |
568 | * problem we face is that a new bus reset can start while we | |
569 | * read out the self IDs from the DMA buffer. If this happens, | |
570 | * the DMA buffer will be overwritten with new self IDs and we | |
571 | * will read out inconsistent data. The OHCI specification | |
572 | * (section 11.2) recommends a technique similar to | |
573 | * linux/seqlock.h, where we remember the generation of the | |
574 | * self IDs in the buffer before reading them out and compare | |
575 | * it to the current generation after reading them out. If | |
576 | * the two generations match we know we have a consistent set | |
577 | * of self IDs. */ | |
578 | ||
579 | new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff; | |
580 | if (new_generation != generation) { | |
581 | fw_notify("recursive bus reset detected, " | |
582 | "discarding self ids\n"); | |
583 | return; | |
584 | } | |
585 | ||
586 | /* FIXME: Document how the locking works. */ | |
587 | spin_lock_irqsave(&ohci->lock, flags); | |
588 | ||
589 | ohci->generation = generation; | |
590 | at_context_stop(&ohci->at_request_ctx); | |
591 | at_context_stop(&ohci->at_response_ctx); | |
592 | reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset); | |
593 | ||
594 | /* This next bit is unrelated to the AT context stuff but we | |
595 | * have to do it under the spinlock also. If a new config rom | |
596 | * was set up before this reset, the old one is now no longer | |
597 | * in use and we can free it. Update the config rom pointers | |
598 | * to point to the current config rom and clear the | |
599 | * next_config_rom pointer so a new udpate can take place. */ | |
600 | ||
601 | if (ohci->next_config_rom != NULL) { | |
602 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
603 | ohci->config_rom, ohci->config_rom_bus); | |
604 | ohci->config_rom = ohci->next_config_rom; | |
605 | ohci->config_rom_bus = ohci->next_config_rom_bus; | |
606 | ohci->next_config_rom = NULL; | |
607 | ||
608 | /* Restore config_rom image and manually update | |
609 | * config_rom registers. Writing the header quadlet | |
610 | * will indicate that the config rom is ready, so we | |
611 | * do that last. */ | |
612 | reg_write(ohci, OHCI1394_BusOptions, | |
613 | be32_to_cpu(ohci->config_rom[2])); | |
614 | ohci->config_rom[0] = cpu_to_be32(ohci->next_header); | |
615 | reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header); | |
616 | } | |
617 | ||
618 | spin_unlock_irqrestore(&ohci->lock, flags); | |
619 | ||
620 | fw_core_handle_bus_reset(&ohci->card, node_id, generation, | |
621 | self_id_count, ohci->self_id_buffer); | |
622 | } | |
623 | ||
624 | static irqreturn_t irq_handler(int irq, void *data) | |
625 | { | |
626 | struct fw_ohci *ohci = data; | |
627 | u32 event, iso_event; | |
628 | int i; | |
629 | ||
630 | event = reg_read(ohci, OHCI1394_IntEventClear); | |
631 | ||
632 | if (!event) | |
633 | return IRQ_NONE; | |
634 | ||
635 | reg_write(ohci, OHCI1394_IntEventClear, event); | |
636 | ||
637 | if (event & OHCI1394_selfIDComplete) | |
638 | tasklet_schedule(&ohci->bus_reset_tasklet); | |
639 | ||
640 | if (event & OHCI1394_RQPkt) | |
641 | tasklet_schedule(&ohci->ar_request_ctx.tasklet); | |
642 | ||
643 | if (event & OHCI1394_RSPkt) | |
644 | tasklet_schedule(&ohci->ar_response_ctx.tasklet); | |
645 | ||
646 | if (event & OHCI1394_reqTxComplete) | |
647 | tasklet_schedule(&ohci->at_request_ctx.tasklet); | |
648 | ||
649 | if (event & OHCI1394_respTxComplete) | |
650 | tasklet_schedule(&ohci->at_response_ctx.tasklet); | |
651 | ||
652 | iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventSet); | |
653 | reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event); | |
654 | ||
655 | while (iso_event) { | |
656 | i = ffs(iso_event) - 1; | |
657 | tasklet_schedule(&ohci->ir_context_list[i].tasklet); | |
658 | iso_event &= ~(1 << i); | |
659 | } | |
660 | ||
661 | iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventSet); | |
662 | reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event); | |
663 | ||
664 | while (iso_event) { | |
665 | i = ffs(iso_event) - 1; | |
666 | tasklet_schedule(&ohci->it_context_list[i].tasklet); | |
667 | iso_event &= ~(1 << i); | |
668 | } | |
669 | ||
670 | return IRQ_HANDLED; | |
671 | } | |
672 | ||
673 | static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length) | |
674 | { | |
675 | struct fw_ohci *ohci = fw_ohci(card); | |
676 | struct pci_dev *dev = to_pci_dev(card->device); | |
677 | ||
678 | /* When the link is not yet enabled, the atomic config rom | |
679 | * update mechanism described below in ohci_set_config_rom() | |
680 | * is not active. We have to update ConfigRomHeader and | |
681 | * BusOptions manually, and the write to ConfigROMmap takes | |
682 | * effect immediately. We tie this to the enabling of the | |
683 | * link, so we have a valid config rom before enabling - the | |
684 | * OHCI requires that ConfigROMhdr and BusOptions have valid | |
685 | * values before enabling. | |
686 | * | |
687 | * However, when the ConfigROMmap is written, some controllers | |
688 | * always read back quadlets 0 and 2 from the config rom to | |
689 | * the ConfigRomHeader and BusOptions registers on bus reset. | |
690 | * They shouldn't do that in this initial case where the link | |
691 | * isn't enabled. This means we have to use the same | |
692 | * workaround here, setting the bus header to 0 and then write | |
693 | * the right values in the bus reset tasklet. | |
694 | */ | |
695 | ||
696 | ohci->next_config_rom = | |
697 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
698 | &ohci->next_config_rom_bus, GFP_KERNEL); | |
699 | if (ohci->next_config_rom == NULL) | |
700 | return -ENOMEM; | |
701 | ||
702 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
703 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4); | |
704 | ||
705 | ohci->next_header = config_rom[0]; | |
706 | ohci->next_config_rom[0] = 0; | |
707 | reg_write(ohci, OHCI1394_ConfigROMhdr, 0); | |
708 | reg_write(ohci, OHCI1394_BusOptions, config_rom[2]); | |
709 | reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus); | |
710 | ||
711 | reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000); | |
712 | ||
713 | if (request_irq(dev->irq, irq_handler, | |
714 | SA_SHIRQ, ohci_driver_name, ohci)) { | |
715 | fw_error("Failed to allocate shared interrupt %d.\n", | |
716 | dev->irq); | |
717 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
718 | ohci->config_rom, ohci->config_rom_bus); | |
719 | return -EIO; | |
720 | } | |
721 | ||
722 | reg_write(ohci, OHCI1394_HCControlSet, | |
723 | OHCI1394_HCControl_linkEnable | | |
724 | OHCI1394_HCControl_BIBimageValid); | |
725 | flush_writes(ohci); | |
726 | ||
727 | /* We are ready to go, initiate bus reset to finish the | |
728 | * initialization. */ | |
729 | ||
730 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
731 | ||
732 | return 0; | |
733 | } | |
734 | ||
735 | static int | |
736 | ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length) | |
737 | { | |
738 | struct fw_ohci *ohci; | |
739 | unsigned long flags; | |
740 | int retval = 0; | |
741 | __be32 *next_config_rom; | |
742 | dma_addr_t next_config_rom_bus; | |
743 | ||
744 | ohci = fw_ohci(card); | |
745 | ||
746 | /* When the OHCI controller is enabled, the config rom update | |
747 | * mechanism is a bit tricky, but easy enough to use. See | |
748 | * section 5.5.6 in the OHCI specification. | |
749 | * | |
750 | * The OHCI controller caches the new config rom address in a | |
751 | * shadow register (ConfigROMmapNext) and needs a bus reset | |
752 | * for the changes to take place. When the bus reset is | |
753 | * detected, the controller loads the new values for the | |
754 | * ConfigRomHeader and BusOptions registers from the specified | |
755 | * config rom and loads ConfigROMmap from the ConfigROMmapNext | |
756 | * shadow register. All automatically and atomically. | |
757 | * | |
758 | * Now, there's a twist to this story. The automatic load of | |
759 | * ConfigRomHeader and BusOptions doesn't honor the | |
760 | * noByteSwapData bit, so with a be32 config rom, the | |
761 | * controller will load be32 values in to these registers | |
762 | * during the atomic update, even on litte endian | |
763 | * architectures. The workaround we use is to put a 0 in the | |
764 | * header quadlet; 0 is endian agnostic and means that the | |
765 | * config rom isn't ready yet. In the bus reset tasklet we | |
766 | * then set up the real values for the two registers. | |
767 | * | |
768 | * We use ohci->lock to avoid racing with the code that sets | |
769 | * ohci->next_config_rom to NULL (see bus_reset_tasklet). | |
770 | */ | |
771 | ||
772 | next_config_rom = | |
773 | dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
774 | &next_config_rom_bus, GFP_KERNEL); | |
775 | if (next_config_rom == NULL) | |
776 | return -ENOMEM; | |
777 | ||
778 | spin_lock_irqsave(&ohci->lock, flags); | |
779 | ||
780 | if (ohci->next_config_rom == NULL) { | |
781 | ohci->next_config_rom = next_config_rom; | |
782 | ohci->next_config_rom_bus = next_config_rom_bus; | |
783 | ||
784 | memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE); | |
785 | fw_memcpy_to_be32(ohci->next_config_rom, config_rom, | |
786 | length * 4); | |
787 | ||
788 | ohci->next_header = config_rom[0]; | |
789 | ohci->next_config_rom[0] = 0; | |
790 | ||
791 | reg_write(ohci, OHCI1394_ConfigROMmap, | |
792 | ohci->next_config_rom_bus); | |
793 | } else { | |
794 | dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE, | |
795 | next_config_rom, next_config_rom_bus); | |
796 | retval = -EBUSY; | |
797 | } | |
798 | ||
799 | spin_unlock_irqrestore(&ohci->lock, flags); | |
800 | ||
801 | /* Now initiate a bus reset to have the changes take | |
802 | * effect. We clean up the old config rom memory and DMA | |
803 | * mappings in the bus reset tasklet, since the OHCI | |
804 | * controller could need to access it before the bus reset | |
805 | * takes effect. */ | |
806 | if (retval == 0) | |
807 | fw_core_initiate_bus_reset(&ohci->card, 1); | |
808 | ||
809 | return retval; | |
810 | } | |
811 | ||
812 | static void ohci_send_request(struct fw_card *card, struct fw_packet *packet) | |
813 | { | |
814 | struct fw_ohci *ohci = fw_ohci(card); | |
815 | ||
816 | at_context_transmit(&ohci->at_request_ctx, packet); | |
817 | } | |
818 | ||
819 | static void ohci_send_response(struct fw_card *card, struct fw_packet *packet) | |
820 | { | |
821 | struct fw_ohci *ohci = fw_ohci(card); | |
822 | ||
823 | at_context_transmit(&ohci->at_response_ctx, packet); | |
824 | } | |
825 | ||
826 | static int | |
827 | ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation) | |
828 | { | |
829 | struct fw_ohci *ohci = fw_ohci(card); | |
830 | unsigned long flags; | |
831 | int retval = 0; | |
832 | ||
833 | /* FIXME: make sure this bitmask is cleared when we clear the | |
834 | * busReset interrupt bit. */ | |
835 | ||
836 | spin_lock_irqsave(&ohci->lock, flags); | |
837 | ||
838 | if (ohci->generation != generation) { | |
839 | retval = -ESTALE; | |
840 | goto out; | |
841 | } | |
842 | ||
843 | if (node_id < 32) { | |
844 | reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << node_id); | |
845 | } else { | |
846 | reg_write(ohci, OHCI1394_PhyReqFilterHiSet, | |
847 | 1 << (node_id - 32)); | |
848 | } | |
849 | flush_writes(ohci); | |
ed568912 | 850 | out: |
6cad95fe | 851 | spin_unlock_irqrestore(&ohci->lock, flags); |
ed568912 KH |
852 | return retval; |
853 | } | |
854 | ||
855 | static void ir_context_tasklet(unsigned long data) | |
856 | { | |
857 | struct iso_context *ctx = (struct iso_context *)data; | |
858 | ||
859 | (void)ctx; | |
860 | } | |
861 | ||
862 | #define ISO_BUFFER_SIZE (64 * 1024) | |
863 | ||
864 | static void flush_iso_context(struct iso_context *ctx) | |
865 | { | |
866 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
867 | struct descriptor *d, *last; | |
868 | u32 address; | |
869 | int z; | |
870 | ||
871 | dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus, | |
872 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
873 | ||
874 | d = ctx->tail_descriptor; | |
875 | last = ctx->tail_descriptor_last; | |
876 | ||
877 | while (last->branch_address != 0 && last->transfer_status != 0) { | |
878 | address = le32_to_cpu(last->branch_address); | |
879 | z = address & 0xf; | |
880 | d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d; | |
881 | ||
882 | if (z == 2) | |
883 | last = d; | |
884 | else | |
885 | last = d + z - 1; | |
886 | ||
887 | if (le16_to_cpu(last->control) & descriptor_irq_always) | |
888 | ctx->base.callback(&ctx->base, | |
889 | 0, le16_to_cpu(last->res_count), | |
890 | ctx->base.callback_data); | |
891 | } | |
892 | ||
893 | ctx->tail_descriptor = d; | |
894 | ctx->tail_descriptor_last = last; | |
895 | } | |
896 | ||
897 | static void it_context_tasklet(unsigned long data) | |
898 | { | |
899 | struct iso_context *ctx = (struct iso_context *)data; | |
900 | ||
901 | flush_iso_context(ctx); | |
902 | } | |
903 | ||
904 | static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, | |
905 | int type) | |
906 | { | |
907 | struct fw_ohci *ohci = fw_ohci(card); | |
908 | struct iso_context *ctx, *list; | |
909 | void (*tasklet) (unsigned long data); | |
910 | u32 *mask; | |
911 | unsigned long flags; | |
912 | int index; | |
913 | ||
914 | if (type == FW_ISO_CONTEXT_TRANSMIT) { | |
915 | mask = &ohci->it_context_mask; | |
916 | list = ohci->it_context_list; | |
917 | tasklet = it_context_tasklet; | |
918 | } else { | |
919 | mask = &ohci->ir_context_mask; | |
920 | list = ohci->ir_context_list; | |
921 | tasklet = ir_context_tasklet; | |
922 | } | |
923 | ||
924 | spin_lock_irqsave(&ohci->lock, flags); | |
925 | index = ffs(*mask) - 1; | |
926 | if (index >= 0) | |
927 | *mask &= ~(1 << index); | |
928 | spin_unlock_irqrestore(&ohci->lock, flags); | |
929 | ||
930 | if (index < 0) | |
931 | return ERR_PTR(-EBUSY); | |
932 | ||
933 | ctx = &list[index]; | |
934 | memset(ctx, 0, sizeof *ctx); | |
935 | tasklet_init(&ctx->tasklet, tasklet, (unsigned long)ctx); | |
936 | ||
937 | ctx->buffer = kmalloc(ISO_BUFFER_SIZE, GFP_KERNEL); | |
938 | if (ctx->buffer == NULL) { | |
939 | spin_lock_irqsave(&ohci->lock, flags); | |
940 | *mask |= 1 << index; | |
941 | spin_unlock_irqrestore(&ohci->lock, flags); | |
942 | return ERR_PTR(-ENOMEM); | |
943 | } | |
944 | ||
945 | ctx->buffer_bus = | |
946 | dma_map_single(card->device, ctx->buffer, | |
947 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
948 | ||
949 | ctx->head_descriptor = ctx->buffer; | |
950 | ctx->prev_descriptor = ctx->buffer; | |
951 | ctx->tail_descriptor = ctx->buffer; | |
952 | ctx->tail_descriptor_last = ctx->buffer; | |
953 | ||
954 | /* We put a dummy descriptor in the buffer that has a NULL | |
955 | * branch address and looks like it's been sent. That way we | |
956 | * have a descriptor to append DMA programs to. Also, the | |
957 | * ring buffer invariant is that it always has at least one | |
958 | * element so that head == tail means buffer full. */ | |
959 | ||
960 | memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor); | |
5e20c282 SR |
961 | ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last); |
962 | ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011); | |
ed568912 KH |
963 | ctx->head_descriptor++; |
964 | ||
965 | return &ctx->base; | |
966 | } | |
967 | ||
968 | static int ohci_send_iso(struct fw_iso_context *base, s32 cycle) | |
969 | { | |
970 | struct iso_context *ctx = (struct iso_context *)base; | |
971 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
972 | u32 cycle_match = 0; | |
973 | int index; | |
974 | ||
975 | index = ctx - ohci->it_context_list; | |
976 | if (cycle > 0) | |
977 | cycle_match = CONTEXT_CYCLE_MATCH_ENABLE | | |
978 | (cycle & 0x7fff) << 16; | |
979 | ||
980 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index); | |
981 | reg_write(ohci, OHCI1394_IsoXmitCommandPtr(index), | |
982 | le32_to_cpu(ctx->tail_descriptor_last->branch_address)); | |
983 | reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0); | |
984 | reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), | |
985 | CONTEXT_RUN | cycle_match); | |
986 | flush_writes(ohci); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static void ohci_free_iso_context(struct fw_iso_context *base) | |
992 | { | |
993 | struct fw_ohci *ohci = fw_ohci(base->card); | |
994 | struct iso_context *ctx = (struct iso_context *)base; | |
995 | unsigned long flags; | |
996 | int index; | |
997 | ||
998 | flush_iso_context(ctx); | |
999 | ||
1000 | spin_lock_irqsave(&ohci->lock, flags); | |
1001 | ||
1002 | if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) { | |
1003 | index = ctx - ohci->it_context_list; | |
1004 | reg_write(ohci, OHCI1394_IsoXmitContextControlClear(index), ~0); | |
1005 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index); | |
1006 | ohci->it_context_mask |= 1 << index; | |
1007 | } else { | |
1008 | index = ctx - ohci->ir_context_list; | |
1009 | reg_write(ohci, OHCI1394_IsoRcvContextControlClear(index), ~0); | |
1010 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index); | |
1011 | ohci->ir_context_mask |= 1 << index; | |
1012 | } | |
1013 | flush_writes(ohci); | |
1014 | ||
1015 | dma_unmap_single(ohci->card.device, ctx->buffer_bus, | |
1016 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1017 | ||
1018 | spin_unlock_irqrestore(&ohci->lock, flags); | |
1019 | } | |
1020 | ||
1021 | static int | |
1022 | ohci_queue_iso(struct fw_iso_context *base, | |
1023 | struct fw_iso_packet *packet, void *payload) | |
1024 | { | |
1025 | struct iso_context *ctx = (struct iso_context *)base; | |
1026 | struct fw_ohci *ohci = fw_ohci(ctx->base.card); | |
1027 | struct descriptor *d, *end, *last, *tail, *pd; | |
1028 | struct fw_iso_packet *p; | |
1029 | __le32 *header; | |
1030 | dma_addr_t d_bus; | |
1031 | u32 z, header_z, payload_z, irq; | |
1032 | u32 payload_index, payload_end_index, next_page_index; | |
1033 | int index, page, end_page, i, length, offset; | |
1034 | ||
1035 | /* FIXME: Cycle lost behavior should be configurable: lose | |
1036 | * packet, retransmit or terminate.. */ | |
1037 | ||
1038 | p = packet; | |
1039 | payload_index = payload - ctx->base.buffer; | |
1040 | d = ctx->head_descriptor; | |
1041 | tail = ctx->tail_descriptor; | |
1042 | end = ctx->buffer + ISO_BUFFER_SIZE / sizeof(struct descriptor); | |
1043 | ||
1044 | if (p->skip) | |
1045 | z = 1; | |
1046 | else | |
1047 | z = 2; | |
1048 | if (p->header_length > 0) | |
1049 | z++; | |
1050 | ||
1051 | /* Determine the first page the payload isn't contained in. */ | |
1052 | end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT; | |
1053 | if (p->payload_length > 0) | |
1054 | payload_z = end_page - (payload_index >> PAGE_SHIFT); | |
1055 | else | |
1056 | payload_z = 0; | |
1057 | ||
1058 | z += payload_z; | |
1059 | ||
1060 | /* Get header size in number of descriptors. */ | |
1061 | header_z = DIV_ROUND_UP(p->header_length, sizeof *d); | |
1062 | ||
1063 | if (d + z + header_z <= tail) { | |
1064 | goto has_space; | |
1065 | } else if (d > tail && d + z + header_z <= end) { | |
1066 | goto has_space; | |
1067 | } else if (d > tail && ctx->buffer + z + header_z <= tail) { | |
1068 | d = ctx->buffer; | |
1069 | goto has_space; | |
1070 | } | |
1071 | ||
1072 | /* No space in buffer */ | |
1073 | return -1; | |
1074 | ||
1075 | has_space: | |
1076 | memset(d, 0, (z + header_z) * sizeof *d); | |
1077 | d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d; | |
1078 | ||
1079 | if (!p->skip) { | |
1080 | d[0].control = cpu_to_le16(descriptor_key_immediate); | |
1081 | d[0].req_count = cpu_to_le16(8); | |
1082 | ||
1083 | header = (__le32 *) &d[1]; | |
1084 | header[0] = cpu_to_le32(it_header_sy(p->sy) | | |
1085 | it_header_tag(p->tag) | | |
1086 | it_header_tcode(TCODE_STREAM_DATA) | | |
1087 | it_header_channel(ctx->base.channel) | | |
1088 | it_header_speed(ctx->base.speed)); | |
1089 | header[1] = | |
1090 | cpu_to_le32(it_header_data_length(p->header_length + | |
1091 | p->payload_length)); | |
1092 | } | |
1093 | ||
1094 | if (p->header_length > 0) { | |
1095 | d[2].req_count = cpu_to_le16(p->header_length); | |
1096 | d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d); | |
1097 | memcpy(&d[z], p->header, p->header_length); | |
1098 | } | |
1099 | ||
1100 | pd = d + z - payload_z; | |
1101 | payload_end_index = payload_index + p->payload_length; | |
1102 | for (i = 0; i < payload_z; i++) { | |
1103 | page = payload_index >> PAGE_SHIFT; | |
1104 | offset = payload_index & ~PAGE_MASK; | |
1105 | next_page_index = (page + 1) << PAGE_SHIFT; | |
1106 | length = | |
1107 | min(next_page_index, payload_end_index) - payload_index; | |
1108 | pd[i].req_count = cpu_to_le16(length); | |
1109 | pd[i].data_address = cpu_to_le32(ctx->base.pages[page] + offset); | |
1110 | ||
1111 | payload_index += length; | |
1112 | } | |
1113 | ||
1114 | if (z == 2) | |
1115 | last = d; | |
1116 | else | |
1117 | last = d + z - 1; | |
1118 | ||
1119 | if (p->interrupt) | |
1120 | irq = descriptor_irq_always; | |
1121 | else | |
1122 | irq = descriptor_no_irq; | |
1123 | ||
1124 | last->control = cpu_to_le16(descriptor_output_last | | |
1125 | descriptor_status | | |
1126 | descriptor_branch_always | | |
1127 | irq); | |
1128 | ||
1129 | dma_sync_single_for_device(ohci->card.device, ctx->buffer_bus, | |
1130 | ISO_BUFFER_SIZE, DMA_TO_DEVICE); | |
1131 | ||
1132 | ctx->head_descriptor = d + z + header_z; | |
1133 | ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z); | |
1134 | ctx->prev_descriptor = last; | |
1135 | ||
1136 | index = ctx - ohci->it_context_list; | |
1137 | reg_write(ohci, OHCI1394_IsoXmitContextControlSet(index), CONTEXT_WAKE); | |
1138 | flush_writes(ohci); | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
21ebcd12 | 1143 | static const struct fw_card_driver ohci_driver = { |
ed568912 KH |
1144 | .name = ohci_driver_name, |
1145 | .enable = ohci_enable, | |
1146 | .update_phy_reg = ohci_update_phy_reg, | |
1147 | .set_config_rom = ohci_set_config_rom, | |
1148 | .send_request = ohci_send_request, | |
1149 | .send_response = ohci_send_response, | |
1150 | .enable_phys_dma = ohci_enable_phys_dma, | |
1151 | ||
1152 | .allocate_iso_context = ohci_allocate_iso_context, | |
1153 | .free_iso_context = ohci_free_iso_context, | |
1154 | .queue_iso = ohci_queue_iso, | |
5af4e5ea | 1155 | .send_iso = ohci_send_iso, |
ed568912 KH |
1156 | }; |
1157 | ||
1158 | static int software_reset(struct fw_ohci *ohci) | |
1159 | { | |
1160 | int i; | |
1161 | ||
1162 | reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); | |
1163 | ||
1164 | for (i = 0; i < OHCI_LOOP_COUNT; i++) { | |
1165 | if ((reg_read(ohci, OHCI1394_HCControlSet) & | |
1166 | OHCI1394_HCControl_softReset) == 0) | |
1167 | return 0; | |
1168 | msleep(1); | |
1169 | } | |
1170 | ||
1171 | return -EBUSY; | |
1172 | } | |
1173 | ||
1174 | /* ---------- pci subsystem interface ---------- */ | |
1175 | ||
1176 | enum { | |
1177 | CLEANUP_SELF_ID, | |
1178 | CLEANUP_REGISTERS, | |
1179 | CLEANUP_IOMEM, | |
1180 | CLEANUP_DISABLE, | |
1181 | CLEANUP_PUT_CARD, | |
1182 | }; | |
1183 | ||
1184 | static int cleanup(struct fw_ohci *ohci, int stage, int code) | |
1185 | { | |
1186 | struct pci_dev *dev = to_pci_dev(ohci->card.device); | |
1187 | ||
1188 | switch (stage) { | |
1189 | case CLEANUP_SELF_ID: | |
1190 | dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE, | |
1191 | ohci->self_id_cpu, ohci->self_id_bus); | |
1192 | case CLEANUP_REGISTERS: | |
1193 | kfree(ohci->it_context_list); | |
1194 | kfree(ohci->ir_context_list); | |
1195 | pci_iounmap(dev, ohci->registers); | |
1196 | case CLEANUP_IOMEM: | |
1197 | pci_release_region(dev, 0); | |
1198 | case CLEANUP_DISABLE: | |
1199 | pci_disable_device(dev); | |
1200 | case CLEANUP_PUT_CARD: | |
1201 | fw_card_put(&ohci->card); | |
1202 | } | |
1203 | ||
1204 | return code; | |
1205 | } | |
1206 | ||
1207 | static int __devinit | |
1208 | pci_probe(struct pci_dev *dev, const struct pci_device_id *ent) | |
1209 | { | |
1210 | struct fw_ohci *ohci; | |
1211 | u32 bus_options, max_receive, link_speed; | |
1212 | u64 guid; | |
1213 | int error_code; | |
1214 | size_t size; | |
1215 | ||
1216 | ohci = kzalloc(sizeof *ohci, GFP_KERNEL); | |
1217 | if (ohci == NULL) { | |
1218 | fw_error("Could not malloc fw_ohci data.\n"); | |
1219 | return -ENOMEM; | |
1220 | } | |
1221 | ||
1222 | fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev); | |
1223 | ||
1224 | if (pci_enable_device(dev)) { | |
1225 | fw_error("Failed to enable OHCI hardware.\n"); | |
1226 | return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV); | |
1227 | } | |
1228 | ||
1229 | pci_set_master(dev); | |
1230 | pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0); | |
1231 | pci_set_drvdata(dev, ohci); | |
1232 | ||
1233 | spin_lock_init(&ohci->lock); | |
1234 | ||
1235 | tasklet_init(&ohci->bus_reset_tasklet, | |
1236 | bus_reset_tasklet, (unsigned long)ohci); | |
1237 | ||
1238 | if (pci_request_region(dev, 0, ohci_driver_name)) { | |
1239 | fw_error("MMIO resource unavailable\n"); | |
1240 | return cleanup(ohci, CLEANUP_DISABLE, -EBUSY); | |
1241 | } | |
1242 | ||
1243 | ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE); | |
1244 | if (ohci->registers == NULL) { | |
1245 | fw_error("Failed to remap registers\n"); | |
1246 | return cleanup(ohci, CLEANUP_IOMEM, -ENXIO); | |
1247 | } | |
1248 | ||
1249 | if (software_reset(ohci)) { | |
1250 | fw_error("Failed to reset ohci card.\n"); | |
1251 | return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY); | |
1252 | } | |
1253 | ||
1254 | /* Now enable LPS, which we need in order to start accessing | |
1255 | * most of the registers. In fact, on some cards (ALI M5251), | |
1256 | * accessing registers in the SClk domain without LPS enabled | |
1257 | * will lock up the machine. Wait 50msec to make sure we have | |
1258 | * full link enabled. */ | |
1259 | reg_write(ohci, OHCI1394_HCControlSet, | |
1260 | OHCI1394_HCControl_LPS | | |
1261 | OHCI1394_HCControl_postedWriteEnable); | |
1262 | flush_writes(ohci); | |
1263 | msleep(50); | |
1264 | ||
1265 | reg_write(ohci, OHCI1394_HCControlClear, | |
1266 | OHCI1394_HCControl_noByteSwapData); | |
1267 | ||
1268 | reg_write(ohci, OHCI1394_LinkControlSet, | |
1269 | OHCI1394_LinkControl_rcvSelfID | | |
1270 | OHCI1394_LinkControl_cycleTimerEnable | | |
1271 | OHCI1394_LinkControl_cycleMaster); | |
1272 | ||
1273 | ar_context_init(&ohci->ar_request_ctx, ohci, | |
1274 | OHCI1394_AsReqRcvContextControlSet); | |
1275 | ||
1276 | ar_context_init(&ohci->ar_response_ctx, ohci, | |
1277 | OHCI1394_AsRspRcvContextControlSet); | |
1278 | ||
1279 | at_context_init(&ohci->at_request_ctx, ohci, | |
1280 | OHCI1394_AsReqTrContextControlSet); | |
1281 | ||
1282 | at_context_init(&ohci->at_response_ctx, ohci, | |
1283 | OHCI1394_AsRspTrContextControlSet); | |
1284 | ||
1285 | reg_write(ohci, OHCI1394_ATRetries, | |
1286 | OHCI1394_MAX_AT_REQ_RETRIES | | |
1287 | (OHCI1394_MAX_AT_RESP_RETRIES << 4) | | |
1288 | (OHCI1394_MAX_PHYS_RESP_RETRIES << 8)); | |
1289 | ||
1290 | reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0); | |
1291 | ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet); | |
1292 | reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0); | |
1293 | size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask); | |
1294 | ohci->it_context_list = kzalloc(size, GFP_KERNEL); | |
1295 | ||
1296 | reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0); | |
1297 | ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet); | |
1298 | reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0); | |
1299 | size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask); | |
1300 | ohci->ir_context_list = kzalloc(size, GFP_KERNEL); | |
1301 | ||
1302 | if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) { | |
1303 | fw_error("Out of memory for it/ir contexts.\n"); | |
1304 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1305 | } | |
1306 | ||
1307 | /* self-id dma buffer allocation */ | |
1308 | ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device, | |
1309 | SELF_ID_BUF_SIZE, | |
1310 | &ohci->self_id_bus, | |
1311 | GFP_KERNEL); | |
1312 | if (ohci->self_id_cpu == NULL) { | |
1313 | fw_error("Out of memory for self ID buffer.\n"); | |
1314 | return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM); | |
1315 | } | |
1316 | ||
1317 | reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus); | |
1318 | reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000); | |
1319 | reg_write(ohci, OHCI1394_IntEventClear, ~0); | |
1320 | reg_write(ohci, OHCI1394_IntMaskClear, ~0); | |
1321 | reg_write(ohci, OHCI1394_IntMaskSet, | |
1322 | OHCI1394_selfIDComplete | | |
1323 | OHCI1394_RQPkt | OHCI1394_RSPkt | | |
1324 | OHCI1394_reqTxComplete | OHCI1394_respTxComplete | | |
1325 | OHCI1394_isochRx | OHCI1394_isochTx | | |
1326 | OHCI1394_masterIntEnable); | |
1327 | ||
1328 | bus_options = reg_read(ohci, OHCI1394_BusOptions); | |
1329 | max_receive = (bus_options >> 12) & 0xf; | |
1330 | link_speed = bus_options & 0x7; | |
1331 | guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) | | |
1332 | reg_read(ohci, OHCI1394_GUIDLo); | |
1333 | ||
1334 | error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid); | |
1335 | if (error_code < 0) | |
1336 | return cleanup(ohci, CLEANUP_SELF_ID, error_code); | |
1337 | ||
1338 | fw_notify("Added fw-ohci device %s.\n", dev->dev.bus_id); | |
1339 | ||
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | static void pci_remove(struct pci_dev *dev) | |
1344 | { | |
1345 | struct fw_ohci *ohci; | |
1346 | ||
1347 | ohci = pci_get_drvdata(dev); | |
1348 | reg_write(ohci, OHCI1394_IntMaskClear, OHCI1394_masterIntEnable); | |
1349 | fw_core_remove_card(&ohci->card); | |
1350 | ||
1351 | /* FIXME: Fail all pending packets here, now that the upper | |
1352 | * layers can't queue any more. */ | |
1353 | ||
1354 | software_reset(ohci); | |
1355 | free_irq(dev->irq, ohci); | |
1356 | cleanup(ohci, CLEANUP_SELF_ID, 0); | |
1357 | ||
1358 | fw_notify("Removed fw-ohci device.\n"); | |
1359 | } | |
1360 | ||
1361 | static struct pci_device_id pci_table[] = { | |
1362 | { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) }, | |
1363 | { } | |
1364 | }; | |
1365 | ||
1366 | MODULE_DEVICE_TABLE(pci, pci_table); | |
1367 | ||
1368 | static struct pci_driver fw_ohci_pci_driver = { | |
1369 | .name = ohci_driver_name, | |
1370 | .id_table = pci_table, | |
1371 | .probe = pci_probe, | |
1372 | .remove = pci_remove, | |
1373 | }; | |
1374 | ||
1375 | MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>"); | |
1376 | MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers"); | |
1377 | MODULE_LICENSE("GPL"); | |
1378 | ||
1379 | static int __init fw_ohci_init(void) | |
1380 | { | |
1381 | return pci_register_driver(&fw_ohci_pci_driver); | |
1382 | } | |
1383 | ||
1384 | static void __exit fw_ohci_cleanup(void) | |
1385 | { | |
1386 | pci_unregister_driver(&fw_ohci_pci_driver); | |
1387 | } | |
1388 | ||
1389 | module_init(fw_ohci_init); | |
1390 | module_exit(fw_ohci_cleanup); |