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edac i5000: fix error messages
[net-next-2.6.git] / drivers / edac / i5000_edac.c
CommitLineData
eb60705a
EW		 1/*
2 * Intel 5000(P/V/X) class Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Douglas Thompson Linux Networx (http://lnxi.com)
8 * norsk5@xmission.com
9 *
10 * This module is based on the following document:
11 *
12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://developer.intel.com/design/chipsets/datashts/313070.htm
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/pci.h>
20#include <linux/pci_ids.h>
21#include <linux/slab.h>
c0d12172 22#include <linux/edac.h>
eb60705a
EW		 23#include <asm/mmzone.h>
24
20bcb7a8 25#include "edac_core.h"
eb60705a
EW		 26
27/*
28 * Alter this version for the I5000 module when modifications are made
29 */
20bcb7a8 30#define I5000_REVISION " Ver: 2.0.12 " __DATE__
456a2f95 31#define EDAC_MOD_STR "i5000_edac"
eb60705a
EW		 32
33#define i5000_printk(level, fmt, arg...) \
34 edac_printk(level, "i5000", fmt, ##arg)
35
36#define i5000_mc_printk(mci, level, fmt, arg...) \
37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
38
39#ifndef PCI_DEVICE_ID_INTEL_FBD_0
40#define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5
41#endif
42#ifndef PCI_DEVICE_ID_INTEL_FBD_1
43#define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6
44#endif
45
46/* Device 16,
47 * Function 0: System Address
48 * Function 1: Memory Branch Map, Control, Errors Register
49 * Function 2: FSB Error Registers
50 *
51 * All 3 functions of Device 16 (0,1,2) share the SAME DID
52 */
53#define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
54
55/* OFFSETS for Function 0 */
56
57/* OFFSETS for Function 1 */
58#define AMBASE 0x48
59#define MAXCH 0x56
60#define MAXDIMMPERCH 0x57
61#define TOLM 0x6C
62#define REDMEMB 0x7C
63#define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF)
64#define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
65#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00)
66#define MIR0 0x80
67#define MIR1 0x84
68#define MIR2 0x88
69#define AMIR0 0x8C
70#define AMIR1 0x90
71#define AMIR2 0x94
72
73#define FERR_FAT_FBD 0x98
74#define NERR_FAT_FBD 0x9C
75#define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
76#define FERR_FAT_FBDCHAN 0x30000000
77#define FERR_FAT_M3ERR 0x00000004
78#define FERR_FAT_M2ERR 0x00000002
79#define FERR_FAT_M1ERR 0x00000001
052dfb45 80#define FERR_FAT_MASK (FERR_FAT_M1ERR | \
eb60705a
EW		 81 FERR_FAT_M2ERR | \
82 FERR_FAT_M3ERR)
83
84#define FERR_NF_FBD 0xA0
85
86/* Thermal and SPD or BFD errors */
87#define FERR_NF_M28ERR 0x01000000
88#define FERR_NF_M27ERR 0x00800000
89#define FERR_NF_M26ERR 0x00400000
90#define FERR_NF_M25ERR 0x00200000
91#define FERR_NF_M24ERR 0x00100000
92#define FERR_NF_M23ERR 0x00080000
93#define FERR_NF_M22ERR 0x00040000
94#define FERR_NF_M21ERR 0x00020000
95
96/* Correctable errors */
97#define FERR_NF_M20ERR 0x00010000
98#define FERR_NF_M19ERR 0x00008000
99#define FERR_NF_M18ERR 0x00004000
100#define FERR_NF_M17ERR 0x00002000
101
102/* Non-Retry or redundant Retry errors */
103#define FERR_NF_M16ERR 0x00001000
104#define FERR_NF_M15ERR 0x00000800
105#define FERR_NF_M14ERR 0x00000400
106#define FERR_NF_M13ERR 0x00000200
107
108/* Uncorrectable errors */
109#define FERR_NF_M12ERR 0x00000100
110#define FERR_NF_M11ERR 0x00000080
111#define FERR_NF_M10ERR 0x00000040
112#define FERR_NF_M9ERR 0x00000020
113#define FERR_NF_M8ERR 0x00000010
114#define FERR_NF_M7ERR 0x00000008
115#define FERR_NF_M6ERR 0x00000004
116#define FERR_NF_M5ERR 0x00000002
117#define FERR_NF_M4ERR 0x00000001
118
119#define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
120 FERR_NF_M11ERR | \
121 FERR_NF_M10ERR | \
c0667407 122 FERR_NF_M9ERR | \
052dfb45 123 FERR_NF_M8ERR | \
eb60705a
EW		 124 FERR_NF_M7ERR | \
125 FERR_NF_M6ERR | \
126 FERR_NF_M5ERR | \
127 FERR_NF_M4ERR)
128#define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
129 FERR_NF_M19ERR | \
130 FERR_NF_M18ERR | \
131 FERR_NF_M17ERR)
132#define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
133 FERR_NF_M28ERR)
134#define FERR_NF_THERMAL (FERR_NF_M26ERR | \
052dfb45 135 FERR_NF_M25ERR | \
eb60705a
EW		 136 FERR_NF_M24ERR | \
137 FERR_NF_M23ERR)
138#define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
139#define FERR_NF_NORTH_CRC (FERR_NF_M21ERR)
140#define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \
141 FERR_NF_M14ERR | \
142 FERR_NF_M15ERR)
143
144#define NERR_NF_FBD 0xA4
145#define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \
146 FERR_NF_CORRECTABLE | \
147 FERR_NF_DIMM_SPARE | \
148 FERR_NF_THERMAL | \
149 FERR_NF_SPD_PROTOCOL | \
150 FERR_NF_NORTH_CRC | \
151 FERR_NF_NON_RETRY)
152
153#define EMASK_FBD 0xA8
154#define EMASK_FBD_M28ERR 0x08000000
155#define EMASK_FBD_M27ERR 0x04000000
156#define EMASK_FBD_M26ERR 0x02000000
157#define EMASK_FBD_M25ERR 0x01000000
158#define EMASK_FBD_M24ERR 0x00800000
159#define EMASK_FBD_M23ERR 0x00400000
160#define EMASK_FBD_M22ERR 0x00200000
161#define EMASK_FBD_M21ERR 0x00100000
162#define EMASK_FBD_M20ERR 0x00080000
163#define EMASK_FBD_M19ERR 0x00040000
164#define EMASK_FBD_M18ERR 0x00020000
165#define EMASK_FBD_M17ERR 0x00010000
166
167#define EMASK_FBD_M15ERR 0x00004000
168#define EMASK_FBD_M14ERR 0x00002000
169#define EMASK_FBD_M13ERR 0x00001000
170#define EMASK_FBD_M12ERR 0x00000800
171#define EMASK_FBD_M11ERR 0x00000400
172#define EMASK_FBD_M10ERR 0x00000200
173#define EMASK_FBD_M9ERR 0x00000100
174#define EMASK_FBD_M8ERR 0x00000080
175#define EMASK_FBD_M7ERR 0x00000040
176#define EMASK_FBD_M6ERR 0x00000020
177#define EMASK_FBD_M5ERR 0x00000010
178#define EMASK_FBD_M4ERR 0x00000008
179#define EMASK_FBD_M3ERR 0x00000004
180#define EMASK_FBD_M2ERR 0x00000002
181#define EMASK_FBD_M1ERR 0x00000001
182
183#define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \
184 EMASK_FBD_M2ERR | \
185 EMASK_FBD_M3ERR)
186
187#define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \
188 EMASK_FBD_M5ERR | \
189 EMASK_FBD_M6ERR | \
190 EMASK_FBD_M7ERR | \
191 EMASK_FBD_M8ERR | \
192 EMASK_FBD_M9ERR | \
193 EMASK_FBD_M10ERR | \
194 EMASK_FBD_M11ERR | \
195 EMASK_FBD_M12ERR)
196#define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \
197 EMASK_FBD_M18ERR | \
198 EMASK_FBD_M19ERR | \
199 EMASK_FBD_M20ERR)
200#define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
201 EMASK_FBD_M28ERR)
202#define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \
203 EMASK_FBD_M25ERR | \
204 EMASK_FBD_M24ERR | \
205 EMASK_FBD_M23ERR)
206#define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR)
207#define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR)
208#define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \
209 EMASK_FBD_M14ERR | \
210 EMASK_FBD_M13ERR)
211
212#define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \
213 ENABLE_EMASK_FBD_NORTH_CRC | \
214 ENABLE_EMASK_FBD_SPD_PROTOCOL | \
215 ENABLE_EMASK_FBD_THERMALS | \
216 ENABLE_EMASK_FBD_DIMM_SPARE | \
217 ENABLE_EMASK_FBD_FATAL_ERRORS | \
218 ENABLE_EMASK_FBD_CORRECTABLE | \
219 ENABLE_EMASK_FBD_UNCORRECTABLE)
220
221#define ERR0_FBD 0xAC
222#define ERR1_FBD 0xB0
223#define ERR2_FBD 0xB4
224#define MCERR_FBD 0xB8
225#define NRECMEMA 0xBE
226#define NREC_BANK(x) (((x)>>12) & 0x7)
227#define NREC_RDWR(x) (((x)>>11) & 1)
228#define NREC_RANK(x) (((x)>>8) & 0x7)
229#define NRECMEMB 0xC0
230#define NREC_CAS(x) (((x)>>16) & 0xFFFFFF)
231#define NREC_RAS(x) ((x) & 0x7FFF)
232#define NRECFGLOG 0xC4
233#define NREEECFBDA 0xC8
234#define NREEECFBDB 0xCC
235#define NREEECFBDC 0xD0
236#define NREEECFBDD 0xD4
237#define NREEECFBDE 0xD8
238#define REDMEMA 0xDC
239#define RECMEMA 0xE2
240#define REC_BANK(x) (((x)>>12) & 0x7)
241#define REC_RDWR(x) (((x)>>11) & 1)
242#define REC_RANK(x) (((x)>>8) & 0x7)
243#define RECMEMB 0xE4
244#define REC_CAS(x) (((x)>>16) & 0xFFFFFF)
245#define REC_RAS(x) ((x) & 0x7FFF)
246#define RECFGLOG 0xE8
247#define RECFBDA 0xEC
248#define RECFBDB 0xF0
249#define RECFBDC 0xF4
250#define RECFBDD 0xF8
251#define RECFBDE 0xFC
252
253/* OFFSETS for Function 2 */
254
255/*
256 * Device 21,
257 * Function 0: Memory Map Branch 0
258 *
259 * Device 22,
260 * Function 0: Memory Map Branch 1
261 */
262#define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5
263#define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6
264
265#define AMB_PRESENT_0 0x64
266#define AMB_PRESENT_1 0x66
267#define MTR0 0x80
268#define MTR1 0x84
269#define MTR2 0x88
270#define MTR3 0x8C
271
272#define NUM_MTRS 4
273#define CHANNELS_PER_BRANCH (2)
274
275/* Defines to extract the vaious fields from the
276 * MTRx - Memory Technology Registers
277 */
278#define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
279#define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
280#define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
281#define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
282#define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
977c76bd 283#define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
eb60705a
EW		 284#define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
285#define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
286#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
287#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
288
289#ifdef CONFIG_EDAC_DEBUG
290static char *numrow_toString[] = {
291 "8,192 - 13 rows",
292 "16,384 - 14 rows",
293 "32,768 - 15 rows",
294 "reserved"
295};
296
297static char *numcol_toString[] = {
298 "1,024 - 10 columns",
299 "2,048 - 11 columns",
300 "4,096 - 12 columns",
301 "reserved"
302};
303#endif
304
c0667407
AR		 305/* enables the report of miscellaneous messages as CE errors - default off */
306static int misc_messages;
307
eb60705a
EW		 308/* Enumeration of supported devices */
309enum i5000_chips {
310 I5000P = 0,
311 I5000V = 1, /* future */
312 I5000X = 2 /* future */
313};
314
315/* Device name and register DID (Device ID) */
316struct i5000_dev_info {
317 const char *ctl_name; /* name for this device */
318 u16 fsb_mapping_errors; /* DID for the branchmap,control */
319};
320
321/* Table of devices attributes supported by this driver */
322static const struct i5000_dev_info i5000_devs[] = {
323 [I5000P] = {
052dfb45
DT		 324 .ctl_name = "I5000",
325 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
326 },
eb60705a
EW		 327};
328
329struct i5000_dimm_info {
330 int megabytes; /* size, 0 means not present */
331 int dual_rank;
332};
333
334#define MAX_CHANNELS 6 /* max possible channels */
335#define MAX_CSROWS (8*2) /* max possible csrows per channel */
336
337/* driver private data structure */
338struct i5000_pvt {
339 struct pci_dev *system_address; /* 16.0 */
340 struct pci_dev *branchmap_werrors; /* 16.1 */
341 struct pci_dev *fsb_error_regs; /* 16.2 */
342 struct pci_dev *branch_0; /* 21.0 */
343 struct pci_dev *branch_1; /* 22.0 */
344
eb60705a
EW		 345 u16 tolm; /* top of low memory */
346 u64 ambase; /* AMB BAR */
347
348 u16 mir0, mir1, mir2;
349
350 u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
351 u16 b0_ambpresent0; /* Branch 0, Channel 0 */
352 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
353
354 u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
355 u16 b1_ambpresent0; /* Branch 1, Channel 8 */
356 u16 b1_ambpresent1; /* Branch 1, Channel 1 */
357
6f042b50 358 /* DIMM information matrix, allocating architecture maximums */
eb60705a
EW		 359 struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
360
361 /* Actual values for this controller */
362 int maxch; /* Max channels */
363 int maxdimmperch; /* Max DIMMs per channel */
364};
365
366/* I5000 MCH error information retrieved from Hardware */
367struct i5000_error_info {
368
369 /* These registers are always read from the MC */
370 u32 ferr_fat_fbd; /* First Errors Fatal */
371 u32 nerr_fat_fbd; /* Next Errors Fatal */
372 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
373 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
374
375 /* These registers are input ONLY if there was a Recoverable Error */
376 u32 redmemb; /* Recoverable Mem Data Error log B */
377 u16 recmema; /* Recoverable Mem Error log A */
378 u32 recmemb; /* Recoverable Mem Error log B */
379
380 /* These registers are input ONLY if there was a
381 * Non-Recoverable Error */
382 u16 nrecmema; /* Non-Recoverable Mem log A */
383 u16 nrecmemb; /* Non-Recoverable Mem log B */
384
385};
386
456a2f95
DJ		 387static struct edac_pci_ctl_info *i5000_pci;
388
b2ccaeca 389/*
eb60705a
EW		 390 * i5000_get_error_info Retrieve the hardware error information from
391 * the hardware and cache it in the 'info'
392 * structure
393 */
394static void i5000_get_error_info(struct mem_ctl_info *mci,
b2ccaeca 395 struct i5000_error_info *info)
eb60705a
EW		 396{
397 struct i5000_pvt *pvt;
398 u32 value;
399
b2ccaeca 400 pvt = mci->pvt_info;
eb60705a
EW		 401
402 /* read in the 1st FATAL error register */
403 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
404
405 /* Mask only the bits that the doc says are valid
406 */
407 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
408
409 /* If there is an error, then read in the */
410 /* NEXT FATAL error register and the Memory Error Log Register A */
411 if (value & FERR_FAT_MASK) {
412 info->ferr_fat_fbd = value;
413
414 /* harvest the various error data we need */
415 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 416 NERR_FAT_FBD, &info->nerr_fat_fbd);
eb60705a 417 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 418 NRECMEMA, &info->nrecmema);
eb60705a 419 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 420 NRECMEMB, &info->nrecmemb);
eb60705a
EW		 421
422 /* Clear the error bits, by writing them back */
423 pci_write_config_dword(pvt->branchmap_werrors,
052dfb45 424 FERR_FAT_FBD, value);
eb60705a
EW		 425 } else {
426 info->ferr_fat_fbd = 0;
427 info->nerr_fat_fbd = 0;
428 info->nrecmema = 0;
429 info->nrecmemb = 0;
430 }
431
432 /* read in the 1st NON-FATAL error register */
433 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
434
435 /* If there is an error, then read in the 1st NON-FATAL error
436 * register as well */
437 if (value & FERR_NF_MASK) {
438 info->ferr_nf_fbd = value;
439
440 /* harvest the various error data we need */
441 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 442 NERR_NF_FBD, &info->nerr_nf_fbd);
eb60705a 443 pci_read_config_word(pvt->branchmap_werrors,
052dfb45 444 RECMEMA, &info->recmema);
eb60705a 445 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 446 RECMEMB, &info->recmemb);
eb60705a 447 pci_read_config_dword(pvt->branchmap_werrors,
052dfb45 448 REDMEMB, &info->redmemb);
eb60705a
EW		 449
450 /* Clear the error bits, by writing them back */
451 pci_write_config_dword(pvt->branchmap_werrors,
052dfb45 452 FERR_NF_FBD, value);
eb60705a
EW		 453 } else {
454 info->ferr_nf_fbd = 0;
455 info->nerr_nf_fbd = 0;
456 info->recmema = 0;
457 info->recmemb = 0;
458 info->redmemb = 0;
459 }
460}
461
b2ccaeca 462/*
eb60705a
EW		 463 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
464 * struct i5000_error_info *info,
465 * int handle_errors);
466 *
467 * handle the Intel FATAL errors, if any
468 */
469static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
b2ccaeca 470 struct i5000_error_info *info,
052dfb45 471 int handle_errors)
eb60705a 472{
c0667407
AR		 473 char msg[EDAC_MC_LABEL_LEN + 1 + 160];
474 char *specific = NULL;
eb60705a
EW		 475 u32 allErrors;
476 int branch;
477 int channel;
478 int bank;
479 int rank;
480 int rdwr;
481 int ras, cas;
482
483 /* mask off the Error bits that are possible */
484 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
485 if (!allErrors)
486 return; /* if no error, return now */
487
eb60705a
EW		 488 branch = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
489 channel = branch;
490
491 /* Use the NON-Recoverable macros to extract data */
492 bank = NREC_BANK(info->nrecmema);
493 rank = NREC_RANK(info->nrecmema);
494 rdwr = NREC_RDWR(info->nrecmema);
495 ras = NREC_RAS(info->nrecmemb);
496 cas = NREC_CAS(info->nrecmemb);
497
498 debugf0("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
499 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
500 rank, channel, channel + 1, branch >> 1, bank,
501 rdwr ? "Write" : "Read", ras, cas);
502
503 /* Only 1 bit will be on */
c0667407
AR		 504 switch (allErrors) {
505 case FERR_FAT_M1ERR:
506 specific = "Alert on non-redundant retry or fast "
507 "reset timeout";
508 break;
509 case FERR_FAT_M2ERR:
510 specific = "Northbound CRC error on non-redundant "
511 "retry";
512 break;
513 case FERR_FAT_M3ERR:
514 specific = ">Tmid Thermal event with intelligent "
515 "throttling disabled";
516 break;
eb60705a
EW		 517 }
518
519 /* Form out message */
520 snprintf(msg, sizeof(msg),
521 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d CAS=%d "
c0667407 522 "FATAL Err=0x%x (%s))",
eb60705a 523 branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
c0667407 524 allErrors, specific);
eb60705a
EW		 525
526 /* Call the helper to output message */
527 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
528}
529
b2ccaeca 530/*
eb60705a 531 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
052dfb45
DT		 532 * struct i5000_error_info *info,
533 * int handle_errors);
eb60705a
EW		 534 *
535 * handle the Intel NON-FATAL errors, if any
536 */
537static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
b2ccaeca 538 struct i5000_error_info *info,
052dfb45 539 int handle_errors)
eb60705a 540{
c0667407
AR		 541 char msg[EDAC_MC_LABEL_LEN + 1 + 170];
542 char *specific = NULL;
eb60705a
EW		 543 u32 allErrors;
544 u32 ue_errors;
545 u32 ce_errors;
546 u32 misc_errors;
547 int branch;
548 int channel;
549 int bank;
550 int rank;
551 int rdwr;
552 int ras, cas;
553
554 /* mask off the Error bits that are possible */
555 allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
556 if (!allErrors)
557 return; /* if no error, return now */
558
559 /* ONLY ONE of the possible error bits will be set, as per the docs */
eb60705a
EW		 560 ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
561 if (ue_errors) {
562 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
563
564 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
565 channel = branch;
566 bank = NREC_BANK(info->nrecmema);
567 rank = NREC_RANK(info->nrecmema);
568 rdwr = NREC_RDWR(info->nrecmema);
569 ras = NREC_RAS(info->nrecmemb);
570 cas = NREC_CAS(info->nrecmemb);
571
572 debugf0
052dfb45
DT		 573 ("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
574 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
575 rank, channel, channel + 1, branch >> 1, bank,
576 rdwr ? "Write" : "Read", ras, cas);
eb60705a 577
c0667407
AR		 578 switch (ue_errors) {
579 case FERR_NF_M12ERR:
580 specific = "Non-Aliased Uncorrectable Patrol Data ECC";
581 break;
582 case FERR_NF_M11ERR:
583 specific = "Non-Aliased Uncorrectable Spare-Copy "
584 "Data ECC";
585 break;
586 case FERR_NF_M10ERR:
587 specific = "Non-Aliased Uncorrectable Mirrored Demand "
588 "Data ECC";
589 break;
590 case FERR_NF_M9ERR:
591 specific = "Non-Aliased Uncorrectable Non-Mirrored "
592 "Demand Data ECC";
593 break;
594 case FERR_NF_M8ERR:
595 specific = "Aliased Uncorrectable Patrol Data ECC";
596 break;
597 case FERR_NF_M7ERR:
598 specific = "Aliased Uncorrectable Spare-Copy Data ECC";
599 break;
600 case FERR_NF_M6ERR:
601 specific = "Aliased Uncorrectable Mirrored Demand "
602 "Data ECC";
603 break;
604 case FERR_NF_M5ERR:
605 specific = "Aliased Uncorrectable Non-Mirrored Demand "
606 "Data ECC";
607 break;
608 case FERR_NF_M4ERR:
609 specific = "Uncorrectable Data ECC on Replay";
610 break;
611 }
612
eb60705a
EW		 613 /* Form out message */
614 snprintf(msg, sizeof(msg),
615 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
c0667407 616 "CAS=%d, UE Err=0x%x (%s))",
eb60705a 617 branch >> 1, bank, rdwr ? "Write" : "Read", ras, cas,
c0667407 618 ue_errors, specific);
eb60705a
EW		 619
620 /* Call the helper to output message */
621 edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
622 }
623
624 /* Check correctable errors */
625 ce_errors = allErrors & FERR_NF_CORRECTABLE;
626 if (ce_errors) {
627 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
628
629 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
630
631 channel = 0;
632 if (REC_ECC_LOCATOR_ODD(info->redmemb))
633 channel = 1;
634
635 /* Convert channel to be based from zero, instead of
636 * from branch base of 0 */
637 channel += branch;
638
639 bank = REC_BANK(info->recmema);
640 rank = REC_RANK(info->recmema);
641 rdwr = REC_RDWR(info->recmema);
642 ras = REC_RAS(info->recmemb);
643 cas = REC_CAS(info->recmemb);
644
645 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
646 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
647 rank, channel, branch >> 1, bank,
648 rdwr ? "Write" : "Read", ras, cas);
649
c0667407
AR		 650 switch (ce_errors) {
651 case FERR_NF_M17ERR:
652 specific = "Correctable Non-Mirrored Demand Data ECC";
653 break;
654 case FERR_NF_M18ERR:
655 specific = "Correctable Mirrored Demand Data ECC";
656 break;
657 case FERR_NF_M19ERR:
658 specific = "Correctable Spare-Copy Data ECC";
659 break;
660 case FERR_NF_M20ERR:
661 specific = "Correctable Patrol Data ECC";
662 break;
663 }
664
eb60705a
EW		 665 /* Form out message */
666 snprintf(msg, sizeof(msg),
667 "(Branch=%d DRAM-Bank=%d RDWR=%s RAS=%d "
c0667407
AR		 668 "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
669 rdwr ? "Write" : "Read", ras, cas, ce_errors,
670 specific);
eb60705a
EW		 671
672 /* Call the helper to output message */
673 edac_mc_handle_fbd_ce(mci, rank, channel, msg);
674 }
675
c0667407
AR		 676 if (!misc_messages)
677 return;
eb60705a 678
c0667407
AR		 679 misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
680 FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
eb60705a 681 if (misc_errors) {
c0667407
AR		 682 switch (misc_errors) {
683 case FERR_NF_M13ERR:
684 specific = "Non-Retry or Redundant Retry FBD Memory "
685 "Alert or Redundant Fast Reset Timeout";
686 break;
687 case FERR_NF_M14ERR:
688 specific = "Non-Retry or Redundant Retry FBD "
689 "Configuration Alert";
690 break;
691 case FERR_NF_M15ERR:
692 specific = "Non-Retry or Redundant Retry FBD "
693 "Northbound CRC error on read data";
694 break;
695 case FERR_NF_M21ERR:
696 specific = "FBD Northbound CRC error on "
697 "FBD Sync Status";
698 break;
699 case FERR_NF_M22ERR:
700 specific = "SPD protocol error";
701 break;
702 case FERR_NF_M27ERR:
703 specific = "DIMM-spare copy started";
704 break;
705 case FERR_NF_M28ERR:
706 specific = "DIMM-spare copy completed";
707 break;
708 }
709 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
eb60705a 710
c0667407
AR		 711 /* Form out message */
712 snprintf(msg, sizeof(msg),
713 "(Branch=%d Err=%#x (%s))", branch >> 1,
714 misc_errors, specific);
eb60705a 715
c0667407
AR		 716 /* Call the helper to output message */
717 edac_mc_handle_fbd_ce(mci, 0, 0, msg);
eb60705a
EW		 718 }
719}
720
b2ccaeca 721/*
eb60705a
EW		 722 * i5000_process_error_info Process the error info that is
723 * in the 'info' structure, previously retrieved from hardware
724 */
725static void i5000_process_error_info(struct mem_ctl_info *mci,
b2ccaeca 726 struct i5000_error_info *info,
052dfb45 727 int handle_errors)
eb60705a
EW		 728{
729 /* First handle any fatal errors that occurred */
730 i5000_process_fatal_error_info(mci, info, handle_errors);
731
732 /* now handle any non-fatal errors that occurred */
733 i5000_process_nonfatal_error_info(mci, info, handle_errors);
734}
735
b2ccaeca 736/*
eb60705a
EW		 737 * i5000_clear_error Retrieve any error from the hardware
738 * but do NOT process that error.
739 * Used for 'clearing' out of previous errors
740 * Called by the Core module.
741 */
742static void i5000_clear_error(struct mem_ctl_info *mci)
743{
744 struct i5000_error_info info;
745
746 i5000_get_error_info(mci, &info);
747}
748
b2ccaeca 749/*
eb60705a
EW		 750 * i5000_check_error Retrieve and process errors reported by the
751 * hardware. Called by the Core module.
752 */
753static void i5000_check_error(struct mem_ctl_info *mci)
754{
755 struct i5000_error_info info;
756 debugf4("MC%d: " __FILE__ ": %s()\n", mci->mc_idx, __func__);
757 i5000_get_error_info(mci, &info);
758 i5000_process_error_info(mci, &info, 1);
759}
760
b2ccaeca 761/*
eb60705a
EW		 762 * i5000_get_devices Find and perform 'get' operation on the MCH's
763 * device/functions we want to reference for this driver
764 *
765 * Need to 'get' device 16 func 1 and func 2
766 */
767static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
768{
769 //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
770 struct i5000_pvt *pvt;
771 struct pci_dev *pdev;
772
b2ccaeca 773 pvt = mci->pvt_info;
eb60705a
EW		 774
775 /* Attempt to 'get' the MCH register we want */
776 pdev = NULL;
777 while (1) {
778 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 779 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
eb60705a
EW		 780
781 /* End of list, leave */
782 if (pdev == NULL) {
783 i5000_printk(KERN_ERR,
052dfb45
DT		 784 "'system address,Process Bus' "
785 "device not found:"
786 "vendor 0x%x device 0x%x FUNC 1 "
787 "(broken BIOS?)\n",
788 PCI_VENDOR_ID_INTEL,
789 PCI_DEVICE_ID_INTEL_I5000_DEV16);
eb60705a
EW		 790
791 return 1;
792 }
793
794 /* Scan for device 16 func 1 */
795 if (PCI_FUNC(pdev->devfn) == 1)
796 break;
797 }
798
799 pvt->branchmap_werrors = pdev;
800
801 /* Attempt to 'get' the MCH register we want */
802 pdev = NULL;
803 while (1) {
804 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 805 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
eb60705a
EW		 806
807 if (pdev == NULL) {
808 i5000_printk(KERN_ERR,
052dfb45
DT		 809 "MC: 'branchmap,control,errors' "
810 "device not found:"
811 "vendor 0x%x device 0x%x Func 2 "
812 "(broken BIOS?)\n",
813 PCI_VENDOR_ID_INTEL,
814 PCI_DEVICE_ID_INTEL_I5000_DEV16);
eb60705a
EW		 815
816 pci_dev_put(pvt->branchmap_werrors);
817 return 1;
818 }
819
820 /* Scan for device 16 func 1 */
821 if (PCI_FUNC(pdev->devfn) == 2)
822 break;
823 }
824
825 pvt->fsb_error_regs = pdev;
826
827 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
828 pci_name(pvt->system_address),
829 pvt->system_address->vendor, pvt->system_address->device);
830 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
831 pci_name(pvt->branchmap_werrors),
832 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
833 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
834 pci_name(pvt->fsb_error_regs),
835 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
836
837 pdev = NULL;
838 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 839 PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
eb60705a
EW		 840
841 if (pdev == NULL) {
842 i5000_printk(KERN_ERR,
052dfb45
DT		 843 "MC: 'BRANCH 0' device not found:"
844 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
845 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
eb60705a
EW		 846
847 pci_dev_put(pvt->branchmap_werrors);
848 pci_dev_put(pvt->fsb_error_regs);
849 return 1;
850 }
851
852 pvt->branch_0 = pdev;
853
854 /* If this device claims to have more than 2 channels then
855 * fetch Branch 1's information
856 */
857 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
858 pdev = NULL;
859 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
052dfb45 860 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
eb60705a
EW		 861
862 if (pdev == NULL) {
863 i5000_printk(KERN_ERR,
052dfb45
DT		 864 "MC: 'BRANCH 1' device not found:"
865 "vendor 0x%x device 0x%x Func 0 "
866 "(broken BIOS?)\n",
867 PCI_VENDOR_ID_INTEL,
868 PCI_DEVICE_ID_I5000_BRANCH_1);
eb60705a
EW		 869
870 pci_dev_put(pvt->branchmap_werrors);
871 pci_dev_put(pvt->fsb_error_regs);
872 pci_dev_put(pvt->branch_0);
873 return 1;
874 }
875
876 pvt->branch_1 = pdev;
877 }
878
879 return 0;
880}
881
b2ccaeca 882/*
eb60705a
EW		 883 * i5000_put_devices 'put' all the devices that we have
884 * reserved via 'get'
885 */
886static void i5000_put_devices(struct mem_ctl_info *mci)
887{
888 struct i5000_pvt *pvt;
889
b2ccaeca 890 pvt = mci->pvt_info;
eb60705a
EW		 891
892 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
893 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
894 pci_dev_put(pvt->branch_0); /* DEV 21 */
895
896 /* Only if more than 2 channels do we release the second branch */
b2ccaeca 897 if (pvt->maxch >= CHANNELS_PER_BRANCH)
eb60705a 898 pci_dev_put(pvt->branch_1); /* DEV 22 */
eb60705a
EW		 899}
900
b2ccaeca 901/*
eb60705a
EW		 902 * determine_amb_resent
903 *
904 * the information is contained in NUM_MTRS different registers
905 * determineing which of the NUM_MTRS requires knowing
906 * which channel is in question
907 *
908 * 2 branches, each with 2 channels
909 * b0_ambpresent0 for channel '0'
910 * b0_ambpresent1 for channel '1'
911 * b1_ambpresent0 for channel '2'
912 * b1_ambpresent1 for channel '3'
913 */
914static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
915{
916 int amb_present;
917
918 if (channel < CHANNELS_PER_BRANCH) {
919 if (channel & 0x1)
920 amb_present = pvt->b0_ambpresent1;
921 else
922 amb_present = pvt->b0_ambpresent0;
923 } else {
924 if (channel & 0x1)
925 amb_present = pvt->b1_ambpresent1;
926 else
927 amb_present = pvt->b1_ambpresent0;
928 }
929
930 return amb_present;
931}
932
b2ccaeca 933/*
eb60705a
EW		 934 * determine_mtr(pvt, csrow, channel)
935 *
936 * return the proper MTR register as determine by the csrow and channel desired
937 */
938static int determine_mtr(struct i5000_pvt *pvt, int csrow, int channel)
939{
940 int mtr;
941
942 if (channel < CHANNELS_PER_BRANCH)
943 mtr = pvt->b0_mtr[csrow >> 1];
944 else
945 mtr = pvt->b1_mtr[csrow >> 1];
946
947 return mtr;
948}
949
b2ccaeca 950/*
eb60705a
EW		 951 */
952static void decode_mtr(int slot_row, u16 mtr)
953{
954 int ans;
955
956 ans = MTR_DIMMS_PRESENT(mtr);
957
958 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr,
959 ans ? "Present" : "NOT Present");
960 if (!ans)
961 return;
962
963 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
964 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
965 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
966 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
967 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
968}
969
970static void handle_channel(struct i5000_pvt *pvt, int csrow, int channel,
052dfb45 971 struct i5000_dimm_info *dinfo)
eb60705a
EW		 972{
973 int mtr;
974 int amb_present_reg;
975 int addrBits;
976
977 mtr = determine_mtr(pvt, csrow, channel);
978 if (MTR_DIMMS_PRESENT(mtr)) {
979 amb_present_reg = determine_amb_present_reg(pvt, channel);
980
981 /* Determine if there is a DIMM present in this DIMM slot */
982 if (amb_present_reg & (1 << (csrow >> 1))) {
983 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
984
985 if (!((dinfo->dual_rank == 0) &&
052dfb45 986 ((csrow & 0x1) == 0x1))) {
eb60705a
EW		 987 /* Start with the number of bits for a Bank
988 * on the DRAM */
989 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
990 /* Add thenumber of ROW bits */
991 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
992 /* add the number of COLUMN bits */
993 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
994
995 addrBits += 6; /* add 64 bits per DIMM */
996 addrBits -= 20; /* divide by 2^^20 */
997 addrBits -= 3; /* 8 bits per bytes */
998
999 dinfo->megabytes = 1 << addrBits;
1000 }
1001 }
1002 }
1003}
1004
b2ccaeca 1005/*
eb60705a
EW		 1006 * calculate_dimm_size
1007 *
1008 * also will output a DIMM matrix map, if debug is enabled, for viewing
1009 * how the DIMMs are populated
1010 */
1011static void calculate_dimm_size(struct i5000_pvt *pvt)
1012{
1013 struct i5000_dimm_info *dinfo;
1014 int csrow, max_csrows;
1015 char *p, *mem_buffer;
1016 int space, n;
1017 int channel;
1018
1019 /* ================= Generate some debug output ================= */
1020 space = PAGE_SIZE;
1021 mem_buffer = p = kmalloc(space, GFP_KERNEL);
1022 if (p == NULL) {
1023 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
052dfb45 1024 __FILE__, __func__);
eb60705a
EW		 1025 return;
1026 }
1027
1028 n = snprintf(p, space, "\n");
1029 p += n;
1030 space -= n;
1031
1032 /* Scan all the actual CSROWS (which is # of DIMMS * 2)
1033 * and calculate the information for each DIMM
1034 * Start with the highest csrow first, to display it first
1035 * and work toward the 0th csrow
1036 */
1037 max_csrows = pvt->maxdimmperch * 2;
1038 for (csrow = max_csrows - 1; csrow >= 0; csrow--) {
1039
1040 /* on an odd csrow, first output a 'boundary' marker,
1041 * then reset the message buffer */
1042 if (csrow & 0x1) {
1043 n = snprintf(p, space, "---------------------------"
052dfb45 1044 "--------------------------------");
eb60705a
EW		 1045 p += n;
1046 space -= n;
1047 debugf2("%s\n", mem_buffer);
1048 p = mem_buffer;
1049 space = PAGE_SIZE;
1050 }
1051 n = snprintf(p, space, "csrow %2d ", csrow);
1052 p += n;
1053 space -= n;
1054
1055 for (channel = 0; channel < pvt->maxch; channel++) {
1056 dinfo = &pvt->dimm_info[csrow][channel];
1057 handle_channel(pvt, csrow, channel, dinfo);
1058 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes);
1059 p += n;
1060 space -= n;
1061 }
1062 n = snprintf(p, space, "\n");
1063 p += n;
1064 space -= n;
1065 }
1066
1067 /* Output the last bottom 'boundary' marker */
1068 n = snprintf(p, space, "---------------------------"
052dfb45 1069 "--------------------------------\n");
eb60705a
EW		 1070 p += n;
1071 space -= n;
1072
1073 /* now output the 'channel' labels */
1074 n = snprintf(p, space, " ");
1075 p += n;
1076 space -= n;
1077 for (channel = 0; channel < pvt->maxch; channel++) {
1078 n = snprintf(p, space, "channel %d | ", channel);
1079 p += n;
1080 space -= n;
1081 }
1082 n = snprintf(p, space, "\n");
1083 p += n;
1084 space -= n;
1085
1086 /* output the last message and free buffer */
1087 debugf2("%s\n", mem_buffer);
1088 kfree(mem_buffer);
1089}
1090
b2ccaeca 1091/*
eb60705a
EW		 1092 * i5000_get_mc_regs read in the necessary registers and
1093 * cache locally
1094 *
1095 * Fills in the private data members
1096 */
1097static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1098{
1099 struct i5000_pvt *pvt;
1100 u32 actual_tolm;
1101 u16 limit;
1102 int slot_row;
1103 int maxch;
1104 int maxdimmperch;
1105 int way0, way1;
1106
b2ccaeca 1107 pvt = mci->pvt_info;
eb60705a
EW		 1108
1109 pci_read_config_dword(pvt->system_address, AMBASE,
052dfb45 1110 (u32 *) & pvt->ambase);
eb60705a 1111 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
052dfb45 1112 ((u32 *) & pvt->ambase) + sizeof(u32));
eb60705a
EW		 1113
1114 maxdimmperch = pvt->maxdimmperch;
1115 maxch = pvt->maxch;
1116
1117 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1118 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1119
1120 /* Get the Branch Map regs */
1121 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1122 pvt->tolm >>= 12;
1123 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1124 pvt->tolm);
1125
1126 actual_tolm = pvt->tolm << 28;
1127 debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1128
1129 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1130 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1131 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1132
1133 /* Get the MIR[0-2] regs */
1134 limit = (pvt->mir0 >> 4) & 0x0FFF;
1135 way0 = pvt->mir0 & 0x1;
1136 way1 = pvt->mir0 & 0x2;
1137 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1138 limit = (pvt->mir1 >> 4) & 0x0FFF;
1139 way0 = pvt->mir1 & 0x1;
1140 way1 = pvt->mir1 & 0x2;
1141 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1142 limit = (pvt->mir2 >> 4) & 0x0FFF;
1143 way0 = pvt->mir2 & 0x1;
1144 way1 = pvt->mir2 & 0x2;
1145 debugf2("MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1146
1147 /* Get the MTR[0-3] regs */
1148 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1149 int where = MTR0 + (slot_row * sizeof(u32));
1150
1151 pci_read_config_word(pvt->branch_0, where,
052dfb45 1152 &pvt->b0_mtr[slot_row]);
eb60705a
EW		 1153
1154 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1155 pvt->b0_mtr[slot_row]);
1156
1157 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1158 pci_read_config_word(pvt->branch_1, where,
052dfb45 1159 &pvt->b1_mtr[slot_row]);
eb60705a
EW		 1160 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1161 where, pvt->b0_mtr[slot_row]);
1162 } else {
1163 pvt->b1_mtr[slot_row] = 0;
1164 }
1165 }
1166
1167 /* Read and dump branch 0's MTRs */
1168 debugf2("\nMemory Technology Registers:\n");
1169 debugf2(" Branch 0:\n");
1170 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1171 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1172 }
1173 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
052dfb45 1174 &pvt->b0_ambpresent0);
eb60705a
EW		 1175 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1176 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
052dfb45 1177 &pvt->b0_ambpresent1);
eb60705a
EW		 1178 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1179
1180 /* Only if we have 2 branchs (4 channels) */
1181 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1182 pvt->b1_ambpresent0 = 0;
1183 pvt->b1_ambpresent1 = 0;
1184 } else {
1185 /* Read and dump branch 1's MTRs */
1186 debugf2(" Branch 1:\n");
1187 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1188 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1189 }
1190 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
052dfb45 1191 &pvt->b1_ambpresent0);
eb60705a
EW		 1192 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1193 pvt->b1_ambpresent0);
1194 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
052dfb45 1195 &pvt->b1_ambpresent1);
eb60705a
EW		 1196 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1197 pvt->b1_ambpresent1);
1198 }
1199
1200 /* Go and determine the size of each DIMM and place in an
1201 * orderly matrix */
1202 calculate_dimm_size(pvt);
1203}
1204
b2ccaeca 1205/*
eb60705a
EW		 1206 * i5000_init_csrows Initialize the 'csrows' table within
1207 * the mci control structure with the
1208 * addressing of memory.
1209 *
1210 * return:
1211 * 0 success
1212 * 1 no actual memory found on this MC
1213 */
1214static int i5000_init_csrows(struct mem_ctl_info *mci)
1215{
1216 struct i5000_pvt *pvt;
1217 struct csrow_info *p_csrow;
1218 int empty, channel_count;
1219 int max_csrows;
1220 int mtr;
1221 int csrow_megs;
1222 int channel;
1223 int csrow;
1224
b2ccaeca 1225 pvt = mci->pvt_info;
eb60705a
EW		 1226
1227 channel_count = pvt->maxch;
1228 max_csrows = pvt->maxdimmperch * 2;
1229
1230 empty = 1; /* Assume NO memory */
1231
1232 for (csrow = 0; csrow < max_csrows; csrow++) {
1233 p_csrow = &mci->csrows[csrow];
1234
1235 p_csrow->csrow_idx = csrow;
1236
1237 /* use branch 0 for the basis */
1238 mtr = pvt->b0_mtr[csrow >> 1];
1239
1240 /* if no DIMMS on this row, continue */
1241 if (!MTR_DIMMS_PRESENT(mtr))
1242 continue;
1243
1244 /* FAKE OUT VALUES, FIXME */
1245 p_csrow->first_page = 0 + csrow * 20;
1246 p_csrow->last_page = 9 + csrow * 20;
1247 p_csrow->page_mask = 0xFFF;
1248
1249 p_csrow->grain = 8;
1250
1251 csrow_megs = 0;
1252 for (channel = 0; channel < pvt->maxch; channel++) {
1253 csrow_megs += pvt->dimm_info[csrow][channel].megabytes;
1254 }
1255
1256 p_csrow->nr_pages = csrow_megs << 8;
1257
1258 /* Assume DDR2 for now */
1259 p_csrow->mtype = MEM_FB_DDR2;
1260
1261 /* ask what device type on this row */
1262 if (MTR_DRAM_WIDTH(mtr))
1263 p_csrow->dtype = DEV_X8;
1264 else
1265 p_csrow->dtype = DEV_X4;
1266
1267 p_csrow->edac_mode = EDAC_S8ECD8ED;
1268
1269 empty = 0;
1270 }
1271
1272 return empty;
1273}
1274
b2ccaeca 1275/*
eb60705a
EW		 1276 * i5000_enable_error_reporting
1277 * Turn on the memory reporting features of the hardware
1278 */
1279static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1280{
1281 struct i5000_pvt *pvt;
1282 u32 fbd_error_mask;
1283
b2ccaeca 1284 pvt = mci->pvt_info;
eb60705a
EW		 1285
1286 /* Read the FBD Error Mask Register */
1287 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
052dfb45 1288 &fbd_error_mask);
eb60705a
EW		 1289
1290 /* Enable with a '0' */
1291 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1292
1293 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
052dfb45 1294 fbd_error_mask);
eb60705a
EW		 1295}
1296
b2ccaeca 1297/*
eb60705a
EW		 1298 * i5000_get_dimm_and_channel_counts(pdev, &num_csrows, &num_channels)
1299 *
1300 * ask the device how many channels are present and how many CSROWS
1301 * as well
1302 */
1303static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
052dfb45
DT		 1304 int *num_dimms_per_channel,
1305 int *num_channels)
eb60705a
EW		 1306{
1307 u8 value;
1308
1309 /* Need to retrieve just how many channels and dimms per channel are
1310 * supported on this memory controller
1311 */
1312 pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1313 *num_dimms_per_channel = (int)value *2;
1314
1315 pci_read_config_byte(pdev, MAXCH, &value);
1316 *num_channels = (int)value;
1317}
1318
b2ccaeca 1319/*
eb60705a
EW		 1320 * i5000_probe1 Probe for ONE instance of device to see if it is
1321 * present.
1322 * return:
1323 * 0 for FOUND a device
1324 * < 0 for error code
1325 */
1326static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1327{
1328 struct mem_ctl_info *mci;
1329 struct i5000_pvt *pvt;
1330 int num_channels;
1331 int num_dimms_per_channel;
1332 int num_csrows;
1333
1334 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1335 __func__,
1336 pdev->bus->number,
1337 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1338
1339 /* We only are looking for func 0 of the set */
1340 if (PCI_FUNC(pdev->devfn) != 0)
1341 return -ENODEV;
1342
1343 /* Ask the devices for the number of CSROWS and CHANNELS so
1344 * that we can calculate the memory resources, etc
1345 *
1346 * The Chipset will report what it can handle which will be greater
1347 * or equal to what the motherboard manufacturer will implement.
1348 *
1349 * As we don't have a motherboard identification routine to determine
1350 * actual number of slots/dimms per channel, we thus utilize the
1351 * resource as specified by the chipset. Thus, we might have
1352 * have more DIMMs per channel than actually on the mobo, but this
1353 * allows the driver to support upto the chipset max, without
1354 * some fancy mobo determination.
1355 */
1356 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
052dfb45 1357 &num_channels);
eb60705a
EW		 1358 num_csrows = num_dimms_per_channel * 2;
1359
1360 debugf0("MC: %s(): Number of - Channels= %d DIMMS= %d CSROWS= %d\n",
1361 __func__, num_channels, num_dimms_per_channel, num_csrows);
1362
1363 /* allocate a new MC control structure */
b8f6f975 1364 mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
eb60705a
EW		 1365
1366 if (mci == NULL)
1367 return -ENOMEM;
1368
1369 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
1370
1371 mci->dev = &pdev->dev; /* record ptr to the generic device */
1372
b2ccaeca 1373 pvt = mci->pvt_info;
eb60705a
EW		 1374 pvt->system_address = pdev; /* Record this device in our private */
1375 pvt->maxch = num_channels;
1376 pvt->maxdimmperch = num_dimms_per_channel;
1377
1378 /* 'get' the pci devices we want to reserve for our use */
1379 if (i5000_get_devices(mci, dev_idx))
1380 goto fail0;
1381
1382 /* Time to get serious */
1383 i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1384
1385 mci->mc_idx = 0;
1386 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1387 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1388 mci->edac_cap = EDAC_FLAG_NONE;
1389 mci->mod_name = "i5000_edac.c";
1390 mci->mod_ver = I5000_REVISION;
1391 mci->ctl_name = i5000_devs[dev_idx].ctl_name;
c4192705 1392 mci->dev_name = pci_name(pdev);
eb60705a
EW		 1393 mci->ctl_page_to_phys = NULL;
1394
1395 /* Set the function pointer to an actual operation function */
1396 mci->edac_check = i5000_check_error;
1397
1398 /* initialize the MC control structure 'csrows' table
1399 * with the mapping and control information */
1400 if (i5000_init_csrows(mci)) {
1401 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1402 " because i5000_init_csrows() returned nonzero "
1403 "value\n");
1404 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1405 } else {
1406 debugf1("MC: Enable error reporting now\n");
1407 i5000_enable_error_reporting(mci);
1408 }
1409
1410 /* add this new MC control structure to EDAC's list of MCs */
b8f6f975 1411 if (edac_mc_add_mc(mci)) {
eb60705a
EW		 1412 debugf0("MC: " __FILE__
1413 ": %s(): failed edac_mc_add_mc()\n", __func__);
1414 /* FIXME: perhaps some code should go here that disables error
1415 * reporting if we just enabled it
1416 */
1417 goto fail1;
1418 }
1419
1420 i5000_clear_error(mci);
1421
456a2f95
DJ		 1422 /* allocating generic PCI control info */
1423 i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1424 if (!i5000_pci) {
1425 printk(KERN_WARNING
1426 "%s(): Unable to create PCI control\n",
1427 __func__);
1428 printk(KERN_WARNING
1429 "%s(): PCI error report via EDAC not setup\n",
1430 __func__);
1431 }
1432
eb60705a
EW		 1433 return 0;
1434
1435 /* Error exit unwinding stack */
052dfb45 1436fail1:
eb60705a
EW		 1437
1438 i5000_put_devices(mci);
1439
052dfb45 1440fail0:
eb60705a
EW		 1441 edac_mc_free(mci);
1442 return -ENODEV;
1443}
1444
b2ccaeca 1445/*
eb60705a
EW		 1446 * i5000_init_one constructor for one instance of device
1447 *
1448 * returns:
1449 * negative on error
1450 * count (>= 0)
1451 */
1452static int __devinit i5000_init_one(struct pci_dev *pdev,
052dfb45 1453 const struct pci_device_id *id)
eb60705a
EW		 1454{
1455 int rc;
1456
1457 debugf0("MC: " __FILE__ ": %s()\n", __func__);
1458
1459 /* wake up device */
1460 rc = pci_enable_device(pdev);
1461 if (rc == -EIO)
1462 return rc;
1463
1464 /* now probe and enable the device */
1465 return i5000_probe1(pdev, id->driver_data);
1466}
1467
b2ccaeca 1468/*
eb60705a
EW		 1469 * i5000_remove_one destructor for one instance of device
1470 *
1471 */
1472static void __devexit i5000_remove_one(struct pci_dev *pdev)
1473{
1474 struct mem_ctl_info *mci;
1475
1476 debugf0(__FILE__ ": %s()\n", __func__);
1477
456a2f95
DJ		 1478 if (i5000_pci)
1479 edac_pci_release_generic_ctl(i5000_pci);
1480
eb60705a
EW		 1481 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1482 return;
1483
1484 /* retrieve references to resources, and free those resources */
1485 i5000_put_devices(mci);
1486
1487 edac_mc_free(mci);
1488}
1489
b2ccaeca 1490/*
eb60705a
EW		 1491 * pci_device_id table for which devices we are looking for
1492 *
1493 * The "E500P" device is the first device supported.
1494 */
1495static const struct pci_device_id i5000_pci_tbl[] __devinitdata = {
1496 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1497 .driver_data = I5000P},
1498
1499 {0,} /* 0 terminated list. */
1500};
1501
1502MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1503
b2ccaeca 1504/*
eb60705a
EW		 1505 * i5000_driver pci_driver structure for this module
1506 *
1507 */
1508static struct pci_driver i5000_driver = {
57510c2f 1509 .name = KBUILD_BASENAME,
eb60705a
EW		 1510 .probe = i5000_init_one,
1511 .remove = __devexit_p(i5000_remove_one),
1512 .id_table = i5000_pci_tbl,
1513};
1514
b2ccaeca 1515/*
eb60705a
EW		 1516 * i5000_init Module entry function
1517 * Try to initialize this module for its devices
1518 */
1519static int __init i5000_init(void)
1520{
1521 int pci_rc;
1522
1523 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1524
c3c52bce
HM		 1525 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1526 opstate_init();
1527
eb60705a
EW		 1528 pci_rc = pci_register_driver(&i5000_driver);
1529
1530 return (pci_rc < 0) ? pci_rc : 0;
1531}
1532
b2ccaeca 1533/*
eb60705a
EW		 1534 * i5000_exit() Module exit function
1535 * Unregister the driver
1536 */
1537static void __exit i5000_exit(void)
1538{
1539 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1540 pci_unregister_driver(&i5000_driver);
1541}
1542
1543module_init(i5000_init);
1544module_exit(i5000_exit);
1545
1546MODULE_LICENSE("GPL");
1547MODULE_AUTHOR
1548 ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1549MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
052dfb45 1550 I5000_REVISION);
c3c52bce 1551
c0d12172
DJ		 1552module_param(edac_op_state, int, 0444);
1553MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
c0667407
AR		 1554module_param(misc_messages, int, 0444);
1555MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");
1556
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