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1#
2# EDAC Kconfig
4577ca55 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
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4# Licensed and distributed under the GPL
5#
da9bb1d2 6
751cb5e5 7menuconfig EDAC
e24aca67 8 bool "EDAC (Error Detection And Correction) reporting"
e25df120 9 depends on HAS_IOMEM
4c6a1c13 10 depends on X86 || PPC
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11 help
12 EDAC is designed to report errors in the core system.
13 These are low-level errors that are reported in the CPU or
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14 supporting chipset or other subsystems:
15 memory errors, cache errors, PCI errors, thermal throttling, etc..
16 If unsure, select 'Y'.
da9bb1d2 17
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18 If this code is reporting problems on your system, please
19 see the EDAC project web pages for more information at:
20
21 <http://bluesmoke.sourceforge.net/>
22
23 and:
24
25 <http://buttersideup.com/edacwiki>
26
27 There is also a mailing list for the EDAC project, which can
28 be found via the sourceforge page.
29
751cb5e5 30if EDAC
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31
32comment "Reporting subsystems"
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33
34config EDAC_DEBUG
35 bool "Debugging"
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36 help
37 This turns on debugging information for the entire EDAC
38 sub-system. You can insert module with "debug_level=x", current
39 there're four debug levels (x=0,1,2,3 from low to high).
40 Usually you should select 'N'.
41
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42config EDAC_DEBUG_VERBOSE
43 bool "More verbose debugging"
44 depends on EDAC_DEBUG
45 help
46 This option makes debugging information more verbose.
47 Source file name and line number where debugging message
48 printed will be added to debugging message.
49
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50 config EDAC_DECODE_MCE
51 tristate "Decode MCEs in human-readable form (only on AMD for now)"
52 depends on CPU_SUP_AMD && X86_MCE
53 default y
54 ---help---
55 Enable this option if you want to decode Machine Check Exceptions
56 occuring on your machine in human-readable form.
57
58 You should definitely say Y here in case you want to decode MCEs
59 which occur really early upon boot, before the module infrastructure
60 has been initialized.
61
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62config EDAC_MM_EDAC
63 tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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64 help
65 Some systems are able to detect and correct errors in main
66 memory. EDAC can report statistics on memory error
67 detection and correction (EDAC - or commonly referred to ECC
68 errors). EDAC will also try to decode where these errors
69 occurred so that a particular failing memory module can be
70 replaced. If unsure, select 'Y'.
71
696e409d 72config EDAC_MCE
963c5ba3 73 bool
696e409d 74
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75config EDAC_AMD64
76 tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
0d18b2e3 77 depends on EDAC_MM_EDAC && K8_NB && X86_64 && PCI && EDAC_DECODE_MCE
7d6034d3 78 help
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79 Support for error detection and correction on the AMD 64
80 Families of Memory Controllers (K8, F10h and F11h)
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81
82config EDAC_AMD64_ERROR_INJECTION
83 bool "Sysfs Error Injection facilities"
84 depends on EDAC_AMD64
85 help
86 Recent Opterons (Family 10h and later) provide for Memory Error
87 Injection into the ECC detection circuits. The amd64_edac module
88 allows the operator/user to inject Uncorrectable and Correctable
89 errors into DRAM.
90
91 When enabled, in each of the respective memory controller directories
92 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
93
94 - inject_section (0..3, 16-byte section of 64-byte cacheline),
95 - inject_word (0..8, 16-bit word of 16-byte section),
96 - inject_ecc_vector (hex ecc vector: select bits of inject word)
97
98 In addition, there are two control files, inject_read and inject_write,
99 which trigger the DRAM ECC Read and Write respectively.
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100
101config EDAC_AMD76X
102 tristate "AMD 76x (760, 762, 768)"
90cbc45b 103 depends on EDAC_MM_EDAC && PCI && X86_32
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104 help
105 Support for error detection and correction on the AMD 76x
106 series of chipsets used with the Athlon processor.
107
108config EDAC_E7XXX
109 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
39f1d8d3 110 depends on EDAC_MM_EDAC && PCI && X86_32
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111 help
112 Support for error detection and correction on the Intel
113 E7205, E7500, E7501 and E7505 server chipsets.
114
115config EDAC_E752X
5135b797 116 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
da960a6a 117 depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG
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118 help
119 Support for error detection and correction on the Intel
120 E7520, E7525, E7320 server chipsets.
121
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122config EDAC_I82443BXGX
123 tristate "Intel 82443BX/GX (440BX/GX)"
124 depends on EDAC_MM_EDAC && PCI && X86_32
28f96eea 125 depends on BROKEN
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126 help
127 Support for error detection and correction on the Intel
128 82443BX/GX memory controllers (440BX/GX chipsets).
129
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130config EDAC_I82875P
131 tristate "Intel 82875p (D82875P, E7210)"
39f1d8d3 132 depends on EDAC_MM_EDAC && PCI && X86_32
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133 help
134 Support for error detection and correction on the Intel
135 DP82785P and E7210 server chipsets.
136
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137config EDAC_I82975X
138 tristate "Intel 82975x (D82975x)"
139 depends on EDAC_MM_EDAC && PCI && X86
140 help
141 Support for error detection and correction on the Intel
142 DP82975x server chipsets.
143
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144config EDAC_I3000
145 tristate "Intel 3000/3010"
f5c0454c 146 depends on EDAC_MM_EDAC && PCI && X86
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147 help
148 Support for error detection and correction on the Intel
149 3000 and 3010 server chipsets.
150
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151config EDAC_I3200
152 tristate "Intel 3200"
153 depends on EDAC_MM_EDAC && PCI && X86 && EXPERIMENTAL
154 help
155 Support for error detection and correction on the Intel
156 3200 and 3210 server chipsets.
157
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158config EDAC_X38
159 tristate "Intel X38"
160 depends on EDAC_MM_EDAC && PCI && X86
161 help
162 Support for error detection and correction on the Intel
163 X38 server chipsets.
164
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165config EDAC_I5400
166 tristate "Intel 5400 (Seaburg) chipsets"
167 depends on EDAC_MM_EDAC && PCI && X86
168 help
169 Support for error detection and correction the Intel
170 i5400 MCH chipset (Seaburg).
171
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172config EDAC_I7CORE
173 tristate "Intel i7 Core (Nehalem) processors"
174 depends on EDAC_MM_EDAC && PCI && X86
696e409d 175 select EDAC_MCE
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176 help
177 Support for error detection and correction the Intel
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178 i7 Core (Nehalem) Integrated Memory Controller that exists on
179 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
180 and Xeon 55xx processors.
a0c36a1f 181
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182config EDAC_I82860
183 tristate "Intel 82860"
39f1d8d3 184 depends on EDAC_MM_EDAC && PCI && X86_32
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185 help
186 Support for error detection and correction on the Intel
187 82860 chipset.
188
189config EDAC_R82600
190 tristate "Radisys 82600 embedded chipset"
39f1d8d3 191 depends on EDAC_MM_EDAC && PCI && X86_32
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192 help
193 Support for error detection and correction on the Radisys
194 82600 embedded chipset.
195
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196config EDAC_I5000
197 tristate "Intel Greencreek/Blackford chipset"
198 depends on EDAC_MM_EDAC && X86 && PCI
199 help
200 Support for error detection and correction the Intel
201 Greekcreek/Blackford chipsets.
202
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203config EDAC_I5100
204 tristate "Intel San Clemente MCH"
205 depends on EDAC_MM_EDAC && X86 && PCI
206 help
207 Support for error detection and correction the Intel
208 San Clemente MCH.
209
a9a753d5 210config EDAC_MPC85XX
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211 tristate "Freescale MPC83xx / MPC85xx"
212 depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || MPC85xx)
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213 help
214 Support for error detection and correction on the Freescale
b4846251 215 MPC8349, MPC8560, MPC8540, MPC8548
a9a753d5 216
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217config EDAC_MV64X60
218 tristate "Marvell MV64x60"
219 depends on EDAC_MM_EDAC && MV64X60
220 help
221 Support for error detection and correction on the Marvell
222 MV64360 and MV64460 chipsets.
223
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224config EDAC_PASEMI
225 tristate "PA Semi PWRficient"
226 depends on EDAC_MM_EDAC && PCI
ddcc3050 227 depends on PPC_PASEMI
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228 help
229 Support for error detection and correction on PA Semi
230 PWRficient.
231
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232config EDAC_CELL
233 tristate "Cell Broadband Engine memory controller"
def434c2 234 depends on EDAC_MM_EDAC && PPC_CELL_COMMON
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235 help
236 Support for error detection and correction on the
237 Cell Broadband Engine internal memory controller
238 on platform without a hypervisor
7d8536fb 239
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240config EDAC_PPC4XX
241 tristate "PPC4xx IBM DDR2 Memory Controller"
242 depends on EDAC_MM_EDAC && 4xx
243 help
244 This enables support for EDAC on the ECC memory used
245 with the IBM DDR2 memory controller found in various
246 PowerPC 4xx embedded processors such as the 405EX[r],
247 440SP, 440SPe, 460EX, 460GT and 460SX.
248
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249config EDAC_AMD8131
250 tristate "AMD8131 HyperTransport PCI-X Tunnel"
715fe7af 251 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
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252 help
253 Support for error detection and correction on the
254 AMD8131 HyperTransport PCI-X Tunnel chip.
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255 Note, add more Kconfig dependency if it's adopted
256 on some machine other than Maple.
e8765584 257
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258config EDAC_AMD8111
259 tristate "AMD8111 HyperTransport I/O Hub"
715fe7af 260 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
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261 help
262 Support for error detection and correction on the
263 AMD8111 HyperTransport I/O Hub chip.
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264 Note, add more Kconfig dependency if it's adopted
265 on some machine other than Maple.
58b4ce6f 266
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267config EDAC_CPC925
268 tristate "IBM CPC925 Memory Controller (PPC970FX)"
269 depends on EDAC_MM_EDAC && PPC64
270 help
271 Support for error detection and correction on the
272 IBM CPC925 Bridge and Memory Controller, which is
273 a companion chip to the PowerPC 970 family of
274 processors.
275
751cb5e5 276endif # EDAC