[net-next-2.6.git] / drivers / dma / ioatdma_registers.h

/*
 * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef _IOAT_REGISTERS_H_
#define _IOAT_REGISTERS_H_

#define IOAT_PCI_DMACTRL_OFFSET			0x48
#define IOAT_PCI_DMACTRL_DMA_EN			0x00000001
#define IOAT_PCI_DMACTRL_MSI_EN			0x00000002

/* MMIO Device Registers */
#define IOAT_CHANCNT_OFFSET			0x00	/*  8-bit */

#define IOAT_XFERCAP_OFFSET			0x01	/*  8-bit */
#define IOAT_XFERCAP_4KB			12
#define IOAT_XFERCAP_8KB			13
#define IOAT_XFERCAP_16KB			14
#define IOAT_XFERCAP_32KB			15
#define IOAT_XFERCAP_32GB			0

#define IOAT_GENCTRL_OFFSET			0x02	/*  8-bit */
#define IOAT_GENCTRL_DEBUG_EN			0x01

#define IOAT_INTRCTRL_OFFSET			0x03	/*  8-bit */
#define IOAT_INTRCTRL_MASTER_INT_EN		0x01	/* Master Interrupt Enable */
#define IOAT_INTRCTRL_INT_STATUS		0x02	/* ATTNSTATUS -or- Channel Int */
#define IOAT_INTRCTRL_INT			0x04	/* INT_STATUS -and- MASTER_INT_EN */
#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL	0x08	/* Enable all MSI-X vectors */

#define IOAT_ATTNSTATUS_OFFSET			0x04	/* Each bit is a channel */

#define IOAT_VER_OFFSET				0x08	/*  8-bit */
#define IOAT_VER_MAJOR_MASK			0xF0
#define IOAT_VER_MINOR_MASK			0x0F
#define GET_IOAT_VER_MAJOR(x)			(((x) & IOAT_VER_MAJOR_MASK) >> 4)
#define GET_IOAT_VER_MINOR(x)			((x) & IOAT_VER_MINOR_MASK)

#define IOAT_PERPORTOFFSET_OFFSET		0x0A	/* 16-bit */

#define IOAT_INTRDELAY_OFFSET			0x0C	/* 16-bit */
#define IOAT_INTRDELAY_INT_DELAY_MASK		0x3FFF	/* Interrupt Delay Time */
#define IOAT_INTRDELAY_COALESE_SUPPORT		0x8000	/* Interrupt Coalescing Supported */

#define IOAT_DEVICE_STATUS_OFFSET		0x0E	/* 16-bit */
#define IOAT_DEVICE_STATUS_DEGRADED_MODE	0x0001

#define IOAT_CHANNEL_MMIO_SIZE			0x80	/* Each Channel MMIO space is this size */

/* DMA Channel Registers */
#define IOAT_CHANCTRL_OFFSET			0x00	/* 16-bit Channel Control Register */
#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK	0xF000
#define IOAT_CHANCTRL_CHANNEL_IN_USE		0x0100
#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL	0x0020
#define IOAT_CHANCTRL_ERR_INT_EN		0x0010
#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN		0x0008
#define IOAT_CHANCTRL_ERR_COMPLETION_EN		0x0004
#define IOAT_CHANCTRL_INT_DISABLE		0x0001

#define IOAT_DMA_COMP_OFFSET			0x02	/* 16-bit DMA channel compatibility */
#define IOAT_DMA_COMP_V1			0x0001	/* Compatibility with DMA version 1 */
#define IOAT_DMA_COMP_V2			0x0002	/* Compatibility with DMA version 2 */


#define IOAT1_CHANSTS_OFFSET		0x04	/* 64-bit Channel Status Register */
#define IOAT2_CHANSTS_OFFSET		0x08	/* 64-bit Channel Status Register */
#define IOAT_CHANSTS_OFFSET(ver)		((ver) < IOAT_VER_2_0 \
						? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
#define IOAT1_CHANSTS_OFFSET_LOW	0x04
#define IOAT2_CHANSTS_OFFSET_LOW	0x08
#define IOAT_CHANSTS_OFFSET_LOW(ver)		((ver) < IOAT_VER_2_0 \
						? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
#define IOAT1_CHANSTS_OFFSET_HIGH	0x08
#define IOAT2_CHANSTS_OFFSET_HIGH	0x0C
#define IOAT_CHANSTS_OFFSET_HIGH(ver)		((ver) < IOAT_VER_2_0 \
						? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR	~0x3F
#define IOAT_CHANSTS_SOFT_ERR			0x0000000000000010
#define IOAT_CHANSTS_UNAFFILIATED_ERR		0x0000000000000008
#define IOAT_CHANSTS_DMA_TRANSFER_STATUS	0x0000000000000007
#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE	0x0
#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE	0x1
#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED	0x2
#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED	0x3


#define IOAT_CHAN_DMACOUNT_OFFSET	0x06    /* 16-bit DMA Count register */

#define IOAT_DCACTRL_OFFSET         0x30   /* 32 bit Direct Cache Access Control Register */
#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
#define IOAT_DCACTRL_TARGET_CPU_MASK   0xFFFF /* APIC ID */

/* CB DCA Memory Space Registers */
#define IOAT_DCAOFFSET_OFFSET       0x14
/* CB_BAR + IOAT_DCAOFFSET value */
#define IOAT_DCA_VER_OFFSET         0x00
#define IOAT_DCA_VER_MAJOR_MASK     0xF0
#define IOAT_DCA_VER_MINOR_MASK     0x0F

#define IOAT_DCA_COMP_OFFSET        0x02
#define IOAT_DCA_COMP_V1            0x1

#define IOAT_FSB_CAPABILITY_OFFSET  0x04
#define IOAT_FSB_CAPABILITY_PREFETCH    0x1

#define IOAT_PCI_CAPABILITY_OFFSET  0x06
#define IOAT_PCI_CAPABILITY_MEMWR   0x1

#define IOAT_FSB_CAP_ENABLE_OFFSET  0x08
#define IOAT_FSB_CAP_ENABLE_PREFETCH    0x1

#define IOAT_PCI_CAP_ENABLE_OFFSET  0x0A
#define IOAT_PCI_CAP_ENABLE_MEMWR   0x1

#define IOAT_APICID_TAG_MAP_OFFSET  0x0C
#define IOAT_APICID_TAG_MAP_TAG0    0x0000000F
#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
#define IOAT_APICID_TAG_MAP_TAG1    0x000000F0
#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
#define IOAT_APICID_TAG_MAP_TAG2    0x00000F00
#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
#define IOAT_APICID_TAG_MAP_TAG3    0x0000F000
#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
#define IOAT_APICID_TAG_MAP_TAG4    0x000F0000
#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
#define IOAT_APICID_TAG_CB2_VALID   0x8080808080

#define IOAT_DCA_GREQID_OFFSET      0x10
#define IOAT_DCA_GREQID_SIZE        0x04
#define IOAT_DCA_GREQID_MASK        0xFFFF
#define IOAT_DCA_GREQID_IGNOREFUN   0x10000000
#define IOAT_DCA_GREQID_VALID       0x20000000
#define IOAT_DCA_GREQID_LASTID      0x80000000


#define IOAT1_CHAINADDR_OFFSET		0x0C	/* 64-bit Descriptor Chain Address Register */
#define IOAT2_CHAINADDR_OFFSET		0x10	/* 64-bit Descriptor Chain Address Register */
#define IOAT_CHAINADDR_OFFSET(ver)		((ver) < IOAT_VER_2_0 \
						? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
#define IOAT1_CHAINADDR_OFFSET_LOW	0x0C
#define IOAT2_CHAINADDR_OFFSET_LOW	0x10
#define IOAT_CHAINADDR_OFFSET_LOW(ver)		((ver) < IOAT_VER_2_0 \
						? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
#define IOAT1_CHAINADDR_OFFSET_HIGH	0x10
#define IOAT2_CHAINADDR_OFFSET_HIGH	0x14
#define IOAT_CHAINADDR_OFFSET_HIGH(ver)		((ver) < IOAT_VER_2_0 \
						? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)

#define IOAT1_CHANCMD_OFFSET		0x14	/*  8-bit DMA Channel Command Register */
#define IOAT2_CHANCMD_OFFSET		0x04	/*  8-bit DMA Channel Command Register */
#define IOAT_CHANCMD_OFFSET(ver)		((ver) < IOAT_VER_2_0 \
						? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
#define IOAT_CHANCMD_RESET			0x20
#define IOAT_CHANCMD_RESUME			0x10
#define IOAT_CHANCMD_ABORT			0x08
#define IOAT_CHANCMD_SUSPEND			0x04
#define IOAT_CHANCMD_APPEND			0x02
#define IOAT_CHANCMD_START			0x01

#define IOAT_CHANCMP_OFFSET			0x18	/* 64-bit Channel Completion Address Register */
#define IOAT_CHANCMP_OFFSET_LOW			0x18
#define IOAT_CHANCMP_OFFSET_HIGH		0x1C

#define IOAT_CDAR_OFFSET			0x20	/* 64-bit Current Descriptor Address Register */
#define IOAT_CDAR_OFFSET_LOW			0x20
#define IOAT_CDAR_OFFSET_HIGH			0x24

#define IOAT_CHANERR_OFFSET			0x28	/* 32-bit Channel Error Register */
#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR	0x0001
#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR	0x0002
#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR	0x0004
#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR	0x0008
#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR	0x0010
#define IOAT_CHANERR_CHANCMD_ERR		0x0020
#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR	0x0040
#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR	0x0080
#define IOAT_CHANERR_READ_DATA_ERR		0x0100
#define IOAT_CHANERR_WRITE_DATA_ERR		0x0200
#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR	0x0400
#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR	0x0800
#define IOAT_CHANERR_COMPLETION_ADDR_ERR	0x1000
#define IOAT_CHANERR_INT_CONFIGURATION_ERR	0x2000
#define IOAT_CHANERR_SOFT_ERR			0x4000
#define IOAT_CHANERR_UNAFFILIATED_ERR		0x8000

#define IOAT_CHANERR_MASK_OFFSET		0x2C	/* 32-bit Channel Error Register */

#endif /* _IOAT_REGISTERS_H_ */
Commit	Line	Data
0bbd5f4e	1	/*
3e037454	2	* Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
0bbd5f4e CL	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59
	16	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called COPYING.
	20	*/
	21	#ifndef _IOAT_REGISTERS_H_
	22	#define _IOAT_REGISTERS_H_
	23
3e037454 SN	24	#define IOAT_PCI_DMACTRL_OFFSET 0x48
	25	#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
	26	#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
0bbd5f4e CL	27
	28	/* MMIO Device Registers */
	29	#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
	30
	31	#define IOAT_XFERCAP_OFFSET 0x01 /* 8-bit */
	32	#define IOAT_XFERCAP_4KB 12
	33	#define IOAT_XFERCAP_8KB 13
	34	#define IOAT_XFERCAP_16KB 14
	35	#define IOAT_XFERCAP_32KB 15
	36	#define IOAT_XFERCAP_32GB 0
	37
	38	#define IOAT_GENCTRL_OFFSET 0x02 /* 8-bit */
	39	#define IOAT_GENCTRL_DEBUG_EN 0x01
	40
	41	#define IOAT_INTRCTRL_OFFSET 0x03 /* 8-bit */
	42	#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
	43	#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
	44	#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
7bb67c14	45	#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
0bbd5f4e CL	46
	47	#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
	48
	49	#define IOAT_VER_OFFSET 0x08 /* 8-bit */
	50	#define IOAT_VER_MAJOR_MASK 0xF0
	51	#define IOAT_VER_MINOR_MASK 0x0F
7bb67c14	52	#define GET_IOAT_VER_MAJOR(x) (((x) & IOAT_VER_MAJOR_MASK) >> 4)
0bbd5f4e CL	53	#define GET_IOAT_VER_MINOR(x) ((x) & IOAT_VER_MINOR_MASK)
	54
	55	#define IOAT_PERPORTOFFSET_OFFSET 0x0A /* 16-bit */
	56
	57	#define IOAT_INTRDELAY_OFFSET 0x0C /* 16-bit */
	58	#define IOAT_INTRDELAY_INT_DELAY_MASK 0x3FFF /* Interrupt Delay Time */
7bb67c14	59	#define IOAT_INTRDELAY_COALESE_SUPPORT 0x8000 /* Interrupt Coalescing Supported */
0bbd5f4e CL	60
	61	#define IOAT_DEVICE_STATUS_OFFSET 0x0E /* 16-bit */
	62	#define IOAT_DEVICE_STATUS_DEGRADED_MODE 0x0001
	63
0bbd5f4e CL	64	#define IOAT_CHANNEL_MMIO_SIZE 0x80 /* Each Channel MMIO space is this size */
	65
	66	/* DMA Channel Registers */
	67	#define IOAT_CHANCTRL_OFFSET 0x00 /* 16-bit Channel Control Register */
	68	#define IOAT_CHANCTRL_CHANNEL_PRIORITY_MASK 0xF000
	69	#define IOAT_CHANCTRL_CHANNEL_IN_USE 0x0100
	70	#define IOAT_CHANCTRL_DESCRIPTOR_ADDR_SNOOP_CONTROL 0x0020
	71	#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
	72	#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
	73	#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
	74	#define IOAT_CHANCTRL_INT_DISABLE 0x0001
	75
7bb67c14 SN	76	#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
	77	#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
	78	#define IOAT_DMA_COMP_V2 0x0002 /* Compatibility with DMA version 2 */
	79
	80
	81	#define IOAT1_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
	82	#define IOAT2_CHANSTS_OFFSET 0x08 /* 64-bit Channel Status Register */
	83	#define IOAT_CHANSTS_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
	84	? IOAT1_CHANSTS_OFFSET : IOAT2_CHANSTS_OFFSET)
	85	#define IOAT1_CHANSTS_OFFSET_LOW 0x04
	86	#define IOAT2_CHANSTS_OFFSET_LOW 0x08
	87	#define IOAT_CHANSTS_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
	88	? IOAT1_CHANSTS_OFFSET_LOW : IOAT2_CHANSTS_OFFSET_LOW)
	89	#define IOAT1_CHANSTS_OFFSET_HIGH 0x08
	90	#define IOAT2_CHANSTS_OFFSET_HIGH 0x0C
	91	#define IOAT_CHANSTS_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
	92	? IOAT1_CHANSTS_OFFSET_HIGH : IOAT2_CHANSTS_OFFSET_HIGH)
	93	#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR ~0x3F
0bbd5f4e	94	#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010
7bb67c14	95	#define IOAT_CHANSTS_UNAFFILIATED_ERR 0x0000000000000008
0bbd5f4e CL	96	#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007
	97	#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0
	98	#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_DONE 0x1
	99	#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_SUSPENDED 0x2
	100	#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED 0x3
	101
0bbd5f4e	102
7bb67c14 SN	103
	104	#define IOAT_CHAN_DMACOUNT_OFFSET 0x06 /* 16-bit DMA Count register */
	105
	106	#define IOAT_DCACTRL_OFFSET 0x30 /* 32 bit Direct Cache Access Control Register */
	107	#define IOAT_DCACTRL_CMPL_WRITE_ENABLE 0x10000
	108	#define IOAT_DCACTRL_TARGET_CPU_MASK 0xFFFF /* APIC ID */
	109
	110	/* CB DCA Memory Space Registers */
	111	#define IOAT_DCAOFFSET_OFFSET 0x14
	112	/* CB_BAR + IOAT_DCAOFFSET value */
	113	#define IOAT_DCA_VER_OFFSET 0x00
	114	#define IOAT_DCA_VER_MAJOR_MASK 0xF0
	115	#define IOAT_DCA_VER_MINOR_MASK 0x0F
	116
	117	#define IOAT_DCA_COMP_OFFSET 0x02
	118	#define IOAT_DCA_COMP_V1 0x1
	119
	120	#define IOAT_FSB_CAPABILITY_OFFSET 0x04
	121	#define IOAT_FSB_CAPABILITY_PREFETCH 0x1
	122
	123	#define IOAT_PCI_CAPABILITY_OFFSET 0x06
	124	#define IOAT_PCI_CAPABILITY_MEMWR 0x1
	125
	126	#define IOAT_FSB_CAP_ENABLE_OFFSET 0x08
	127	#define IOAT_FSB_CAP_ENABLE_PREFETCH 0x1
	128
	129	#define IOAT_PCI_CAP_ENABLE_OFFSET 0x0A
	130	#define IOAT_PCI_CAP_ENABLE_MEMWR 0x1
	131
	132	#define IOAT_APICID_TAG_MAP_OFFSET 0x0C
	133	#define IOAT_APICID_TAG_MAP_TAG0 0x0000000F
	134	#define IOAT_APICID_TAG_MAP_TAG0_SHIFT 0
	135	#define IOAT_APICID_TAG_MAP_TAG1 0x000000F0
	136	#define IOAT_APICID_TAG_MAP_TAG1_SHIFT 4
	137	#define IOAT_APICID_TAG_MAP_TAG2 0x00000F00
	138	#define IOAT_APICID_TAG_MAP_TAG2_SHIFT 8
	139	#define IOAT_APICID_TAG_MAP_TAG3 0x0000F000
	140	#define IOAT_APICID_TAG_MAP_TAG3_SHIFT 12
	141	#define IOAT_APICID_TAG_MAP_TAG4 0x000F0000
	142	#define IOAT_APICID_TAG_MAP_TAG4_SHIFT 16
	143	#define IOAT_APICID_TAG_CB2_VALID 0x8080808080
	144
	145	#define IOAT_DCA_GREQID_OFFSET 0x10
	146	#define IOAT_DCA_GREQID_SIZE 0x04
	147	#define IOAT_DCA_GREQID_MASK 0xFFFF
	148	#define IOAT_DCA_GREQID_IGNOREFUN 0x10000000
	149	#define IOAT_DCA_GREQID_VALID 0x20000000
	150	#define IOAT_DCA_GREQID_LASTID 0x80000000
	151
	152
	153
	154	#define IOAT1_CHAINADDR_OFFSET 0x0C /* 64-bit Descriptor Chain Address Register */
	155	#define IOAT2_CHAINADDR_OFFSET 0x10 /* 64-bit Descriptor Chain Address Register */
	156	#define IOAT_CHAINADDR_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
	157	? IOAT1_CHAINADDR_OFFSET : IOAT2_CHAINADDR_OFFSET)
	158	#define IOAT1_CHAINADDR_OFFSET_LOW 0x0C
	159	#define IOAT2_CHAINADDR_OFFSET_LOW 0x10
	160	#define IOAT_CHAINADDR_OFFSET_LOW(ver) ((ver) < IOAT_VER_2_0 \
	161	? IOAT1_CHAINADDR_OFFSET_LOW : IOAT2_CHAINADDR_OFFSET_LOW)
	162	#define IOAT1_CHAINADDR_OFFSET_HIGH 0x10
	163	#define IOAT2_CHAINADDR_OFFSET_HIGH 0x14
	164	#define IOAT_CHAINADDR_OFFSET_HIGH(ver) ((ver) < IOAT_VER_2_0 \
	165	? IOAT1_CHAINADDR_OFFSET_HIGH : IOAT2_CHAINADDR_OFFSET_HIGH)
	166
167	#define IOAT1_CHANCMD_OFFSET 0x14 /* 8-bit DMA Channel Command Register */
168	#define IOAT2_CHANCMD_OFFSET 0x04 /* 8-bit DMA Channel Command Register */
169	#define IOAT_CHANCMD_OFFSET(ver) ((ver) < IOAT_VER_2_0 \
170	? IOAT1_CHANCMD_OFFSET : IOAT2_CHANCMD_OFFSET)
0bbd5f4e CL	171	#define IOAT_CHANCMD_RESET 0x20
	172	#define IOAT_CHANCMD_RESUME 0x10
	173	#define IOAT_CHANCMD_ABORT 0x08
	174	#define IOAT_CHANCMD_SUSPEND 0x04
	175	#define IOAT_CHANCMD_APPEND 0x02
	176	#define IOAT_CHANCMD_START 0x01
	177
	178	#define IOAT_CHANCMP_OFFSET 0x18 /* 64-bit Channel Completion Address Register */
	179	#define IOAT_CHANCMP_OFFSET_LOW 0x18
	180	#define IOAT_CHANCMP_OFFSET_HIGH 0x1C
	181
	182	#define IOAT_CDAR_OFFSET 0x20 /* 64-bit Current Descriptor Address Register */
	183	#define IOAT_CDAR_OFFSET_LOW 0x20
	184	#define IOAT_CDAR_OFFSET_HIGH 0x24
	185
	186	#define IOAT_CHANERR_OFFSET 0x28 /* 32-bit Channel Error Register */
	187	#define IOAT_CHANERR_DMA_TRANSFER_SRC_ADDR_ERR 0x0001
	188	#define IOAT_CHANERR_DMA_TRANSFER_DEST_ADDR_ERR 0x0002
	189	#define IOAT_CHANERR_NEXT_DESCRIPTOR_ADDR_ERR 0x0004
	190	#define IOAT_CHANERR_NEXT_DESCRIPTOR_ALIGNMENT_ERR 0x0008
	191	#define IOAT_CHANERR_CHAIN_ADDR_VALUE_ERR 0x0010
	192	#define IOAT_CHANERR_CHANCMD_ERR 0x0020
	193	#define IOAT_CHANERR_CHIPSET_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0040
	194	#define IOAT_CHANERR_DMA_UNCORRECTABLE_DATA_INTEGRITY_ERR 0x0080
	195	#define IOAT_CHANERR_READ_DATA_ERR 0x0100
	196	#define IOAT_CHANERR_WRITE_DATA_ERR 0x0200
	197	#define IOAT_CHANERR_DESCRIPTOR_CONTROL_ERR 0x0400
	198	#define IOAT_CHANERR_DESCRIPTOR_LENGTH_ERR 0x0800
	199	#define IOAT_CHANERR_COMPLETION_ADDR_ERR 0x1000
	200	#define IOAT_CHANERR_INT_CONFIGURATION_ERR 0x2000
	201	#define IOAT_CHANERR_SOFT_ERR 0x4000
7bb67c14	202	#define IOAT_CHANERR_UNAFFILIATED_ERR 0x8000
0bbd5f4e CL	203
	204	#define IOAT_CHANERR_MASK_OFFSET 0x2C /* 32-bit Channel Error Register */
	205
	206	#endif /* _IOAT_REGISTERS_H_ */