[net-next-2.6.git] / drivers / dma / ioat / dma_v2.h

/*
 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
#ifndef IOATDMA_V2_H
#define IOATDMA_V2_H

#include <linux/dmaengine.h>
#include "dma.h"
#include "hw.h"


extern int ioat_pending_level;
extern int ioat_ring_alloc_order;

/*
 * workaround for IOAT ver.3.0 null descriptor issue
 * (channel returns error when size is 0)
 */
#define NULL_DESC_BUFFER_SIZE 1

#define IOAT_MAX_ORDER 16
#define ioat_get_alloc_order() \
	(min(ioat_ring_alloc_order, IOAT_MAX_ORDER))
#define ioat_get_max_alloc_order() \
	(min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER))

/* struct ioat2_dma_chan - ioat v2 / v3 channel attributes
 * @base: common ioat channel parameters
 * @xfercap_log; log2 of channel max transfer length (for fast division)
 * @head: allocated index
 * @issued: hardware notification point
 * @tail: cleanup index
 * @dmacount: identical to 'head' except for occasionally resetting to zero
 * @alloc_order: log2 of the number of allocated descriptors
 * @ring: software ring buffer implementation of hardware ring
 * @ring_lock: protects ring attributes
 */
struct ioat2_dma_chan {
	struct ioat_chan_common base;
	size_t xfercap_log;
	u16 head;
	u16 issued;
	u16 tail;
	u16 dmacount;
	u16 alloc_order;
	struct ioat_ring_ent **ring;
	spinlock_t ring_lock;
};

static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c)
{
	struct ioat_chan_common *chan = to_chan_common(c);

	return container_of(chan, struct ioat2_dma_chan, base);
}

static inline u16 ioat2_ring_mask(struct ioat2_dma_chan *ioat)
{
	return (1 << ioat->alloc_order) - 1;
}

/* count of descriptors in flight with the engine */
static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat)
{
	return (ioat->head - ioat->tail) & ioat2_ring_mask(ioat);
}

/* count of descriptors pending submission to hardware */
static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat)
{
	return (ioat->head - ioat->issued) & ioat2_ring_mask(ioat);
}

static inline u16 ioat2_ring_space(struct ioat2_dma_chan *ioat)
{
	u16 num_descs = ioat2_ring_mask(ioat) + 1;
	u16 active = ioat2_ring_active(ioat);

	BUG_ON(active > num_descs);

	return num_descs - active;
}

/* assumes caller already checked space */
static inline u16 ioat2_desc_alloc(struct ioat2_dma_chan *ioat, u16 len)
{
	ioat->head += len;
	return ioat->head - len;
}

static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len)
{
	u16 num_descs = len >> ioat->xfercap_log;

	num_descs += !!(len & ((1 << ioat->xfercap_log) - 1));
	return num_descs;
}

/**
 * struct ioat_ring_ent - wrapper around hardware descriptor
 * @hw: hardware DMA descriptor (for memcpy)
 * @fill: hardware fill descriptor
 * @xor: hardware xor descriptor
 * @xor_ex: hardware xor extension descriptor
 * @pq: hardware pq descriptor
 * @pq_ex: hardware pq extension descriptor
 * @pqu: hardware pq update descriptor
 * @raw: hardware raw (un-typed) descriptor
 * @txd: the generic software descriptor for all engines
 * @len: total transaction length for unmap
 * @result: asynchronous result of validate operations
 * @id: identifier for debug
 */

struct ioat_ring_ent {
	union {
		struct ioat_dma_descriptor *hw;
		struct ioat_fill_descriptor *fill;
		struct ioat_xor_descriptor *xor;
		struct ioat_xor_ext_descriptor *xor_ex;
		struct ioat_pq_descriptor *pq;
		struct ioat_pq_ext_descriptor *pq_ex;
		struct ioat_pq_update_descriptor *pqu;
		struct ioat_raw_descriptor *raw;
	};
	size_t len;
	struct dma_async_tx_descriptor txd;
	enum sum_check_flags *result;
	#ifdef DEBUG
	int id;
	#endif
};

static inline struct ioat_ring_ent *
ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx)
{
	return ioat->ring[idx & ioat2_ring_mask(ioat)];
}

static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
{
	struct ioat_chan_common *chan = &ioat->base;

	writel(addr & 0x00000000FFFFFFFF,
	       chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
	writel(addr >> 32,
	       chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
}

int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca);
int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca);
struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
struct dca_provider * __devinit ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
int ioat2_alloc_and_lock(u16 *idx, struct ioat2_dma_chan *ioat, int num_descs);
int ioat2_enumerate_channels(struct ioatdma_device *device);
struct dma_async_tx_descriptor *
ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
			   dma_addr_t dma_src, size_t len, unsigned long flags);
void ioat2_issue_pending(struct dma_chan *chan);
int ioat2_alloc_chan_resources(struct dma_chan *c);
void ioat2_free_chan_resources(struct dma_chan *c);
void __ioat2_restart_chan(struct ioat2_dma_chan *ioat);
bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
void __ioat2_issue_pending(struct ioat2_dma_chan *ioat);
void ioat2_cleanup_event(unsigned long data);
void ioat2_timer_event(unsigned long data);
int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo);
int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo);
extern struct kobj_type ioat2_ktype;
extern struct kmem_cache *ioat2_cache;
#endif /* IOATDMA_V2_H */
Commit	Line	Data
5cbafa65 DW	1	/*
	2	* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License as published by the Free
	6	* Software Foundation; either version 2 of the License, or (at your option)
	7	* any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc., 59
	16	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called COPYING.
	20	*/
	21	#ifndef IOATDMA_V2_H
	22	#define IOATDMA_V2_H
	23
	24	#include <linux/dmaengine.h>
	25	#include "dma.h"
	26	#include "hw.h"
	27
	28
	29	extern int ioat_pending_level;
bf40a686	30	extern int ioat_ring_alloc_order;
5cbafa65 DW	31
	32	/*
	33	* workaround for IOAT ver.3.0 null descriptor issue
	34	* (channel returns error when size is 0)
	35	*/
	36	#define NULL_DESC_BUFFER_SIZE 1
	37
	38	#define IOAT_MAX_ORDER 16
	39	#define ioat_get_alloc_order() \
	40	(min(ioat_ring_alloc_order, IOAT_MAX_ORDER))
a309218a DW	41	#define ioat_get_max_alloc_order() \
a309218a DW	42	(min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER))
5cbafa65 DW	43
	44	/* struct ioat2_dma_chan - ioat v2 / v3 channel attributes
	45	* @base: common ioat channel parameters
	46	* @xfercap_log; log2 of channel max transfer length (for fast division)
	47	* @head: allocated index
	48	* @issued: hardware notification point
	49	* @tail: cleanup index
5cbafa65 DW	50	* @dmacount: identical to 'head' except for occasionally resetting to zero
	51	* @alloc_order: log2 of the number of allocated descriptors
	52	* @ring: software ring buffer implementation of hardware ring
	53	* @ring_lock: protects ring attributes
	54	*/
	55	struct ioat2_dma_chan {
	56	struct ioat_chan_common base;
	57	size_t xfercap_log;
	58	u16 head;
	59	u16 issued;
	60	u16 tail;
	61	u16 dmacount;
	62	u16 alloc_order;
5cbafa65 DW	63	struct ioat_ring_ent **ring;
	64	spinlock_t ring_lock;
	65	};
	66
	67	static inline struct ioat2_dma_chan to_ioat2_chan(struct dma_chan c)
	68	{
	69	struct ioat_chan_common *chan = to_chan_common(c);
	70
	71	return container_of(chan, struct ioat2_dma_chan, base);
	72	}
	73
	74	static inline u16 ioat2_ring_mask(struct ioat2_dma_chan *ioat)
	75	{
	76	return (1 << ioat->alloc_order) - 1;
	77	}
	78
	79	/* count of descriptors in flight with the engine */
	80	static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat)
	81	{
	82	return (ioat->head - ioat->tail) & ioat2_ring_mask(ioat);
	83	}
	84
	85	/* count of descriptors pending submission to hardware */
	86	static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat)
	87	{
	88	return (ioat->head - ioat->issued) & ioat2_ring_mask(ioat);
	89	}
	90
	91	static inline u16 ioat2_ring_space(struct ioat2_dma_chan *ioat)
	92	{
	93	u16 num_descs = ioat2_ring_mask(ioat) + 1;
	94	u16 active = ioat2_ring_active(ioat);
	95
	96	BUG_ON(active > num_descs);
	97
	98	return num_descs - active;
	99	}
	100
	101	/* assumes caller already checked space */
	102	static inline u16 ioat2_desc_alloc(struct ioat2_dma_chan *ioat, u16 len)
	103	{
	104	ioat->head += len;
	105	return ioat->head - len;
	106	}
	107
	108	static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len)
	109	{
	110	u16 num_descs = len >> ioat->xfercap_log;
	111
	112	num_descs += !!(len & ((1 << ioat->xfercap_log) - 1));
	113	return num_descs;
	114	}
	115
2aec048c DW	116	/**
	117	* struct ioat_ring_ent - wrapper around hardware descriptor
	118	* @hw: hardware DMA descriptor (for memcpy)
	119	* @fill: hardware fill descriptor
	120	* @xor: hardware xor descriptor
	121	* @xor_ex: hardware xor extension descriptor
	122	* @pq: hardware pq descriptor
	123	* @pq_ex: hardware pq extension descriptor
	124	* @pqu: hardware pq update descriptor
	125	* @raw: hardware raw (un-typed) descriptor
	126	* @txd: the generic software descriptor for all engines
	127	* @len: total transaction length for unmap
b094ad3b	128	* @result: asynchronous result of validate operations
2aec048c DW	129	* @id: identifier for debug
	130	*/
	131
5cbafa65	132	struct ioat_ring_ent {
2aec048c DW	133	union {
	134	struct ioat_dma_descriptor *hw;
	135	struct ioat_fill_descriptor *fill;
	136	struct ioat_xor_descriptor *xor;
	137	struct ioat_xor_ext_descriptor *xor_ex;
	138	struct ioat_pq_descriptor *pq;
	139	struct ioat_pq_ext_descriptor *pq_ex;
	140	struct ioat_pq_update_descriptor *pqu;
	141	struct ioat_raw_descriptor *raw;
	142	};
5cbafa65	143	size_t len;
162b96e6	144	struct dma_async_tx_descriptor txd;
b094ad3b	145	enum sum_check_flags *result;
6df9183a DW	146	#ifdef DEBUG
	147	int id;
	148	#endif
5cbafa65 DW	149	};
	150
	151	static inline struct ioat_ring_ent *
	152	ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx)
	153	{
	154	return ioat->ring[idx & ioat2_ring_mask(ioat)];
	155	}
	156
09c8a5b8 DW	157	static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
	158	{
	159	struct ioat_chan_common *chan = &ioat->base;
	160
	161	writel(addr & 0x00000000FFFFFFFF,
	162	chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
	163	writel(addr >> 32,
	164	chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
	165	}
	166
345d8523 DW	167	int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca);
	168	int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca);
	169	struct dca_provider * __devinit ioat2_dca_init(struct pci_dev pdev, void __iomem iobase);
	170	struct dca_provider * __devinit ioat3_dca_init(struct pci_dev pdev, void __iomem iobase);
bf40a686 DW	171	int ioat2_alloc_and_lock(u16 idx, struct ioat2_dma_chan ioat, int num_descs);
	172	int ioat2_enumerate_channels(struct ioatdma_device *device);
	173	struct dma_async_tx_descriptor *
	174	ioat2_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
	175	dma_addr_t dma_src, size_t len, unsigned long flags);
	176	void ioat2_issue_pending(struct dma_chan *chan);
	177	int ioat2_alloc_chan_resources(struct dma_chan *c);
	178	void ioat2_free_chan_resources(struct dma_chan *c);
bf40a686 DW	179	void __ioat2_restart_chan(struct ioat2_dma_chan *ioat);
bf40a686 DW	180	bool reshape_ring(struct ioat2_dma_chan *ioat, int order);
b094ad3b	181	void __ioat2_issue_pending(struct ioat2_dma_chan *ioat);
aa4d72ae	182	void ioat2_cleanup_event(unsigned long data);
e3232714	183	void ioat2_timer_event(unsigned long data);
a6d52d70 DW	184	int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo);
a6d52d70 DW	185	int ioat2_reset_sync(struct ioat_chan_common *chan, unsigned long tmo);
5669e31c	186	extern struct kobj_type ioat2_ktype;
162b96e6	187	extern struct kmem_cache *ioat2_cache;
5cbafa65	188	#endif /* IOATDMA_V2_H */