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0bbd5f4e | 1 | /* |
43d6e369 | 2 | * Intel I/OAT DMA Linux driver |
211a22ce | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. |
0bbd5f4e CL |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
43d6e369 SN |
6 | * under the terms and conditions of the GNU General Public License, |
7 | * version 2, as published by the Free Software Foundation. | |
0bbd5f4e CL |
8 | * |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
43d6e369 SN |
15 | * this program; if not, write to the Free Software Foundation, Inc., |
16 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
0bbd5f4e | 20 | * |
0bbd5f4e CL |
21 | */ |
22 | ||
23 | /* | |
24 | * This driver supports an Intel I/OAT DMA engine, which does asynchronous | |
25 | * copy operations. | |
26 | */ | |
27 | ||
28 | #include <linux/init.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/delay.h> | |
6b00c92c | 34 | #include <linux/dma-mapping.h> |
09177e85 | 35 | #include <linux/workqueue.h> |
3ad0b02e | 36 | #include <linux/i7300_idle.h> |
584ec227 DW |
37 | #include "dma.h" |
38 | #include "registers.h" | |
39 | #include "hw.h" | |
0bbd5f4e | 40 | |
5cbafa65 | 41 | int ioat_pending_level = 4; |
7bb67c14 SN |
42 | module_param(ioat_pending_level, int, 0644); |
43 | MODULE_PARM_DESC(ioat_pending_level, | |
44 | "high-water mark for pushing ioat descriptors (default: 4)"); | |
45 | ||
0bbd5f4e | 46 | /* internal functions */ |
5cbafa65 DW |
47 | static void ioat1_cleanup(struct ioat_dma_chan *ioat); |
48 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat); | |
3e037454 SN |
49 | |
50 | /** | |
51 | * ioat_dma_do_interrupt - handler used for single vector interrupt mode | |
52 | * @irq: interrupt id | |
53 | * @data: interrupt data | |
54 | */ | |
55 | static irqreturn_t ioat_dma_do_interrupt(int irq, void *data) | |
56 | { | |
57 | struct ioatdma_device *instance = data; | |
dcbc853a | 58 | struct ioat_chan_common *chan; |
3e037454 SN |
59 | unsigned long attnstatus; |
60 | int bit; | |
61 | u8 intrctrl; | |
62 | ||
63 | intrctrl = readb(instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
64 | ||
65 | if (!(intrctrl & IOAT_INTRCTRL_MASTER_INT_EN)) | |
66 | return IRQ_NONE; | |
67 | ||
68 | if (!(intrctrl & IOAT_INTRCTRL_INT_STATUS)) { | |
69 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
70 | return IRQ_NONE; | |
71 | } | |
72 | ||
73 | attnstatus = readl(instance->reg_base + IOAT_ATTNSTATUS_OFFSET); | |
74 | for_each_bit(bit, &attnstatus, BITS_PER_LONG) { | |
dcbc853a DW |
75 | chan = ioat_chan_by_index(instance, bit); |
76 | tasklet_schedule(&chan->cleanup_task); | |
3e037454 SN |
77 | } |
78 | ||
79 | writeb(intrctrl, instance->reg_base + IOAT_INTRCTRL_OFFSET); | |
80 | return IRQ_HANDLED; | |
81 | } | |
82 | ||
83 | /** | |
84 | * ioat_dma_do_interrupt_msix - handler used for vector-per-channel interrupt mode | |
85 | * @irq: interrupt id | |
86 | * @data: interrupt data | |
87 | */ | |
88 | static irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data) | |
89 | { | |
dcbc853a | 90 | struct ioat_chan_common *chan = data; |
3e037454 | 91 | |
dcbc853a | 92 | tasklet_schedule(&chan->cleanup_task); |
3e037454 SN |
93 | |
94 | return IRQ_HANDLED; | |
95 | } | |
96 | ||
5cbafa65 DW |
97 | static void ioat1_cleanup_tasklet(unsigned long data); |
98 | ||
99 | /* common channel initialization */ | |
100 | void ioat_init_channel(struct ioatdma_device *device, | |
101 | struct ioat_chan_common *chan, int idx, | |
102 | work_func_t work_fn, void (*tasklet)(unsigned long), | |
103 | unsigned long tasklet_data) | |
104 | { | |
105 | struct dma_device *dma = &device->common; | |
106 | ||
107 | chan->device = device; | |
108 | chan->reg_base = device->reg_base + (0x80 * (idx + 1)); | |
109 | INIT_DELAYED_WORK(&chan->work, work_fn); | |
110 | spin_lock_init(&chan->cleanup_lock); | |
111 | chan->common.device = dma; | |
112 | list_add_tail(&chan->common.device_node, &dma->channels); | |
113 | device->idx[idx] = chan; | |
114 | tasklet_init(&chan->cleanup_task, tasklet, tasklet_data); | |
115 | tasklet_disable(&chan->cleanup_task); | |
116 | } | |
117 | ||
118 | static void ioat1_reset_part2(struct work_struct *work); | |
3e037454 SN |
119 | |
120 | /** | |
5cbafa65 | 121 | * ioat1_dma_enumerate_channels - find and initialize the device's channels |
3e037454 SN |
122 | * @device: the device to be enumerated |
123 | */ | |
5cbafa65 | 124 | static int ioat1_enumerate_channels(struct ioatdma_device *device) |
0bbd5f4e CL |
125 | { |
126 | u8 xfercap_scale; | |
127 | u32 xfercap; | |
128 | int i; | |
dcbc853a | 129 | struct ioat_dma_chan *ioat; |
e6c0b69a | 130 | struct device *dev = &device->pdev->dev; |
f2427e27 | 131 | struct dma_device *dma = &device->common; |
0bbd5f4e | 132 | |
f2427e27 DW |
133 | INIT_LIST_HEAD(&dma->channels); |
134 | dma->chancnt = readb(device->reg_base + IOAT_CHANCNT_OFFSET); | |
bb320786 DW |
135 | dma->chancnt &= 0x1f; /* bits [4:0] valid */ |
136 | if (dma->chancnt > ARRAY_SIZE(device->idx)) { | |
137 | dev_warn(dev, "(%d) exceeds max supported channels (%zu)\n", | |
138 | dma->chancnt, ARRAY_SIZE(device->idx)); | |
139 | dma->chancnt = ARRAY_SIZE(device->idx); | |
140 | } | |
e3828811 | 141 | xfercap_scale = readb(device->reg_base + IOAT_XFERCAP_OFFSET); |
bb320786 | 142 | xfercap_scale &= 0x1f; /* bits [4:0] valid */ |
0bbd5f4e | 143 | xfercap = (xfercap_scale == 0 ? -1 : (1UL << xfercap_scale)); |
6df9183a | 144 | dev_dbg(dev, "%s: xfercap = %d\n", __func__, xfercap); |
0bbd5f4e | 145 | |
f371be63 | 146 | #ifdef CONFIG_I7300_IDLE_IOAT_CHANNEL |
f2427e27 DW |
147 | if (i7300_idle_platform_probe(NULL, NULL, 1) == 0) |
148 | dma->chancnt--; | |
27471fdb | 149 | #endif |
f2427e27 | 150 | for (i = 0; i < dma->chancnt; i++) { |
dcbc853a | 151 | ioat = devm_kzalloc(dev, sizeof(*ioat), GFP_KERNEL); |
5cbafa65 | 152 | if (!ioat) |
0bbd5f4e | 153 | break; |
0bbd5f4e | 154 | |
5cbafa65 DW |
155 | ioat_init_channel(device, &ioat->base, i, |
156 | ioat1_reset_part2, | |
157 | ioat1_cleanup_tasklet, | |
158 | (unsigned long) ioat); | |
dcbc853a | 159 | ioat->xfercap = xfercap; |
dcbc853a DW |
160 | spin_lock_init(&ioat->desc_lock); |
161 | INIT_LIST_HEAD(&ioat->free_desc); | |
162 | INIT_LIST_HEAD(&ioat->used_desc); | |
0bbd5f4e | 163 | } |
5cbafa65 DW |
164 | dma->chancnt = i; |
165 | return i; | |
0bbd5f4e CL |
166 | } |
167 | ||
711924b1 SN |
168 | /** |
169 | * ioat_dma_memcpy_issue_pending - push potentially unrecognized appended | |
170 | * descriptors to hw | |
171 | * @chan: DMA channel handle | |
172 | */ | |
bc3c7025 | 173 | static inline void |
dcbc853a | 174 | __ioat1_dma_memcpy_issue_pending(struct ioat_dma_chan *ioat) |
711924b1 | 175 | { |
dcbc853a DW |
176 | void __iomem *reg_base = ioat->base.reg_base; |
177 | ||
6df9183a DW |
178 | dev_dbg(to_dev(&ioat->base), "%s: pending: %d\n", |
179 | __func__, ioat->pending); | |
dcbc853a DW |
180 | ioat->pending = 0; |
181 | writeb(IOAT_CHANCMD_APPEND, reg_base + IOAT1_CHANCMD_OFFSET); | |
711924b1 SN |
182 | } |
183 | ||
184 | static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan) | |
185 | { | |
dcbc853a | 186 | struct ioat_dma_chan *ioat = to_ioat_chan(chan); |
711924b1 | 187 | |
dcbc853a DW |
188 | if (ioat->pending > 0) { |
189 | spin_lock_bh(&ioat->desc_lock); | |
190 | __ioat1_dma_memcpy_issue_pending(ioat); | |
191 | spin_unlock_bh(&ioat->desc_lock); | |
711924b1 SN |
192 | } |
193 | } | |
194 | ||
09177e85 | 195 | /** |
5cbafa65 | 196 | * ioat1_reset_part2 - reinit the channel after a reset |
09177e85 | 197 | */ |
5cbafa65 | 198 | static void ioat1_reset_part2(struct work_struct *work) |
09177e85 | 199 | { |
dcbc853a DW |
200 | struct ioat_chan_common *chan; |
201 | struct ioat_dma_chan *ioat; | |
09177e85 | 202 | struct ioat_desc_sw *desc; |
5cbafa65 DW |
203 | int dmacount; |
204 | bool start_null = false; | |
09177e85 | 205 | |
dcbc853a DW |
206 | chan = container_of(work, struct ioat_chan_common, work.work); |
207 | ioat = container_of(chan, struct ioat_dma_chan, base); | |
208 | spin_lock_bh(&chan->cleanup_lock); | |
209 | spin_lock_bh(&ioat->desc_lock); | |
09177e85 | 210 | |
4fb9b9e8 | 211 | *chan->completion = 0; |
dcbc853a | 212 | ioat->pending = 0; |
09177e85 | 213 | |
5cbafa65 DW |
214 | /* count the descriptors waiting */ |
215 | dmacount = 0; | |
dcbc853a DW |
216 | if (ioat->used_desc.prev) { |
217 | desc = to_ioat_desc(ioat->used_desc.prev); | |
09177e85 | 218 | do { |
5cbafa65 | 219 | dmacount++; |
09177e85 | 220 | desc = to_ioat_desc(desc->node.next); |
dcbc853a | 221 | } while (&desc->node != ioat->used_desc.next); |
09177e85 MS |
222 | } |
223 | ||
5cbafa65 DW |
224 | if (dmacount) { |
225 | /* | |
226 | * write the new starting descriptor address | |
227 | * this puts channel engine into ARMED state | |
228 | */ | |
229 | desc = to_ioat_desc(ioat->used_desc.prev); | |
bc3c7025 | 230 | writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, |
dcbc853a | 231 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); |
bc3c7025 | 232 | writel(((u64) desc->txd.phys) >> 32, |
dcbc853a | 233 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); |
09177e85 | 234 | |
dcbc853a DW |
235 | writeb(IOAT_CHANCMD_START, chan->reg_base |
236 | + IOAT_CHANCMD_OFFSET(chan->device->version)); | |
5cbafa65 DW |
237 | } else |
238 | start_null = true; | |
239 | spin_unlock_bh(&ioat->desc_lock); | |
240 | spin_unlock_bh(&chan->cleanup_lock); | |
09177e85 | 241 | |
dcbc853a | 242 | dev_err(to_dev(chan), |
09177e85 | 243 | "chan%d reset - %d descs waiting, %d total desc\n", |
5cbafa65 | 244 | chan_num(chan), dmacount, ioat->desccount); |
09177e85 | 245 | |
5cbafa65 DW |
246 | if (start_null) |
247 | ioat1_dma_start_null_desc(ioat); | |
09177e85 MS |
248 | } |
249 | ||
250 | /** | |
5cbafa65 | 251 | * ioat1_reset_channel - restart a channel |
dcbc853a | 252 | * @ioat: IOAT DMA channel handle |
09177e85 | 253 | */ |
5cbafa65 | 254 | static void ioat1_reset_channel(struct ioat_dma_chan *ioat) |
09177e85 | 255 | { |
dcbc853a DW |
256 | struct ioat_chan_common *chan = &ioat->base; |
257 | void __iomem *reg_base = chan->reg_base; | |
09177e85 MS |
258 | u32 chansts, chanerr; |
259 | ||
dcbc853a | 260 | if (!ioat->used_desc.prev) |
09177e85 MS |
261 | return; |
262 | ||
6df9183a | 263 | dev_dbg(to_dev(chan), "%s\n", __func__); |
dcbc853a | 264 | chanerr = readl(reg_base + IOAT_CHANERR_OFFSET); |
4fb9b9e8 | 265 | chansts = *chan->completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS; |
09177e85 | 266 | if (chanerr) { |
dcbc853a | 267 | dev_err(to_dev(chan), |
09177e85 | 268 | "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n", |
dcbc853a DW |
269 | chan_num(chan), chansts, chanerr); |
270 | writel(chanerr, reg_base + IOAT_CHANERR_OFFSET); | |
09177e85 MS |
271 | } |
272 | ||
273 | /* | |
274 | * whack it upside the head with a reset | |
275 | * and wait for things to settle out. | |
276 | * force the pending count to a really big negative | |
277 | * to make sure no one forces an issue_pending | |
278 | * while we're waiting. | |
279 | */ | |
280 | ||
dcbc853a DW |
281 | spin_lock_bh(&ioat->desc_lock); |
282 | ioat->pending = INT_MIN; | |
09177e85 | 283 | writeb(IOAT_CHANCMD_RESET, |
dcbc853a DW |
284 | reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
285 | spin_unlock_bh(&ioat->desc_lock); | |
09177e85 MS |
286 | |
287 | /* schedule the 2nd half instead of sleeping a long time */ | |
dcbc853a | 288 | schedule_delayed_work(&chan->work, RESET_DELAY); |
09177e85 MS |
289 | } |
290 | ||
291 | /** | |
5cbafa65 | 292 | * ioat1_chan_watchdog - watch for stuck channels |
09177e85 | 293 | */ |
5cbafa65 | 294 | static void ioat1_chan_watchdog(struct work_struct *work) |
09177e85 MS |
295 | { |
296 | struct ioatdma_device *device = | |
297 | container_of(work, struct ioatdma_device, work.work); | |
dcbc853a DW |
298 | struct ioat_dma_chan *ioat; |
299 | struct ioat_chan_common *chan; | |
09177e85 | 300 | int i; |
4fb9b9e8 DW |
301 | u64 completion; |
302 | u32 completion_low; | |
09177e85 MS |
303 | unsigned long compl_desc_addr_hw; |
304 | ||
305 | for (i = 0; i < device->common.chancnt; i++) { | |
dcbc853a DW |
306 | chan = ioat_chan_by_index(device, i); |
307 | ioat = container_of(chan, struct ioat_dma_chan, base); | |
09177e85 | 308 | |
5cbafa65 DW |
309 | if (/* have we started processing anything yet */ |
310 | chan->last_completion | |
311 | /* have we completed any since last watchdog cycle? */ | |
dcbc853a | 312 | && (chan->last_completion == chan->watchdog_completion) |
5cbafa65 | 313 | /* has TCP stuck on one cookie since last watchdog? */ |
dcbc853a DW |
314 | && (chan->watchdog_tcp_cookie == chan->watchdog_last_tcp_cookie) |
315 | && (chan->watchdog_tcp_cookie != chan->completed_cookie) | |
5cbafa65 DW |
316 | /* is there something in the chain to be processed? */ |
317 | /* CB1 chain always has at least the last one processed */ | |
dcbc853a DW |
318 | && (ioat->used_desc.prev != ioat->used_desc.next) |
319 | && ioat->pending == 0) { | |
09177e85 MS |
320 | |
321 | /* | |
322 | * check CHANSTS register for completed | |
323 | * descriptor address. | |
324 | * if it is different than completion writeback, | |
325 | * it is not zero | |
326 | * and it has changed since the last watchdog | |
327 | * we can assume that channel | |
328 | * is still working correctly | |
329 | * and the problem is in completion writeback. | |
330 | * update completion writeback | |
331 | * with actual CHANSTS value | |
332 | * else | |
333 | * try resetting the channel | |
334 | */ | |
335 | ||
4fb9b9e8 DW |
336 | /* we need to read the low address first as this |
337 | * causes the chipset to latch the upper bits | |
338 | * for the subsequent read | |
339 | */ | |
340 | completion_low = readl(chan->reg_base + | |
dcbc853a | 341 | IOAT_CHANSTS_OFFSET_LOW(chan->device->version)); |
4fb9b9e8 | 342 | completion = readl(chan->reg_base + |
dcbc853a | 343 | IOAT_CHANSTS_OFFSET_HIGH(chan->device->version)); |
4fb9b9e8 DW |
344 | completion <<= 32; |
345 | completion |= completion_low; | |
346 | compl_desc_addr_hw = completion & | |
347 | IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; | |
09177e85 MS |
348 | |
349 | if ((compl_desc_addr_hw != 0) | |
dcbc853a DW |
350 | && (compl_desc_addr_hw != chan->watchdog_completion) |
351 | && (compl_desc_addr_hw != chan->last_compl_desc_addr_hw)) { | |
352 | chan->last_compl_desc_addr_hw = compl_desc_addr_hw; | |
4fb9b9e8 | 353 | *chan->completion = completion; |
09177e85 | 354 | } else { |
5cbafa65 | 355 | ioat1_reset_channel(ioat); |
dcbc853a DW |
356 | chan->watchdog_completion = 0; |
357 | chan->last_compl_desc_addr_hw = 0; | |
09177e85 | 358 | } |
09177e85 | 359 | } else { |
dcbc853a DW |
360 | chan->last_compl_desc_addr_hw = 0; |
361 | chan->watchdog_completion = chan->last_completion; | |
09177e85 | 362 | } |
5cbafa65 | 363 | |
dcbc853a | 364 | chan->watchdog_last_tcp_cookie = chan->watchdog_tcp_cookie; |
09177e85 MS |
365 | } |
366 | ||
367 | schedule_delayed_work(&device->work, WATCHDOG_DELAY); | |
368 | } | |
369 | ||
7bb67c14 | 370 | static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx) |
7405f74b | 371 | { |
dcbc853a DW |
372 | struct dma_chan *c = tx->chan; |
373 | struct ioat_dma_chan *ioat = to_ioat_chan(c); | |
a0587bcf DW |
374 | struct ioat_desc_sw *desc = tx_to_ioat_desc(tx); |
375 | struct ioat_desc_sw *first; | |
376 | struct ioat_desc_sw *chain_tail; | |
7405f74b | 377 | dma_cookie_t cookie; |
7405f74b | 378 | |
dcbc853a | 379 | spin_lock_bh(&ioat->desc_lock); |
7405f74b | 380 | /* cookie incr and addition to used_list must be atomic */ |
dcbc853a | 381 | cookie = c->cookie; |
7405f74b DW |
382 | cookie++; |
383 | if (cookie < 0) | |
384 | cookie = 1; | |
dcbc853a DW |
385 | c->cookie = cookie; |
386 | tx->cookie = cookie; | |
6df9183a | 387 | dev_dbg(to_dev(&ioat->base), "%s: cookie: %d\n", __func__, cookie); |
7405f74b DW |
388 | |
389 | /* write address into NextDescriptor field of last desc in chain */ | |
a0587bcf | 390 | first = to_ioat_desc(tx->tx_list.next); |
dcbc853a | 391 | chain_tail = to_ioat_desc(ioat->used_desc.prev); |
a0587bcf DW |
392 | /* make descriptor updates globally visible before chaining */ |
393 | wmb(); | |
394 | chain_tail->hw->next = first->txd.phys; | |
dcbc853a | 395 | list_splice_tail_init(&tx->tx_list, &ioat->used_desc); |
6df9183a DW |
396 | dump_desc_dbg(ioat, chain_tail); |
397 | dump_desc_dbg(ioat, first); | |
a0587bcf | 398 | |
dcbc853a DW |
399 | ioat->pending += desc->tx_cnt; |
400 | if (ioat->pending >= ioat_pending_level) | |
401 | __ioat1_dma_memcpy_issue_pending(ioat); | |
402 | spin_unlock_bh(&ioat->desc_lock); | |
7405f74b | 403 | |
7bb67c14 SN |
404 | return cookie; |
405 | } | |
406 | ||
7bb67c14 SN |
407 | /** |
408 | * ioat_dma_alloc_descriptor - allocate and return a sw and hw descriptor pair | |
dcbc853a | 409 | * @ioat: the channel supplying the memory pool for the descriptors |
7bb67c14 SN |
410 | * @flags: allocation flags |
411 | */ | |
bc3c7025 | 412 | static struct ioat_desc_sw * |
dcbc853a | 413 | ioat_dma_alloc_descriptor(struct ioat_dma_chan *ioat, gfp_t flags) |
0bbd5f4e CL |
414 | { |
415 | struct ioat_dma_descriptor *desc; | |
416 | struct ioat_desc_sw *desc_sw; | |
8ab89567 | 417 | struct ioatdma_device *ioatdma_device; |
0bbd5f4e CL |
418 | dma_addr_t phys; |
419 | ||
dcbc853a | 420 | ioatdma_device = ioat->base.device; |
8ab89567 | 421 | desc = pci_pool_alloc(ioatdma_device->dma_pool, flags, &phys); |
0bbd5f4e CL |
422 | if (unlikely(!desc)) |
423 | return NULL; | |
424 | ||
425 | desc_sw = kzalloc(sizeof(*desc_sw), flags); | |
426 | if (unlikely(!desc_sw)) { | |
8ab89567 | 427 | pci_pool_free(ioatdma_device->dma_pool, desc, phys); |
0bbd5f4e CL |
428 | return NULL; |
429 | } | |
430 | ||
431 | memset(desc, 0, sizeof(*desc)); | |
7bb67c14 | 432 | |
5cbafa65 DW |
433 | dma_async_tx_descriptor_init(&desc_sw->txd, &ioat->base.common); |
434 | desc_sw->txd.tx_submit = ioat1_tx_submit; | |
0bbd5f4e | 435 | desc_sw->hw = desc; |
bc3c7025 | 436 | desc_sw->txd.phys = phys; |
6df9183a | 437 | set_desc_id(desc_sw, -1); |
0bbd5f4e CL |
438 | |
439 | return desc_sw; | |
440 | } | |
441 | ||
7bb67c14 SN |
442 | static int ioat_initial_desc_count = 256; |
443 | module_param(ioat_initial_desc_count, int, 0644); | |
444 | MODULE_PARM_DESC(ioat_initial_desc_count, | |
5cbafa65 | 445 | "ioat1: initial descriptors per channel (default: 256)"); |
7bb67c14 | 446 | /** |
5cbafa65 | 447 | * ioat1_dma_alloc_chan_resources - returns the number of allocated descriptors |
7bb67c14 SN |
448 | * @chan: the channel to be filled out |
449 | */ | |
5cbafa65 | 450 | static int ioat1_dma_alloc_chan_resources(struct dma_chan *c) |
0bbd5f4e | 451 | { |
dcbc853a DW |
452 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
453 | struct ioat_chan_common *chan = &ioat->base; | |
711924b1 | 454 | struct ioat_desc_sw *desc; |
0bbd5f4e CL |
455 | u32 chanerr; |
456 | int i; | |
457 | LIST_HEAD(tmp_list); | |
458 | ||
e4223976 | 459 | /* have we already been set up? */ |
dcbc853a DW |
460 | if (!list_empty(&ioat->free_desc)) |
461 | return ioat->desccount; | |
0bbd5f4e | 462 | |
43d6e369 | 463 | /* Setup register to interrupt and write completion status on error */ |
f6ab95b5 | 464 | writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET); |
0bbd5f4e | 465 | |
dcbc853a | 466 | chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); |
0bbd5f4e | 467 | if (chanerr) { |
dcbc853a DW |
468 | dev_err(to_dev(chan), "CHANERR = %x, clearing\n", chanerr); |
469 | writel(chanerr, chan->reg_base + IOAT_CHANERR_OFFSET); | |
0bbd5f4e CL |
470 | } |
471 | ||
472 | /* Allocate descriptors */ | |
7bb67c14 | 473 | for (i = 0; i < ioat_initial_desc_count; i++) { |
dcbc853a | 474 | desc = ioat_dma_alloc_descriptor(ioat, GFP_KERNEL); |
0bbd5f4e | 475 | if (!desc) { |
dcbc853a | 476 | dev_err(to_dev(chan), "Only %d initial descriptors\n", i); |
0bbd5f4e CL |
477 | break; |
478 | } | |
6df9183a | 479 | set_desc_id(desc, i); |
0bbd5f4e CL |
480 | list_add_tail(&desc->node, &tmp_list); |
481 | } | |
dcbc853a DW |
482 | spin_lock_bh(&ioat->desc_lock); |
483 | ioat->desccount = i; | |
484 | list_splice(&tmp_list, &ioat->free_desc); | |
dcbc853a | 485 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e CL |
486 | |
487 | /* allocate a completion writeback area */ | |
488 | /* doing 2 32bit writes to mmio since 1 64b write doesn't work */ | |
4fb9b9e8 DW |
489 | chan->completion = pci_pool_alloc(chan->device->completion_pool, |
490 | GFP_KERNEL, &chan->completion_dma); | |
491 | memset(chan->completion, 0, sizeof(*chan->completion)); | |
492 | writel(((u64) chan->completion_dma) & 0x00000000FFFFFFFF, | |
dcbc853a | 493 | chan->reg_base + IOAT_CHANCMP_OFFSET_LOW); |
4fb9b9e8 | 494 | writel(((u64) chan->completion_dma) >> 32, |
dcbc853a DW |
495 | chan->reg_base + IOAT_CHANCMP_OFFSET_HIGH); |
496 | ||
497 | tasklet_enable(&chan->cleanup_task); | |
5cbafa65 | 498 | ioat1_dma_start_null_desc(ioat); /* give chain to dma device */ |
6df9183a DW |
499 | dev_dbg(to_dev(chan), "%s: allocated %d descriptors\n", |
500 | __func__, ioat->desccount); | |
dcbc853a | 501 | return ioat->desccount; |
0bbd5f4e CL |
502 | } |
503 | ||
7bb67c14 | 504 | /** |
5cbafa65 | 505 | * ioat1_dma_free_chan_resources - release all the descriptors |
7bb67c14 SN |
506 | * @chan: the channel to be cleaned |
507 | */ | |
5cbafa65 | 508 | static void ioat1_dma_free_chan_resources(struct dma_chan *c) |
0bbd5f4e | 509 | { |
dcbc853a DW |
510 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
511 | struct ioat_chan_common *chan = &ioat->base; | |
512 | struct ioatdma_device *ioatdma_device = chan->device; | |
0bbd5f4e | 513 | struct ioat_desc_sw *desc, *_desc; |
0bbd5f4e CL |
514 | int in_use_descs = 0; |
515 | ||
c3d4f44f MS |
516 | /* Before freeing channel resources first check |
517 | * if they have been previously allocated for this channel. | |
518 | */ | |
dcbc853a | 519 | if (ioat->desccount == 0) |
c3d4f44f MS |
520 | return; |
521 | ||
dcbc853a | 522 | tasklet_disable(&chan->cleanup_task); |
5cbafa65 | 523 | ioat1_cleanup(ioat); |
0bbd5f4e | 524 | |
3e037454 SN |
525 | /* Delay 100ms after reset to allow internal DMA logic to quiesce |
526 | * before removing DMA descriptor resources. | |
527 | */ | |
7bb67c14 | 528 | writeb(IOAT_CHANCMD_RESET, |
dcbc853a | 529 | chan->reg_base + IOAT_CHANCMD_OFFSET(chan->device->version)); |
3e037454 | 530 | mdelay(100); |
0bbd5f4e | 531 | |
dcbc853a | 532 | spin_lock_bh(&ioat->desc_lock); |
6df9183a DW |
533 | list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { |
534 | dev_dbg(to_dev(chan), "%s: freeing %d from used list\n", | |
535 | __func__, desc_id(desc)); | |
536 | dump_desc_dbg(ioat, desc); | |
5cbafa65 DW |
537 | in_use_descs++; |
538 | list_del(&desc->node); | |
539 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, | |
540 | desc->txd.phys); | |
541 | kfree(desc); | |
542 | } | |
543 | list_for_each_entry_safe(desc, _desc, | |
544 | &ioat->free_desc, node) { | |
545 | list_del(&desc->node); | |
8ab89567 | 546 | pci_pool_free(ioatdma_device->dma_pool, desc->hw, |
bc3c7025 | 547 | desc->txd.phys); |
0bbd5f4e CL |
548 | kfree(desc); |
549 | } | |
dcbc853a | 550 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e | 551 | |
8ab89567 | 552 | pci_pool_free(ioatdma_device->completion_pool, |
4fb9b9e8 DW |
553 | chan->completion, |
554 | chan->completion_dma); | |
0bbd5f4e CL |
555 | |
556 | /* one is ok since we left it on there on purpose */ | |
557 | if (in_use_descs > 1) | |
dcbc853a | 558 | dev_err(to_dev(chan), "Freeing %d in use descriptors!\n", |
0bbd5f4e CL |
559 | in_use_descs - 1); |
560 | ||
4fb9b9e8 DW |
561 | chan->last_completion = 0; |
562 | chan->completion_dma = 0; | |
dcbc853a DW |
563 | chan->watchdog_completion = 0; |
564 | chan->last_compl_desc_addr_hw = 0; | |
565 | chan->watchdog_tcp_cookie = chan->watchdog_last_tcp_cookie = 0; | |
566 | ioat->pending = 0; | |
dcbc853a | 567 | ioat->desccount = 0; |
3e037454 | 568 | } |
7f2b291f | 569 | |
3e037454 | 570 | /** |
dcbc853a DW |
571 | * ioat1_dma_get_next_descriptor - return the next available descriptor |
572 | * @ioat: IOAT DMA channel handle | |
3e037454 SN |
573 | * |
574 | * Gets the next descriptor from the chain, and must be called with the | |
575 | * channel's desc_lock held. Allocates more descriptors if the channel | |
576 | * has run out. | |
577 | */ | |
7f2b291f | 578 | static struct ioat_desc_sw * |
dcbc853a | 579 | ioat1_dma_get_next_descriptor(struct ioat_dma_chan *ioat) |
3e037454 | 580 | { |
711924b1 | 581 | struct ioat_desc_sw *new; |
3e037454 | 582 | |
dcbc853a DW |
583 | if (!list_empty(&ioat->free_desc)) { |
584 | new = to_ioat_desc(ioat->free_desc.next); | |
3e037454 SN |
585 | list_del(&new->node); |
586 | } else { | |
587 | /* try to get another desc */ | |
dcbc853a | 588 | new = ioat_dma_alloc_descriptor(ioat, GFP_ATOMIC); |
711924b1 | 589 | if (!new) { |
dcbc853a | 590 | dev_err(to_dev(&ioat->base), "alloc failed\n"); |
711924b1 SN |
591 | return NULL; |
592 | } | |
3e037454 | 593 | } |
6df9183a DW |
594 | dev_dbg(to_dev(&ioat->base), "%s: allocated: %d\n", |
595 | __func__, desc_id(new)); | |
3e037454 SN |
596 | prefetch(new->hw); |
597 | return new; | |
0bbd5f4e CL |
598 | } |
599 | ||
bc3c7025 | 600 | static struct dma_async_tx_descriptor * |
dcbc853a | 601 | ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest, |
bc3c7025 | 602 | dma_addr_t dma_src, size_t len, unsigned long flags) |
0bbd5f4e | 603 | { |
dcbc853a | 604 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
a0587bcf DW |
605 | struct ioat_desc_sw *desc; |
606 | size_t copy; | |
607 | LIST_HEAD(chain); | |
608 | dma_addr_t src = dma_src; | |
609 | dma_addr_t dest = dma_dest; | |
610 | size_t total_len = len; | |
611 | struct ioat_dma_descriptor *hw = NULL; | |
612 | int tx_cnt = 0; | |
0bbd5f4e | 613 | |
dcbc853a | 614 | spin_lock_bh(&ioat->desc_lock); |
5cbafa65 | 615 | desc = ioat1_dma_get_next_descriptor(ioat); |
a0587bcf DW |
616 | do { |
617 | if (!desc) | |
618 | break; | |
0bbd5f4e | 619 | |
a0587bcf | 620 | tx_cnt++; |
dcbc853a | 621 | copy = min_t(size_t, len, ioat->xfercap); |
a0587bcf DW |
622 | |
623 | hw = desc->hw; | |
624 | hw->size = copy; | |
625 | hw->ctl = 0; | |
626 | hw->src_addr = src; | |
627 | hw->dst_addr = dest; | |
628 | ||
629 | list_add_tail(&desc->node, &chain); | |
630 | ||
631 | len -= copy; | |
632 | dest += copy; | |
633 | src += copy; | |
634 | if (len) { | |
635 | struct ioat_desc_sw *next; | |
636 | ||
637 | async_tx_ack(&desc->txd); | |
5cbafa65 | 638 | next = ioat1_dma_get_next_descriptor(ioat); |
a0587bcf | 639 | hw->next = next ? next->txd.phys : 0; |
6df9183a | 640 | dump_desc_dbg(ioat, desc); |
a0587bcf DW |
641 | desc = next; |
642 | } else | |
643 | hw->next = 0; | |
644 | } while (len); | |
645 | ||
646 | if (!desc) { | |
dcbc853a DW |
647 | struct ioat_chan_common *chan = &ioat->base; |
648 | ||
649 | dev_err(to_dev(chan), | |
5cbafa65 | 650 | "chan%d - get_next_desc failed\n", chan_num(chan)); |
dcbc853a DW |
651 | list_splice(&chain, &ioat->free_desc); |
652 | spin_unlock_bh(&ioat->desc_lock); | |
711924b1 | 653 | return NULL; |
09177e85 | 654 | } |
dcbc853a | 655 | spin_unlock_bh(&ioat->desc_lock); |
a0587bcf DW |
656 | |
657 | desc->txd.flags = flags; | |
658 | desc->tx_cnt = tx_cnt; | |
a0587bcf DW |
659 | desc->len = total_len; |
660 | list_splice(&chain, &desc->txd.tx_list); | |
661 | hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT); | |
662 | hw->ctl_f.compl_write = 1; | |
6df9183a | 663 | dump_desc_dbg(ioat, desc); |
a0587bcf DW |
664 | |
665 | return &desc->txd; | |
0bbd5f4e CL |
666 | } |
667 | ||
5cbafa65 | 668 | static void ioat1_cleanup_tasklet(unsigned long data) |
3e037454 SN |
669 | { |
670 | struct ioat_dma_chan *chan = (void *)data; | |
f6ab95b5 | 671 | |
5cbafa65 | 672 | ioat1_cleanup(chan); |
f6ab95b5 | 673 | writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET); |
3e037454 SN |
674 | } |
675 | ||
5cbafa65 DW |
676 | static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, |
677 | int direction, enum dma_ctrl_flags flags, bool dst) | |
e1d181ef | 678 | { |
5cbafa65 DW |
679 | if ((dst && (flags & DMA_COMPL_DEST_UNMAP_SINGLE)) || |
680 | (!dst && (flags & DMA_COMPL_SRC_UNMAP_SINGLE))) | |
681 | pci_unmap_single(pdev, addr, len, direction); | |
682 | else | |
683 | pci_unmap_page(pdev, addr, len, direction); | |
e1d181ef DW |
684 | } |
685 | ||
5cbafa65 DW |
686 | |
687 | void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags, | |
688 | size_t len, struct ioat_dma_descriptor *hw) | |
0bbd5f4e | 689 | { |
5cbafa65 DW |
690 | struct pci_dev *pdev = chan->device->pdev; |
691 | size_t offset = len - hw->size; | |
0bbd5f4e | 692 | |
5cbafa65 DW |
693 | if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) |
694 | ioat_unmap(pdev, hw->dst_addr - offset, len, | |
695 | PCI_DMA_FROMDEVICE, flags, 1); | |
0bbd5f4e | 696 | |
5cbafa65 DW |
697 | if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) |
698 | ioat_unmap(pdev, hw->src_addr - offset, len, | |
699 | PCI_DMA_TODEVICE, flags, 0); | |
700 | } | |
701 | ||
702 | unsigned long ioat_get_current_completion(struct ioat_chan_common *chan) | |
703 | { | |
704 | unsigned long phys_complete; | |
4fb9b9e8 | 705 | u64 completion; |
0bbd5f4e | 706 | |
4fb9b9e8 DW |
707 | completion = *chan->completion; |
708 | phys_complete = completion & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR; | |
0bbd5f4e | 709 | |
6df9183a DW |
710 | dev_dbg(to_dev(chan), "%s: phys_complete: %#llx\n", __func__, |
711 | (unsigned long long) phys_complete); | |
712 | ||
4fb9b9e8 | 713 | if ((completion & IOAT_CHANSTS_DMA_TRANSFER_STATUS) == |
43d6e369 | 714 | IOAT_CHANSTS_DMA_TRANSFER_STATUS_HALTED) { |
dcbc853a DW |
715 | dev_err(to_dev(chan), "Channel halted, chanerr = %x\n", |
716 | readl(chan->reg_base + IOAT_CHANERR_OFFSET)); | |
0bbd5f4e CL |
717 | |
718 | /* TODO do something to salvage the situation */ | |
719 | } | |
720 | ||
5cbafa65 DW |
721 | return phys_complete; |
722 | } | |
723 | ||
724 | /** | |
725 | * ioat1_cleanup - cleanup up finished descriptors | |
726 | * @chan: ioat channel to be cleaned up | |
727 | */ | |
728 | static void ioat1_cleanup(struct ioat_dma_chan *ioat) | |
729 | { | |
730 | struct ioat_chan_common *chan = &ioat->base; | |
731 | unsigned long phys_complete; | |
732 | struct ioat_desc_sw *desc, *_desc; | |
733 | dma_cookie_t cookie = 0; | |
734 | struct dma_async_tx_descriptor *tx; | |
735 | ||
4fb9b9e8 | 736 | prefetch(chan->completion); |
5cbafa65 DW |
737 | |
738 | if (!spin_trylock_bh(&chan->cleanup_lock)) | |
739 | return; | |
740 | ||
741 | phys_complete = ioat_get_current_completion(chan); | |
dcbc853a DW |
742 | if (phys_complete == chan->last_completion) { |
743 | spin_unlock_bh(&chan->cleanup_lock); | |
09177e85 MS |
744 | /* |
745 | * perhaps we're stuck so hard that the watchdog can't go off? | |
746 | * try to catch it after 2 seconds | |
747 | */ | |
5cbafa65 DW |
748 | if (time_after(jiffies, |
749 | chan->last_completion_time + HZ*WATCHDOG_DELAY)) { | |
750 | ioat1_chan_watchdog(&(chan->device->work.work)); | |
751 | chan->last_completion_time = jiffies; | |
09177e85 | 752 | } |
0bbd5f4e CL |
753 | return; |
754 | } | |
dcbc853a | 755 | chan->last_completion_time = jiffies; |
0bbd5f4e | 756 | |
3e037454 | 757 | cookie = 0; |
dcbc853a DW |
758 | if (!spin_trylock_bh(&ioat->desc_lock)) { |
759 | spin_unlock_bh(&chan->cleanup_lock); | |
09177e85 MS |
760 | return; |
761 | } | |
762 | ||
6df9183a DW |
763 | dev_dbg(to_dev(chan), "%s: phys_complete: %lx\n", |
764 | __func__, phys_complete); | |
5cbafa65 DW |
765 | list_for_each_entry_safe(desc, _desc, &ioat->used_desc, node) { |
766 | tx = &desc->txd; | |
767 | /* | |
768 | * Incoming DMA requests may use multiple descriptors, | |
769 | * due to exceeding xfercap, perhaps. If so, only the | |
770 | * last one will have a cookie, and require unmapping. | |
771 | */ | |
6df9183a | 772 | dump_desc_dbg(ioat, desc); |
5cbafa65 DW |
773 | if (tx->cookie) { |
774 | cookie = tx->cookie; | |
775 | ioat_dma_unmap(chan, tx->flags, desc->len, desc->hw); | |
776 | if (tx->callback) { | |
777 | tx->callback(tx->callback_param); | |
778 | tx->callback = NULL; | |
95218430 | 779 | } |
5cbafa65 | 780 | } |
0bbd5f4e | 781 | |
5cbafa65 DW |
782 | if (tx->phys != phys_complete) { |
783 | /* | |
784 | * a completed entry, but not the last, so clean | |
785 | * up if the client is done with the descriptor | |
786 | */ | |
787 | if (async_tx_test_ack(tx)) | |
788 | list_move_tail(&desc->node, &ioat->free_desc); | |
789 | else | |
bc3c7025 | 790 | tx->cookie = 0; |
5cbafa65 DW |
791 | } else { |
792 | /* | |
793 | * last used desc. Do not remove, so we can | |
794 | * append from it, but don't look at it next | |
795 | * time, either | |
796 | */ | |
797 | tx->cookie = 0; | |
0bbd5f4e | 798 | |
5cbafa65 | 799 | /* TODO check status bits? */ |
0bbd5f4e CL |
800 | break; |
801 | } | |
802 | } | |
803 | ||
dcbc853a | 804 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e | 805 | |
dcbc853a | 806 | chan->last_completion = phys_complete; |
0bbd5f4e | 807 | if (cookie != 0) |
dcbc853a | 808 | chan->completed_cookie = cookie; |
0bbd5f4e | 809 | |
dcbc853a | 810 | spin_unlock_bh(&chan->cleanup_lock); |
0bbd5f4e CL |
811 | } |
812 | ||
bc3c7025 | 813 | static enum dma_status |
5cbafa65 DW |
814 | ioat1_dma_is_complete(struct dma_chan *c, dma_cookie_t cookie, |
815 | dma_cookie_t *done, dma_cookie_t *used) | |
0bbd5f4e | 816 | { |
dcbc853a | 817 | struct ioat_dma_chan *ioat = to_ioat_chan(c); |
0bbd5f4e | 818 | |
5cbafa65 DW |
819 | if (ioat_is_complete(c, cookie, done, used) == DMA_SUCCESS) |
820 | return DMA_SUCCESS; | |
0bbd5f4e | 821 | |
5cbafa65 | 822 | ioat1_cleanup(ioat); |
0bbd5f4e | 823 | |
5cbafa65 | 824 | return ioat_is_complete(c, cookie, done, used); |
0bbd5f4e CL |
825 | } |
826 | ||
5cbafa65 | 827 | static void ioat1_dma_start_null_desc(struct ioat_dma_chan *ioat) |
0bbd5f4e | 828 | { |
dcbc853a | 829 | struct ioat_chan_common *chan = &ioat->base; |
0bbd5f4e | 830 | struct ioat_desc_sw *desc; |
c7984f4e | 831 | struct ioat_dma_descriptor *hw; |
0bbd5f4e | 832 | |
dcbc853a | 833 | spin_lock_bh(&ioat->desc_lock); |
0bbd5f4e | 834 | |
5cbafa65 | 835 | desc = ioat1_dma_get_next_descriptor(ioat); |
7f1b358a MS |
836 | |
837 | if (!desc) { | |
dcbc853a | 838 | dev_err(to_dev(chan), |
7f1b358a | 839 | "Unable to start null desc - get next desc failed\n"); |
dcbc853a | 840 | spin_unlock_bh(&ioat->desc_lock); |
7f1b358a MS |
841 | return; |
842 | } | |
843 | ||
c7984f4e DW |
844 | hw = desc->hw; |
845 | hw->ctl = 0; | |
846 | hw->ctl_f.null = 1; | |
847 | hw->ctl_f.int_en = 1; | |
848 | hw->ctl_f.compl_write = 1; | |
7f1b358a | 849 | /* set size to non-zero value (channel returns error when size is 0) */ |
c7984f4e DW |
850 | hw->size = NULL_DESC_BUFFER_SIZE; |
851 | hw->src_addr = 0; | |
852 | hw->dst_addr = 0; | |
bc3c7025 | 853 | async_tx_ack(&desc->txd); |
5cbafa65 DW |
854 | hw->next = 0; |
855 | list_add_tail(&desc->node, &ioat->used_desc); | |
6df9183a | 856 | dump_desc_dbg(ioat, desc); |
7bb67c14 | 857 | |
5cbafa65 DW |
858 | writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF, |
859 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW); | |
860 | writel(((u64) desc->txd.phys) >> 32, | |
861 | chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH); | |
7bb67c14 | 862 | |
5cbafa65 DW |
863 | writeb(IOAT_CHANCMD_START, chan->reg_base |
864 | + IOAT_CHANCMD_OFFSET(chan->device->version)); | |
dcbc853a | 865 | spin_unlock_bh(&ioat->desc_lock); |
0bbd5f4e CL |
866 | } |
867 | ||
868 | /* | |
869 | * Perform a IOAT transaction to verify the HW works. | |
870 | */ | |
871 | #define IOAT_TEST_SIZE 2000 | |
872 | ||
95218430 SN |
873 | static void ioat_dma_test_callback(void *dma_async_param) |
874 | { | |
b9bdcbba DW |
875 | struct completion *cmp = dma_async_param; |
876 | ||
877 | complete(cmp); | |
95218430 SN |
878 | } |
879 | ||
3e037454 SN |
880 | /** |
881 | * ioat_dma_self_test - Perform a IOAT transaction to verify the HW works. | |
882 | * @device: device to be tested | |
883 | */ | |
884 | static int ioat_dma_self_test(struct ioatdma_device *device) | |
0bbd5f4e CL |
885 | { |
886 | int i; | |
887 | u8 *src; | |
888 | u8 *dest; | |
bc3c7025 DW |
889 | struct dma_device *dma = &device->common; |
890 | struct device *dev = &device->pdev->dev; | |
0bbd5f4e | 891 | struct dma_chan *dma_chan; |
711924b1 | 892 | struct dma_async_tx_descriptor *tx; |
0036731c | 893 | dma_addr_t dma_dest, dma_src; |
0bbd5f4e CL |
894 | dma_cookie_t cookie; |
895 | int err = 0; | |
b9bdcbba | 896 | struct completion cmp; |
0c33e1ca | 897 | unsigned long tmo; |
4f005dbe | 898 | unsigned long flags; |
0bbd5f4e | 899 | |
e94b1766 | 900 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
0bbd5f4e CL |
901 | if (!src) |
902 | return -ENOMEM; | |
e94b1766 | 903 | dest = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
0bbd5f4e CL |
904 | if (!dest) { |
905 | kfree(src); | |
906 | return -ENOMEM; | |
907 | } | |
908 | ||
909 | /* Fill in src buffer */ | |
910 | for (i = 0; i < IOAT_TEST_SIZE; i++) | |
911 | src[i] = (u8)i; | |
912 | ||
913 | /* Start copy, using first DMA channel */ | |
bc3c7025 | 914 | dma_chan = container_of(dma->channels.next, struct dma_chan, |
43d6e369 | 915 | device_node); |
bc3c7025 DW |
916 | if (dma->device_alloc_chan_resources(dma_chan) < 1) { |
917 | dev_err(dev, "selftest cannot allocate chan resource\n"); | |
0bbd5f4e CL |
918 | err = -ENODEV; |
919 | goto out; | |
920 | } | |
921 | ||
bc3c7025 DW |
922 | dma_src = dma_map_single(dev, src, IOAT_TEST_SIZE, DMA_TO_DEVICE); |
923 | dma_dest = dma_map_single(dev, dest, IOAT_TEST_SIZE, DMA_FROM_DEVICE); | |
a6a39ca1 DW |
924 | flags = DMA_COMPL_SRC_UNMAP_SINGLE | DMA_COMPL_DEST_UNMAP_SINGLE | |
925 | DMA_PREP_INTERRUPT; | |
0036731c | 926 | tx = device->common.device_prep_dma_memcpy(dma_chan, dma_dest, dma_src, |
4f005dbe | 927 | IOAT_TEST_SIZE, flags); |
5149fd01 | 928 | if (!tx) { |
bc3c7025 | 929 | dev_err(dev, "Self-test prep failed, disabling\n"); |
5149fd01 SN |
930 | err = -ENODEV; |
931 | goto free_resources; | |
932 | } | |
933 | ||
7405f74b | 934 | async_tx_ack(tx); |
b9bdcbba | 935 | init_completion(&cmp); |
95218430 | 936 | tx->callback = ioat_dma_test_callback; |
b9bdcbba | 937 | tx->callback_param = &cmp; |
7bb67c14 | 938 | cookie = tx->tx_submit(tx); |
7f2b291f | 939 | if (cookie < 0) { |
bc3c7025 | 940 | dev_err(dev, "Self-test setup failed, disabling\n"); |
7f2b291f SN |
941 | err = -ENODEV; |
942 | goto free_resources; | |
943 | } | |
bc3c7025 | 944 | dma->device_issue_pending(dma_chan); |
532d3b1f | 945 | |
0c33e1ca | 946 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
0bbd5f4e | 947 | |
0c33e1ca | 948 | if (tmo == 0 || |
bc3c7025 | 949 | dma->device_is_tx_complete(dma_chan, cookie, NULL, NULL) |
7bb67c14 | 950 | != DMA_SUCCESS) { |
bc3c7025 | 951 | dev_err(dev, "Self-test copy timed out, disabling\n"); |
0bbd5f4e CL |
952 | err = -ENODEV; |
953 | goto free_resources; | |
954 | } | |
955 | if (memcmp(src, dest, IOAT_TEST_SIZE)) { | |
bc3c7025 | 956 | dev_err(dev, "Self-test copy failed compare, disabling\n"); |
0bbd5f4e CL |
957 | err = -ENODEV; |
958 | goto free_resources; | |
959 | } | |
960 | ||
961 | free_resources: | |
bc3c7025 | 962 | dma->device_free_chan_resources(dma_chan); |
0bbd5f4e CL |
963 | out: |
964 | kfree(src); | |
965 | kfree(dest); | |
966 | return err; | |
967 | } | |
968 | ||
3e037454 SN |
969 | static char ioat_interrupt_style[32] = "msix"; |
970 | module_param_string(ioat_interrupt_style, ioat_interrupt_style, | |
971 | sizeof(ioat_interrupt_style), 0644); | |
972 | MODULE_PARM_DESC(ioat_interrupt_style, | |
973 | "set ioat interrupt style: msix (default), " | |
974 | "msix-single-vector, msi, intx)"); | |
975 | ||
976 | /** | |
977 | * ioat_dma_setup_interrupts - setup interrupt handler | |
978 | * @device: ioat device | |
979 | */ | |
980 | static int ioat_dma_setup_interrupts(struct ioatdma_device *device) | |
981 | { | |
dcbc853a | 982 | struct ioat_chan_common *chan; |
e6c0b69a DW |
983 | struct pci_dev *pdev = device->pdev; |
984 | struct device *dev = &pdev->dev; | |
985 | struct msix_entry *msix; | |
986 | int i, j, msixcnt; | |
987 | int err = -EINVAL; | |
3e037454 SN |
988 | u8 intrctrl = 0; |
989 | ||
990 | if (!strcmp(ioat_interrupt_style, "msix")) | |
991 | goto msix; | |
992 | if (!strcmp(ioat_interrupt_style, "msix-single-vector")) | |
993 | goto msix_single_vector; | |
994 | if (!strcmp(ioat_interrupt_style, "msi")) | |
995 | goto msi; | |
996 | if (!strcmp(ioat_interrupt_style, "intx")) | |
997 | goto intx; | |
e6c0b69a | 998 | dev_err(dev, "invalid ioat_interrupt_style %s\n", ioat_interrupt_style); |
5149fd01 | 999 | goto err_no_irq; |
3e037454 SN |
1000 | |
1001 | msix: | |
1002 | /* The number of MSI-X vectors should equal the number of channels */ | |
1003 | msixcnt = device->common.chancnt; | |
1004 | for (i = 0; i < msixcnt; i++) | |
1005 | device->msix_entries[i].entry = i; | |
1006 | ||
e6c0b69a | 1007 | err = pci_enable_msix(pdev, device->msix_entries, msixcnt); |
3e037454 SN |
1008 | if (err < 0) |
1009 | goto msi; | |
1010 | if (err > 0) | |
1011 | goto msix_single_vector; | |
1012 | ||
1013 | for (i = 0; i < msixcnt; i++) { | |
e6c0b69a | 1014 | msix = &device->msix_entries[i]; |
dcbc853a | 1015 | chan = ioat_chan_by_index(device, i); |
e6c0b69a DW |
1016 | err = devm_request_irq(dev, msix->vector, |
1017 | ioat_dma_do_interrupt_msix, 0, | |
dcbc853a | 1018 | "ioat-msix", chan); |
3e037454 SN |
1019 | if (err) { |
1020 | for (j = 0; j < i; j++) { | |
e6c0b69a | 1021 | msix = &device->msix_entries[j]; |
dcbc853a DW |
1022 | chan = ioat_chan_by_index(device, j); |
1023 | devm_free_irq(dev, msix->vector, chan); | |
3e037454 SN |
1024 | } |
1025 | goto msix_single_vector; | |
1026 | } | |
1027 | } | |
1028 | intrctrl |= IOAT_INTRCTRL_MSIX_VECTOR_CONTROL; | |
3e037454 SN |
1029 | goto done; |
1030 | ||
1031 | msix_single_vector: | |
e6c0b69a DW |
1032 | msix = &device->msix_entries[0]; |
1033 | msix->entry = 0; | |
1034 | err = pci_enable_msix(pdev, device->msix_entries, 1); | |
3e037454 SN |
1035 | if (err) |
1036 | goto msi; | |
1037 | ||
e6c0b69a DW |
1038 | err = devm_request_irq(dev, msix->vector, ioat_dma_do_interrupt, 0, |
1039 | "ioat-msix", device); | |
3e037454 | 1040 | if (err) { |
e6c0b69a | 1041 | pci_disable_msix(pdev); |
3e037454 SN |
1042 | goto msi; |
1043 | } | |
3e037454 SN |
1044 | goto done; |
1045 | ||
1046 | msi: | |
e6c0b69a | 1047 | err = pci_enable_msi(pdev); |
3e037454 SN |
1048 | if (err) |
1049 | goto intx; | |
1050 | ||
e6c0b69a DW |
1051 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, 0, |
1052 | "ioat-msi", device); | |
3e037454 | 1053 | if (err) { |
e6c0b69a | 1054 | pci_disable_msi(pdev); |
3e037454 SN |
1055 | goto intx; |
1056 | } | |
3e037454 SN |
1057 | goto done; |
1058 | ||
1059 | intx: | |
e6c0b69a DW |
1060 | err = devm_request_irq(dev, pdev->irq, ioat_dma_do_interrupt, |
1061 | IRQF_SHARED, "ioat-intx", device); | |
3e037454 SN |
1062 | if (err) |
1063 | goto err_no_irq; | |
3e037454 SN |
1064 | |
1065 | done: | |
f2427e27 DW |
1066 | if (device->intr_quirk) |
1067 | device->intr_quirk(device); | |
3e037454 SN |
1068 | intrctrl |= IOAT_INTRCTRL_MASTER_INT_EN; |
1069 | writeb(intrctrl, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
1070 | return 0; | |
1071 | ||
1072 | err_no_irq: | |
1073 | /* Disable all interrupt generation */ | |
1074 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
e6c0b69a DW |
1075 | dev_err(dev, "no usable interrupts\n"); |
1076 | return err; | |
3e037454 SN |
1077 | } |
1078 | ||
e6c0b69a | 1079 | static void ioat_disable_interrupts(struct ioatdma_device *device) |
3e037454 | 1080 | { |
3e037454 SN |
1081 | /* Disable all interrupt generation */ |
1082 | writeb(0, device->reg_base + IOAT_INTRCTRL_OFFSET); | |
3e037454 SN |
1083 | } |
1084 | ||
5cbafa65 | 1085 | int ioat_probe(struct ioatdma_device *device) |
0bbd5f4e | 1086 | { |
f2427e27 DW |
1087 | int err = -ENODEV; |
1088 | struct dma_device *dma = &device->common; | |
1089 | struct pci_dev *pdev = device->pdev; | |
e6c0b69a | 1090 | struct device *dev = &pdev->dev; |
0bbd5f4e CL |
1091 | |
1092 | /* DMA coherent memory pool for DMA descriptor allocations */ | |
1093 | device->dma_pool = pci_pool_create("dma_desc_pool", pdev, | |
8ab89567 SN |
1094 | sizeof(struct ioat_dma_descriptor), |
1095 | 64, 0); | |
0bbd5f4e CL |
1096 | if (!device->dma_pool) { |
1097 | err = -ENOMEM; | |
1098 | goto err_dma_pool; | |
1099 | } | |
1100 | ||
43d6e369 SN |
1101 | device->completion_pool = pci_pool_create("completion_pool", pdev, |
1102 | sizeof(u64), SMP_CACHE_BYTES, | |
1103 | SMP_CACHE_BYTES); | |
5cbafa65 | 1104 | |
0bbd5f4e CL |
1105 | if (!device->completion_pool) { |
1106 | err = -ENOMEM; | |
1107 | goto err_completion_pool; | |
1108 | } | |
1109 | ||
5cbafa65 | 1110 | device->enumerate_channels(device); |
0bbd5f4e | 1111 | |
f2427e27 | 1112 | dma_cap_set(DMA_MEMCPY, dma->cap_mask); |
f2427e27 | 1113 | dma->dev = &pdev->dev; |
7bb67c14 | 1114 | |
e6c0b69a | 1115 | dev_err(dev, "Intel(R) I/OAT DMA Engine found," |
5149fd01 | 1116 | " %d channels, device version 0x%02x, driver version %s\n", |
bc3c7025 | 1117 | dma->chancnt, device->version, IOAT_DMA_VERSION); |
8ab89567 | 1118 | |
bc3c7025 | 1119 | if (!dma->chancnt) { |
e6c0b69a | 1120 | dev_err(dev, "Intel(R) I/OAT DMA Engine problem found: " |
8b794b14 MS |
1121 | "zero channels detected\n"); |
1122 | goto err_setup_interrupts; | |
1123 | } | |
1124 | ||
3e037454 | 1125 | err = ioat_dma_setup_interrupts(device); |
8ab89567 | 1126 | if (err) |
3e037454 | 1127 | goto err_setup_interrupts; |
0bbd5f4e | 1128 | |
3e037454 | 1129 | err = ioat_dma_self_test(device); |
0bbd5f4e CL |
1130 | if (err) |
1131 | goto err_self_test; | |
1132 | ||
f2427e27 | 1133 | return 0; |
0bbd5f4e CL |
1134 | |
1135 | err_self_test: | |
e6c0b69a | 1136 | ioat_disable_interrupts(device); |
3e037454 | 1137 | err_setup_interrupts: |
0bbd5f4e CL |
1138 | pci_pool_destroy(device->completion_pool); |
1139 | err_completion_pool: | |
1140 | pci_pool_destroy(device->dma_pool); | |
1141 | err_dma_pool: | |
f2427e27 DW |
1142 | return err; |
1143 | } | |
1144 | ||
5cbafa65 | 1145 | int ioat_register(struct ioatdma_device *device) |
f2427e27 DW |
1146 | { |
1147 | int err = dma_async_device_register(&device->common); | |
1148 | ||
1149 | if (err) { | |
1150 | ioat_disable_interrupts(device); | |
1151 | pci_pool_destroy(device->completion_pool); | |
1152 | pci_pool_destroy(device->dma_pool); | |
1153 | } | |
1154 | ||
1155 | return err; | |
1156 | } | |
1157 | ||
1158 | /* ioat1_intr_quirk - fix up dma ctrl register to enable / disable msi */ | |
1159 | static void ioat1_intr_quirk(struct ioatdma_device *device) | |
1160 | { | |
1161 | struct pci_dev *pdev = device->pdev; | |
1162 | u32 dmactrl; | |
1163 | ||
1164 | pci_read_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, &dmactrl); | |
1165 | if (pdev->msi_enabled) | |
1166 | dmactrl |= IOAT_PCI_DMACTRL_MSI_EN; | |
1167 | else | |
1168 | dmactrl &= ~IOAT_PCI_DMACTRL_MSI_EN; | |
1169 | pci_write_config_dword(pdev, IOAT_PCI_DMACTRL_OFFSET, dmactrl); | |
1170 | } | |
1171 | ||
1172 | int ioat1_dma_probe(struct ioatdma_device *device, int dca) | |
1173 | { | |
1174 | struct pci_dev *pdev = device->pdev; | |
1175 | struct dma_device *dma; | |
1176 | int err; | |
1177 | ||
1178 | device->intr_quirk = ioat1_intr_quirk; | |
5cbafa65 | 1179 | device->enumerate_channels = ioat1_enumerate_channels; |
f2427e27 DW |
1180 | dma = &device->common; |
1181 | dma->device_prep_dma_memcpy = ioat1_dma_prep_memcpy; | |
1182 | dma->device_issue_pending = ioat1_dma_memcpy_issue_pending; | |
5cbafa65 DW |
1183 | dma->device_alloc_chan_resources = ioat1_dma_alloc_chan_resources; |
1184 | dma->device_free_chan_resources = ioat1_dma_free_chan_resources; | |
1185 | dma->device_is_tx_complete = ioat1_dma_is_complete; | |
f2427e27 DW |
1186 | |
1187 | err = ioat_probe(device); | |
1188 | if (err) | |
1189 | return err; | |
1190 | ioat_set_tcp_copy_break(4096); | |
1191 | err = ioat_register(device); | |
1192 | if (err) | |
1193 | return err; | |
1194 | if (dca) | |
1195 | device->dca = ioat_dca_init(pdev, device->reg_base); | |
1196 | ||
5cbafa65 | 1197 | INIT_DELAYED_WORK(&device->work, ioat1_chan_watchdog); |
f2427e27 DW |
1198 | schedule_delayed_work(&device->work, WATCHDOG_DELAY); |
1199 | ||
1200 | return err; | |
1201 | } | |
1202 | ||
8ab89567 | 1203 | void ioat_dma_remove(struct ioatdma_device *device) |
0bbd5f4e | 1204 | { |
bc3c7025 | 1205 | struct dma_device *dma = &device->common; |
0bbd5f4e | 1206 | |
2b8a6bf8 MS |
1207 | if (device->version != IOAT_VER_3_0) |
1208 | cancel_delayed_work(&device->work); | |
1209 | ||
e6c0b69a | 1210 | ioat_disable_interrupts(device); |
8ab89567 | 1211 | |
bc3c7025 | 1212 | dma_async_device_unregister(dma); |
dfe2299e | 1213 | |
0bbd5f4e CL |
1214 | pci_pool_destroy(device->dma_pool); |
1215 | pci_pool_destroy(device->completion_pool); | |
8ab89567 | 1216 | |
dcbc853a | 1217 | INIT_LIST_HEAD(&dma->channels); |
0bbd5f4e | 1218 | } |