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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
[net-next-2.6.git] / drivers / char / synclinkmp.c
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1da177e4 1/*
7f3edb94 2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
1da177e4
LT		 3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
1da177e4
LT		 37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
53#include <linux/slab.h>
54#include <linux/netdevice.h>
55#include <linux/vmalloc.h>
56#include <linux/init.h>
1da177e4
LT		 57#include <linux/delay.h>
58#include <linux/ioctl.h>
59
60#include <asm/system.h>
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/dma.h>
64#include <linux/bitops.h>
65#include <asm/types.h>
66#include <linux/termios.h>
67#include <linux/workqueue.h>
68#include <linux/hdlc.h>
69
70#ifdef CONFIG_HDLC_MODULE
71#define CONFIG_HDLC 1
72#endif
73
74#define GET_USER(error,value,addr) error = get_user(value,addr)
75#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
76#define PUT_USER(error,value,addr) error = put_user(value,addr)
77#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
78
79#include <asm/uaccess.h>
80
81#include "linux/synclink.h"
82
83static MGSL_PARAMS default_params = {
84 MGSL_MODE_HDLC, /* unsigned long mode */
85 0, /* unsigned char loopback; */
86 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
87 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
88 0, /* unsigned long clock_speed; */
89 0xff, /* unsigned char addr_filter; */
90 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
91 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
92 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
93 9600, /* unsigned long data_rate; */
94 8, /* unsigned char data_bits; */
95 1, /* unsigned char stop_bits; */
96 ASYNC_PARITY_NONE /* unsigned char parity; */
97};
98
99/* size in bytes of DMA data buffers */
100#define SCABUFSIZE 1024
101#define SCA_MEM_SIZE 0x40000
102#define SCA_BASE_SIZE 512
103#define SCA_REG_SIZE 16
104#define SCA_MAX_PORTS 4
105#define SCAMAXDESC 128
106
107#define BUFFERLISTSIZE 4096
108
109/* SCA-I style DMA buffer descriptor */
110typedef struct _SCADESC
111{
112 u16 next; /* lower l6 bits of next descriptor addr */
113 u16 buf_ptr; /* lower 16 bits of buffer addr */
114 u8 buf_base; /* upper 8 bits of buffer addr */
115 u8 pad1;
116 u16 length; /* length of buffer */
117 u8 status; /* status of buffer */
118 u8 pad2;
119} SCADESC, *PSCADESC;
120
121typedef struct _SCADESC_EX
122{
123 /* device driver bookkeeping section */
124 char *virt_addr; /* virtual address of data buffer */
125 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
126} SCADESC_EX, *PSCADESC_EX;
127
128/* The queue of BH actions to be performed */
129
130#define BH_RECEIVE 1
131#define BH_TRANSMIT 2
132#define BH_STATUS 4
133
134#define IO_PIN_SHUTDOWN_LIMIT 100
135
136#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
137
138struct _input_signal_events {
139 int ri_up;
140 int ri_down;
141 int dsr_up;
142 int dsr_down;
143 int dcd_up;
144 int dcd_down;
145 int cts_up;
146 int cts_down;
147};
148
149/*
150 * Device instance data structure
151 */
152typedef struct _synclinkmp_info {
153 void *if_ptr; /* General purpose pointer (used by SPPP) */
154 int magic;
155 int flags;
156 int count; /* count of opens */
157 int line;
158 unsigned short close_delay;
159 unsigned short closing_wait; /* time to wait before closing */
160
161 struct mgsl_icount icount;
162
163 struct tty_struct *tty;
164 int timeout;
165 int x_char; /* xon/xoff character */
166 int blocked_open; /* # of blocked opens */
167 u16 read_status_mask1; /* break detection (SR1 indications) */
168 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
169 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
170 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
171 unsigned char *tx_buf;
172 int tx_put;
173 int tx_get;
174 int tx_count;
175
176 wait_queue_head_t open_wait;
177 wait_queue_head_t close_wait;
178
179 wait_queue_head_t status_event_wait_q;
180 wait_queue_head_t event_wait_q;
181 struct timer_list tx_timer; /* HDLC transmit timeout timer */
182 struct _synclinkmp_info *next_device; /* device list link */
183 struct timer_list status_timer; /* input signal status check timer */
184
185 spinlock_t lock; /* spinlock for synchronizing with ISR */
186 struct work_struct task; /* task structure for scheduling bh */
187
188 u32 max_frame_size; /* as set by device config */
189
190 u32 pending_bh;
191
192 int bh_running; /* Protection from multiple */
193 int isr_overflow;
194 int bh_requested;
195
196 int dcd_chkcount; /* check counts to prevent */
197 int cts_chkcount; /* too many IRQs if a signal */
198 int dsr_chkcount; /* is floating */
199 int ri_chkcount;
200
201 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
202 unsigned long buffer_list_phys;
203
204 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
205 SCADESC *rx_buf_list; /* list of receive buffer entries */
206 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
207 unsigned int current_rx_buf;
208
209 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
210 SCADESC *tx_buf_list; /* list of transmit buffer entries */
211 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
212 unsigned int last_tx_buf;
213
214 unsigned char *tmp_rx_buf;
215 unsigned int tmp_rx_buf_count;
216
217 int rx_enabled;
218 int rx_overflow;
219
220 int tx_enabled;
221 int tx_active;
222 u32 idle_mode;
223
224 unsigned char ie0_value;
225 unsigned char ie1_value;
226 unsigned char ie2_value;
227 unsigned char ctrlreg_value;
228 unsigned char old_signals;
229
230 char device_name[25]; /* device instance name */
231
232 int port_count;
233 int adapter_num;
234 int port_num;
235
236 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
237
238 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
239
240 unsigned int irq_level; /* interrupt level */
241 unsigned long irq_flags;
242 int irq_requested; /* nonzero if IRQ requested */
243
244 MGSL_PARAMS params; /* communications parameters */
245
246 unsigned char serial_signals; /* current serial signal states */
247
248 int irq_occurred; /* for diagnostics use */
249 unsigned int init_error; /* Initialization startup error */
250
251 u32 last_mem_alloc;
252 unsigned char* memory_base; /* shared memory address (PCI only) */
253 u32 phys_memory_base;
254 int shared_mem_requested;
255
256 unsigned char* sca_base; /* HD64570 SCA Memory address */
257 u32 phys_sca_base;
258 u32 sca_offset;
259 int sca_base_requested;
260
261 unsigned char* lcr_base; /* local config registers (PCI only) */
262 u32 phys_lcr_base;
263 u32 lcr_offset;
264 int lcr_mem_requested;
265
266 unsigned char* statctrl_base; /* status/control register memory */
267 u32 phys_statctrl_base;
268 u32 statctrl_offset;
269 int sca_statctrl_requested;
270
271 u32 misc_ctrl_value;
272 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
273 char char_buf[MAX_ASYNC_BUFFER_SIZE];
274 BOOLEAN drop_rts_on_tx_done;
275
276 struct _input_signal_events input_signal_events;
277
278 /* SPPP/Cisco HDLC device parts */
279 int netcount;
280 int dosyncppp;
281 spinlock_t netlock;
282
283#ifdef CONFIG_HDLC
284 struct net_device *netdev;
285#endif
286
287} SLMP_INFO;
288
289#define MGSL_MAGIC 0x5401
290
291/*
292 * define serial signal status change macros
293 */
294#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
295#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
296#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
297#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
298
299/* Common Register macros */
300#define LPR 0x00
301#define PABR0 0x02
302#define PABR1 0x03
303#define WCRL 0x04
304#define WCRM 0x05
305#define WCRH 0x06
306#define DPCR 0x08
307#define DMER 0x09
308#define ISR0 0x10
309#define ISR1 0x11
310#define ISR2 0x12
311#define IER0 0x14
312#define IER1 0x15
313#define IER2 0x16
314#define ITCR 0x18
315#define INTVR 0x1a
316#define IMVR 0x1c
317
318/* MSCI Register macros */
319#define TRB 0x20
320#define TRBL 0x20
321#define TRBH 0x21
322#define SR0 0x22
323#define SR1 0x23
324#define SR2 0x24
325#define SR3 0x25
326#define FST 0x26
327#define IE0 0x28
328#define IE1 0x29
329#define IE2 0x2a
330#define FIE 0x2b
331#define CMD 0x2c
332#define MD0 0x2e
333#define MD1 0x2f
334#define MD2 0x30
335#define CTL 0x31
336#define SA0 0x32
337#define SA1 0x33
338#define IDL 0x34
339#define TMC 0x35
340#define RXS 0x36
341#define TXS 0x37
342#define TRC0 0x38
343#define TRC1 0x39
344#define RRC 0x3a
345#define CST0 0x3c
346#define CST1 0x3d
347
348/* Timer Register Macros */
349#define TCNT 0x60
350#define TCNTL 0x60
351#define TCNTH 0x61
352#define TCONR 0x62
353#define TCONRL 0x62
354#define TCONRH 0x63
355#define TMCS 0x64
356#define TEPR 0x65
357
358/* DMA Controller Register macros */
359#define DARL 0x80
360#define DARH 0x81
361#define DARB 0x82
362#define BAR 0x80
363#define BARL 0x80
364#define BARH 0x81
365#define BARB 0x82
366#define SAR 0x84
367#define SARL 0x84
368#define SARH 0x85
369#define SARB 0x86
370#define CPB 0x86
371#define CDA 0x88
372#define CDAL 0x88
373#define CDAH 0x89
374#define EDA 0x8a
375#define EDAL 0x8a
376#define EDAH 0x8b
377#define BFL 0x8c
378#define BFLL 0x8c
379#define BFLH 0x8d
380#define BCR 0x8e
381#define BCRL 0x8e
382#define BCRH 0x8f
383#define DSR 0x90
384#define DMR 0x91
385#define FCT 0x93
386#define DIR 0x94
387#define DCMD 0x95
388
389/* combine with timer or DMA register address */
390#define TIMER0 0x00
391#define TIMER1 0x08
392#define TIMER2 0x10
393#define TIMER3 0x18
394#define RXDMA 0x00
395#define TXDMA 0x20
396
397/* SCA Command Codes */
398#define NOOP 0x00
399#define TXRESET 0x01
400#define TXENABLE 0x02
401#define TXDISABLE 0x03
402#define TXCRCINIT 0x04
403#define TXCRCEXCL 0x05
404#define TXEOM 0x06
405#define TXABORT 0x07
406#define MPON 0x08
407#define TXBUFCLR 0x09
408#define RXRESET 0x11
409#define RXENABLE 0x12
410#define RXDISABLE 0x13
411#define RXCRCINIT 0x14
412#define RXREJECT 0x15
413#define SEARCHMP 0x16
414#define RXCRCEXCL 0x17
415#define RXCRCCALC 0x18
416#define CHRESET 0x21
417#define HUNT 0x31
418
419/* DMA command codes */
420#define SWABORT 0x01
421#define FEICLEAR 0x02
422
423/* IE0 */
424#define TXINTE BIT7
425#define RXINTE BIT6
426#define TXRDYE BIT1
427#define RXRDYE BIT0
428
429/* IE1 & SR1 */
430#define UDRN BIT7
431#define IDLE BIT6
432#define SYNCD BIT4
433#define FLGD BIT4
434#define CCTS BIT3
435#define CDCD BIT2
436#define BRKD BIT1
437#define ABTD BIT1
438#define GAPD BIT1
439#define BRKE BIT0
440#define IDLD BIT0
441
442/* IE2 & SR2 */
443#define EOM BIT7
444#define PMP BIT6
445#define SHRT BIT6
446#define PE BIT5
447#define ABT BIT5
448#define FRME BIT4
449#define RBIT BIT4
450#define OVRN BIT3
451#define CRCE BIT2
452
453
454/*
455 * Global linked list of SyncLink devices
456 */
457static SLMP_INFO *synclinkmp_device_list = NULL;
458static int synclinkmp_adapter_count = -1;
459static int synclinkmp_device_count = 0;
460
461/*
462 * Set this param to non-zero to load eax with the
463 * .text section address and breakpoint on module load.
464 * This is useful for use with gdb and add-symbol-file command.
465 */
466static int break_on_load=0;
467
468/*
469 * Driver major number, defaults to zero to get auto
470 * assigned major number. May be forced as module parameter.
471 */
472static int ttymajor=0;
473
474/*
475 * Array of user specified options for ISA adapters.
476 */
477static int debug_level = 0;
478static int maxframe[MAX_DEVICES] = {0,};
479static int dosyncppp[MAX_DEVICES] = {0,};
480
481module_param(break_on_load, bool, 0);
482module_param(ttymajor, int, 0);
483module_param(debug_level, int, 0);
484module_param_array(maxframe, int, NULL, 0);
485module_param_array(dosyncppp, int, NULL, 0);
486
487static char *driver_name = "SyncLink MultiPort driver";
7f3edb94 488static char *driver_version = "$Revision: 4.38 $";
1da177e4
LT		 489
490static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
491static void synclinkmp_remove_one(struct pci_dev *dev);
492
493static struct pci_device_id synclinkmp_pci_tbl[] = {
494 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
495 { 0, }, /* terminate list */
496};
497MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
498
499MODULE_LICENSE("GPL");
500
501static struct pci_driver synclinkmp_pci_driver = {
502 .name = "synclinkmp",
503 .id_table = synclinkmp_pci_tbl,
504 .probe = synclinkmp_init_one,
505 .remove = __devexit_p(synclinkmp_remove_one),
506};
507
508
509static struct tty_driver *serial_driver;
510
511/* number of characters left in xmit buffer before we ask for more */
512#define WAKEUP_CHARS 256
513
514
515/* tty callbacks */
516
517static int open(struct tty_struct *tty, struct file * filp);
518static void close(struct tty_struct *tty, struct file * filp);
519static void hangup(struct tty_struct *tty);
520static void set_termios(struct tty_struct *tty, struct termios *old_termios);
521
522static int write(struct tty_struct *tty, const unsigned char *buf, int count);
523static void put_char(struct tty_struct *tty, unsigned char ch);
524static void send_xchar(struct tty_struct *tty, char ch);
525static void wait_until_sent(struct tty_struct *tty, int timeout);
526static int write_room(struct tty_struct *tty);
527static void flush_chars(struct tty_struct *tty);
528static void flush_buffer(struct tty_struct *tty);
529static void tx_hold(struct tty_struct *tty);
530static void tx_release(struct tty_struct *tty);
531
532static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
533static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
534static int chars_in_buffer(struct tty_struct *tty);
535static void throttle(struct tty_struct * tty);
536static void unthrottle(struct tty_struct * tty);
537static void set_break(struct tty_struct *tty, int break_state);
538
539#ifdef CONFIG_HDLC
540#define dev_to_port(D) (dev_to_hdlc(D)->priv)
541static void hdlcdev_tx_done(SLMP_INFO *info);
542static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
543static int hdlcdev_init(SLMP_INFO *info);
544static void hdlcdev_exit(SLMP_INFO *info);
545#endif
546
547/* ioctl handlers */
548
549static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
550static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
551static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
552static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
553static int set_txidle(SLMP_INFO *info, int idle_mode);
554static int tx_enable(SLMP_INFO *info, int enable);
555static int tx_abort(SLMP_INFO *info);
556static int rx_enable(SLMP_INFO *info, int enable);
1da177e4
LT		 557static int modem_input_wait(SLMP_INFO *info,int arg);
558static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
559static int tiocmget(struct tty_struct *tty, struct file *file);
560static int tiocmset(struct tty_struct *tty, struct file *file,
561 unsigned int set, unsigned int clear);
562static void set_break(struct tty_struct *tty, int break_state);
563
564static void add_device(SLMP_INFO *info);
565static void device_init(int adapter_num, struct pci_dev *pdev);
566static int claim_resources(SLMP_INFO *info);
567static void release_resources(SLMP_INFO *info);
568
569static int startup(SLMP_INFO *info);
570static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
571static void shutdown(SLMP_INFO *info);
572static void program_hw(SLMP_INFO *info);
573static void change_params(SLMP_INFO *info);
574
575static int init_adapter(SLMP_INFO *info);
576static int register_test(SLMP_INFO *info);
577static int irq_test(SLMP_INFO *info);
578static int loopback_test(SLMP_INFO *info);
579static int adapter_test(SLMP_INFO *info);
580static int memory_test(SLMP_INFO *info);
581
582static void reset_adapter(SLMP_INFO *info);
583static void reset_port(SLMP_INFO *info);
584static void async_mode(SLMP_INFO *info);
585static void hdlc_mode(SLMP_INFO *info);
586
587static void rx_stop(SLMP_INFO *info);
588static void rx_start(SLMP_INFO *info);
589static void rx_reset_buffers(SLMP_INFO *info);
590static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
591static int rx_get_frame(SLMP_INFO *info);
592
593static void tx_start(SLMP_INFO *info);
594static void tx_stop(SLMP_INFO *info);
595static void tx_load_fifo(SLMP_INFO *info);
596static void tx_set_idle(SLMP_INFO *info);
597static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
598
599static void get_signals(SLMP_INFO *info);
600static void set_signals(SLMP_INFO *info);
601static void enable_loopback(SLMP_INFO *info, int enable);
602static void set_rate(SLMP_INFO *info, u32 data_rate);
603
604static int bh_action(SLMP_INFO *info);
605static void bh_handler(void* Context);
606static void bh_receive(SLMP_INFO *info);
607static void bh_transmit(SLMP_INFO *info);
608static void bh_status(SLMP_INFO *info);
609static void isr_timer(SLMP_INFO *info);
610static void isr_rxint(SLMP_INFO *info);
611static void isr_rxrdy(SLMP_INFO *info);
612static void isr_txint(SLMP_INFO *info);
613static void isr_txrdy(SLMP_INFO *info);
614static void isr_rxdmaok(SLMP_INFO *info);
615static void isr_rxdmaerror(SLMP_INFO *info);
616static void isr_txdmaok(SLMP_INFO *info);
617static void isr_txdmaerror(SLMP_INFO *info);
618static void isr_io_pin(SLMP_INFO *info, u16 status);
619
620static int alloc_dma_bufs(SLMP_INFO *info);
621static void free_dma_bufs(SLMP_INFO *info);
622static int alloc_buf_list(SLMP_INFO *info);
623static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
624static int alloc_tmp_rx_buf(SLMP_INFO *info);
625static void free_tmp_rx_buf(SLMP_INFO *info);
626
627static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
628static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
629static void tx_timeout(unsigned long context);
630static void status_timeout(unsigned long context);
631
632static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
633static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
634static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
635static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
636static unsigned char read_status_reg(SLMP_INFO * info);
637static void write_control_reg(SLMP_INFO * info);
638
639
640static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
641static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
642static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
643
644static u32 misc_ctrl_value = 0x007e4040;
761a444d 645static u32 lcr1_brdr_value = 0x00800028;
1da177e4
LT		 646
647static u32 read_ahead_count = 8;
648
649/* DPCR, DMA Priority Control
650 *
651 * 07..05 Not used, must be 0
652 * 04 BRC, bus release condition: 0=all transfers complete
653 * 1=release after 1 xfer on all channels
654 * 03 CCC, channel change condition: 0=every cycle
655 * 1=after each channel completes all xfers
656 * 02..00 PR<2..0>, priority 100=round robin
657 *
658 * 00000100 = 0x00
659 */
660static unsigned char dma_priority = 0x04;
661
662// Number of bytes that can be written to shared RAM
663// in a single write operation
664static u32 sca_pci_load_interval = 64;
665
666/*
667 * 1st function defined in .text section. Calling this function in
668 * init_module() followed by a breakpoint allows a remote debugger
669 * (gdb) to get the .text address for the add-symbol-file command.
670 * This allows remote debugging of dynamically loadable modules.
671 */
672static void* synclinkmp_get_text_ptr(void);
673static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
674
675static inline int sanity_check(SLMP_INFO *info,
676 char *name, const char *routine)
677{
678#ifdef SANITY_CHECK
679 static const char *badmagic =
680 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
681 static const char *badinfo =
682 "Warning: null synclinkmp_struct for (%s) in %s\n";
683
684 if (!info) {
685 printk(badinfo, name, routine);
686 return 1;
687 }
688 if (info->magic != MGSL_MAGIC) {
689 printk(badmagic, name, routine);
690 return 1;
691 }
692#else
693 if (!info)
694 return 1;
695#endif
696 return 0;
697}
698
699/**
700 * line discipline callback wrappers
701 *
702 * The wrappers maintain line discipline references
703 * while calling into the line discipline.
704 *
705 * ldisc_receive_buf - pass receive data to line discipline
706 */
707
708static void ldisc_receive_buf(struct tty_struct *tty,
709 const __u8 *data, char *flags, int count)
710{
711 struct tty_ldisc *ld;
712 if (!tty)
713 return;
714 ld = tty_ldisc_ref(tty);
715 if (ld) {
716 if (ld->receive_buf)
717 ld->receive_buf(tty, data, flags, count);
718 tty_ldisc_deref(ld);
719 }
720}
721
722/* tty callbacks */
723
724/* Called when a port is opened. Init and enable port.
725 */
726static int open(struct tty_struct *tty, struct file *filp)
727{
728 SLMP_INFO *info;
729 int retval, line;
730 unsigned long flags;
731
732 line = tty->index;
733 if ((line < 0) || (line >= synclinkmp_device_count)) {
734 printk("%s(%d): open with invalid line #%d.\n",
735 __FILE__,__LINE__,line);
736 return -ENODEV;
737 }
738
739 info = synclinkmp_device_list;
740 while(info && info->line != line)
741 info = info->next_device;
742 if (sanity_check(info, tty->name, "open"))
743 return -ENODEV;
744 if ( info->init_error ) {
745 printk("%s(%d):%s device is not allocated, init error=%d\n",
746 __FILE__,__LINE__,info->device_name,info->init_error);
747 return -ENODEV;
748 }
749
750 tty->driver_data = info;
751 info->tty = tty;
752
753 if (debug_level >= DEBUG_LEVEL_INFO)
754 printk("%s(%d):%s open(), old ref count = %d\n",
755 __FILE__,__LINE__,tty->driver->name, info->count);
756
757 /* If port is closing, signal caller to try again */
758 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
759 if (info->flags & ASYNC_CLOSING)
760 interruptible_sleep_on(&info->close_wait);
761 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
762 -EAGAIN : -ERESTARTSYS);
763 goto cleanup;
764 }
765
766 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
767
768 spin_lock_irqsave(&info->netlock, flags);
769 if (info->netcount) {
770 retval = -EBUSY;
771 spin_unlock_irqrestore(&info->netlock, flags);
772 goto cleanup;
773 }
774 info->count++;
775 spin_unlock_irqrestore(&info->netlock, flags);
776
777 if (info->count == 1) {
778 /* 1st open on this device, init hardware */
779 retval = startup(info);
780 if (retval < 0)
781 goto cleanup;
782 }
783
784 retval = block_til_ready(tty, filp, info);
785 if (retval) {
786 if (debug_level >= DEBUG_LEVEL_INFO)
787 printk("%s(%d):%s block_til_ready() returned %d\n",
788 __FILE__,__LINE__, info->device_name, retval);
789 goto cleanup;
790 }
791
792 if (debug_level >= DEBUG_LEVEL_INFO)
793 printk("%s(%d):%s open() success\n",
794 __FILE__,__LINE__, info->device_name);
795 retval = 0;
796
797cleanup:
798 if (retval) {
799 if (tty->count == 1)
800 info->tty = NULL; /* tty layer will release tty struct */
801 if(info->count)
802 info->count--;
803 }
804
805 return retval;
806}
807
808/* Called when port is closed. Wait for remaining data to be
809 * sent. Disable port and free resources.
810 */
811static void close(struct tty_struct *tty, struct file *filp)
812{
813 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
814
815 if (sanity_check(info, tty->name, "close"))
816 return;
817
818 if (debug_level >= DEBUG_LEVEL_INFO)
819 printk("%s(%d):%s close() entry, count=%d\n",
820 __FILE__,__LINE__, info->device_name, info->count);
821
822 if (!info->count)
823 return;
824
825 if (tty_hung_up_p(filp))
826 goto cleanup;
827
828 if ((tty->count == 1) && (info->count != 1)) {
829 /*
830 * tty->count is 1 and the tty structure will be freed.
831 * info->count should be one in this case.
832 * if it's not, correct it so that the port is shutdown.
833 */
834 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
835 "info->count is %d\n",
836 __FILE__,__LINE__, info->device_name, info->count);
837 info->count = 1;
838 }
839
840 info->count--;
841
842 /* if at least one open remaining, leave hardware active */
843 if (info->count)
844 goto cleanup;
845
846 info->flags |= ASYNC_CLOSING;
847
848 /* set tty->closing to notify line discipline to
849 * only process XON/XOFF characters. Only the N_TTY
850 * discipline appears to use this (ppp does not).
851 */
852 tty->closing = 1;
853
854 /* wait for transmit data to clear all layers */
855
856 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
857 if (debug_level >= DEBUG_LEVEL_INFO)
858 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
859 __FILE__,__LINE__, info->device_name );
860 tty_wait_until_sent(tty, info->closing_wait);
861 }
862
863 if (info->flags & ASYNC_INITIALIZED)
864 wait_until_sent(tty, info->timeout);
865
866 if (tty->driver->flush_buffer)
867 tty->driver->flush_buffer(tty);
868
869 tty_ldisc_flush(tty);
870
871 shutdown(info);
872
873 tty->closing = 0;
874 info->tty = NULL;
875
876 if (info->blocked_open) {
877 if (info->close_delay) {
878 msleep_interruptible(jiffies_to_msecs(info->close_delay));
879 }
880 wake_up_interruptible(&info->open_wait);
881 }
882
883 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
884
885 wake_up_interruptible(&info->close_wait);
886
887cleanup:
888 if (debug_level >= DEBUG_LEVEL_INFO)
889 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
890 tty->driver->name, info->count);
891}
892
893/* Called by tty_hangup() when a hangup is signaled.
894 * This is the same as closing all open descriptors for the port.
895 */
896static void hangup(struct tty_struct *tty)
897{
898 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
899
900 if (debug_level >= DEBUG_LEVEL_INFO)
901 printk("%s(%d):%s hangup()\n",
902 __FILE__,__LINE__, info->device_name );
903
904 if (sanity_check(info, tty->name, "hangup"))
905 return;
906
907 flush_buffer(tty);
908 shutdown(info);
909
910 info->count = 0;
911 info->flags &= ~ASYNC_NORMAL_ACTIVE;
912 info->tty = NULL;
913
914 wake_up_interruptible(&info->open_wait);
915}
916
917/* Set new termios settings
918 */
919static void set_termios(struct tty_struct *tty, struct termios *old_termios)
920{
921 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
922 unsigned long flags;
923
924 if (debug_level >= DEBUG_LEVEL_INFO)
925 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
926 tty->driver->name );
927
928 /* just return if nothing has changed */
929 if ((tty->termios->c_cflag == old_termios->c_cflag)
930 && (RELEVANT_IFLAG(tty->termios->c_iflag)
931 == RELEVANT_IFLAG(old_termios->c_iflag)))
932 return;
933
934 change_params(info);
935
936 /* Handle transition to B0 status */
937 if (old_termios->c_cflag & CBAUD &&
938 !(tty->termios->c_cflag & CBAUD)) {
939 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
940 spin_lock_irqsave(&info->lock,flags);
941 set_signals(info);
942 spin_unlock_irqrestore(&info->lock,flags);
943 }
944
945 /* Handle transition away from B0 status */
946 if (!(old_termios->c_cflag & CBAUD) &&
947 tty->termios->c_cflag & CBAUD) {
948 info->serial_signals |= SerialSignal_DTR;
949 if (!(tty->termios->c_cflag & CRTSCTS) ||
950 !test_bit(TTY_THROTTLED, &tty->flags)) {
951 info->serial_signals |= SerialSignal_RTS;
952 }
953 spin_lock_irqsave(&info->lock,flags);
954 set_signals(info);
955 spin_unlock_irqrestore(&info->lock,flags);
956 }
957
958 /* Handle turning off CRTSCTS */
959 if (old_termios->c_cflag & CRTSCTS &&
960 !(tty->termios->c_cflag & CRTSCTS)) {
961 tty->hw_stopped = 0;
962 tx_release(tty);
963 }
964}
965
966/* Send a block of data
967 *
968 * Arguments:
969 *
970 * tty pointer to tty information structure
971 * buf pointer to buffer containing send data
972 * count size of send data in bytes
973 *
974 * Return Value: number of characters written
975 */
976static int write(struct tty_struct *tty,
977 const unsigned char *buf, int count)
978{
979 int c, ret = 0;
980 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
981 unsigned long flags;
982
983 if (debug_level >= DEBUG_LEVEL_INFO)
984 printk("%s(%d):%s write() count=%d\n",
985 __FILE__,__LINE__,info->device_name,count);
986
987 if (sanity_check(info, tty->name, "write"))
988 goto cleanup;
989
326f28e9 990 if (!info->tx_buf)
1da177e4
LT		 991 goto cleanup;
992
993 if (info->params.mode == MGSL_MODE_HDLC) {
994 if (count > info->max_frame_size) {
995 ret = -EIO;
996 goto cleanup;
997 }
998 if (info->tx_active)
999 goto cleanup;
1000 if (info->tx_count) {
1001 /* send accumulated data from send_char() calls */
1002 /* as frame and wait before accepting more data. */
1003 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1004 goto start;
1005 }
1006 ret = info->tx_count = count;
1007 tx_load_dma_buffer(info, buf, count);
1008 goto start;
1009 }
1010
1011 for (;;) {
1012 c = min_t(int, count,
1013 min(info->max_frame_size - info->tx_count - 1,
1014 info->max_frame_size - info->tx_put));
1015 if (c <= 0)
1016 break;
1017
1018 memcpy(info->tx_buf + info->tx_put, buf, c);
1019
1020 spin_lock_irqsave(&info->lock,flags);
1021 info->tx_put += c;
1022 if (info->tx_put >= info->max_frame_size)
1023 info->tx_put -= info->max_frame_size;
1024 info->tx_count += c;
1025 spin_unlock_irqrestore(&info->lock,flags);
1026
1027 buf += c;
1028 count -= c;
1029 ret += c;
1030 }
1031
1032 if (info->params.mode == MGSL_MODE_HDLC) {
1033 if (count) {
1034 ret = info->tx_count = 0;
1035 goto cleanup;
1036 }
1037 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1038 }
1039start:
1040 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1041 spin_lock_irqsave(&info->lock,flags);
1042 if (!info->tx_active)
1043 tx_start(info);
1044 spin_unlock_irqrestore(&info->lock,flags);
1045 }
1046
1047cleanup:
1048 if (debug_level >= DEBUG_LEVEL_INFO)
1049 printk( "%s(%d):%s write() returning=%d\n",
1050 __FILE__,__LINE__,info->device_name,ret);
1051 return ret;
1052}
1053
1054/* Add a character to the transmit buffer.
1055 */
1056static void put_char(struct tty_struct *tty, unsigned char ch)
1057{
1058 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1059 unsigned long flags;
1060
1061 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1062 printk( "%s(%d):%s put_char(%d)\n",
1063 __FILE__,__LINE__,info->device_name,ch);
1064 }
1065
1066 if (sanity_check(info, tty->name, "put_char"))
1067 return;
1068
326f28e9 1069 if (!info->tx_buf)
1da177e4
LT		 1070 return;
1071
1072 spin_lock_irqsave(&info->lock,flags);
1073
1074 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1075 !info->tx_active ) {
1076
1077 if (info->tx_count < info->max_frame_size - 1) {
1078 info->tx_buf[info->tx_put++] = ch;
1079 if (info->tx_put >= info->max_frame_size)
1080 info->tx_put -= info->max_frame_size;
1081 info->tx_count++;
1082 }
1083 }
1084
1085 spin_unlock_irqrestore(&info->lock,flags);
1086}
1087
1088/* Send a high-priority XON/XOFF character
1089 */
1090static void send_xchar(struct tty_struct *tty, char ch)
1091{
1092 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1093 unsigned long flags;
1094
1095 if (debug_level >= DEBUG_LEVEL_INFO)
1096 printk("%s(%d):%s send_xchar(%d)\n",
1097 __FILE__,__LINE__, info->device_name, ch );
1098
1099 if (sanity_check(info, tty->name, "send_xchar"))
1100 return;
1101
1102 info->x_char = ch;
1103 if (ch) {
1104 /* Make sure transmit interrupts are on */
1105 spin_lock_irqsave(&info->lock,flags);
1106 if (!info->tx_enabled)
1107 tx_start(info);
1108 spin_unlock_irqrestore(&info->lock,flags);
1109 }
1110}
1111
1112/* Wait until the transmitter is empty.
1113 */
1114static void wait_until_sent(struct tty_struct *tty, int timeout)
1115{
1116 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1117 unsigned long orig_jiffies, char_time;
1118
1119 if (!info )
1120 return;
1121
1122 if (debug_level >= DEBUG_LEVEL_INFO)
1123 printk("%s(%d):%s wait_until_sent() entry\n",
1124 __FILE__,__LINE__, info->device_name );
1125
1126 if (sanity_check(info, tty->name, "wait_until_sent"))
1127 return;
1128
1129 if (!(info->flags & ASYNC_INITIALIZED))
1130 goto exit;
1131
1132 orig_jiffies = jiffies;
1133
1134 /* Set check interval to 1/5 of estimated time to
1135 * send a character, and make it at least 1. The check
1136 * interval should also be less than the timeout.
1137 * Note: use tight timings here to satisfy the NIST-PCTS.
1138 */
1139
1140 if ( info->params.data_rate ) {
1141 char_time = info->timeout/(32 * 5);
1142 if (!char_time)
1143 char_time++;
1144 } else
1145 char_time = 1;
1146
1147 if (timeout)
1148 char_time = min_t(unsigned long, char_time, timeout);
1149
1150 if ( info->params.mode == MGSL_MODE_HDLC ) {
1151 while (info->tx_active) {
1152 msleep_interruptible(jiffies_to_msecs(char_time));
1153 if (signal_pending(current))
1154 break;
1155 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1156 break;
1157 }
1158 } else {
1159 //TODO: determine if there is something similar to USC16C32
1160 // TXSTATUS_ALL_SENT status
1161 while ( info->tx_active && info->tx_enabled) {
1162 msleep_interruptible(jiffies_to_msecs(char_time));
1163 if (signal_pending(current))
1164 break;
1165 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1166 break;
1167 }
1168 }
1169
1170exit:
1171 if (debug_level >= DEBUG_LEVEL_INFO)
1172 printk("%s(%d):%s wait_until_sent() exit\n",
1173 __FILE__,__LINE__, info->device_name );
1174}
1175
1176/* Return the count of free bytes in transmit buffer
1177 */
1178static int write_room(struct tty_struct *tty)
1179{
1180 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1181 int ret;
1182
1183 if (sanity_check(info, tty->name, "write_room"))
1184 return 0;
1185
1186 if (info->params.mode == MGSL_MODE_HDLC) {
1187 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1188 } else {
1189 ret = info->max_frame_size - info->tx_count - 1;
1190 if (ret < 0)
1191 ret = 0;
1192 }
1193
1194 if (debug_level >= DEBUG_LEVEL_INFO)
1195 printk("%s(%d):%s write_room()=%d\n",
1196 __FILE__, __LINE__, info->device_name, ret);
1197
1198 return ret;
1199}
1200
1201/* enable transmitter and send remaining buffered characters
1202 */
1203static void flush_chars(struct tty_struct *tty)
1204{
1205 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1206 unsigned long flags;
1207
1208 if ( debug_level >= DEBUG_LEVEL_INFO )
1209 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1210 __FILE__,__LINE__,info->device_name,info->tx_count);
1211
1212 if (sanity_check(info, tty->name, "flush_chars"))
1213 return;
1214
1215 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1216 !info->tx_buf)
1217 return;
1218
1219 if ( debug_level >= DEBUG_LEVEL_INFO )
1220 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1221 __FILE__,__LINE__,info->device_name );
1222
1223 spin_lock_irqsave(&info->lock,flags);
1224
1225 if (!info->tx_active) {
1226 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1227 info->tx_count ) {
1228 /* operating in synchronous (frame oriented) mode */
1229 /* copy data from circular tx_buf to */
1230 /* transmit DMA buffer. */
1231 tx_load_dma_buffer(info,
1232 info->tx_buf,info->tx_count);
1233 }
1234 tx_start(info);
1235 }
1236
1237 spin_unlock_irqrestore(&info->lock,flags);
1238}
1239
1240/* Discard all data in the send buffer
1241 */
1242static void flush_buffer(struct tty_struct *tty)
1243{
1244 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1245 unsigned long flags;
1246
1247 if (debug_level >= DEBUG_LEVEL_INFO)
1248 printk("%s(%d):%s flush_buffer() entry\n",
1249 __FILE__,__LINE__, info->device_name );
1250
1251 if (sanity_check(info, tty->name, "flush_buffer"))
1252 return;
1253
1254 spin_lock_irqsave(&info->lock,flags);
1255 info->tx_count = info->tx_put = info->tx_get = 0;
1256 del_timer(&info->tx_timer);
1257 spin_unlock_irqrestore(&info->lock,flags);
1258
1259 wake_up_interruptible(&tty->write_wait);
1260 tty_wakeup(tty);
1261}
1262
1263/* throttle (stop) transmitter
1264 */
1265static void tx_hold(struct tty_struct *tty)
1266{
1267 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1268 unsigned long flags;
1269
1270 if (sanity_check(info, tty->name, "tx_hold"))
1271 return;
1272
1273 if ( debug_level >= DEBUG_LEVEL_INFO )
1274 printk("%s(%d):%s tx_hold()\n",
1275 __FILE__,__LINE__,info->device_name);
1276
1277 spin_lock_irqsave(&info->lock,flags);
1278 if (info->tx_enabled)
1279 tx_stop(info);
1280 spin_unlock_irqrestore(&info->lock,flags);
1281}
1282
1283/* release (start) transmitter
1284 */
1285static void tx_release(struct tty_struct *tty)
1286{
1287 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1288 unsigned long flags;
1289
1290 if (sanity_check(info, tty->name, "tx_release"))
1291 return;
1292
1293 if ( debug_level >= DEBUG_LEVEL_INFO )
1294 printk("%s(%d):%s tx_release()\n",
1295 __FILE__,__LINE__,info->device_name);
1296
1297 spin_lock_irqsave(&info->lock,flags);
1298 if (!info->tx_enabled)
1299 tx_start(info);
1300 spin_unlock_irqrestore(&info->lock,flags);
1301}
1302
1303/* Service an IOCTL request
1304 *
1305 * Arguments:
1306 *
1307 * tty pointer to tty instance data
1308 * file pointer to associated file object for device
1309 * cmd IOCTL command code
1310 * arg command argument/context
1311 *
1312 * Return Value: 0 if success, otherwise error code
1313 */
1314static int ioctl(struct tty_struct *tty, struct file *file,
1315 unsigned int cmd, unsigned long arg)
1316{
1317 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1318 int error;
1319 struct mgsl_icount cnow; /* kernel counter temps */
1320 struct serial_icounter_struct __user *p_cuser; /* user space */
1321 unsigned long flags;
1322 void __user *argp = (void __user *)arg;
1323
1324 if (debug_level >= DEBUG_LEVEL_INFO)
1325 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1326 info->device_name, cmd );
1327
1328 if (sanity_check(info, tty->name, "ioctl"))
1329 return -ENODEV;
1330
1331 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1332 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1333 if (tty->flags & (1 << TTY_IO_ERROR))
1334 return -EIO;
1335 }
1336
1337 switch (cmd) {
1338 case MGSL_IOCGPARAMS:
1339 return get_params(info, argp);
1340 case MGSL_IOCSPARAMS:
1341 return set_params(info, argp);
1342 case MGSL_IOCGTXIDLE:
1343 return get_txidle(info, argp);
1344 case MGSL_IOCSTXIDLE:
1345 return set_txidle(info, (int)arg);
1346 case MGSL_IOCTXENABLE:
1347 return tx_enable(info, (int)arg);
1348 case MGSL_IOCRXENABLE:
1349 return rx_enable(info, (int)arg);
1350 case MGSL_IOCTXABORT:
1351 return tx_abort(info);
1352 case MGSL_IOCGSTATS:
1353 return get_stats(info, argp);
1354 case MGSL_IOCWAITEVENT:
1355 return wait_mgsl_event(info, argp);
1356 case MGSL_IOCLOOPTXDONE:
1357 return 0; // TODO: Not supported, need to document
1358 /* Wait for modem input (DCD,RI,DSR,CTS) change
1359 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1360 */
1361 case TIOCMIWAIT:
1362 return modem_input_wait(info,(int)arg);
1363
1364 /*
1365 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1366 * Return: write counters to the user passed counter struct
1367 * NB: both 1->0 and 0->1 transitions are counted except for
1368 * RI where only 0->1 is counted.
1369 */
1370 case TIOCGICOUNT:
1371 spin_lock_irqsave(&info->lock,flags);
1372 cnow = info->icount;
1373 spin_unlock_irqrestore(&info->lock,flags);
1374 p_cuser = argp;
1375 PUT_USER(error,cnow.cts, &p_cuser->cts);
1376 if (error) return error;
1377 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1378 if (error) return error;
1379 PUT_USER(error,cnow.rng, &p_cuser->rng);
1380 if (error) return error;
1381 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1382 if (error) return error;
1383 PUT_USER(error,cnow.rx, &p_cuser->rx);
1384 if (error) return error;
1385 PUT_USER(error,cnow.tx, &p_cuser->tx);
1386 if (error) return error;
1387 PUT_USER(error,cnow.frame, &p_cuser->frame);
1388 if (error) return error;
1389 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1390 if (error) return error;
1391 PUT_USER(error,cnow.parity, &p_cuser->parity);
1392 if (error) return error;
1393 PUT_USER(error,cnow.brk, &p_cuser->brk);
1394 if (error) return error;
1395 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1396 if (error) return error;
1397 return 0;
1398 default:
1399 return -ENOIOCTLCMD;
1400 }
1401 return 0;
1402}
1403
1404/*
1405 * /proc fs routines....
1406 */
1407
1408static inline int line_info(char *buf, SLMP_INFO *info)
1409{
1410 char stat_buf[30];
1411 int ret;
1412 unsigned long flags;
1413
1414 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1415 "\tIRQ=%d MaxFrameSize=%u\n",
1416 info->device_name,
1417 info->phys_sca_base,
1418 info->phys_memory_base,
1419 info->phys_statctrl_base,
1420 info->phys_lcr_base,
1421 info->irq_level,
1422 info->max_frame_size );
1423
1424 /* output current serial signal states */
1425 spin_lock_irqsave(&info->lock,flags);
1426 get_signals(info);
1427 spin_unlock_irqrestore(&info->lock,flags);
1428
1429 stat_buf[0] = 0;
1430 stat_buf[1] = 0;
1431 if (info->serial_signals & SerialSignal_RTS)
1432 strcat(stat_buf, "|RTS");
1433 if (info->serial_signals & SerialSignal_CTS)
1434 strcat(stat_buf, "|CTS");
1435 if (info->serial_signals & SerialSignal_DTR)
1436 strcat(stat_buf, "|DTR");
1437 if (info->serial_signals & SerialSignal_DSR)
1438 strcat(stat_buf, "|DSR");
1439 if (info->serial_signals & SerialSignal_DCD)
1440 strcat(stat_buf, "|CD");
1441 if (info->serial_signals & SerialSignal_RI)
1442 strcat(stat_buf, "|RI");
1443
1444 if (info->params.mode == MGSL_MODE_HDLC) {
1445 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1446 info->icount.txok, info->icount.rxok);
1447 if (info->icount.txunder)
1448 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1449 if (info->icount.txabort)
1450 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1451 if (info->icount.rxshort)
1452 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1453 if (info->icount.rxlong)
1454 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1455 if (info->icount.rxover)
1456 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1457 if (info->icount.rxcrc)
1458 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1459 } else {
1460 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1461 info->icount.tx, info->icount.rx);
1462 if (info->icount.frame)
1463 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1464 if (info->icount.parity)
1465 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1466 if (info->icount.brk)
1467 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1468 if (info->icount.overrun)
1469 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1470 }
1471
1472 /* Append serial signal status to end */
1473 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1474
1475 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1476 info->tx_active,info->bh_requested,info->bh_running,
1477 info->pending_bh);
1478
1479 return ret;
1480}
1481
1482/* Called to print information about devices
1483 */
1484int read_proc(char *page, char **start, off_t off, int count,
1485 int *eof, void *data)
1486{
1487 int len = 0, l;
1488 off_t begin = 0;
1489 SLMP_INFO *info;
1490
1491 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1492
1493 info = synclinkmp_device_list;
1494 while( info ) {
1495 l = line_info(page + len, info);
1496 len += l;
1497 if (len+begin > off+count)
1498 goto done;
1499 if (len+begin < off) {
1500 begin += len;
1501 len = 0;
1502 }
1503 info = info->next_device;
1504 }
1505
1506 *eof = 1;
1507done:
1508 if (off >= len+begin)
1509 return 0;
1510 *start = page + (off-begin);
1511 return ((count < begin+len-off) ? count : begin+len-off);
1512}
1513
1514/* Return the count of bytes in transmit buffer
1515 */
1516static int chars_in_buffer(struct tty_struct *tty)
1517{
1518 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1519
1520 if (sanity_check(info, tty->name, "chars_in_buffer"))
1521 return 0;
1522
1523 if (debug_level >= DEBUG_LEVEL_INFO)
1524 printk("%s(%d):%s chars_in_buffer()=%d\n",
1525 __FILE__, __LINE__, info->device_name, info->tx_count);
1526
1527 return info->tx_count;
1528}
1529
1530/* Signal remote device to throttle send data (our receive data)
1531 */
1532static void throttle(struct tty_struct * tty)
1533{
1534 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1535 unsigned long flags;
1536
1537 if (debug_level >= DEBUG_LEVEL_INFO)
1538 printk("%s(%d):%s throttle() entry\n",
1539 __FILE__,__LINE__, info->device_name );
1540
1541 if (sanity_check(info, tty->name, "throttle"))
1542 return;
1543
1544 if (I_IXOFF(tty))
1545 send_xchar(tty, STOP_CHAR(tty));
1546
1547 if (tty->termios->c_cflag & CRTSCTS) {
1548 spin_lock_irqsave(&info->lock,flags);
1549 info->serial_signals &= ~SerialSignal_RTS;
1550 set_signals(info);
1551 spin_unlock_irqrestore(&info->lock,flags);
1552 }
1553}
1554
1555/* Signal remote device to stop throttling send data (our receive data)
1556 */
1557static void unthrottle(struct tty_struct * tty)
1558{
1559 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1560 unsigned long flags;
1561
1562 if (debug_level >= DEBUG_LEVEL_INFO)
1563 printk("%s(%d):%s unthrottle() entry\n",
1564 __FILE__,__LINE__, info->device_name );
1565
1566 if (sanity_check(info, tty->name, "unthrottle"))
1567 return;
1568
1569 if (I_IXOFF(tty)) {
1570 if (info->x_char)
1571 info->x_char = 0;
1572 else
1573 send_xchar(tty, START_CHAR(tty));
1574 }
1575
1576 if (tty->termios->c_cflag & CRTSCTS) {
1577 spin_lock_irqsave(&info->lock,flags);
1578 info->serial_signals |= SerialSignal_RTS;
1579 set_signals(info);
1580 spin_unlock_irqrestore(&info->lock,flags);
1581 }
1582}
1583
1584/* set or clear transmit break condition
1585 * break_state -1=set break condition, 0=clear
1586 */
1587static void set_break(struct tty_struct *tty, int break_state)
1588{
1589 unsigned char RegValue;
1590 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1591 unsigned long flags;
1592
1593 if (debug_level >= DEBUG_LEVEL_INFO)
1594 printk("%s(%d):%s set_break(%d)\n",
1595 __FILE__,__LINE__, info->device_name, break_state);
1596
1597 if (sanity_check(info, tty->name, "set_break"))
1598 return;
1599
1600 spin_lock_irqsave(&info->lock,flags);
1601 RegValue = read_reg(info, CTL);
1602 if (break_state == -1)
1603 RegValue |= BIT3;
1604 else
1605 RegValue &= ~BIT3;
1606 write_reg(info, CTL, RegValue);
1607 spin_unlock_irqrestore(&info->lock,flags);
1608}
1609
1610#ifdef CONFIG_HDLC
1611
1612/**
1613 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1614 * set encoding and frame check sequence (FCS) options
1615 *
1616 * dev pointer to network device structure
1617 * encoding serial encoding setting
1618 * parity FCS setting
1619 *
1620 * returns 0 if success, otherwise error code
1621 */
1622static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1623 unsigned short parity)
1624{
1625 SLMP_INFO *info = dev_to_port(dev);
1626 unsigned char new_encoding;
1627 unsigned short new_crctype;
1628
1629 /* return error if TTY interface open */
1630 if (info->count)
1631 return -EBUSY;
1632
1633 switch (encoding)
1634 {
1635 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1636 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1637 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1638 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1639 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1640 default: return -EINVAL;
1641 }
1642
1643 switch (parity)
1644 {
1645 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1646 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1647 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1648 default: return -EINVAL;
1649 }
1650
1651 info->params.encoding = new_encoding;
53b3531b 1652 info->params.crc_type = new_crctype;
1da177e4
LT		 1653
1654 /* if network interface up, reprogram hardware */
1655 if (info->netcount)
1656 program_hw(info);
1657
1658 return 0;
1659}
1660
1661/**
1662 * called by generic HDLC layer to send frame
1663 *
1664 * skb socket buffer containing HDLC frame
1665 * dev pointer to network device structure
1666 *
1667 * returns 0 if success, otherwise error code
1668 */
1669static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1670{
1671 SLMP_INFO *info = dev_to_port(dev);
1672 struct net_device_stats *stats = hdlc_stats(dev);
1673 unsigned long flags;
1674
1675 if (debug_level >= DEBUG_LEVEL_INFO)
1676 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1677
1678 /* stop sending until this frame completes */
1679 netif_stop_queue(dev);
1680
1681 /* copy data to device buffers */
1682 info->tx_count = skb->len;
1683 tx_load_dma_buffer(info, skb->data, skb->len);
1684
1685 /* update network statistics */
1686 stats->tx_packets++;
1687 stats->tx_bytes += skb->len;
1688
1689 /* done with socket buffer, so free it */
1690 dev_kfree_skb(skb);
1691
1692 /* save start time for transmit timeout detection */
1693 dev->trans_start = jiffies;
1694
1695 /* start hardware transmitter if necessary */
1696 spin_lock_irqsave(&info->lock,flags);
1697 if (!info->tx_active)
1698 tx_start(info);
1699 spin_unlock_irqrestore(&info->lock,flags);
1700
1701 return 0;
1702}
1703
1704/**
1705 * called by network layer when interface enabled
1706 * claim resources and initialize hardware
1707 *
1708 * dev pointer to network device structure
1709 *
1710 * returns 0 if success, otherwise error code
1711 */
1712static int hdlcdev_open(struct net_device *dev)
1713{
1714 SLMP_INFO *info = dev_to_port(dev);
1715 int rc;
1716 unsigned long flags;
1717
1718 if (debug_level >= DEBUG_LEVEL_INFO)
1719 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1720
1721 /* generic HDLC layer open processing */
1722 if ((rc = hdlc_open(dev)))
1723 return rc;
1724
1725 /* arbitrate between network and tty opens */
1726 spin_lock_irqsave(&info->netlock, flags);
1727 if (info->count != 0 || info->netcount != 0) {
1728 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1729 spin_unlock_irqrestore(&info->netlock, flags);
1730 return -EBUSY;
1731 }
1732 info->netcount=1;
1733 spin_unlock_irqrestore(&info->netlock, flags);
1734
1735 /* claim resources and init adapter */
1736 if ((rc = startup(info)) != 0) {
1737 spin_lock_irqsave(&info->netlock, flags);
1738 info->netcount=0;
1739 spin_unlock_irqrestore(&info->netlock, flags);
1740 return rc;
1741 }
1742
1743 /* assert DTR and RTS, apply hardware settings */
1744 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1745 program_hw(info);
1746
1747 /* enable network layer transmit */
1748 dev->trans_start = jiffies;
1749 netif_start_queue(dev);
1750
1751 /* inform generic HDLC layer of current DCD status */
1752 spin_lock_irqsave(&info->lock, flags);
1753 get_signals(info);
1754 spin_unlock_irqrestore(&info->lock, flags);
fbeff3c1
KH		 1755 if (info->serial_signals & SerialSignal_DCD)
1756 netif_carrier_on(dev);
1757 else
1758 netif_carrier_off(dev);
1da177e4
LT		 1759 return 0;
1760}
1761
1762/**
1763 * called by network layer when interface is disabled
1764 * shutdown hardware and release resources
1765 *
1766 * dev pointer to network device structure
1767 *
1768 * returns 0 if success, otherwise error code
1769 */
1770static int hdlcdev_close(struct net_device *dev)
1771{
1772 SLMP_INFO *info = dev_to_port(dev);
1773 unsigned long flags;
1774
1775 if (debug_level >= DEBUG_LEVEL_INFO)
1776 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1777
1778 netif_stop_queue(dev);
1779
1780 /* shutdown adapter and release resources */
1781 shutdown(info);
1782
1783 hdlc_close(dev);
1784
1785 spin_lock_irqsave(&info->netlock, flags);
1786 info->netcount=0;
1787 spin_unlock_irqrestore(&info->netlock, flags);
1788
1789 return 0;
1790}
1791
1792/**
1793 * called by network layer to process IOCTL call to network device
1794 *
1795 * dev pointer to network device structure
1796 * ifr pointer to network interface request structure
1797 * cmd IOCTL command code
1798 *
1799 * returns 0 if success, otherwise error code
1800 */
1801static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1802{
1803 const size_t size = sizeof(sync_serial_settings);
1804 sync_serial_settings new_line;
1805 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1806 SLMP_INFO *info = dev_to_port(dev);
1807 unsigned int flags;
1808
1809 if (debug_level >= DEBUG_LEVEL_INFO)
1810 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1811
1812 /* return error if TTY interface open */
1813 if (info->count)
1814 return -EBUSY;
1815
1816 if (cmd != SIOCWANDEV)
1817 return hdlc_ioctl(dev, ifr, cmd);
1818
1819 switch(ifr->ifr_settings.type) {
1820 case IF_GET_IFACE: /* return current sync_serial_settings */
1821
1822 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1823 if (ifr->ifr_settings.size < size) {
1824 ifr->ifr_settings.size = size; /* data size wanted */
1825 return -ENOBUFS;
1826 }
1827
1828 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1829 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1830 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1831 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1832
1833 switch (flags){
1834 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1835 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1836 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1837 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1838 default: new_line.clock_type = CLOCK_DEFAULT;
1839 }
1840
1841 new_line.clock_rate = info->params.clock_speed;
1842 new_line.loopback = info->params.loopback ? 1:0;
1843
1844 if (copy_to_user(line, &new_line, size))
1845 return -EFAULT;
1846 return 0;
1847
1848 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1849
1850 if(!capable(CAP_NET_ADMIN))
1851 return -EPERM;
1852 if (copy_from_user(&new_line, line, size))
1853 return -EFAULT;
1854
1855 switch (new_line.clock_type)
1856 {
1857 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1858 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1859 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1860 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1861 case CLOCK_DEFAULT: flags = info->params.flags &
1862 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1863 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1864 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1865 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1866 default: return -EINVAL;
1867 }
1868
1869 if (new_line.loopback != 0 && new_line.loopback != 1)
1870 return -EINVAL;
1871
1872 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1873 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1874 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1875 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1876 info->params.flags |= flags;
1877
1878 info->params.loopback = new_line.loopback;
1879
1880 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1881 info->params.clock_speed = new_line.clock_rate;
1882 else
1883 info->params.clock_speed = 0;
1884
1885 /* if network interface up, reprogram hardware */
1886 if (info->netcount)
1887 program_hw(info);
1888 return 0;
1889
1890 default:
1891 return hdlc_ioctl(dev, ifr, cmd);
1892 }
1893}
1894
1895/**
1896 * called by network layer when transmit timeout is detected
1897 *
1898 * dev pointer to network device structure
1899 */
1900static void hdlcdev_tx_timeout(struct net_device *dev)
1901{
1902 SLMP_INFO *info = dev_to_port(dev);
1903 struct net_device_stats *stats = hdlc_stats(dev);
1904 unsigned long flags;
1905
1906 if (debug_level >= DEBUG_LEVEL_INFO)
1907 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1908
1909 stats->tx_errors++;
1910 stats->tx_aborted_errors++;
1911
1912 spin_lock_irqsave(&info->lock,flags);
1913 tx_stop(info);
1914 spin_unlock_irqrestore(&info->lock,flags);
1915
1916 netif_wake_queue(dev);
1917}
1918
1919/**
1920 * called by device driver when transmit completes
1921 * reenable network layer transmit if stopped
1922 *
1923 * info pointer to device instance information
1924 */
1925static void hdlcdev_tx_done(SLMP_INFO *info)
1926{
1927 if (netif_queue_stopped(info->netdev))
1928 netif_wake_queue(info->netdev);
1929}
1930
1931/**
1932 * called by device driver when frame received
1933 * pass frame to network layer
1934 *
1935 * info pointer to device instance information
1936 * buf pointer to buffer contianing frame data
1937 * size count of data bytes in buf
1938 */
1939static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1940{
1941 struct sk_buff *skb = dev_alloc_skb(size);
1942 struct net_device *dev = info->netdev;
1943 struct net_device_stats *stats = hdlc_stats(dev);
1944
1945 if (debug_level >= DEBUG_LEVEL_INFO)
1946 printk("hdlcdev_rx(%s)\n",dev->name);
1947
1948 if (skb == NULL) {
1949 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1950 stats->rx_dropped++;
1951 return;
1952 }
1953
1954 memcpy(skb_put(skb, size),buf,size);
1955
1956 skb->protocol = hdlc_type_trans(skb, info->netdev);
1957
1958 stats->rx_packets++;
1959 stats->rx_bytes += size;
1960
1961 netif_rx(skb);
1962
1963 info->netdev->last_rx = jiffies;
1964}
1965
1966/**
1967 * called by device driver when adding device instance
1968 * do generic HDLC initialization
1969 *
1970 * info pointer to device instance information
1971 *
1972 * returns 0 if success, otherwise error code
1973 */
1974static int hdlcdev_init(SLMP_INFO *info)
1975{
1976 int rc;
1977 struct net_device *dev;
1978 hdlc_device *hdlc;
1979
1980 /* allocate and initialize network and HDLC layer objects */
1981
1982 if (!(dev = alloc_hdlcdev(info))) {
1983 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1984 return -ENOMEM;
1985 }
1986
1987 /* for network layer reporting purposes only */
1988 dev->mem_start = info->phys_sca_base;
1989 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1990 dev->irq = info->irq_level;
1991
1992 /* network layer callbacks and settings */
1993 dev->do_ioctl = hdlcdev_ioctl;
1994 dev->open = hdlcdev_open;
1995 dev->stop = hdlcdev_close;
1996 dev->tx_timeout = hdlcdev_tx_timeout;
1997 dev->watchdog_timeo = 10*HZ;
1998 dev->tx_queue_len = 50;
1999
2000 /* generic HDLC layer callbacks and settings */
2001 hdlc = dev_to_hdlc(dev);
2002 hdlc->attach = hdlcdev_attach;
2003 hdlc->xmit = hdlcdev_xmit;
2004
2005 /* register objects with HDLC layer */
2006 if ((rc = register_hdlc_device(dev))) {
2007 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2008 free_netdev(dev);
2009 return rc;
2010 }
2011
2012 info->netdev = dev;
2013 return 0;
2014}
2015
2016/**
2017 * called by device driver when removing device instance
2018 * do generic HDLC cleanup
2019 *
2020 * info pointer to device instance information
2021 */
2022static void hdlcdev_exit(SLMP_INFO *info)
2023{
2024 unregister_hdlc_device(info->netdev);
2025 free_netdev(info->netdev);
2026 info->netdev = NULL;
2027}
2028
2029#endif /* CONFIG_HDLC */
2030
2031
2032/* Return next bottom half action to perform.
2033 * Return Value: BH action code or 0 if nothing to do.
2034 */
2035int bh_action(SLMP_INFO *info)
2036{
2037 unsigned long flags;
2038 int rc = 0;
2039
2040 spin_lock_irqsave(&info->lock,flags);
2041
2042 if (info->pending_bh & BH_RECEIVE) {
2043 info->pending_bh &= ~BH_RECEIVE;
2044 rc = BH_RECEIVE;
2045 } else if (info->pending_bh & BH_TRANSMIT) {
2046 info->pending_bh &= ~BH_TRANSMIT;
2047 rc = BH_TRANSMIT;
2048 } else if (info->pending_bh & BH_STATUS) {
2049 info->pending_bh &= ~BH_STATUS;
2050 rc = BH_STATUS;
2051 }
2052
2053 if (!rc) {
2054 /* Mark BH routine as complete */
2055 info->bh_running = 0;
2056 info->bh_requested = 0;
2057 }
2058
2059 spin_unlock_irqrestore(&info->lock,flags);
2060
2061 return rc;
2062}
2063
2064/* Perform bottom half processing of work items queued by ISR.
2065 */
2066void bh_handler(void* Context)
2067{
2068 SLMP_INFO *info = (SLMP_INFO*)Context;
2069 int action;
2070
2071 if (!info)
2072 return;
2073
2074 if ( debug_level >= DEBUG_LEVEL_BH )
2075 printk( "%s(%d):%s bh_handler() entry\n",
2076 __FILE__,__LINE__,info->device_name);
2077
2078 info->bh_running = 1;
2079
2080 while((action = bh_action(info)) != 0) {
2081
2082 /* Process work item */
2083 if ( debug_level >= DEBUG_LEVEL_BH )
2084 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2085 __FILE__,__LINE__,info->device_name, action);
2086
2087 switch (action) {
2088
2089 case BH_RECEIVE:
2090 bh_receive(info);
2091 break;
2092 case BH_TRANSMIT:
2093 bh_transmit(info);
2094 break;
2095 case BH_STATUS:
2096 bh_status(info);
2097 break;
2098 default:
2099 /* unknown work item ID */
2100 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2101 __FILE__,__LINE__,info->device_name,action);
2102 break;
2103 }
2104 }
2105
2106 if ( debug_level >= DEBUG_LEVEL_BH )
2107 printk( "%s(%d):%s bh_handler() exit\n",
2108 __FILE__,__LINE__,info->device_name);
2109}
2110
2111void bh_receive(SLMP_INFO *info)
2112{
2113 if ( debug_level >= DEBUG_LEVEL_BH )
2114 printk( "%s(%d):%s bh_receive()\n",
2115 __FILE__,__LINE__,info->device_name);
2116
2117 while( rx_get_frame(info) );
2118}
2119
2120void bh_transmit(SLMP_INFO *info)
2121{
2122 struct tty_struct *tty = info->tty;
2123
2124 if ( debug_level >= DEBUG_LEVEL_BH )
2125 printk( "%s(%d):%s bh_transmit() entry\n",
2126 __FILE__,__LINE__,info->device_name);
2127
2128 if (tty) {
2129 tty_wakeup(tty);
2130 wake_up_interruptible(&tty->write_wait);
2131 }
2132}
2133
2134void bh_status(SLMP_INFO *info)
2135{
2136 if ( debug_level >= DEBUG_LEVEL_BH )
2137 printk( "%s(%d):%s bh_status() entry\n",
2138 __FILE__,__LINE__,info->device_name);
2139
2140 info->ri_chkcount = 0;
2141 info->dsr_chkcount = 0;
2142 info->dcd_chkcount = 0;
2143 info->cts_chkcount = 0;
2144}
2145
2146void isr_timer(SLMP_INFO * info)
2147{
2148 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2149
2150 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2151 write_reg(info, IER2, 0);
2152
2153 /* TMCS, Timer Control/Status Register
2154 *
2155 * 07 CMF, Compare match flag (read only) 1=match
2156 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2157 * 05 Reserved, must be 0
2158 * 04 TME, Timer Enable
2159 * 03..00 Reserved, must be 0
2160 *
2161 * 0000 0000
2162 */
2163 write_reg(info, (unsigned char)(timer + TMCS), 0);
2164
2165 info->irq_occurred = TRUE;
2166
2167 if ( debug_level >= DEBUG_LEVEL_ISR )
2168 printk("%s(%d):%s isr_timer()\n",
2169 __FILE__,__LINE__,info->device_name);
2170}
2171
2172void isr_rxint(SLMP_INFO * info)
2173{
2174 struct tty_struct *tty = info->tty;
2175 struct mgsl_icount *icount = &info->icount;
2176 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2177 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2178
2179 /* clear status bits */
2180 if (status)
2181 write_reg(info, SR1, status);
2182
2183 if (status2)
2184 write_reg(info, SR2, status2);
2185
2186 if ( debug_level >= DEBUG_LEVEL_ISR )
2187 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2188 __FILE__,__LINE__,info->device_name,status,status2);
2189
2190 if (info->params.mode == MGSL_MODE_ASYNC) {
2191 if (status & BRKD) {
2192 icount->brk++;
2193
2194 /* process break detection if tty control
2195 * is not set to ignore it
2196 */
2197 if ( tty ) {
2198 if (!(status & info->ignore_status_mask1)) {
2199 if (info->read_status_mask1 & BRKD) {
33f0f88f 2200 tty_insert_flip_char(tty, 0, TTY_BREAK);
1da177e4
LT		 2201 if (info->flags & ASYNC_SAK)
2202 do_SAK(tty);
2203 }
2204 }
2205 }
2206 }
2207 }
2208 else {
2209 if (status & (FLGD|IDLD)) {
2210 if (status & FLGD)
2211 info->icount.exithunt++;
2212 else if (status & IDLD)
2213 info->icount.rxidle++;
2214 wake_up_interruptible(&info->event_wait_q);
2215 }
2216 }
2217
2218 if (status & CDCD) {
2219 /* simulate a common modem status change interrupt
2220 * for our handler
2221 */
2222 get_signals( info );
2223 isr_io_pin(info,
2224 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2225 }
2226}
2227
2228/*
2229 * handle async rx data interrupts
2230 */
2231void isr_rxrdy(SLMP_INFO * info)
2232{
2233 u16 status;
2234 unsigned char DataByte;
2235 struct tty_struct *tty = info->tty;
2236 struct mgsl_icount *icount = &info->icount;
2237
2238 if ( debug_level >= DEBUG_LEVEL_ISR )
2239 printk("%s(%d):%s isr_rxrdy\n",
2240 __FILE__,__LINE__,info->device_name);
2241
2242 while((status = read_reg(info,CST0)) & BIT0)
2243 {
33f0f88f
AC		 2244 int flag = 0;
2245 int over = 0;
1da177e4
LT		 2246 DataByte = read_reg(info,TRB);
2247
1da177e4
LT		 2248 icount->rx++;
2249
2250 if ( status & (PE + FRME + OVRN) ) {
2251 printk("%s(%d):%s rxerr=%04X\n",
2252 __FILE__,__LINE__,info->device_name,status);
2253
2254 /* update error statistics */
2255 if (status & PE)
2256 icount->parity++;
2257 else if (status & FRME)
2258 icount->frame++;
2259 else if (status & OVRN)
2260 icount->overrun++;
2261
2262 /* discard char if tty control flags say so */
2263 if (status & info->ignore_status_mask2)
2264 continue;
2265
2266 status &= info->read_status_mask2;
2267
2268 if ( tty ) {
2269 if (status & PE)
33f0f88f 2270 flag = TTY_PARITY;
1da177e4 2271 else if (status & FRME)
33f0f88f 2272 flag = TTY_FRAME;
1da177e4
LT		 2273 if (status & OVRN) {
2274 /* Overrun is special, since it's
2275 * reported immediately, and doesn't
2276 * affect the current character
2277 */
33f0f88f 2278 over = 1;
1da177e4
LT		 2279 }
2280 }
2281 } /* end of if (error) */
2282
2283 if ( tty ) {
33f0f88f
AC		 2284 tty_insert_flip_char(tty, DataByte, flag);
2285 if (over)
2286 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1da177e4
LT		 2287 }
2288 }
2289
2290 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1da177e4
LT		 2291 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2292 __FILE__,__LINE__,info->device_name,
2293 icount->rx,icount->brk,icount->parity,
2294 icount->frame,icount->overrun);
2295 }
2296
33f0f88f 2297 if ( tty )
1da177e4
LT		 2298 tty_flip_buffer_push(tty);
2299}
2300
2301static void isr_txeom(SLMP_INFO * info, unsigned char status)
2302{
2303 if ( debug_level >= DEBUG_LEVEL_ISR )
2304 printk("%s(%d):%s isr_txeom status=%02x\n",
2305 __FILE__,__LINE__,info->device_name,status);
2306
2307 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2308 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2309 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2310
2311 if (status & UDRN) {
2312 write_reg(info, CMD, TXRESET);
2313 write_reg(info, CMD, TXENABLE);
2314 } else
2315 write_reg(info, CMD, TXBUFCLR);
2316
2317 /* disable and clear tx interrupts */
2318 info->ie0_value &= ~TXRDYE;
2319 info->ie1_value &= ~(IDLE + UDRN);
2320 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2321 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2322
2323 if ( info->tx_active ) {
2324 if (info->params.mode != MGSL_MODE_ASYNC) {
2325 if (status & UDRN)
2326 info->icount.txunder++;
2327 else if (status & IDLE)
2328 info->icount.txok++;
2329 }
2330
2331 info->tx_active = 0;
2332 info->tx_count = info->tx_put = info->tx_get = 0;
2333
2334 del_timer(&info->tx_timer);
2335
2336 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2337 info->serial_signals &= ~SerialSignal_RTS;
2338 info->drop_rts_on_tx_done = 0;
2339 set_signals(info);
2340 }
2341
2342#ifdef CONFIG_HDLC
2343 if (info->netcount)
2344 hdlcdev_tx_done(info);
2345 else
2346#endif
2347 {
2348 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2349 tx_stop(info);
2350 return;
2351 }
2352 info->pending_bh |= BH_TRANSMIT;
2353 }
2354 }
2355}
2356
2357
2358/*
2359 * handle tx status interrupts
2360 */
2361void isr_txint(SLMP_INFO * info)
2362{
2363 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2364
2365 /* clear status bits */
2366 write_reg(info, SR1, status);
2367
2368 if ( debug_level >= DEBUG_LEVEL_ISR )
2369 printk("%s(%d):%s isr_txint status=%02x\n",
2370 __FILE__,__LINE__,info->device_name,status);
2371
2372 if (status & (UDRN + IDLE))
2373 isr_txeom(info, status);
2374
2375 if (status & CCTS) {
2376 /* simulate a common modem status change interrupt
2377 * for our handler
2378 */
2379 get_signals( info );
2380 isr_io_pin(info,
2381 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2382
2383 }
2384}
2385
2386/*
2387 * handle async tx data interrupts
2388 */
2389void isr_txrdy(SLMP_INFO * info)
2390{
2391 if ( debug_level >= DEBUG_LEVEL_ISR )
2392 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2393 __FILE__,__LINE__,info->device_name,info->tx_count);
2394
2395 if (info->params.mode != MGSL_MODE_ASYNC) {
2396 /* disable TXRDY IRQ, enable IDLE IRQ */
2397 info->ie0_value &= ~TXRDYE;
2398 info->ie1_value |= IDLE;
2399 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2400 return;
2401 }
2402
2403 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2404 tx_stop(info);
2405 return;
2406 }
2407
2408 if ( info->tx_count )
2409 tx_load_fifo( info );
2410 else {
2411 info->tx_active = 0;
2412 info->ie0_value &= ~TXRDYE;
2413 write_reg(info, IE0, info->ie0_value);
2414 }
2415
2416 if (info->tx_count < WAKEUP_CHARS)
2417 info->pending_bh |= BH_TRANSMIT;
2418}
2419
2420void isr_rxdmaok(SLMP_INFO * info)
2421{
2422 /* BIT7 = EOT (end of transfer)
2423 * BIT6 = EOM (end of message/frame)
2424 */
2425 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2426
2427 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2428 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2429
2430 if ( debug_level >= DEBUG_LEVEL_ISR )
2431 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2432 __FILE__,__LINE__,info->device_name,status);
2433
2434 info->pending_bh |= BH_RECEIVE;
2435}
2436
2437void isr_rxdmaerror(SLMP_INFO * info)
2438{
2439 /* BIT5 = BOF (buffer overflow)
2440 * BIT4 = COF (counter overflow)
2441 */
2442 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2443
2444 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2445 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2446
2447 if ( debug_level >= DEBUG_LEVEL_ISR )
2448 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2449 __FILE__,__LINE__,info->device_name,status);
2450
2451 info->rx_overflow = TRUE;
2452 info->pending_bh |= BH_RECEIVE;
2453}
2454
2455void isr_txdmaok(SLMP_INFO * info)
2456{
2457 unsigned char status_reg1 = read_reg(info, SR1);
2458
2459 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2460 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2461 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2462
2463 if ( debug_level >= DEBUG_LEVEL_ISR )
2464 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2465 __FILE__,__LINE__,info->device_name,status_reg1);
2466
2467 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2468 write_reg16(info, TRC0, 0);
2469 info->ie0_value |= TXRDYE;
2470 write_reg(info, IE0, info->ie0_value);
2471}
2472
2473void isr_txdmaerror(SLMP_INFO * info)
2474{
2475 /* BIT5 = BOF (buffer overflow)
2476 * BIT4 = COF (counter overflow)
2477 */
2478 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2479
2480 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2481 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2482
2483 if ( debug_level >= DEBUG_LEVEL_ISR )
2484 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2485 __FILE__,__LINE__,info->device_name,status);
2486}
2487
2488/* handle input serial signal changes
2489 */
2490void isr_io_pin( SLMP_INFO *info, u16 status )
2491{
2492 struct mgsl_icount *icount;
2493
2494 if ( debug_level >= DEBUG_LEVEL_ISR )
2495 printk("%s(%d):isr_io_pin status=%04X\n",
2496 __FILE__,__LINE__,status);
2497
2498 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2499 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2500 icount = &info->icount;
2501 /* update input line counters */
2502 if (status & MISCSTATUS_RI_LATCHED) {
2503 icount->rng++;
2504 if ( status & SerialSignal_RI )
2505 info->input_signal_events.ri_up++;
2506 else
2507 info->input_signal_events.ri_down++;
2508 }
2509 if (status & MISCSTATUS_DSR_LATCHED) {
2510 icount->dsr++;
2511 if ( status & SerialSignal_DSR )
2512 info->input_signal_events.dsr_up++;
2513 else
2514 info->input_signal_events.dsr_down++;
2515 }
2516 if (status & MISCSTATUS_DCD_LATCHED) {
2517 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2518 info->ie1_value &= ~CDCD;
2519 write_reg(info, IE1, info->ie1_value);
2520 }
2521 icount->dcd++;
2522 if (status & SerialSignal_DCD) {
2523 info->input_signal_events.dcd_up++;
2524 } else
2525 info->input_signal_events.dcd_down++;
2526#ifdef CONFIG_HDLC
fbeff3c1
KH		 2527 if (info->netcount) {
2528 if (status & SerialSignal_DCD)
2529 netif_carrier_on(info->netdev);
2530 else
2531 netif_carrier_off(info->netdev);
2532 }
1da177e4
LT		 2533#endif
2534 }
2535 if (status & MISCSTATUS_CTS_LATCHED)
2536 {
2537 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2538 info->ie1_value &= ~CCTS;
2539 write_reg(info, IE1, info->ie1_value);
2540 }
2541 icount->cts++;
2542 if ( status & SerialSignal_CTS )
2543 info->input_signal_events.cts_up++;
2544 else
2545 info->input_signal_events.cts_down++;
2546 }
2547 wake_up_interruptible(&info->status_event_wait_q);
2548 wake_up_interruptible(&info->event_wait_q);
2549
2550 if ( (info->flags & ASYNC_CHECK_CD) &&
2551 (status & MISCSTATUS_DCD_LATCHED) ) {
2552 if ( debug_level >= DEBUG_LEVEL_ISR )
2553 printk("%s CD now %s...", info->device_name,
2554 (status & SerialSignal_DCD) ? "on" : "off");
2555 if (status & SerialSignal_DCD)
2556 wake_up_interruptible(&info->open_wait);
2557 else {
2558 if ( debug_level >= DEBUG_LEVEL_ISR )
2559 printk("doing serial hangup...");
2560 if (info->tty)
2561 tty_hangup(info->tty);
2562 }
2563 }
2564
2565 if ( (info->flags & ASYNC_CTS_FLOW) &&
2566 (status & MISCSTATUS_CTS_LATCHED) ) {
2567 if ( info->tty ) {
2568 if (info->tty->hw_stopped) {
2569 if (status & SerialSignal_CTS) {
2570 if ( debug_level >= DEBUG_LEVEL_ISR )
2571 printk("CTS tx start...");
2572 info->tty->hw_stopped = 0;
2573 tx_start(info);
2574 info->pending_bh |= BH_TRANSMIT;
2575 return;
2576 }
2577 } else {
2578 if (!(status & SerialSignal_CTS)) {
2579 if ( debug_level >= DEBUG_LEVEL_ISR )
2580 printk("CTS tx stop...");
2581 info->tty->hw_stopped = 1;
2582 tx_stop(info);
2583 }
2584 }
2585 }
2586 }
2587 }
2588
2589 info->pending_bh |= BH_STATUS;
2590}
2591
2592/* Interrupt service routine entry point.
2593 *
2594 * Arguments:
2595 * irq interrupt number that caused interrupt
2596 * dev_id device ID supplied during interrupt registration
2597 * regs interrupted processor context
2598 */
7d12e780 2599static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id)
1da177e4
LT		 2600{
2601 SLMP_INFO * info;
2602 unsigned char status, status0, status1=0;
2603 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2604 unsigned char timerstatus0, timerstatus1=0;
2605 unsigned char shift;
2606 unsigned int i;
2607 unsigned short tmp;
2608
2609 if ( debug_level >= DEBUG_LEVEL_ISR )
2610 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2611 __FILE__,__LINE__,irq);
2612
2613 info = (SLMP_INFO *)dev_id;
2614 if (!info)
2615 return IRQ_NONE;
2616
2617 spin_lock(&info->lock);
2618
2619 for(;;) {
2620
2621 /* get status for SCA0 (ports 0-1) */
2622 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2623 status0 = (unsigned char)tmp;
2624 dmastatus0 = (unsigned char)(tmp>>8);
2625 timerstatus0 = read_reg(info, ISR2);
2626
2627 if ( debug_level >= DEBUG_LEVEL_ISR )
2628 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2629 __FILE__,__LINE__,info->device_name,
2630 status0,dmastatus0,timerstatus0);
2631
2632 if (info->port_count == 4) {
2633 /* get status for SCA1 (ports 2-3) */
2634 tmp = read_reg16(info->port_array[2], ISR0);
2635 status1 = (unsigned char)tmp;
2636 dmastatus1 = (unsigned char)(tmp>>8);
2637 timerstatus1 = read_reg(info->port_array[2], ISR2);
2638
2639 if ( debug_level >= DEBUG_LEVEL_ISR )
2640 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2641 __FILE__,__LINE__,info->device_name,
2642 status1,dmastatus1,timerstatus1);
2643 }
2644
2645 if (!status0 && !dmastatus0 && !timerstatus0 &&
2646 !status1 && !dmastatus1 && !timerstatus1)
2647 break;
2648
2649 for(i=0; i < info->port_count ; i++) {
2650 if (info->port_array[i] == NULL)
2651 continue;
2652 if (i < 2) {
2653 status = status0;
2654 dmastatus = dmastatus0;
2655 } else {
2656 status = status1;
2657 dmastatus = dmastatus1;
2658 }
2659
2660 shift = i & 1 ? 4 :0;
2661
2662 if (status & BIT0 << shift)
2663 isr_rxrdy(info->port_array[i]);
2664 if (status & BIT1 << shift)
2665 isr_txrdy(info->port_array[i]);
2666 if (status & BIT2 << shift)
2667 isr_rxint(info->port_array[i]);
2668 if (status & BIT3 << shift)
2669 isr_txint(info->port_array[i]);
2670
2671 if (dmastatus & BIT0 << shift)
2672 isr_rxdmaerror(info->port_array[i]);
2673 if (dmastatus & BIT1 << shift)
2674 isr_rxdmaok(info->port_array[i]);
2675 if (dmastatus & BIT2 << shift)
2676 isr_txdmaerror(info->port_array[i]);
2677 if (dmastatus & BIT3 << shift)
2678 isr_txdmaok(info->port_array[i]);
2679 }
2680
2681 if (timerstatus0 & (BIT5 | BIT4))
2682 isr_timer(info->port_array[0]);
2683 if (timerstatus0 & (BIT7 | BIT6))
2684 isr_timer(info->port_array[1]);
2685 if (timerstatus1 & (BIT5 | BIT4))
2686 isr_timer(info->port_array[2]);
2687 if (timerstatus1 & (BIT7 | BIT6))
2688 isr_timer(info->port_array[3]);
2689 }
2690
2691 for(i=0; i < info->port_count ; i++) {
2692 SLMP_INFO * port = info->port_array[i];
2693
2694 /* Request bottom half processing if there's something
2695 * for it to do and the bh is not already running.
2696 *
2697 * Note: startup adapter diags require interrupts.
2698 * do not request bottom half processing if the
2699 * device is not open in a normal mode.
2700 */
2701 if ( port && (port->count || port->netcount) &&
2702 port->pending_bh && !port->bh_running &&
2703 !port->bh_requested ) {
2704 if ( debug_level >= DEBUG_LEVEL_ISR )
2705 printk("%s(%d):%s queueing bh task.\n",
2706 __FILE__,__LINE__,port->device_name);
2707 schedule_work(&port->task);
2708 port->bh_requested = 1;
2709 }
2710 }
2711
2712 spin_unlock(&info->lock);
2713
2714 if ( debug_level >= DEBUG_LEVEL_ISR )
2715 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2716 __FILE__,__LINE__,irq);
2717 return IRQ_HANDLED;
2718}
2719
2720/* Initialize and start device.
2721 */
2722static int startup(SLMP_INFO * info)
2723{
2724 if ( debug_level >= DEBUG_LEVEL_INFO )
2725 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2726
2727 if (info->flags & ASYNC_INITIALIZED)
2728 return 0;
2729
2730 if (!info->tx_buf) {
2731 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2732 if (!info->tx_buf) {
2733 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2734 __FILE__,__LINE__,info->device_name);
2735 return -ENOMEM;
2736 }
2737 }
2738
2739 info->pending_bh = 0;
2740
166692e4
PF		 2741 memset(&info->icount, 0, sizeof(info->icount));
2742
1da177e4
LT		 2743 /* program hardware for current parameters */
2744 reset_port(info);
2745
2746 change_params(info);
2747
2748 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2749 add_timer(&info->status_timer);
2750
2751 if (info->tty)
2752 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2753
2754 info->flags |= ASYNC_INITIALIZED;
2755
2756 return 0;
2757}
2758
2759/* Called by close() and hangup() to shutdown hardware
2760 */
2761static void shutdown(SLMP_INFO * info)
2762{
2763 unsigned long flags;
2764
2765 if (!(info->flags & ASYNC_INITIALIZED))
2766 return;
2767
2768 if (debug_level >= DEBUG_LEVEL_INFO)
2769 printk("%s(%d):%s synclinkmp_shutdown()\n",
2770 __FILE__,__LINE__, info->device_name );
2771
2772 /* clear status wait queue because status changes */
2773 /* can't happen after shutting down the hardware */
2774 wake_up_interruptible(&info->status_event_wait_q);
2775 wake_up_interruptible(&info->event_wait_q);
2776
2777 del_timer(&info->tx_timer);
2778 del_timer(&info->status_timer);
2779
735d5661
JJ		 2780 kfree(info->tx_buf);
2781 info->tx_buf = NULL;
1da177e4
LT		 2782
2783 spin_lock_irqsave(&info->lock,flags);
2784
2785 reset_port(info);
2786
2787 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2788 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2789 set_signals(info);
2790 }
2791
2792 spin_unlock_irqrestore(&info->lock,flags);
2793
2794 if (info->tty)
2795 set_bit(TTY_IO_ERROR, &info->tty->flags);
2796
2797 info->flags &= ~ASYNC_INITIALIZED;
2798}
2799
2800static void program_hw(SLMP_INFO *info)
2801{
2802 unsigned long flags;
2803
2804 spin_lock_irqsave(&info->lock,flags);
2805
2806 rx_stop(info);
2807 tx_stop(info);
2808
2809 info->tx_count = info->tx_put = info->tx_get = 0;
2810
2811 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2812 hdlc_mode(info);
2813 else
2814 async_mode(info);
2815
2816 set_signals(info);
2817
2818 info->dcd_chkcount = 0;
2819 info->cts_chkcount = 0;
2820 info->ri_chkcount = 0;
2821 info->dsr_chkcount = 0;
2822
2823 info->ie1_value |= (CDCD|CCTS);
2824 write_reg(info, IE1, info->ie1_value);
2825
2826 get_signals(info);
2827
2828 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2829 rx_start(info);
2830
2831 spin_unlock_irqrestore(&info->lock,flags);
2832}
2833
2834/* Reconfigure adapter based on new parameters
2835 */
2836static void change_params(SLMP_INFO *info)
2837{
2838 unsigned cflag;
2839 int bits_per_char;
2840
2841 if (!info->tty || !info->tty->termios)
2842 return;
2843
2844 if (debug_level >= DEBUG_LEVEL_INFO)
2845 printk("%s(%d):%s change_params()\n",
2846 __FILE__,__LINE__, info->device_name );
2847
2848 cflag = info->tty->termios->c_cflag;
2849
2850 /* if B0 rate (hangup) specified then negate DTR and RTS */
2851 /* otherwise assert DTR and RTS */
2852 if (cflag & CBAUD)
2853 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2854 else
2855 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2856
2857 /* byte size and parity */
2858
2859 switch (cflag & CSIZE) {
2860 case CS5: info->params.data_bits = 5; break;
2861 case CS6: info->params.data_bits = 6; break;
2862 case CS7: info->params.data_bits = 7; break;
2863 case CS8: info->params.data_bits = 8; break;
2864 /* Never happens, but GCC is too dumb to figure it out */
2865 default: info->params.data_bits = 7; break;
2866 }
2867
2868 if (cflag & CSTOPB)
2869 info->params.stop_bits = 2;
2870 else
2871 info->params.stop_bits = 1;
2872
2873 info->params.parity = ASYNC_PARITY_NONE;
2874 if (cflag & PARENB) {
2875 if (cflag & PARODD)
2876 info->params.parity = ASYNC_PARITY_ODD;
2877 else
2878 info->params.parity = ASYNC_PARITY_EVEN;
2879#ifdef CMSPAR
2880 if (cflag & CMSPAR)
2881 info->params.parity = ASYNC_PARITY_SPACE;
2882#endif
2883 }
2884
2885 /* calculate number of jiffies to transmit a full
2886 * FIFO (32 bytes) at specified data rate
2887 */
2888 bits_per_char = info->params.data_bits +
2889 info->params.stop_bits + 1;
2890
2891 /* if port data rate is set to 460800 or less then
2892 * allow tty settings to override, otherwise keep the
2893 * current data rate.
2894 */
2895 if (info->params.data_rate <= 460800) {
2896 info->params.data_rate = tty_get_baud_rate(info->tty);
2897 }
2898
2899 if ( info->params.data_rate ) {
2900 info->timeout = (32*HZ*bits_per_char) /
2901 info->params.data_rate;
2902 }
2903 info->timeout += HZ/50; /* Add .02 seconds of slop */
2904
2905 if (cflag & CRTSCTS)
2906 info->flags |= ASYNC_CTS_FLOW;
2907 else
2908 info->flags &= ~ASYNC_CTS_FLOW;
2909
2910 if (cflag & CLOCAL)
2911 info->flags &= ~ASYNC_CHECK_CD;
2912 else
2913 info->flags |= ASYNC_CHECK_CD;
2914
2915 /* process tty input control flags */
2916
2917 info->read_status_mask2 = OVRN;
2918 if (I_INPCK(info->tty))
2919 info->read_status_mask2 |= PE | FRME;
2920 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2921 info->read_status_mask1 |= BRKD;
2922 if (I_IGNPAR(info->tty))
2923 info->ignore_status_mask2 |= PE | FRME;
2924 if (I_IGNBRK(info->tty)) {
2925 info->ignore_status_mask1 |= BRKD;
2926 /* If ignoring parity and break indicators, ignore
2927 * overruns too. (For real raw support).
2928 */
2929 if (I_IGNPAR(info->tty))
2930 info->ignore_status_mask2 |= OVRN;
2931 }
2932
2933 program_hw(info);
2934}
2935
2936static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2937{
2938 int err;
2939
2940 if (debug_level >= DEBUG_LEVEL_INFO)
2941 printk("%s(%d):%s get_params()\n",
2942 __FILE__,__LINE__, info->device_name);
2943
166692e4
PF		 2944 if (!user_icount) {
2945 memset(&info->icount, 0, sizeof(info->icount));
2946 } else {
2947 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2948 if (err)
2949 return -EFAULT;
1da177e4
LT		 2950 }
2951
2952 return 0;
2953}
2954
2955static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2956{
2957 int err;
2958 if (debug_level >= DEBUG_LEVEL_INFO)
2959 printk("%s(%d):%s get_params()\n",
2960 __FILE__,__LINE__, info->device_name);
2961
2962 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2963 if (err) {
2964 if ( debug_level >= DEBUG_LEVEL_INFO )
2965 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2966 __FILE__,__LINE__,info->device_name);
2967 return -EFAULT;
2968 }
2969
2970 return 0;
2971}
2972
2973static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2974{
2975 unsigned long flags;
2976 MGSL_PARAMS tmp_params;
2977 int err;
2978
2979 if (debug_level >= DEBUG_LEVEL_INFO)
2980 printk("%s(%d):%s set_params\n",
2981 __FILE__,__LINE__,info->device_name );
2982 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2983 if (err) {
2984 if ( debug_level >= DEBUG_LEVEL_INFO )
2985 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2986 __FILE__,__LINE__,info->device_name);
2987 return -EFAULT;
2988 }
2989
2990 spin_lock_irqsave(&info->lock,flags);
2991 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2992 spin_unlock_irqrestore(&info->lock,flags);
2993
2994 change_params(info);
2995
2996 return 0;
2997}
2998
2999static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
3000{
3001 int err;
3002
3003 if (debug_level >= DEBUG_LEVEL_INFO)
3004 printk("%s(%d):%s get_txidle()=%d\n",
3005 __FILE__,__LINE__, info->device_name, info->idle_mode);
3006
3007 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3008 if (err) {
3009 if ( debug_level >= DEBUG_LEVEL_INFO )
3010 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3011 __FILE__,__LINE__,info->device_name);
3012 return -EFAULT;
3013 }
3014
3015 return 0;
3016}
3017
3018static int set_txidle(SLMP_INFO * info, int idle_mode)
3019{
3020 unsigned long flags;
3021
3022 if (debug_level >= DEBUG_LEVEL_INFO)
3023 printk("%s(%d):%s set_txidle(%d)\n",
3024 __FILE__,__LINE__,info->device_name, idle_mode );
3025
3026 spin_lock_irqsave(&info->lock,flags);
3027 info->idle_mode = idle_mode;
3028 tx_set_idle( info );
3029 spin_unlock_irqrestore(&info->lock,flags);
3030 return 0;
3031}
3032
3033static int tx_enable(SLMP_INFO * info, int enable)
3034{
3035 unsigned long flags;
3036
3037 if (debug_level >= DEBUG_LEVEL_INFO)
3038 printk("%s(%d):%s tx_enable(%d)\n",
3039 __FILE__,__LINE__,info->device_name, enable);
3040
3041 spin_lock_irqsave(&info->lock,flags);
3042 if ( enable ) {
3043 if ( !info->tx_enabled ) {
3044 tx_start(info);
3045 }
3046 } else {
3047 if ( info->tx_enabled )
3048 tx_stop(info);
3049 }
3050 spin_unlock_irqrestore(&info->lock,flags);
3051 return 0;
3052}
3053
3054/* abort send HDLC frame
3055 */
3056static int tx_abort(SLMP_INFO * info)
3057{
3058 unsigned long flags;
3059
3060 if (debug_level >= DEBUG_LEVEL_INFO)
3061 printk("%s(%d):%s tx_abort()\n",
3062 __FILE__,__LINE__,info->device_name);
3063
3064 spin_lock_irqsave(&info->lock,flags);
3065 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3066 info->ie1_value &= ~UDRN;
3067 info->ie1_value |= IDLE;
3068 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3069 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3070
3071 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3072 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3073
3074 write_reg(info, CMD, TXABORT);
3075 }
3076 spin_unlock_irqrestore(&info->lock,flags);
3077 return 0;
3078}
3079
3080static int rx_enable(SLMP_INFO * info, int enable)
3081{
3082 unsigned long flags;
3083
3084 if (debug_level >= DEBUG_LEVEL_INFO)
3085 printk("%s(%d):%s rx_enable(%d)\n",
3086 __FILE__,__LINE__,info->device_name,enable);
3087
3088 spin_lock_irqsave(&info->lock,flags);
3089 if ( enable ) {
3090 if ( !info->rx_enabled )
3091 rx_start(info);
3092 } else {
3093 if ( info->rx_enabled )
3094 rx_stop(info);
3095 }
3096 spin_unlock_irqrestore(&info->lock,flags);
3097 return 0;
3098}
3099
1da177e4
LT		 3100/* wait for specified event to occur
3101 */
3102static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3103{
3104 unsigned long flags;
3105 int s;
3106 int rc=0;
3107 struct mgsl_icount cprev, cnow;
3108 int events;
3109 int mask;
3110 struct _input_signal_events oldsigs, newsigs;
3111 DECLARE_WAITQUEUE(wait, current);
3112
3113 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3114 if (rc) {
3115 return -EFAULT;
3116 }
3117
3118 if (debug_level >= DEBUG_LEVEL_INFO)
3119 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3120 __FILE__,__LINE__,info->device_name,mask);
3121
3122 spin_lock_irqsave(&info->lock,flags);
3123
3124 /* return immediately if state matches requested events */
3125 get_signals(info);
7f3edb94 3126 s = info->serial_signals;
1da177e4
LT		 3127
3128 events = mask &
3129 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3130 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3131 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3132 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3133 if (events) {
3134 spin_unlock_irqrestore(&info->lock,flags);
3135 goto exit;
3136 }
3137
3138 /* save current irq counts */
3139 cprev = info->icount;
3140 oldsigs = info->input_signal_events;
3141
3142 /* enable hunt and idle irqs if needed */
3143 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3144 unsigned char oldval = info->ie1_value;
3145 unsigned char newval = oldval +
3146 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3147 (mask & MgslEvent_IdleReceived ? IDLD:0);
3148 if ( oldval != newval ) {
3149 info->ie1_value = newval;
3150 write_reg(info, IE1, info->ie1_value);
3151 }
3152 }
3153
3154 set_current_state(TASK_INTERRUPTIBLE);
3155 add_wait_queue(&info->event_wait_q, &wait);
3156
3157 spin_unlock_irqrestore(&info->lock,flags);
3158
3159 for(;;) {
3160 schedule();
3161 if (signal_pending(current)) {
3162 rc = -ERESTARTSYS;
3163 break;
3164 }
3165
3166 /* get current irq counts */
3167 spin_lock_irqsave(&info->lock,flags);
3168 cnow = info->icount;
3169 newsigs = info->input_signal_events;
3170 set_current_state(TASK_INTERRUPTIBLE);
3171 spin_unlock_irqrestore(&info->lock,flags);
3172
3173 /* if no change, wait aborted for some reason */
3174 if (newsigs.dsr_up == oldsigs.dsr_up &&
3175 newsigs.dsr_down == oldsigs.dsr_down &&
3176 newsigs.dcd_up == oldsigs.dcd_up &&
3177 newsigs.dcd_down == oldsigs.dcd_down &&
3178 newsigs.cts_up == oldsigs.cts_up &&
3179 newsigs.cts_down == oldsigs.cts_down &&
3180 newsigs.ri_up == oldsigs.ri_up &&
3181 newsigs.ri_down == oldsigs.ri_down &&
3182 cnow.exithunt == cprev.exithunt &&
3183 cnow.rxidle == cprev.rxidle) {
3184 rc = -EIO;
3185 break;
3186 }
3187
3188 events = mask &
3189 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3190 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3191 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3192 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3193 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3194 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3195 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3196 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3197 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3198 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3199 if (events)
3200 break;
3201
3202 cprev = cnow;
3203 oldsigs = newsigs;
3204 }
3205
3206 remove_wait_queue(&info->event_wait_q, &wait);
3207 set_current_state(TASK_RUNNING);
3208
3209
3210 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3211 spin_lock_irqsave(&info->lock,flags);
3212 if (!waitqueue_active(&info->event_wait_q)) {
3213 /* disable enable exit hunt mode/idle rcvd IRQs */
3214 info->ie1_value &= ~(FLGD|IDLD);
3215 write_reg(info, IE1, info->ie1_value);
3216 }
3217 spin_unlock_irqrestore(&info->lock,flags);
3218 }
3219exit:
3220 if ( rc == 0 )
3221 PUT_USER(rc, events, mask_ptr);
3222
3223 return rc;
3224}
3225
3226static int modem_input_wait(SLMP_INFO *info,int arg)
3227{
3228 unsigned long flags;
3229 int rc;
3230 struct mgsl_icount cprev, cnow;
3231 DECLARE_WAITQUEUE(wait, current);
3232
3233 /* save current irq counts */
3234 spin_lock_irqsave(&info->lock,flags);
3235 cprev = info->icount;
3236 add_wait_queue(&info->status_event_wait_q, &wait);
3237 set_current_state(TASK_INTERRUPTIBLE);
3238 spin_unlock_irqrestore(&info->lock,flags);
3239
3240 for(;;) {
3241 schedule();
3242 if (signal_pending(current)) {
3243 rc = -ERESTARTSYS;
3244 break;
3245 }
3246
3247 /* get new irq counts */
3248 spin_lock_irqsave(&info->lock,flags);
3249 cnow = info->icount;
3250 set_current_state(TASK_INTERRUPTIBLE);
3251 spin_unlock_irqrestore(&info->lock,flags);
3252
3253 /* if no change, wait aborted for some reason */
3254 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3255 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3256 rc = -EIO;
3257 break;
3258 }
3259
3260 /* check for change in caller specified modem input */
3261 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3262 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3263 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3264 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3265 rc = 0;
3266 break;
3267 }
3268
3269 cprev = cnow;
3270 }
3271 remove_wait_queue(&info->status_event_wait_q, &wait);
3272 set_current_state(TASK_RUNNING);
3273 return rc;
3274}
3275
3276/* return the state of the serial control and status signals
3277 */
3278static int tiocmget(struct tty_struct *tty, struct file *file)
3279{
3280 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3281 unsigned int result;
3282 unsigned long flags;
3283
3284 spin_lock_irqsave(&info->lock,flags);
3285 get_signals(info);
3286 spin_unlock_irqrestore(&info->lock,flags);
3287
3288 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3289 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3290 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3291 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3292 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3293 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3294
3295 if (debug_level >= DEBUG_LEVEL_INFO)
3296 printk("%s(%d):%s tiocmget() value=%08X\n",
3297 __FILE__,__LINE__, info->device_name, result );
3298 return result;
3299}
3300
3301/* set modem control signals (DTR/RTS)
3302 */
3303static int tiocmset(struct tty_struct *tty, struct file *file,
3304 unsigned int set, unsigned int clear)
3305{
3306 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3307 unsigned long flags;
3308
3309 if (debug_level >= DEBUG_LEVEL_INFO)
3310 printk("%s(%d):%s tiocmset(%x,%x)\n",
3311 __FILE__,__LINE__,info->device_name, set, clear);
3312
3313 if (set & TIOCM_RTS)
3314 info->serial_signals |= SerialSignal_RTS;
3315 if (set & TIOCM_DTR)
3316 info->serial_signals |= SerialSignal_DTR;
3317 if (clear & TIOCM_RTS)
3318 info->serial_signals &= ~SerialSignal_RTS;
3319 if (clear & TIOCM_DTR)
3320 info->serial_signals &= ~SerialSignal_DTR;
3321
3322 spin_lock_irqsave(&info->lock,flags);
3323 set_signals(info);
3324 spin_unlock_irqrestore(&info->lock,flags);
3325
3326 return 0;
3327}
3328
3329
3330
3331/* Block the current process until the specified port is ready to open.
3332 */
3333static int block_til_ready(struct tty_struct *tty, struct file *filp,
3334 SLMP_INFO *info)
3335{
3336 DECLARE_WAITQUEUE(wait, current);
3337 int retval;
3338 int do_clocal = 0, extra_count = 0;
3339 unsigned long flags;
3340
3341 if (debug_level >= DEBUG_LEVEL_INFO)
3342 printk("%s(%d):%s block_til_ready()\n",
3343 __FILE__,__LINE__, tty->driver->name );
3344
3345 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3346 /* nonblock mode is set or port is not enabled */
3347 /* just verify that callout device is not active */
3348 info->flags |= ASYNC_NORMAL_ACTIVE;
3349 return 0;
3350 }
3351
3352 if (tty->termios->c_cflag & CLOCAL)
3353 do_clocal = 1;
3354
3355 /* Wait for carrier detect and the line to become
3356 * free (i.e., not in use by the callout). While we are in
3357 * this loop, info->count is dropped by one, so that
3358 * close() knows when to free things. We restore it upon
3359 * exit, either normal or abnormal.
3360 */
3361
3362 retval = 0;
3363 add_wait_queue(&info->open_wait, &wait);
3364
3365 if (debug_level >= DEBUG_LEVEL_INFO)
3366 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3367 __FILE__,__LINE__, tty->driver->name, info->count );
3368
3369 spin_lock_irqsave(&info->lock, flags);
3370 if (!tty_hung_up_p(filp)) {
3371 extra_count = 1;
3372 info->count--;
3373 }
3374 spin_unlock_irqrestore(&info->lock, flags);
3375 info->blocked_open++;
3376
3377 while (1) {
3378 if ((tty->termios->c_cflag & CBAUD)) {
3379 spin_lock_irqsave(&info->lock,flags);
3380 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3381 set_signals(info);
3382 spin_unlock_irqrestore(&info->lock,flags);
3383 }
3384
3385 set_current_state(TASK_INTERRUPTIBLE);
3386
3387 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3388 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3389 -EAGAIN : -ERESTARTSYS;
3390 break;
3391 }
3392
3393 spin_lock_irqsave(&info->lock,flags);
3394 get_signals(info);
3395 spin_unlock_irqrestore(&info->lock,flags);
3396
3397 if (!(info->flags & ASYNC_CLOSING) &&
3398 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3399 break;
3400 }
3401
3402 if (signal_pending(current)) {
3403 retval = -ERESTARTSYS;
3404 break;
3405 }
3406
3407 if (debug_level >= DEBUG_LEVEL_INFO)
3408 printk("%s(%d):%s block_til_ready() count=%d\n",
3409 __FILE__,__LINE__, tty->driver->name, info->count );
3410
3411 schedule();
3412 }
3413
3414 set_current_state(TASK_RUNNING);
3415 remove_wait_queue(&info->open_wait, &wait);
3416
3417 if (extra_count)
3418 info->count++;
3419 info->blocked_open--;
3420
3421 if (debug_level >= DEBUG_LEVEL_INFO)
3422 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3423 __FILE__,__LINE__, tty->driver->name, info->count );
3424
3425 if (!retval)
3426 info->flags |= ASYNC_NORMAL_ACTIVE;
3427
3428 return retval;
3429}
3430
3431int alloc_dma_bufs(SLMP_INFO *info)
3432{
3433 unsigned short BuffersPerFrame;
3434 unsigned short BufferCount;
3435
3436 // Force allocation to start at 64K boundary for each port.
3437 // This is necessary because *all* buffer descriptors for a port
3438 // *must* be in the same 64K block. All descriptors on a port
3439 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3440 // into the CBP register.
3441 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3442
3443 /* Calculate the number of DMA buffers necessary to hold the */
3444 /* largest allowable frame size. Note: If the max frame size is */
3445 /* not an even multiple of the DMA buffer size then we need to */
3446 /* round the buffer count per frame up one. */
3447
3448 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3449 if ( info->max_frame_size % SCABUFSIZE )
3450 BuffersPerFrame++;
3451
3452 /* calculate total number of data buffers (SCABUFSIZE) possible
3453 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3454 * for the descriptor list (BUFFERLISTSIZE).
3455 */
3456 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3457
3458 /* limit number of buffers to maximum amount of descriptors */
3459 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3460 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3461
3462 /* use enough buffers to transmit one max size frame */
3463 info->tx_buf_count = BuffersPerFrame + 1;
3464
3465 /* never use more than half the available buffers for transmit */
3466 if (info->tx_buf_count > (BufferCount/2))
3467 info->tx_buf_count = BufferCount/2;
3468
3469 if (info->tx_buf_count > SCAMAXDESC)
3470 info->tx_buf_count = SCAMAXDESC;
3471
3472 /* use remaining buffers for receive */
3473 info->rx_buf_count = BufferCount - info->tx_buf_count;
3474
3475 if (info->rx_buf_count > SCAMAXDESC)
3476 info->rx_buf_count = SCAMAXDESC;
3477
3478 if ( debug_level >= DEBUG_LEVEL_INFO )
3479 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3480 __FILE__,__LINE__, info->device_name,
3481 info->tx_buf_count,info->rx_buf_count);
3482
3483 if ( alloc_buf_list( info ) < 0 ||
3484 alloc_frame_bufs(info,
3485 info->rx_buf_list,
3486 info->rx_buf_list_ex,
3487 info->rx_buf_count) < 0 ||
3488 alloc_frame_bufs(info,
3489 info->tx_buf_list,
3490 info->tx_buf_list_ex,
3491 info->tx_buf_count) < 0 ||
3492 alloc_tmp_rx_buf(info) < 0 ) {
3493 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3494 __FILE__,__LINE__, info->device_name);
3495 return -ENOMEM;
3496 }
3497
3498 rx_reset_buffers( info );
3499
3500 return 0;
3501}
3502
3503/* Allocate DMA buffers for the transmit and receive descriptor lists.
3504 */
3505int alloc_buf_list(SLMP_INFO *info)
3506{
3507 unsigned int i;
3508
3509 /* build list in adapter shared memory */
3510 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3511 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3512 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3513
3514 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3515
3516 /* Save virtual address pointers to the receive and */
3517 /* transmit buffer lists. (Receive 1st). These pointers will */
3518 /* be used by the processor to access the lists. */
3519 info->rx_buf_list = (SCADESC *)info->buffer_list;
3520
3521 info->tx_buf_list = (SCADESC *)info->buffer_list;
3522 info->tx_buf_list += info->rx_buf_count;
3523
3524 /* Build links for circular buffer entry lists (tx and rx)
3525 *
3526 * Note: links are physical addresses read by the SCA device
3527 * to determine the next buffer entry to use.
3528 */
3529
3530 for ( i = 0; i < info->rx_buf_count; i++ ) {
3531 /* calculate and store physical address of this buffer entry */
3532 info->rx_buf_list_ex[i].phys_entry =
3533 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3534
3535 /* calculate and store physical address of */
3536 /* next entry in cirular list of entries */
3537 info->rx_buf_list[i].next = info->buffer_list_phys;
3538 if ( i < info->rx_buf_count - 1 )
3539 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3540
3541 info->rx_buf_list[i].length = SCABUFSIZE;
3542 }
3543
3544 for ( i = 0; i < info->tx_buf_count; i++ ) {
3545 /* calculate and store physical address of this buffer entry */
3546 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3547 ((info->rx_buf_count + i) * sizeof(SCADESC));
3548
3549 /* calculate and store physical address of */
3550 /* next entry in cirular list of entries */
3551
3552 info->tx_buf_list[i].next = info->buffer_list_phys +
3553 info->rx_buf_count * sizeof(SCADESC);
3554
3555 if ( i < info->tx_buf_count - 1 )
3556 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3557 }
3558
3559 return 0;
3560}
3561
3562/* Allocate the frame DMA buffers used by the specified buffer list.
3563 */
3564int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3565{
3566 int i;
3567 unsigned long phys_addr;
3568
3569 for ( i = 0; i < count; i++ ) {
3570 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3571 phys_addr = info->port_array[0]->last_mem_alloc;
3572 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3573
3574 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3575 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3576 }
3577
3578 return 0;
3579}
3580
3581void free_dma_bufs(SLMP_INFO *info)
3582{
3583 info->buffer_list = NULL;
3584 info->rx_buf_list = NULL;
3585 info->tx_buf_list = NULL;
3586}
3587
3588/* allocate buffer large enough to hold max_frame_size.
3589 * This buffer is used to pass an assembled frame to the line discipline.
3590 */
3591int alloc_tmp_rx_buf(SLMP_INFO *info)
3592{
3593 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3594 if (info->tmp_rx_buf == NULL)
3595 return -ENOMEM;
3596 return 0;
3597}
3598
3599void free_tmp_rx_buf(SLMP_INFO *info)
3600{
735d5661 3601 kfree(info->tmp_rx_buf);
1da177e4
LT		 3602 info->tmp_rx_buf = NULL;
3603}
3604
3605int claim_resources(SLMP_INFO *info)
3606{
3607 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3608 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3609 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3610 info->init_error = DiagStatus_AddressConflict;
3611 goto errout;
3612 }
3613 else
3614 info->shared_mem_requested = 1;
3615
3616 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3617 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3618 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3619 info->init_error = DiagStatus_AddressConflict;
3620 goto errout;
3621 }
3622 else
3623 info->lcr_mem_requested = 1;
3624
3625 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3626 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3627 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3628 info->init_error = DiagStatus_AddressConflict;
3629 goto errout;
3630 }
3631 else
3632 info->sca_base_requested = 1;
3633
3634 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3635 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3636 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3637 info->init_error = DiagStatus_AddressConflict;
3638 goto errout;
3639 }
3640 else
3641 info->sca_statctrl_requested = 1;
3642
3643 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3644 if (!info->memory_base) {
3645 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3646 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3647 info->init_error = DiagStatus_CantAssignPciResources;
3648 goto errout;
3649 }
3650
3651 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3652 if (!info->lcr_base) {
3653 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3654 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3655 info->init_error = DiagStatus_CantAssignPciResources;
3656 goto errout;
3657 }
3658 info->lcr_base += info->lcr_offset;
3659
3660 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3661 if (!info->sca_base) {
3662 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3663 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3664 info->init_error = DiagStatus_CantAssignPciResources;
3665 goto errout;
3666 }
3667 info->sca_base += info->sca_offset;
3668
3669 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3670 if (!info->statctrl_base) {
3671 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3672 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3673 info->init_error = DiagStatus_CantAssignPciResources;
3674 goto errout;
3675 }
3676 info->statctrl_base += info->statctrl_offset;
3677
3678 if ( !memory_test(info) ) {
3679 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3680 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3681 info->init_error = DiagStatus_MemoryError;
3682 goto errout;
3683 }
3684
3685 return 0;
3686
3687errout:
3688 release_resources( info );
3689 return -ENODEV;
3690}
3691
3692void release_resources(SLMP_INFO *info)
3693{
3694 if ( debug_level >= DEBUG_LEVEL_INFO )
3695 printk( "%s(%d):%s release_resources() entry\n",
3696 __FILE__,__LINE__,info->device_name );
3697
3698 if ( info->irq_requested ) {
3699 free_irq(info->irq_level, info);
3700 info->irq_requested = 0;
3701 }
3702
3703 if ( info->shared_mem_requested ) {
3704 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3705 info->shared_mem_requested = 0;
3706 }
3707 if ( info->lcr_mem_requested ) {
3708 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3709 info->lcr_mem_requested = 0;
3710 }
3711 if ( info->sca_base_requested ) {
3712 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3713 info->sca_base_requested = 0;
3714 }
3715 if ( info->sca_statctrl_requested ) {
3716 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3717 info->sca_statctrl_requested = 0;
3718 }
3719
3720 if (info->memory_base){
3721 iounmap(info->memory_base);
3722 info->memory_base = NULL;
3723 }
3724
3725 if (info->sca_base) {
3726 iounmap(info->sca_base - info->sca_offset);
3727 info->sca_base=NULL;
3728 }
3729
3730 if (info->statctrl_base) {
3731 iounmap(info->statctrl_base - info->statctrl_offset);
3732 info->statctrl_base=NULL;
3733 }
3734
3735 if (info->lcr_base){
3736 iounmap(info->lcr_base - info->lcr_offset);
3737 info->lcr_base = NULL;
3738 }
3739
3740 if ( debug_level >= DEBUG_LEVEL_INFO )
3741 printk( "%s(%d):%s release_resources() exit\n",
3742 __FILE__,__LINE__,info->device_name );
3743}
3744
3745/* Add the specified device instance data structure to the
3746 * global linked list of devices and increment the device count.
3747 */
3748void add_device(SLMP_INFO *info)
3749{
3750 info->next_device = NULL;
3751 info->line = synclinkmp_device_count;
3752 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3753
3754 if (info->line < MAX_DEVICES) {
3755 if (maxframe[info->line])
3756 info->max_frame_size = maxframe[info->line];
3757 info->dosyncppp = dosyncppp[info->line];
3758 }
3759
3760 synclinkmp_device_count++;
3761
3762 if ( !synclinkmp_device_list )
3763 synclinkmp_device_list = info;
3764 else {
3765 SLMP_INFO *current_dev = synclinkmp_device_list;
3766 while( current_dev->next_device )
3767 current_dev = current_dev->next_device;
3768 current_dev->next_device = info;
3769 }
3770
3771 if ( info->max_frame_size < 4096 )
3772 info->max_frame_size = 4096;
3773 else if ( info->max_frame_size > 65535 )
3774 info->max_frame_size = 65535;
3775
3776 printk( "SyncLink MultiPort %s: "
3777 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3778 info->device_name,
3779 info->phys_sca_base,
3780 info->phys_memory_base,
3781 info->phys_statctrl_base,
3782 info->phys_lcr_base,
3783 info->irq_level,
3784 info->max_frame_size );
3785
3786#ifdef CONFIG_HDLC
3787 hdlcdev_init(info);
3788#endif
3789}
3790
3791/* Allocate and initialize a device instance structure
3792 *
3793 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3794 */
3795static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3796{
3797 SLMP_INFO *info;
3798
3799 info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3800 GFP_KERNEL);
3801
3802 if (!info) {
3803 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3804 __FILE__,__LINE__, adapter_num, port_num);
3805 } else {
3806 memset(info, 0, sizeof(SLMP_INFO));
3807 info->magic = MGSL_MAGIC;
3808 INIT_WORK(&info->task, bh_handler, info);
3809 info->max_frame_size = 4096;
3810 info->close_delay = 5*HZ/10;
3811 info->closing_wait = 30*HZ;
3812 init_waitqueue_head(&info->open_wait);
3813 init_waitqueue_head(&info->close_wait);
3814 init_waitqueue_head(&info->status_event_wait_q);
3815 init_waitqueue_head(&info->event_wait_q);
3816 spin_lock_init(&info->netlock);
3817 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3818 info->idle_mode = HDLC_TXIDLE_FLAGS;
3819 info->adapter_num = adapter_num;
3820 info->port_num = port_num;
3821
3822 /* Copy configuration info to device instance data */
3823 info->irq_level = pdev->irq;
3824 info->phys_lcr_base = pci_resource_start(pdev,0);
3825 info->phys_sca_base = pci_resource_start(pdev,2);
3826 info->phys_memory_base = pci_resource_start(pdev,3);
3827 info->phys_statctrl_base = pci_resource_start(pdev,4);
3828
3829 /* Because veremap only works on page boundaries we must map
3830 * a larger area than is actually implemented for the LCR
3831 * memory range. We map a full page starting at the page boundary.
3832 */
3833 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3834 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3835
3836 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3837 info->phys_sca_base &= ~(PAGE_SIZE-1);
3838
3839 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3840 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3841
3842 info->bus_type = MGSL_BUS_TYPE_PCI;
0f2ed4c6 3843 info->irq_flags = IRQF_SHARED;
1da177e4
LT		 3844
3845 init_timer(&info->tx_timer);
3846 info->tx_timer.data = (unsigned long)info;
3847 info->tx_timer.function = tx_timeout;
3848
3849 init_timer(&info->status_timer);
3850 info->status_timer.data = (unsigned long)info;
3851 info->status_timer.function = status_timeout;
3852
3853 /* Store the PCI9050 misc control register value because a flaw
3854 * in the PCI9050 prevents LCR registers from being read if
3855 * BIOS assigns an LCR base address with bit 7 set.
3856 *
3857 * Only the misc control register is accessed for which only
3858 * write access is needed, so set an initial value and change
3859 * bits to the device instance data as we write the value
3860 * to the actual misc control register.
3861 */
3862 info->misc_ctrl_value = 0x087e4546;
3863
3864 /* initial port state is unknown - if startup errors
3865 * occur, init_error will be set to indicate the
3866 * problem. Once the port is fully initialized,
3867 * this value will be set to 0 to indicate the
3868 * port is available.
3869 */
3870 info->init_error = -1;
3871 }
3872
3873 return info;
3874}
3875
3876void device_init(int adapter_num, struct pci_dev *pdev)
3877{
3878 SLMP_INFO *port_array[SCA_MAX_PORTS];
3879 int port;
3880
3881 /* allocate device instances for up to SCA_MAX_PORTS devices */
3882 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3883 port_array[port] = alloc_dev(adapter_num,port,pdev);
3884 if( port_array[port] == NULL ) {
3885 for ( --port; port >= 0; --port )
3886 kfree(port_array[port]);
3887 return;
3888 }
3889 }
3890
3891 /* give copy of port_array to all ports and add to device list */
3892 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3893 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3894 add_device( port_array[port] );
3895 spin_lock_init(&port_array[port]->lock);
3896 }
3897
3898 /* Allocate and claim adapter resources */
3899 if ( !claim_resources(port_array[0]) ) {
3900
3901 alloc_dma_bufs(port_array[0]);
3902
3903 /* copy resource information from first port to others */
3904 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3905 port_array[port]->lock = port_array[0]->lock;
3906 port_array[port]->irq_level = port_array[0]->irq_level;
3907 port_array[port]->memory_base = port_array[0]->memory_base;
3908 port_array[port]->sca_base = port_array[0]->sca_base;
3909 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3910 port_array[port]->lcr_base = port_array[0]->lcr_base;
3911 alloc_dma_bufs(port_array[port]);
3912 }
3913
3914 if ( request_irq(port_array[0]->irq_level,
3915 synclinkmp_interrupt,
3916 port_array[0]->irq_flags,
3917 port_array[0]->device_name,
3918 port_array[0]) < 0 ) {
3919 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3920 __FILE__,__LINE__,
3921 port_array[0]->device_name,
3922 port_array[0]->irq_level );
3923 }
3924 else {
3925 port_array[0]->irq_requested = 1;
3926 adapter_test(port_array[0]);
3927 }
3928 }
3929}
3930
b68e31d0 3931static const struct tty_operations ops = {
1da177e4
LT		 3932 .open = open,
3933 .close = close,
3934 .write = write,
3935 .put_char = put_char,
3936 .flush_chars = flush_chars,
3937 .write_room = write_room,
3938 .chars_in_buffer = chars_in_buffer,
3939 .flush_buffer = flush_buffer,
3940 .ioctl = ioctl,
3941 .throttle = throttle,
3942 .unthrottle = unthrottle,
3943 .send_xchar = send_xchar,
3944 .break_ctl = set_break,
3945 .wait_until_sent = wait_until_sent,
3946 .read_proc = read_proc,
3947 .set_termios = set_termios,
3948 .stop = tx_hold,
3949 .start = tx_release,
3950 .hangup = hangup,
3951 .tiocmget = tiocmget,
3952 .tiocmset = tiocmset,
3953};
3954
3955static void synclinkmp_cleanup(void)
3956{
3957 int rc;
3958 SLMP_INFO *info;
3959 SLMP_INFO *tmp;
3960
3961 printk("Unloading %s %s\n", driver_name, driver_version);
3962
3963 if (serial_driver) {
3964 if ((rc = tty_unregister_driver(serial_driver)))
3965 printk("%s(%d) failed to unregister tty driver err=%d\n",
3966 __FILE__,__LINE__,rc);
3967 put_tty_driver(serial_driver);
3968 }
3969
3970 /* reset devices */
3971 info = synclinkmp_device_list;
3972 while(info) {
3973 reset_port(info);
3974 info = info->next_device;
3975 }
3976
3977 /* release devices */
3978 info = synclinkmp_device_list;
3979 while(info) {
3980#ifdef CONFIG_HDLC
3981 hdlcdev_exit(info);
3982#endif
3983 free_dma_bufs(info);
3984 free_tmp_rx_buf(info);
3985 if ( info->port_num == 0 ) {
3986 if (info->sca_base)
3987 write_reg(info, LPR, 1); /* set low power mode */
3988 release_resources(info);
3989 }
3990 tmp = info;
3991 info = info->next_device;
3992 kfree(tmp);
3993 }
3994
3995 pci_unregister_driver(&synclinkmp_pci_driver);
3996}
3997
3998/* Driver initialization entry point.
3999 */
4000
4001static int __init synclinkmp_init(void)
4002{
4003 int rc;
4004
4005 if (break_on_load) {
4006 synclinkmp_get_text_ptr();
4007 BREAKPOINT();
4008 }
4009
4010 printk("%s %s\n", driver_name, driver_version);
4011
4012 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4013 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4014 return rc;
4015 }
4016
4017 serial_driver = alloc_tty_driver(128);
4018 if (!serial_driver) {
4019 rc = -ENOMEM;
4020 goto error;
4021 }
4022
4023 /* Initialize the tty_driver structure */
4024
4025 serial_driver->owner = THIS_MODULE;
4026 serial_driver->driver_name = "synclinkmp";
4027 serial_driver->name = "ttySLM";
4028 serial_driver->major = ttymajor;
4029 serial_driver->minor_start = 64;
4030 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4031 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4032 serial_driver->init_termios = tty_std_termios;
4033 serial_driver->init_termios.c_cflag =
4034 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4035 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4036 tty_set_operations(serial_driver, &ops);
4037 if ((rc = tty_register_driver(serial_driver)) < 0) {
4038 printk("%s(%d):Couldn't register serial driver\n",
4039 __FILE__,__LINE__);
4040 put_tty_driver(serial_driver);
4041 serial_driver = NULL;
4042 goto error;
4043 }
4044
4045 printk("%s %s, tty major#%d\n",
4046 driver_name, driver_version,
4047 serial_driver->major);
4048
4049 return 0;
4050
4051error:
4052 synclinkmp_cleanup();
4053 return rc;
4054}
4055
4056static void __exit synclinkmp_exit(void)
4057{
4058 synclinkmp_cleanup();
4059}
4060
4061module_init(synclinkmp_init);
4062module_exit(synclinkmp_exit);
4063
4064/* Set the port for internal loopback mode.
4065 * The TxCLK and RxCLK signals are generated from the BRG and
4066 * the TxD is looped back to the RxD internally.
4067 */
4068void enable_loopback(SLMP_INFO *info, int enable)
4069{
4070 if (enable) {
4071 /* MD2 (Mode Register 2)
4072 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4073 */
4074 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4075
4076 /* degate external TxC clock source */
4077 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4078 write_control_reg(info);
4079
4080 /* RXS/TXS (Rx/Tx clock source)
4081 * 07 Reserved, must be 0
4082 * 06..04 Clock Source, 100=BRG
4083 * 03..00 Clock Divisor, 0000=1
4084 */
4085 write_reg(info, RXS, 0x40);
4086 write_reg(info, TXS, 0x40);
4087
4088 } else {
4089 /* MD2 (Mode Register 2)
4090 * 01..00 CNCT<1..0> Channel connection, 0=normal
4091 */
4092 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4093
4094 /* RXS/TXS (Rx/Tx clock source)
4095 * 07 Reserved, must be 0
4096 * 06..04 Clock Source, 000=RxC/TxC Pin
4097 * 03..00 Clock Divisor, 0000=1
4098 */
4099 write_reg(info, RXS, 0x00);
4100 write_reg(info, TXS, 0x00);
4101 }
4102
4103 /* set LinkSpeed if available, otherwise default to 2Mbps */
4104 if (info->params.clock_speed)
4105 set_rate(info, info->params.clock_speed);
4106 else
4107 set_rate(info, 3686400);
4108}
4109
4110/* Set the baud rate register to the desired speed
4111 *
4112 * data_rate data rate of clock in bits per second
4113 * A data rate of 0 disables the AUX clock.
4114 */
4115void set_rate( SLMP_INFO *info, u32 data_rate )
4116{
4117 u32 TMCValue;
4118 unsigned char BRValue;
4119 u32 Divisor=0;
4120
4121 /* fBRG = fCLK/(TMC * 2^BR)
4122 */
4123 if (data_rate != 0) {
4124 Divisor = 14745600/data_rate;
4125 if (!Divisor)
4126 Divisor = 1;
4127
4128 TMCValue = Divisor;
4129
4130 BRValue = 0;
4131 if (TMCValue != 1 && TMCValue != 2) {
4132 /* BRValue of 0 provides 50/50 duty cycle *only* when
4133 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4134 * 50/50 duty cycle.
4135 */
4136 BRValue = 1;
4137 TMCValue >>= 1;
4138 }
4139
4140 /* while TMCValue is too big for TMC register, divide
4141 * by 2 and increment BR exponent.
4142 */
4143 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4144 TMCValue >>= 1;
4145
4146 write_reg(info, TXS,
4147 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4148 write_reg(info, RXS,
4149 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4150 write_reg(info, TMC, (unsigned char)TMCValue);
4151 }
4152 else {
4153 write_reg(info, TXS,0);
4154 write_reg(info, RXS,0);
4155 write_reg(info, TMC, 0);
4156 }
4157}
4158
4159/* Disable receiver
4160 */
4161void rx_stop(SLMP_INFO *info)
4162{
4163 if (debug_level >= DEBUG_LEVEL_ISR)
4164 printk("%s(%d):%s rx_stop()\n",
4165 __FILE__,__LINE__, info->device_name );
4166
4167 write_reg(info, CMD, RXRESET);
4168
4169 info->ie0_value &= ~RXRDYE;
4170 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4171
4172 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4173 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4174 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4175
4176 info->rx_enabled = 0;
4177 info->rx_overflow = 0;
4178}
4179
4180/* enable the receiver
4181 */
4182void rx_start(SLMP_INFO *info)
4183{
4184 int i;
4185
4186 if (debug_level >= DEBUG_LEVEL_ISR)
4187 printk("%s(%d):%s rx_start()\n",
4188 __FILE__,__LINE__, info->device_name );
4189
4190 write_reg(info, CMD, RXRESET);
4191
4192 if ( info->params.mode == MGSL_MODE_HDLC ) {
4193 /* HDLC, disabe IRQ on rxdata */
4194 info->ie0_value &= ~RXRDYE;
4195 write_reg(info, IE0, info->ie0_value);
4196
4197 /* Reset all Rx DMA buffers and program rx dma */
4198 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4199 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4200
4201 for (i = 0; i < info->rx_buf_count; i++) {
4202 info->rx_buf_list[i].status = 0xff;
4203
4204 // throttle to 4 shared memory writes at a time to prevent
4205 // hogging local bus (keep latency time for DMA requests low).
4206 if (!(i % 4))
4207 read_status_reg(info);
4208 }
4209 info->current_rx_buf = 0;
4210
4211 /* set current/1st descriptor address */
4212 write_reg16(info, RXDMA + CDA,
4213 info->rx_buf_list_ex[0].phys_entry);
4214
4215 /* set new last rx descriptor address */
4216 write_reg16(info, RXDMA + EDA,
4217 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4218
4219 /* set buffer length (shared by all rx dma data buffers) */
4220 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4221
4222 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4223 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4224 } else {
4225 /* async, enable IRQ on rxdata */
4226 info->ie0_value |= RXRDYE;
4227 write_reg(info, IE0, info->ie0_value);
4228 }
4229
4230 write_reg(info, CMD, RXENABLE);
4231
4232 info->rx_overflow = FALSE;
4233 info->rx_enabled = 1;
4234}
4235
4236/* Enable the transmitter and send a transmit frame if
4237 * one is loaded in the DMA buffers.
4238 */
4239void tx_start(SLMP_INFO *info)
4240{
4241 if (debug_level >= DEBUG_LEVEL_ISR)
4242 printk("%s(%d):%s tx_start() tx_count=%d\n",
4243 __FILE__,__LINE__, info->device_name,info->tx_count );
4244
4245 if (!info->tx_enabled ) {
4246 write_reg(info, CMD, TXRESET);
4247 write_reg(info, CMD, TXENABLE);
4248 info->tx_enabled = TRUE;
4249 }
4250
4251 if ( info->tx_count ) {
4252
4253 /* If auto RTS enabled and RTS is inactive, then assert */
4254 /* RTS and set a flag indicating that the driver should */
4255 /* negate RTS when the transmission completes. */
4256
4257 info->drop_rts_on_tx_done = 0;
4258
4259 if (info->params.mode != MGSL_MODE_ASYNC) {
4260
4261 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4262 get_signals( info );
4263 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4264 info->serial_signals |= SerialSignal_RTS;
4265 set_signals( info );
4266 info->drop_rts_on_tx_done = 1;
4267 }
4268 }
4269
4270 write_reg16(info, TRC0,
4271 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4272
4273 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4274 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4275
4276 /* set TX CDA (current descriptor address) */
4277 write_reg16(info, TXDMA + CDA,
4278 info->tx_buf_list_ex[0].phys_entry);
4279
4280 /* set TX EDA (last descriptor address) */
4281 write_reg16(info, TXDMA + EDA,
4282 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4283
4284 /* enable underrun IRQ */
4285 info->ie1_value &= ~IDLE;
4286 info->ie1_value |= UDRN;
4287 write_reg(info, IE1, info->ie1_value);
4288 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4289
4290 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4291 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4292
4293 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4294 add_timer(&info->tx_timer);
4295 }
4296 else {
4297 tx_load_fifo(info);
4298 /* async, enable IRQ on txdata */
4299 info->ie0_value |= TXRDYE;
4300 write_reg(info, IE0, info->ie0_value);
4301 }
4302
4303 info->tx_active = 1;
4304 }
4305}
4306
4307/* stop the transmitter and DMA
4308 */
4309void tx_stop( SLMP_INFO *info )
4310{
4311 if (debug_level >= DEBUG_LEVEL_ISR)
4312 printk("%s(%d):%s tx_stop()\n",
4313 __FILE__,__LINE__, info->device_name );
4314
4315 del_timer(&info->tx_timer);
4316
4317 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4318 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4319
4320 write_reg(info, CMD, TXRESET);
4321
4322 info->ie1_value &= ~(UDRN + IDLE);
4323 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4324 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4325
4326 info->ie0_value &= ~TXRDYE;
4327 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4328
4329 info->tx_enabled = 0;
4330 info->tx_active = 0;
4331}
4332
4333/* Fill the transmit FIFO until the FIFO is full or
4334 * there is no more data to load.
4335 */
4336void tx_load_fifo(SLMP_INFO *info)
4337{
4338 u8 TwoBytes[2];
4339
4340 /* do nothing is now tx data available and no XON/XOFF pending */
4341
4342 if ( !info->tx_count && !info->x_char )
4343 return;
4344
4345 /* load the Transmit FIFO until FIFOs full or all data sent */
4346
4347 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4348
4349 /* there is more space in the transmit FIFO and */
4350 /* there is more data in transmit buffer */
4351
4352 if ( (info->tx_count > 1) && !info->x_char ) {
4353 /* write 16-bits */
4354 TwoBytes[0] = info->tx_buf[info->tx_get++];
4355 if (info->tx_get >= info->max_frame_size)
4356 info->tx_get -= info->max_frame_size;
4357 TwoBytes[1] = info->tx_buf[info->tx_get++];
4358 if (info->tx_get >= info->max_frame_size)
4359 info->tx_get -= info->max_frame_size;
4360
4361 write_reg16(info, TRB, *((u16 *)TwoBytes));
4362
4363 info->tx_count -= 2;
4364 info->icount.tx += 2;
4365 } else {
4366 /* only 1 byte left to transmit or 1 FIFO slot left */
4367
4368 if (info->x_char) {
4369 /* transmit pending high priority char */
4370 write_reg(info, TRB, info->x_char);
4371 info->x_char = 0;
4372 } else {
4373 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4374 if (info->tx_get >= info->max_frame_size)
4375 info->tx_get -= info->max_frame_size;
4376 info->tx_count--;
4377 }
4378 info->icount.tx++;
4379 }
4380 }
4381}
4382
4383/* Reset a port to a known state
4384 */
4385void reset_port(SLMP_INFO *info)
4386{
4387 if (info->sca_base) {
4388
4389 tx_stop(info);
4390 rx_stop(info);
4391
4392 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4393 set_signals(info);
4394
4395 /* disable all port interrupts */
4396 info->ie0_value = 0;
4397 info->ie1_value = 0;
4398 info->ie2_value = 0;
4399 write_reg(info, IE0, info->ie0_value);
4400 write_reg(info, IE1, info->ie1_value);
4401 write_reg(info, IE2, info->ie2_value);
4402
4403 write_reg(info, CMD, CHRESET);
4404 }
4405}
4406
4407/* Reset all the ports to a known state.
4408 */
4409void reset_adapter(SLMP_INFO *info)
4410{
4411 int i;
4412
4413 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4414 if (info->port_array[i])
4415 reset_port(info->port_array[i]);
4416 }
4417}
4418
4419/* Program port for asynchronous communications.
4420 */
4421void async_mode(SLMP_INFO *info)
4422{
4423
4424 unsigned char RegValue;
4425
4426 tx_stop(info);
4427 rx_stop(info);
4428
4429 /* MD0, Mode Register 0
4430 *
4431 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4432 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4433 * 03 Reserved, must be 0
4434 * 02 CRCCC, CRC Calculation, 0=disabled
4435 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4436 *
4437 * 0000 0000
4438 */
4439 RegValue = 0x00;
4440 if (info->params.stop_bits != 1)
4441 RegValue |= BIT1;
4442 write_reg(info, MD0, RegValue);
4443
4444 /* MD1, Mode Register 1
4445 *
4446 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4447 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4448 * 03..02 RXCHR<1..0>, rx char size
4449 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4450 *
4451 * 0100 0000
4452 */
4453 RegValue = 0x40;
4454 switch (info->params.data_bits) {
4455 case 7: RegValue |= BIT4 + BIT2; break;
4456 case 6: RegValue |= BIT5 + BIT3; break;
4457 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4458 }
4459 if (info->params.parity != ASYNC_PARITY_NONE) {
4460 RegValue |= BIT1;
4461 if (info->params.parity == ASYNC_PARITY_ODD)
4462 RegValue |= BIT0;
4463 }
4464 write_reg(info, MD1, RegValue);
4465
4466 /* MD2, Mode Register 2
4467 *
4468 * 07..02 Reserved, must be 0
6e8dcee3 4469 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
1da177e4
LT		 4470 *
4471 * 0000 0000
4472 */
4473 RegValue = 0x00;
6e8dcee3
PF		 4474 if (info->params.loopback)
4475 RegValue |= (BIT1 + BIT0);
1da177e4
LT		 4476 write_reg(info, MD2, RegValue);
4477
4478 /* RXS, Receive clock source
4479 *
4480 * 07 Reserved, must be 0
4481 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4482 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4483 */
4484 RegValue=BIT6;
4485 write_reg(info, RXS, RegValue);
4486
4487 /* TXS, Transmit clock source
4488 *
4489 * 07 Reserved, must be 0
4490 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4491 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4492 */
4493 RegValue=BIT6;
4494 write_reg(info, TXS, RegValue);
4495
4496 /* Control Register
4497 *
4498 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4499 */
4500 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4501 write_control_reg(info);
4502
4503 tx_set_idle(info);
4504
4505 /* RRC Receive Ready Control 0
4506 *
4507 * 07..05 Reserved, must be 0
4508 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4509 */
4510 write_reg(info, RRC, 0x00);
4511
4512 /* TRC0 Transmit Ready Control 0
4513 *
4514 * 07..05 Reserved, must be 0
4515 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4516 */
4517 write_reg(info, TRC0, 0x10);
4518
4519 /* TRC1 Transmit Ready Control 1
4520 *
4521 * 07..05 Reserved, must be 0
4522 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4523 */
4524 write_reg(info, TRC1, 0x1e);
4525
4526 /* CTL, MSCI control register
4527 *
4528 * 07..06 Reserved, set to 0
4529 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4530 * 04 IDLC, idle control, 0=mark 1=idle register
4531 * 03 BRK, break, 0=off 1 =on (async)
4532 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4533 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4534 * 00 RTS, RTS output control, 0=active 1=inactive
4535 *
4536 * 0001 0001
4537 */
4538 RegValue = 0x10;
4539 if (!(info->serial_signals & SerialSignal_RTS))
4540 RegValue |= 0x01;
4541 write_reg(info, CTL, RegValue);
4542
4543 /* enable status interrupts */
4544 info->ie0_value |= TXINTE + RXINTE;
4545 write_reg(info, IE0, info->ie0_value);
4546
4547 /* enable break detect interrupt */
4548 info->ie1_value = BRKD;
4549 write_reg(info, IE1, info->ie1_value);
4550
4551 /* enable rx overrun interrupt */
4552 info->ie2_value = OVRN;
4553 write_reg(info, IE2, info->ie2_value);
4554
4555 set_rate( info, info->params.data_rate * 16 );
1da177e4
LT		 4556}
4557
4558/* Program the SCA for HDLC communications.
4559 */
4560void hdlc_mode(SLMP_INFO *info)
4561{
4562 unsigned char RegValue;
4563 u32 DpllDivisor;
4564
4565 // Can't use DPLL because SCA outputs recovered clock on RxC when
4566 // DPLL mode selected. This causes output contention with RxC receiver.
4567 // Use of DPLL would require external hardware to disable RxC receiver
4568 // when DPLL mode selected.
4569 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4570
4571 /* disable DMA interrupts */
4572 write_reg(info, TXDMA + DIR, 0);
4573 write_reg(info, RXDMA + DIR, 0);
4574
4575 /* MD0, Mode Register 0
4576 *
4577 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4578 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4579 * 03 Reserved, must be 0
4580 * 02 CRCCC, CRC Calculation, 1=enabled
4581 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4582 * 00 CRC0, CRC initial value, 1 = all 1s
4583 *
4584 * 1000 0001
4585 */
4586 RegValue = 0x81;
4587 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4588 RegValue |= BIT4;
4589 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4590 RegValue |= BIT4;
4591 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4592 RegValue |= BIT2 + BIT1;
4593 write_reg(info, MD0, RegValue);
4594
4595 /* MD1, Mode Register 1
4596 *
4597 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4598 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4599 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4600 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4601 *
4602 * 0000 0000
4603 */
4604 RegValue = 0x00;
4605 write_reg(info, MD1, RegValue);
4606
4607 /* MD2, Mode Register 2
4608 *
4609 * 07 NRZFM, 0=NRZ, 1=FM
4610 * 06..05 CODE<1..0> Encoding, 00=NRZ
4611 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4612 * 02 Reserved, must be 0
4613 * 01..00 CNCT<1..0> Channel connection, 0=normal
4614 *
4615 * 0000 0000
4616 */
4617 RegValue = 0x00;
4618 switch(info->params.encoding) {
4619 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4620 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4621 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4622 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4623#if 0
4624 case HDLC_ENCODING_NRZB: /* not supported */
4625 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4626 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4627#endif
4628 }
4629 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4630 DpllDivisor = 16;
4631 RegValue |= BIT3;
4632 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4633 DpllDivisor = 8;
4634 } else {
4635 DpllDivisor = 32;
4636 RegValue |= BIT4;
4637 }
4638 write_reg(info, MD2, RegValue);
4639
4640
4641 /* RXS, Receive clock source
4642 *
4643 * 07 Reserved, must be 0
4644 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4645 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4646 */
4647 RegValue=0;
4648 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4649 RegValue |= BIT6;
4650 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4651 RegValue |= BIT6 + BIT5;
4652 write_reg(info, RXS, RegValue);
4653
4654 /* TXS, Transmit clock source
4655 *
4656 * 07 Reserved, must be 0
4657 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4658 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4659 */
4660 RegValue=0;
4661 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4662 RegValue |= BIT6;
4663 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4664 RegValue |= BIT6 + BIT5;
4665 write_reg(info, TXS, RegValue);
4666
4667 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4668 set_rate(info, info->params.clock_speed * DpllDivisor);
4669 else
4670 set_rate(info, info->params.clock_speed);
4671
4672 /* GPDATA (General Purpose I/O Data Register)
4673 *
4674 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4675 */
4676 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4677 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4678 else
4679 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4680 write_control_reg(info);
4681
4682 /* RRC Receive Ready Control 0
4683 *
4684 * 07..05 Reserved, must be 0
4685 * 04..00 RRC<4..0> Rx FIFO trigger active
4686 */
4687 write_reg(info, RRC, rx_active_fifo_level);
4688
4689 /* TRC0 Transmit Ready Control 0
4690 *
4691 * 07..05 Reserved, must be 0
4692 * 04..00 TRC<4..0> Tx FIFO trigger active
4693 */
4694 write_reg(info, TRC0, tx_active_fifo_level);
4695
4696 /* TRC1 Transmit Ready Control 1
4697 *
4698 * 07..05 Reserved, must be 0
4699 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4700 */
4701 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4702
4703 /* DMR, DMA Mode Register
4704 *
4705 * 07..05 Reserved, must be 0
4706 * 04 TMOD, Transfer Mode: 1=chained-block
4707 * 03 Reserved, must be 0
4708 * 02 NF, Number of Frames: 1=multi-frame
4709 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4710 * 00 Reserved, must be 0
4711 *
4712 * 0001 0100
4713 */
4714 write_reg(info, TXDMA + DMR, 0x14);
4715 write_reg(info, RXDMA + DMR, 0x14);
4716
4717 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4718 write_reg(info, RXDMA + CPB,
4719 (unsigned char)(info->buffer_list_phys >> 16));
4720
4721 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4722 write_reg(info, TXDMA + CPB,
4723 (unsigned char)(info->buffer_list_phys >> 16));
4724
4725 /* enable status interrupts. other code enables/disables
4726 * the individual sources for these two interrupt classes.
4727 */
4728 info->ie0_value |= TXINTE + RXINTE;
4729 write_reg(info, IE0, info->ie0_value);
4730
4731 /* CTL, MSCI control register
4732 *
4733 * 07..06 Reserved, set to 0
4734 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4735 * 04 IDLC, idle control, 0=mark 1=idle register
4736 * 03 BRK, break, 0=off 1 =on (async)
4737 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4738 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4739 * 00 RTS, RTS output control, 0=active 1=inactive
4740 *
4741 * 0001 0001
4742 */
4743 RegValue = 0x10;
4744 if (!(info->serial_signals & SerialSignal_RTS))
4745 RegValue |= 0x01;
4746 write_reg(info, CTL, RegValue);
4747
4748 /* preamble not supported ! */
4749
4750 tx_set_idle(info);
4751 tx_stop(info);
4752 rx_stop(info);
4753
4754 set_rate(info, info->params.clock_speed);
4755
4756 if (info->params.loopback)
4757 enable_loopback(info,1);
4758}
4759
4760/* Set the transmit HDLC idle mode
4761 */
4762void tx_set_idle(SLMP_INFO *info)
4763{
4764 unsigned char RegValue = 0xff;
4765
4766 /* Map API idle mode to SCA register bits */
4767 switch(info->idle_mode) {
4768 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4769 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4770 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4771 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4772 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4773 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4774 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4775 }
4776
4777 write_reg(info, IDL, RegValue);
4778}
4779
4780/* Query the adapter for the state of the V24 status (input) signals.
4781 */
4782void get_signals(SLMP_INFO *info)
4783{
4784 u16 status = read_reg(info, SR3);
4785 u16 gpstatus = read_status_reg(info);
4786 u16 testbit;
4787
4788 /* clear all serial signals except DTR and RTS */
4789 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4790
4791 /* set serial signal bits to reflect MISR */
4792
4793 if (!(status & BIT3))
4794 info->serial_signals |= SerialSignal_CTS;
4795
4796 if ( !(status & BIT2))
4797 info->serial_signals |= SerialSignal_DCD;
4798
4799 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4800 if (!(gpstatus & testbit))
4801 info->serial_signals |= SerialSignal_RI;
4802
4803 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4804 if (!(gpstatus & testbit))
4805 info->serial_signals |= SerialSignal_DSR;
4806}
4807
4808/* Set the state of DTR and RTS based on contents of
4809 * serial_signals member of device context.
4810 */
4811void set_signals(SLMP_INFO *info)
4812{
4813 unsigned char RegValue;
4814 u16 EnableBit;
4815
4816 RegValue = read_reg(info, CTL);
4817 if (info->serial_signals & SerialSignal_RTS)
4818 RegValue &= ~BIT0;
4819 else
4820 RegValue |= BIT0;
4821 write_reg(info, CTL, RegValue);
4822
4823 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4824 EnableBit = BIT1 << (info->port_num*2);
4825 if (info->serial_signals & SerialSignal_DTR)
4826 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4827 else
4828 info->port_array[0]->ctrlreg_value |= EnableBit;
4829 write_control_reg(info);
4830}
4831
4832/*******************/
4833/* DMA Buffer Code */
4834/*******************/
4835
4836/* Set the count for all receive buffers to SCABUFSIZE
4837 * and set the current buffer to the first buffer. This effectively
4838 * makes all buffers free and discards any data in buffers.
4839 */
4840void rx_reset_buffers(SLMP_INFO *info)
4841{
4842 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4843}
4844
4845/* Free the buffers used by a received frame
4846 *
4847 * info pointer to device instance data
4848 * first index of 1st receive buffer of frame
4849 * last index of last receive buffer of frame
4850 */
4851void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4852{
4853 int done = 0;
4854
4855 while(!done) {
4856 /* reset current buffer for reuse */
4857 info->rx_buf_list[first].status = 0xff;
4858
4859 if (first == last) {
4860 done = 1;
4861 /* set new last rx descriptor address */
4862 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4863 }
4864
4865 first++;
4866 if (first == info->rx_buf_count)
4867 first = 0;
4868 }
4869
4870 /* set current buffer to next buffer after last buffer of frame */
4871 info->current_rx_buf = first;
4872}
4873
4874/* Return a received frame from the receive DMA buffers.
4875 * Only frames received without errors are returned.
4876 *
4877 * Return Value: 1 if frame returned, otherwise 0
4878 */
4879int rx_get_frame(SLMP_INFO *info)
4880{
4881 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4882 unsigned short status;
4883 unsigned int framesize = 0;
4884 int ReturnCode = 0;
4885 unsigned long flags;
4886 struct tty_struct *tty = info->tty;
4887 unsigned char addr_field = 0xff;
4888 SCADESC *desc;
4889 SCADESC_EX *desc_ex;
4890
4891CheckAgain:
4892 /* assume no frame returned, set zero length */
4893 framesize = 0;
4894 addr_field = 0xff;
4895
4896 /*
4897 * current_rx_buf points to the 1st buffer of the next available
4898 * receive frame. To find the last buffer of the frame look for
4899 * a non-zero status field in the buffer entries. (The status
4900 * field is set by the 16C32 after completing a receive frame.
4901 */
4902 StartIndex = EndIndex = info->current_rx_buf;
4903
4904 for ( ;; ) {
4905 desc = &info->rx_buf_list[EndIndex];
4906 desc_ex = &info->rx_buf_list_ex[EndIndex];
4907
4908 if (desc->status == 0xff)
4909 goto Cleanup; /* current desc still in use, no frames available */
4910
4911 if (framesize == 0 && info->params.addr_filter != 0xff)
4912 addr_field = desc_ex->virt_addr[0];
4913
4914 framesize += desc->length;
4915
4916 /* Status != 0 means last buffer of frame */
4917 if (desc->status)
4918 break;
4919
4920 EndIndex++;
4921 if (EndIndex == info->rx_buf_count)
4922 EndIndex = 0;
4923
4924 if (EndIndex == info->current_rx_buf) {
4925 /* all buffers have been 'used' but none mark */
4926 /* the end of a frame. Reset buffers and receiver. */
4927 if ( info->rx_enabled ){
4928 spin_lock_irqsave(&info->lock,flags);
4929 rx_start(info);
4930 spin_unlock_irqrestore(&info->lock,flags);
4931 }
4932 goto Cleanup;
4933 }
4934
4935 }
4936
4937 /* check status of receive frame */
4938
4939 /* frame status is byte stored after frame data
4940 *
4941 * 7 EOM (end of msg), 1 = last buffer of frame
4942 * 6 Short Frame, 1 = short frame
4943 * 5 Abort, 1 = frame aborted
4944 * 4 Residue, 1 = last byte is partial
4945 * 3 Overrun, 1 = overrun occurred during frame reception
4946 * 2 CRC, 1 = CRC error detected
4947 *
4948 */
4949 status = desc->status;
4950
4951 /* ignore CRC bit if not using CRC (bit is undefined) */
4952 /* Note:CRC is not save to data buffer */
4953 if (info->params.crc_type == HDLC_CRC_NONE)
4954 status &= ~BIT2;
4955
4956 if (framesize == 0 ||
4957 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4958 /* discard 0 byte frames, this seems to occur sometime
4959 * when remote is idling flags.
4960 */
4961 rx_free_frame_buffers(info, StartIndex, EndIndex);
4962 goto CheckAgain;
4963 }
4964
4965 if (framesize < 2)
4966 status |= BIT6;
4967
4968 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4969 /* received frame has errors,
4970 * update counts and mark frame size as 0
4971 */
4972 if (status & BIT6)
4973 info->icount.rxshort++;
4974 else if (status & BIT5)
4975 info->icount.rxabort++;
4976 else if (status & BIT3)
4977 info->icount.rxover++;
4978 else
4979 info->icount.rxcrc++;
4980
4981 framesize = 0;
4982#ifdef CONFIG_HDLC
4983 {
4984 struct net_device_stats *stats = hdlc_stats(info->netdev);
4985 stats->rx_errors++;
4986 stats->rx_frame_errors++;
4987 }
4988#endif
4989 }
4990
4991 if ( debug_level >= DEBUG_LEVEL_BH )
4992 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4993 __FILE__,__LINE__,info->device_name,status,framesize);
4994
4995 if ( debug_level >= DEBUG_LEVEL_DATA )
4996 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4997 min_t(int, framesize,SCABUFSIZE),0);
4998
4999 if (framesize) {
5000 if (framesize > info->max_frame_size)
5001 info->icount.rxlong++;
5002 else {
5003 /* copy dma buffer(s) to contiguous intermediate buffer */
5004 int copy_count = framesize;
5005 int index = StartIndex;
5006 unsigned char *ptmp = info->tmp_rx_buf;
5007 info->tmp_rx_buf_count = framesize;
5008
5009 info->icount.rxok++;
5010
5011 while(copy_count) {
5012 int partial_count = min(copy_count,SCABUFSIZE);
5013 memcpy( ptmp,
5014 info->rx_buf_list_ex[index].virt_addr,
5015 partial_count );
5016 ptmp += partial_count;
5017 copy_count -= partial_count;
5018
5019 if ( ++index == info->rx_buf_count )
5020 index = 0;
5021 }
5022
5023#ifdef CONFIG_HDLC
5024 if (info->netcount)
5025 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5026 else
5027#endif
5028 ldisc_receive_buf(tty,info->tmp_rx_buf,
5029 info->flag_buf, framesize);
5030 }
5031 }
5032 /* Free the buffers used by this frame. */
5033 rx_free_frame_buffers( info, StartIndex, EndIndex );
5034
5035 ReturnCode = 1;
5036
5037Cleanup:
5038 if ( info->rx_enabled && info->rx_overflow ) {
5039 /* Receiver is enabled, but needs to restarted due to
5040 * rx buffer overflow. If buffers are empty, restart receiver.
5041 */
5042 if (info->rx_buf_list[EndIndex].status == 0xff) {
5043 spin_lock_irqsave(&info->lock,flags);
5044 rx_start(info);
5045 spin_unlock_irqrestore(&info->lock,flags);
5046 }
5047 }
5048
5049 return ReturnCode;
5050}
5051
5052/* load the transmit DMA buffer with data
5053 */
5054void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5055{
5056 unsigned short copy_count;
5057 unsigned int i = 0;
5058 SCADESC *desc;
5059 SCADESC_EX *desc_ex;
5060
5061 if ( debug_level >= DEBUG_LEVEL_DATA )
5062 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5063
5064 /* Copy source buffer to one or more DMA buffers, starting with
5065 * the first transmit dma buffer.
5066 */
5067 for(i=0;;)
5068 {
5069 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5070
5071 desc = &info->tx_buf_list[i];
5072 desc_ex = &info->tx_buf_list_ex[i];
5073
5074 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5075
5076 desc->length = copy_count;
5077 desc->status = 0;
5078
5079 buf += copy_count;
5080 count -= copy_count;
5081
5082 if (!count)
5083 break;
5084
5085 i++;
5086 if (i >= info->tx_buf_count)
5087 i = 0;
5088 }
5089
5090 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5091 info->last_tx_buf = ++i;
5092}
5093
5094int register_test(SLMP_INFO *info)
5095{
5096 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
fe971071 5097 static unsigned int count = ARRAY_SIZE(testval);
1da177e4
LT		 5098 unsigned int i;
5099 int rc = TRUE;
5100 unsigned long flags;
5101
5102 spin_lock_irqsave(&info->lock,flags);
5103 reset_port(info);
5104
5105 /* assume failure */
5106 info->init_error = DiagStatus_AddressFailure;
5107
5108 /* Write bit patterns to various registers but do it out of */
5109 /* sync, then read back and verify values. */
5110
5111 for (i = 0 ; i < count ; i++) {
5112 write_reg(info, TMC, testval[i]);
5113 write_reg(info, IDL, testval[(i+1)%count]);
5114 write_reg(info, SA0, testval[(i+2)%count]);
5115 write_reg(info, SA1, testval[(i+3)%count]);
5116
5117 if ( (read_reg(info, TMC) != testval[i]) ||
5118 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5119 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5120 (read_reg(info, SA1) != testval[(i+3)%count]) )
5121 {
5122 rc = FALSE;
5123 break;
5124 }
5125 }
5126
5127 reset_port(info);
5128 spin_unlock_irqrestore(&info->lock,flags);
5129
5130 return rc;
5131}
5132
5133int irq_test(SLMP_INFO *info)
5134{
5135 unsigned long timeout;
5136 unsigned long flags;
5137
5138 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5139
5140 spin_lock_irqsave(&info->lock,flags);
5141 reset_port(info);
5142
5143 /* assume failure */
5144 info->init_error = DiagStatus_IrqFailure;
5145 info->irq_occurred = FALSE;
5146
5147 /* setup timer0 on SCA0 to interrupt */
5148
5149 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5150 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5151
5152 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5153 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5154
5155
5156 /* TMCS, Timer Control/Status Register
5157 *
5158 * 07 CMF, Compare match flag (read only) 1=match
5159 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5160 * 05 Reserved, must be 0
5161 * 04 TME, Timer Enable
5162 * 03..00 Reserved, must be 0
5163 *
5164 * 0101 0000
5165 */
5166 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5167
5168 spin_unlock_irqrestore(&info->lock,flags);
5169
5170 timeout=100;
5171 while( timeout-- && !info->irq_occurred ) {
5172 msleep_interruptible(10);
5173 }
5174
5175 spin_lock_irqsave(&info->lock,flags);
5176 reset_port(info);
5177 spin_unlock_irqrestore(&info->lock,flags);
5178
5179 return info->irq_occurred;
5180}
5181
5182/* initialize individual SCA device (2 ports)
5183 */
5184static int sca_init(SLMP_INFO *info)
5185{
5186 /* set wait controller to single mem partition (low), no wait states */
5187 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5188 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5189 write_reg(info, WCRL, 0); /* wait controller low range */
5190 write_reg(info, WCRM, 0); /* wait controller mid range */
5191 write_reg(info, WCRH, 0); /* wait controller high range */
5192
5193 /* DPCR, DMA Priority Control
5194 *
5195 * 07..05 Not used, must be 0
5196 * 04 BRC, bus release condition: 0=all transfers complete
5197 * 03 CCC, channel change condition: 0=every cycle
5198 * 02..00 PR<2..0>, priority 100=round robin
5199 *
5200 * 00000100 = 0x04
5201 */
5202 write_reg(info, DPCR, dma_priority);
5203
5204 /* DMA Master Enable, BIT7: 1=enable all channels */
5205 write_reg(info, DMER, 0x80);
5206
5207 /* enable all interrupt classes */
5208 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5209 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5210 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5211
5212 /* ITCR, interrupt control register
5213 * 07 IPC, interrupt priority, 0=MSCI->DMA
5214 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5215 * 04 VOS, Vector Output, 0=unmodified vector
5216 * 03..00 Reserved, must be 0
5217 */
5218 write_reg(info, ITCR, 0);
5219
5220 return TRUE;
5221}
5222
5223/* initialize adapter hardware
5224 */
5225int init_adapter(SLMP_INFO *info)
5226{
5227 int i;
5228
5229 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5230 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5231 u32 readval;
5232
5233 info->misc_ctrl_value |= BIT30;
5234 *MiscCtrl = info->misc_ctrl_value;
5235
5236 /*
5237 * Force at least 170ns delay before clearing
5238 * reset bit. Each read from LCR takes at least
5239 * 30ns so 10 times for 300ns to be safe.
5240 */
5241 for(i=0;i<10;i++)
5242 readval = *MiscCtrl;
5243
5244 info->misc_ctrl_value &= ~BIT30;
5245 *MiscCtrl = info->misc_ctrl_value;
5246
5247 /* init control reg (all DTRs off, all clksel=input) */
5248 info->ctrlreg_value = 0xaa;
5249 write_control_reg(info);
5250
5251 {
5252 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5253 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5254
5255 switch(read_ahead_count)
5256 {
5257 case 16:
5258 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5259 break;
5260 case 8:
5261 lcr1_brdr_value |= BIT5 + BIT4;
5262 break;
5263 case 4:
5264 lcr1_brdr_value |= BIT5 + BIT3;
5265 break;
5266 case 0:
5267 lcr1_brdr_value |= BIT5;
5268 break;
5269 }
5270
5271 *LCR1BRDR = lcr1_brdr_value;
5272 *MiscCtrl = misc_ctrl_value;
5273 }
5274
5275 sca_init(info->port_array[0]);
5276 sca_init(info->port_array[2]);
5277
5278 return TRUE;
5279}
5280
5281/* Loopback an HDLC frame to test the hardware
5282 * interrupt and DMA functions.
5283 */
5284int loopback_test(SLMP_INFO *info)
5285{
5286#define TESTFRAMESIZE 20
5287
5288 unsigned long timeout;
5289 u16 count = TESTFRAMESIZE;
5290 unsigned char buf[TESTFRAMESIZE];
5291 int rc = FALSE;
5292 unsigned long flags;
5293
5294 struct tty_struct *oldtty = info->tty;
5295 u32 speed = info->params.clock_speed;
5296
5297 info->params.clock_speed = 3686400;
5298 info->tty = NULL;
5299
5300 /* assume failure */
5301 info->init_error = DiagStatus_DmaFailure;
5302
5303 /* build and send transmit frame */
5304 for (count = 0; count < TESTFRAMESIZE;++count)
5305 buf[count] = (unsigned char)count;
5306
5307 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5308
5309 /* program hardware for HDLC and enabled receiver */
5310 spin_lock_irqsave(&info->lock,flags);
5311 hdlc_mode(info);
5312 enable_loopback(info,1);
5313 rx_start(info);
5314 info->tx_count = count;
5315 tx_load_dma_buffer(info,buf,count);
5316 tx_start(info);
5317 spin_unlock_irqrestore(&info->lock,flags);
5318
5319 /* wait for receive complete */
5320 /* Set a timeout for waiting for interrupt. */
5321 for ( timeout = 100; timeout; --timeout ) {
5322 msleep_interruptible(10);
5323
5324 if (rx_get_frame(info)) {
5325 rc = TRUE;
5326 break;
5327 }
5328 }
5329
5330 /* verify received frame length and contents */
5331 if (rc == TRUE &&
5332 ( info->tmp_rx_buf_count != count ||
5333 memcmp(buf, info->tmp_rx_buf,count))) {
5334 rc = FALSE;
5335 }
5336
5337 spin_lock_irqsave(&info->lock,flags);
5338 reset_adapter(info);
5339 spin_unlock_irqrestore(&info->lock,flags);
5340
5341 info->params.clock_speed = speed;
5342 info->tty = oldtty;
5343
5344 return rc;
5345}
5346
5347/* Perform diagnostics on hardware
5348 */
5349int adapter_test( SLMP_INFO *info )
5350{
5351 unsigned long flags;
5352 if ( debug_level >= DEBUG_LEVEL_INFO )
5353 printk( "%s(%d):Testing device %s\n",
5354 __FILE__,__LINE__,info->device_name );
5355
5356 spin_lock_irqsave(&info->lock,flags);
5357 init_adapter(info);
5358 spin_unlock_irqrestore(&info->lock,flags);
5359
5360 info->port_array[0]->port_count = 0;
5361
5362 if ( register_test(info->port_array[0]) &&
5363 register_test(info->port_array[1])) {
5364
5365 info->port_array[0]->port_count = 2;
5366
5367 if ( register_test(info->port_array[2]) &&
5368 register_test(info->port_array[3]) )
5369 info->port_array[0]->port_count += 2;
5370 }
5371 else {
5372 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5373 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5374 return -ENODEV;
5375 }
5376
5377 if ( !irq_test(info->port_array[0]) ||
5378 !irq_test(info->port_array[1]) ||
5379 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5380 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5381 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5382 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5383 return -ENODEV;
5384 }
5385
5386 if (!loopback_test(info->port_array[0]) ||
5387 !loopback_test(info->port_array[1]) ||
5388 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5389 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5390 printk( "%s(%d):DMA test failure for device %s\n",
5391 __FILE__,__LINE__,info->device_name);
5392 return -ENODEV;
5393 }
5394
5395 if ( debug_level >= DEBUG_LEVEL_INFO )
5396 printk( "%s(%d):device %s passed diagnostics\n",
5397 __FILE__,__LINE__,info->device_name );
5398
5399 info->port_array[0]->init_error = 0;
5400 info->port_array[1]->init_error = 0;
5401 if ( info->port_count > 2 ) {
5402 info->port_array[2]->init_error = 0;
5403 info->port_array[3]->init_error = 0;
5404 }
5405
5406 return 0;
5407}
5408
5409/* Test the shared memory on a PCI adapter.
5410 */
5411int memory_test(SLMP_INFO *info)
5412{
5413 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5414 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
fe971071 5415 unsigned long count = ARRAY_SIZE(testval);
1da177e4
LT		 5416 unsigned long i;
5417 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5418 unsigned long * addr = (unsigned long *)info->memory_base;
5419
5420 /* Test data lines with test pattern at one location. */
5421
5422 for ( i = 0 ; i < count ; i++ ) {
5423 *addr = testval[i];
5424 if ( *addr != testval[i] )
5425 return FALSE;
5426 }
5427
5428 /* Test address lines with incrementing pattern over */
5429 /* entire address range. */
5430
5431 for ( i = 0 ; i < limit ; i++ ) {
5432 *addr = i * 4;
5433 addr++;
5434 }
5435
5436 addr = (unsigned long *)info->memory_base;
5437
5438 for ( i = 0 ; i < limit ; i++ ) {
5439 if ( *addr != i * 4 )
5440 return FALSE;
5441 addr++;
5442 }
5443
5444 memset( info->memory_base, 0, SCA_MEM_SIZE );
5445 return TRUE;
5446}
5447
5448/* Load data into PCI adapter shared memory.
5449 *
5450 * The PCI9050 releases control of the local bus
5451 * after completing the current read or write operation.
5452 *
5453 * While the PCI9050 write FIFO not empty, the
5454 * PCI9050 treats all of the writes as a single transaction
5455 * and does not release the bus. This causes DMA latency problems
5456 * at high speeds when copying large data blocks to the shared memory.
5457 *
5458 * This function breaks a write into multiple transations by
5459 * interleaving a read which flushes the write FIFO and 'completes'
5460 * the write transation. This allows any pending DMA request to gain control
5461 * of the local bus in a timely fasion.
5462 */
5463void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5464{
5465 /* A load interval of 16 allows for 4 32-bit writes at */
5466 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5467
5468 unsigned short interval = count / sca_pci_load_interval;
5469 unsigned short i;
5470
5471 for ( i = 0 ; i < interval ; i++ )
5472 {
5473 memcpy(dest, src, sca_pci_load_interval);
5474 read_status_reg(info);
5475 dest += sca_pci_load_interval;
5476 src += sca_pci_load_interval;
5477 }
5478
5479 memcpy(dest, src, count % sca_pci_load_interval);
5480}
5481
5482void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5483{
5484 int i;
5485 int linecount;
5486 if (xmit)
5487 printk("%s tx data:\n",info->device_name);
5488 else
5489 printk("%s rx data:\n",info->device_name);
5490
5491 while(count) {
5492 if (count > 16)
5493 linecount = 16;
5494 else
5495 linecount = count;
5496
5497 for(i=0;i<linecount;i++)
5498 printk("%02X ",(unsigned char)data[i]);
5499 for(;i<17;i++)
5500 printk(" ");
5501 for(i=0;i<linecount;i++) {
5502 if (data[i]>=040 && data[i]<=0176)
5503 printk("%c",data[i]);
5504 else
5505 printk(".");
5506 }
5507 printk("\n");
5508
5509 data += linecount;
5510 count -= linecount;
5511 }
5512} /* end of trace_block() */
5513
5514/* called when HDLC frame times out
5515 * update stats and do tx completion processing
5516 */
5517void tx_timeout(unsigned long context)
5518{
5519 SLMP_INFO *info = (SLMP_INFO*)context;
5520 unsigned long flags;
5521
5522 if ( debug_level >= DEBUG_LEVEL_INFO )
5523 printk( "%s(%d):%s tx_timeout()\n",
5524 __FILE__,__LINE__,info->device_name);
5525 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5526 info->icount.txtimeout++;
5527 }
5528 spin_lock_irqsave(&info->lock,flags);
5529 info->tx_active = 0;
5530 info->tx_count = info->tx_put = info->tx_get = 0;
5531
5532 spin_unlock_irqrestore(&info->lock,flags);
5533
5534#ifdef CONFIG_HDLC
5535 if (info->netcount)
5536 hdlcdev_tx_done(info);
5537 else
5538#endif
5539 bh_transmit(info);
5540}
5541
5542/* called to periodically check the DSR/RI modem signal input status
5543 */
5544void status_timeout(unsigned long context)
5545{
5546 u16 status = 0;
5547 SLMP_INFO *info = (SLMP_INFO*)context;
5548 unsigned long flags;
5549 unsigned char delta;
5550
5551
5552 spin_lock_irqsave(&info->lock,flags);
5553 get_signals(info);
5554 spin_unlock_irqrestore(&info->lock,flags);
5555
5556 /* check for DSR/RI state change */
5557
5558 delta = info->old_signals ^ info->serial_signals;
5559 info->old_signals = info->serial_signals;
5560
5561 if (delta & SerialSignal_DSR)
5562 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5563
5564 if (delta & SerialSignal_RI)
5565 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5566
5567 if (delta & SerialSignal_DCD)
5568 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5569
5570 if (delta & SerialSignal_CTS)
5571 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5572
5573 if (status)
5574 isr_io_pin(info,status);
5575
5576 info->status_timer.data = (unsigned long)info;
5577 info->status_timer.function = status_timeout;
5578 info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5579 add_timer(&info->status_timer);
5580}
5581
5582
5583/* Register Access Routines -
5584 * All registers are memory mapped
5585 */
5586#define CALC_REGADDR() \
5587 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5588 if (info->port_num > 1) \
5589 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5590 if ( info->port_num & 1) { \
5591 if (Addr > 0x7f) \
5592 RegAddr += 0x40; /* DMA access */ \
5593 else if (Addr > 0x1f && Addr < 0x60) \
5594 RegAddr += 0x20; /* MSCI access */ \
5595 }
5596
5597
5598unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5599{
5600 CALC_REGADDR();
5601 return *RegAddr;
5602}
5603void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5604{
5605 CALC_REGADDR();
5606 *RegAddr = Value;
5607}
5608
5609u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5610{
5611 CALC_REGADDR();
5612 return *((u16 *)RegAddr);
5613}
5614
5615void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5616{
5617 CALC_REGADDR();
5618 *((u16 *)RegAddr) = Value;
5619}
5620
5621unsigned char read_status_reg(SLMP_INFO * info)
5622{
5623 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5624 return *RegAddr;
5625}
5626
5627void write_control_reg(SLMP_INFO * info)
5628{
5629 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5630 *RegAddr = info->port_array[0]->ctrlreg_value;
5631}
5632
5633
5634static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5635 const struct pci_device_id *ent)
5636{
5637 if (pci_enable_device(dev)) {
5638 printk("error enabling pci device %p\n", dev);
5639 return -EIO;
5640 }
5641 device_init( ++synclinkmp_adapter_count, dev );
5642 return 0;
5643}
5644
5645static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5646{
5647}
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