[net-next-2.6.git] / drivers / char / ipmi / ipmi_smic_sm.c

/*
 * ipmi_smic_sm.c
 *
 * The state-machine driver for an IPMI SMIC driver
 *
 * It started as a copy of Corey Minyard's driver for the KSC interface
 * and the kernel patch "mmcdev-patch-245" by HP
 *
 * modified by:	Hannes Schulz <schulz@schwaar.com>
 *		ipmi@schwaar.com
 *
 *
 * Corey Minyard's driver for the KSC interface has the following
 * copyright notice:
 *   Copyright 2002 MontaVista Software Inc.
 *
 * the kernel patch "mmcdev-patch-245" by HP has the following
 * copyright notice:
 * (c) Copyright 2001 Grant Grundler (c) Copyright
 * 2001 Hewlett-Packard Company
 *
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the
 *  Free Software Foundation; either version 2 of the License, or (at your
 *  option) any later version.
 *
 *
 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, write to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.  */

#include <linux/kernel.h> /* For printk. */
#include <linux/string.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/ipmi_msgdefs.h>		/* for completion codes */
#include "ipmi_si_sm.h"

/* smic_debug is a bit-field
 *	SMIC_DEBUG_ENABLE -	turned on for now
 *	SMIC_DEBUG_MSG -	commands and their responses
 *	SMIC_DEBUG_STATES -	state machine
*/
#define SMIC_DEBUG_STATES	4
#define SMIC_DEBUG_MSG		2
#define	SMIC_DEBUG_ENABLE	1

static int smic_debug = 1;
module_param(smic_debug, int, 0644);
MODULE_PARM_DESC(smic_debug, "debug bitmask, 1=enable, 2=messages, 4=states");

enum smic_states {
	SMIC_IDLE,
	SMIC_START_OP,
	SMIC_OP_OK,
	SMIC_WRITE_START,
	SMIC_WRITE_NEXT,
	SMIC_WRITE_END,
	SMIC_WRITE2READ,
	SMIC_READ_START,
	SMIC_READ_NEXT,
	SMIC_READ_END,
	SMIC_HOSED
};

#define MAX_SMIC_READ_SIZE 80
#define MAX_SMIC_WRITE_SIZE 80
#define SMIC_MAX_ERROR_RETRIES 3

/* Timeouts in microseconds. */
#define SMIC_RETRY_TIMEOUT 2000000

/* SMIC Flags Register Bits */
#define SMIC_RX_DATA_READY	0x80
#define SMIC_TX_DATA_READY	0x40
/*
 * SMIC_SMI and SMIC_EVM_DATA_AVAIL are only used by
 * a few systems, and then only by Systems Management
 * Interrupts, not by the OS.  Always ignore these bits.
 *
 */
#define SMIC_SMI		0x10
#define SMIC_EVM_DATA_AVAIL	0x08
#define SMIC_SMS_DATA_AVAIL	0x04
#define SMIC_FLAG_BSY		0x01

/* SMIC Error Codes */
#define	EC_NO_ERROR		0x00
#define	EC_ABORTED		0x01
#define	EC_ILLEGAL_CONTROL	0x02
#define	EC_NO_RESPONSE		0x03
#define	EC_ILLEGAL_COMMAND	0x04
#define	EC_BUFFER_FULL		0x05

struct si_sm_data
{
	enum smic_states state;
	struct si_sm_io *io;
        unsigned char	 write_data[MAX_SMIC_WRITE_SIZE];
        int		 write_pos;
        int		 write_count;
        int		 orig_write_count;
        unsigned char	 read_data[MAX_SMIC_READ_SIZE];
        int		 read_pos;
        int		 truncated;
        unsigned int	 error_retries;
        long		 smic_timeout;
};

static unsigned int init_smic_data (struct si_sm_data *smic,
				    struct si_sm_io *io)
{
	smic->state = SMIC_IDLE;
	smic->io = io;
	smic->write_pos = 0;
	smic->write_count = 0;
	smic->orig_write_count = 0;
	smic->read_pos = 0;
	smic->error_retries = 0;
	smic->truncated = 0;
	smic->smic_timeout = SMIC_RETRY_TIMEOUT;

	/* We use 3 bytes of I/O. */
	return 3;
}

static int start_smic_transaction(struct si_sm_data *smic,
				  unsigned char *data, unsigned int size)
{
	unsigned int i;

	if ((size < 2) || (size > MAX_SMIC_WRITE_SIZE)) {
		return -1;
	}
	if ((smic->state != SMIC_IDLE) && (smic->state != SMIC_HOSED)) {
		return -2;
	}
	if (smic_debug & SMIC_DEBUG_MSG) {
		printk(KERN_INFO "start_smic_transaction -");
		for (i = 0; i < size; i ++) {
			printk (" %02x", (unsigned char) (data [i]));
		}
		printk ("\n");
	}
	smic->error_retries = 0;
	memcpy(smic->write_data, data, size);
	smic->write_count = size;
	smic->orig_write_count = size;
	smic->write_pos = 0;
	smic->read_pos = 0;
	smic->state = SMIC_START_OP;
	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
	return 0;
}

static int smic_get_result(struct si_sm_data *smic,
			   unsigned char *data, unsigned int length)
{
	int i;

	if (smic_debug & SMIC_DEBUG_MSG) {
		printk (KERN_INFO "smic_get result -");
		for (i = 0; i < smic->read_pos; i ++) {
			printk (" %02x", (smic->read_data [i]));
		}
		printk ("\n");
	}
	if (length < smic->read_pos) {
		smic->read_pos = length;
		smic->truncated = 1;
	}
	memcpy(data, smic->read_data, smic->read_pos);

	if ((length >= 3) && (smic->read_pos < 3)) {
		data[2] = IPMI_ERR_UNSPECIFIED;
		smic->read_pos = 3;
	}
	if (smic->truncated) {
		data[2] = IPMI_ERR_MSG_TRUNCATED;
		smic->truncated = 0;
	}
	return smic->read_pos;
}

static inline unsigned char read_smic_flags(struct si_sm_data *smic)
{
	return smic->io->inputb(smic->io, 2);
}

static inline unsigned char read_smic_status(struct si_sm_data *smic)
{
	return smic->io->inputb(smic->io, 1);
}

static inline unsigned char read_smic_data(struct si_sm_data *smic)
{
	return smic->io->inputb(smic->io, 0);
}

static inline void write_smic_flags(struct si_sm_data *smic,
				    unsigned char   flags)
{
	smic->io->outputb(smic->io, 2, flags);
}

static inline void write_smic_control(struct si_sm_data *smic,
				      unsigned char   control)
{
	smic->io->outputb(smic->io, 1, control);
}

static inline void write_si_sm_data (struct si_sm_data *smic,
				   unsigned char   data)
{
	smic->io->outputb(smic->io, 0, data);
}

static inline void start_error_recovery(struct si_sm_data *smic, char *reason)
{
	(smic->error_retries)++;
	if (smic->error_retries > SMIC_MAX_ERROR_RETRIES) {
		if (smic_debug & SMIC_DEBUG_ENABLE) {
			printk(KERN_WARNING
			       "ipmi_smic_drv: smic hosed: %s\n", reason);
		}
		smic->state = SMIC_HOSED;
	} else {
		smic->write_count = smic->orig_write_count;
		smic->write_pos = 0;
		smic->read_pos = 0;
		smic->state = SMIC_START_OP;
		smic->smic_timeout = SMIC_RETRY_TIMEOUT;
	}
}

static inline void write_next_byte(struct si_sm_data *smic)
{
	write_si_sm_data(smic, smic->write_data[smic->write_pos]);
	(smic->write_pos)++;
	(smic->write_count)--;
}

static inline void read_next_byte (struct si_sm_data *smic)
{
	if (smic->read_pos >= MAX_SMIC_READ_SIZE) {
		read_smic_data (smic);
		smic->truncated = 1;
	} else {
		smic->read_data[smic->read_pos] = read_smic_data(smic);
		(smic->read_pos)++;
	}
}

/*  SMIC Control/Status Code Components */
#define	SMIC_GET_STATUS		0x00	/* Control form's name */
#define	SMIC_READY		0x00	/* Status  form's name */
#define	SMIC_WR_START		0x01	/* Unified Control/Status names... */
#define	SMIC_WR_NEXT		0x02
#define	SMIC_WR_END		0x03
#define	SMIC_RD_START		0x04
#define	SMIC_RD_NEXT		0x05
#define	SMIC_RD_END		0x06
#define	SMIC_CODE_MASK		0x0f

#define	SMIC_CONTROL		0x00
#define	SMIC_STATUS		0x80
#define	SMIC_CS_MASK		0x80

#define	SMIC_SMS		0x40
#define	SMIC_SMM		0x60
#define	SMIC_STREAM_MASK	0x60

/*  SMIC Control Codes */
#define	SMIC_CC_SMS_GET_STATUS	(SMIC_CONTROL|SMIC_SMS|SMIC_GET_STATUS)
#define	SMIC_CC_SMS_WR_START	(SMIC_CONTROL|SMIC_SMS|SMIC_WR_START)
#define	SMIC_CC_SMS_WR_NEXT	(SMIC_CONTROL|SMIC_SMS|SMIC_WR_NEXT)
#define	SMIC_CC_SMS_WR_END	(SMIC_CONTROL|SMIC_SMS|SMIC_WR_END)
#define	SMIC_CC_SMS_RD_START	(SMIC_CONTROL|SMIC_SMS|SMIC_RD_START)
#define	SMIC_CC_SMS_RD_NEXT	(SMIC_CONTROL|SMIC_SMS|SMIC_RD_NEXT)
#define	SMIC_CC_SMS_RD_END	(SMIC_CONTROL|SMIC_SMS|SMIC_RD_END)

#define	SMIC_CC_SMM_GET_STATUS	(SMIC_CONTROL|SMIC_SMM|SMIC_GET_STATUS)
#define	SMIC_CC_SMM_WR_START	(SMIC_CONTROL|SMIC_SMM|SMIC_WR_START)
#define	SMIC_CC_SMM_WR_NEXT	(SMIC_CONTROL|SMIC_SMM|SMIC_WR_NEXT)
#define	SMIC_CC_SMM_WR_END	(SMIC_CONTROL|SMIC_SMM|SMIC_WR_END)
#define	SMIC_CC_SMM_RD_START	(SMIC_CONTROL|SMIC_SMM|SMIC_RD_START)
#define	SMIC_CC_SMM_RD_NEXT	(SMIC_CONTROL|SMIC_SMM|SMIC_RD_NEXT)
#define	SMIC_CC_SMM_RD_END	(SMIC_CONTROL|SMIC_SMM|SMIC_RD_END)

/*  SMIC Status Codes */
#define	SMIC_SC_SMS_READY	(SMIC_STATUS|SMIC_SMS|SMIC_READY)
#define	SMIC_SC_SMS_WR_START	(SMIC_STATUS|SMIC_SMS|SMIC_WR_START)
#define	SMIC_SC_SMS_WR_NEXT	(SMIC_STATUS|SMIC_SMS|SMIC_WR_NEXT)
#define	SMIC_SC_SMS_WR_END	(SMIC_STATUS|SMIC_SMS|SMIC_WR_END)
#define	SMIC_SC_SMS_RD_START	(SMIC_STATUS|SMIC_SMS|SMIC_RD_START)
#define	SMIC_SC_SMS_RD_NEXT	(SMIC_STATUS|SMIC_SMS|SMIC_RD_NEXT)
#define	SMIC_SC_SMS_RD_END	(SMIC_STATUS|SMIC_SMS|SMIC_RD_END)

#define	SMIC_SC_SMM_READY	(SMIC_STATUS|SMIC_SMM|SMIC_READY)
#define	SMIC_SC_SMM_WR_START	(SMIC_STATUS|SMIC_SMM|SMIC_WR_START)
#define	SMIC_SC_SMM_WR_NEXT	(SMIC_STATUS|SMIC_SMM|SMIC_WR_NEXT)
#define	SMIC_SC_SMM_WR_END	(SMIC_STATUS|SMIC_SMM|SMIC_WR_END)
#define	SMIC_SC_SMM_RD_START	(SMIC_STATUS|SMIC_SMM|SMIC_RD_START)
#define	SMIC_SC_SMM_RD_NEXT	(SMIC_STATUS|SMIC_SMM|SMIC_RD_NEXT)
#define	SMIC_SC_SMM_RD_END	(SMIC_STATUS|SMIC_SMM|SMIC_RD_END)

/* these are the control/status codes we actually use
	SMIC_CC_SMS_GET_STATUS	0x40
	SMIC_CC_SMS_WR_START	0x41
	SMIC_CC_SMS_WR_NEXT	0x42
	SMIC_CC_SMS_WR_END	0x43
	SMIC_CC_SMS_RD_START	0x44
	SMIC_CC_SMS_RD_NEXT	0x45
	SMIC_CC_SMS_RD_END	0x46

	SMIC_SC_SMS_READY	0xC0
	SMIC_SC_SMS_WR_START	0xC1
	SMIC_SC_SMS_WR_NEXT	0xC2
	SMIC_SC_SMS_WR_END	0xC3
	SMIC_SC_SMS_RD_START	0xC4
	SMIC_SC_SMS_RD_NEXT	0xC5
	SMIC_SC_SMS_RD_END	0xC6
*/

static enum si_sm_result smic_event (struct si_sm_data *smic, long time)
{
	unsigned char status;
	unsigned char flags;
	unsigned char data;

	if (smic->state == SMIC_HOSED) {
		init_smic_data(smic, smic->io);
		return SI_SM_HOSED;
	}
	if (smic->state != SMIC_IDLE) {
		if (smic_debug & SMIC_DEBUG_STATES) {
			printk(KERN_INFO
			       "smic_event - smic->smic_timeout = %ld,"
			       " time = %ld\n",
			       smic->smic_timeout, time);
		}
/* FIXME: smic_event is sometimes called with time > SMIC_RETRY_TIMEOUT */
		if (time < SMIC_RETRY_TIMEOUT) {
			smic->smic_timeout -= time;
			if (smic->smic_timeout < 0) {
				start_error_recovery(smic, "smic timed out.");
				return SI_SM_CALL_WITH_DELAY;
			}
		}
	}
	flags = read_smic_flags(smic);
	if (flags & SMIC_FLAG_BSY)
		return SI_SM_CALL_WITH_DELAY;

	status = read_smic_status (smic);
	if (smic_debug & SMIC_DEBUG_STATES)
		printk(KERN_INFO
		       "smic_event - state = %d, flags = 0x%02x,"
		       " status = 0x%02x\n",
		       smic->state, flags, status);

	switch (smic->state) {
	case SMIC_IDLE:
		/* in IDLE we check for available messages */
		if (flags & SMIC_SMS_DATA_AVAIL)
		{
			return SI_SM_ATTN;
		}
		return SI_SM_IDLE;

	case SMIC_START_OP:
		/* sanity check whether smic is really idle */
		write_smic_control(smic, SMIC_CC_SMS_GET_STATUS);
		write_smic_flags(smic, flags | SMIC_FLAG_BSY);
		smic->state = SMIC_OP_OK;
		break;

	case SMIC_OP_OK:
		if (status != SMIC_SC_SMS_READY) {
				/* this should not happen */
			start_error_recovery(smic,
					     "state = SMIC_OP_OK,"
					     " status != SMIC_SC_SMS_READY");
			return SI_SM_CALL_WITH_DELAY;
		}
		/* OK so far; smic is idle let us start ... */
		write_smic_control(smic, SMIC_CC_SMS_WR_START);
		write_next_byte(smic);
		write_smic_flags(smic, flags | SMIC_FLAG_BSY);
		smic->state = SMIC_WRITE_START;
		break;

	case SMIC_WRITE_START:
		if (status != SMIC_SC_SMS_WR_START) {
			start_error_recovery(smic,
					     "state = SMIC_WRITE_START, "
					     "status != SMIC_SC_SMS_WR_START");
			return SI_SM_CALL_WITH_DELAY;
		}
		/* we must not issue WR_(NEXT|END) unless
                   TX_DATA_READY is set */
		if (flags & SMIC_TX_DATA_READY) {
			if (smic->write_count == 1) {
				/* last byte */
				write_smic_control(smic, SMIC_CC_SMS_WR_END);
				smic->state = SMIC_WRITE_END;
			} else {
				write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
				smic->state = SMIC_WRITE_NEXT;
			}
			write_next_byte(smic);
			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
		}
		else {
			return SI_SM_CALL_WITH_DELAY;
		}
		break;

	case SMIC_WRITE_NEXT:
		if (status != SMIC_SC_SMS_WR_NEXT) {
			start_error_recovery(smic,
					     "state = SMIC_WRITE_NEXT, "
					     "status != SMIC_SC_SMS_WR_NEXT");
			return SI_SM_CALL_WITH_DELAY;
		}
		/* this is the same code as in SMIC_WRITE_START */
		if (flags & SMIC_TX_DATA_READY) {
			if (smic->write_count == 1) {
				write_smic_control(smic, SMIC_CC_SMS_WR_END);
				smic->state = SMIC_WRITE_END;
			}
			else {
				write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
				smic->state = SMIC_WRITE_NEXT;
			}
			write_next_byte(smic);
			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
		}
		else {
			return SI_SM_CALL_WITH_DELAY;
		}
		break;

	case SMIC_WRITE_END:
		if (status != SMIC_SC_SMS_WR_END) {
			start_error_recovery (smic,
					      "state = SMIC_WRITE_END, "
					      "status != SMIC_SC_SMS_WR_END");
			return SI_SM_CALL_WITH_DELAY;
		}
		/* data register holds an error code */
		data = read_smic_data(smic);
		if (data != 0) {
			if (smic_debug & SMIC_DEBUG_ENABLE) {
				printk(KERN_INFO
				       "SMIC_WRITE_END: data = %02x\n", data);
			}
			start_error_recovery(smic,
					     "state = SMIC_WRITE_END, "
					     "data != SUCCESS");
			return SI_SM_CALL_WITH_DELAY;
		} else {
			smic->state = SMIC_WRITE2READ;
		}
		break;

	case SMIC_WRITE2READ:
		/* we must wait for RX_DATA_READY to be set before we
                   can continue */
		if (flags & SMIC_RX_DATA_READY) {
			write_smic_control(smic, SMIC_CC_SMS_RD_START);
			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
			smic->state = SMIC_READ_START;
		} else {
			return SI_SM_CALL_WITH_DELAY;
		}
		break;

	case SMIC_READ_START:
		if (status != SMIC_SC_SMS_RD_START) {
			start_error_recovery(smic,
					     "state = SMIC_READ_START, "
					     "status != SMIC_SC_SMS_RD_START");
			return SI_SM_CALL_WITH_DELAY;
		}
		if (flags & SMIC_RX_DATA_READY) {
			read_next_byte(smic);
			write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
			smic->state = SMIC_READ_NEXT;
		} else {
			return SI_SM_CALL_WITH_DELAY;
		}
		break;

	case SMIC_READ_NEXT:
		switch (status) {
		/* smic tells us that this is the last byte to be read
                   --> clean up */
		case SMIC_SC_SMS_RD_END:
			read_next_byte(smic);
			write_smic_control(smic, SMIC_CC_SMS_RD_END);
			write_smic_flags(smic, flags | SMIC_FLAG_BSY);
			smic->state = SMIC_READ_END;
			break;
		case SMIC_SC_SMS_RD_NEXT:
			if (flags & SMIC_RX_DATA_READY) {
				read_next_byte(smic);
				write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
				write_smic_flags(smic, flags | SMIC_FLAG_BSY);
				smic->state = SMIC_READ_NEXT;
			} else {
				return SI_SM_CALL_WITH_DELAY;
			}
			break;
		default:
			start_error_recovery(
				smic,
				"state = SMIC_READ_NEXT, "
				"status != SMIC_SC_SMS_RD_(NEXT|END)");
			return SI_SM_CALL_WITH_DELAY;
		}
		break;

	case SMIC_READ_END:
		if (status != SMIC_SC_SMS_READY) {
			start_error_recovery(smic,
					     "state = SMIC_READ_END, "
					     "status != SMIC_SC_SMS_READY");
			return SI_SM_CALL_WITH_DELAY;
		}
		data = read_smic_data(smic);
		/* data register holds an error code */
		if (data != 0) {
			if (smic_debug & SMIC_DEBUG_ENABLE) {
				printk(KERN_INFO
				       "SMIC_READ_END: data = %02x\n", data);
			}
			start_error_recovery(smic,
					     "state = SMIC_READ_END, "
					     "data != SUCCESS");
			return SI_SM_CALL_WITH_DELAY;
		} else {
			smic->state = SMIC_IDLE;
			return SI_SM_TRANSACTION_COMPLETE;
		}

	case SMIC_HOSED:
		init_smic_data(smic, smic->io);
		return SI_SM_HOSED;

	default:
		if (smic_debug & SMIC_DEBUG_ENABLE) {
			printk(KERN_WARNING "smic->state = %d\n", smic->state);
			start_error_recovery(smic, "state = UNKNOWN");
			return SI_SM_CALL_WITH_DELAY;
		}
	}
	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
	return SI_SM_CALL_WITHOUT_DELAY;
}

static int smic_detect(struct si_sm_data *smic)
{
	/* It's impossible for the SMIC fnags register to be all 1's,
	   (assuming a properly functioning, self-initialized BMC)
	   but that's what you get from reading a bogus address, so we
	   test that first. */
	if (read_smic_flags(smic) == 0xff)
		return 1;

	return 0;
}

static void smic_cleanup(struct si_sm_data *kcs)
{
}

static int smic_size(void)
{
	return sizeof(struct si_sm_data);
}

struct si_sm_handlers smic_smi_handlers =
{
	.init_data         = init_smic_data,
	.start_transaction = start_smic_transaction,
	.get_result        = smic_get_result,
	.event             = smic_event,
	.detect            = smic_detect,
	.cleanup           = smic_cleanup,
	.size              = smic_size,
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	* ipmi_smic_sm.c
	3	*
	4	* The state-machine driver for an IPMI SMIC driver
	5	*
	6	* It started as a copy of Corey Minyard's driver for the KSC interface
	7	* and the kernel patch "mmcdev-patch-245" by HP
	8	*
	9	* modified by: Hannes Schulz <schulz@schwaar.com>
	10	* ipmi@schwaar.com
	11	*
	12	*
	13	* Corey Minyard's driver for the KSC interface has the following
	14	* copyright notice:
	15	* Copyright 2002 MontaVista Software Inc.
	16	*
	17	* the kernel patch "mmcdev-patch-245" by HP has the following
	18	* copyright notice:
	19	* (c) Copyright 2001 Grant Grundler (c) Copyright
	20	* 2001 Hewlett-Packard Company
	21	*
	22	*
	23	* This program is free software; you can redistribute it and/or modify it
	24	* under the terms of the GNU General Public License as published by the
	25	* Free Software Foundation; either version 2 of the License, or (at your
	26	* option) any later version.
	27	*
	28	*
	29	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	30	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	31	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
	32	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	33	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
	34	* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
	35	* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	36	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
	37	* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
	38	* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	39	*
	40	* You should have received a copy of the GNU General Public License along
	41	* with this program; if not, write to the Free Software Foundation, Inc.,
	42	* 675 Mass Ave, Cambridge, MA 02139, USA. */
	43
	44	#include <linux/kernel.h> /* For printk. */
	45	#include <linux/string.h>
c4edff1c CM	46	#include <linux/module.h>
c4edff1c CM	47	#include <linux/moduleparam.h>
1da177e4 LT	48	#include <linux/ipmi_msgdefs.h> /* for completion codes */
	49	#include "ipmi_si_sm.h"
	50
1da177e4 LT	51	/* smic_debug is a bit-field
	52	* SMIC_DEBUG_ENABLE - turned on for now
	53	* SMIC_DEBUG_MSG - commands and their responses
	54	* SMIC_DEBUG_STATES - state machine
	55	*/
	56	#define SMIC_DEBUG_STATES 4
	57	#define SMIC_DEBUG_MSG 2
	58	#define SMIC_DEBUG_ENABLE 1
	59
	60	static int smic_debug = 1;
c4edff1c CM	61	module_param(smic_debug, int, 0644);
c4edff1c CM	62	MODULE_PARM_DESC(smic_debug, "debug bitmask, 1=enable, 2=messages, 4=states");
1da177e4 LT	63
	64	enum smic_states {
	65	SMIC_IDLE,
	66	SMIC_START_OP,
	67	SMIC_OP_OK,
	68	SMIC_WRITE_START,
	69	SMIC_WRITE_NEXT,
	70	SMIC_WRITE_END,
	71	SMIC_WRITE2READ,
	72	SMIC_READ_START,
	73	SMIC_READ_NEXT,
	74	SMIC_READ_END,
	75	SMIC_HOSED
	76	};
	77
	78	#define MAX_SMIC_READ_SIZE 80
	79	#define MAX_SMIC_WRITE_SIZE 80
	80	#define SMIC_MAX_ERROR_RETRIES 3
	81
	82	/* Timeouts in microseconds. */
c4edff1c	83	#define SMIC_RETRY_TIMEOUT 2000000
1da177e4 LT	84
	85	/* SMIC Flags Register Bits */
	86	#define SMIC_RX_DATA_READY 0x80
	87	#define SMIC_TX_DATA_READY 0x40
d5a2b89a CM	88	/*
	89	* SMIC_SMI and SMIC_EVM_DATA_AVAIL are only used by
	90	* a few systems, and then only by Systems Management
	91	* Interrupts, not by the OS. Always ignore these bits.
	92	*
	93	*/
1da177e4 LT	94	#define SMIC_SMI 0x10
	95	#define SMIC_EVM_DATA_AVAIL 0x08
	96	#define SMIC_SMS_DATA_AVAIL 0x04
	97	#define SMIC_FLAG_BSY 0x01
	98
	99	/* SMIC Error Codes */
	100	#define EC_NO_ERROR 0x00
	101	#define EC_ABORTED 0x01
	102	#define EC_ILLEGAL_CONTROL 0x02
	103	#define EC_NO_RESPONSE 0x03
	104	#define EC_ILLEGAL_COMMAND 0x04
	105	#define EC_BUFFER_FULL 0x05
	106
	107	struct si_sm_data
	108	{
	109	enum smic_states state;
	110	struct si_sm_io *io;
	111	unsigned char write_data[MAX_SMIC_WRITE_SIZE];
	112	int write_pos;
	113	int write_count;
	114	int orig_write_count;
	115	unsigned char read_data[MAX_SMIC_READ_SIZE];
	116	int read_pos;
	117	int truncated;
	118	unsigned int error_retries;
	119	long smic_timeout;
	120	};
	121
	122	static unsigned int init_smic_data (struct si_sm_data *smic,
	123	struct si_sm_io *io)
	124	{
	125	smic->state = SMIC_IDLE;
	126	smic->io = io;
	127	smic->write_pos = 0;
	128	smic->write_count = 0;
	129	smic->orig_write_count = 0;
	130	smic->read_pos = 0;
	131	smic->error_retries = 0;
	132	smic->truncated = 0;
	133	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
	134
	135	/* We use 3 bytes of I/O. */
	136	return 3;
	137	}
	138
	139	static int start_smic_transaction(struct si_sm_data *smic,
	140	unsigned char *data, unsigned int size)
	141	{
	142	unsigned int i;
	143
	144	if ((size < 2) \|\| (size > MAX_SMIC_WRITE_SIZE)) {
	145	return -1;
	146	}
	147	if ((smic->state != SMIC_IDLE) && (smic->state != SMIC_HOSED)) {
	148	return -2;
	149	}
	150	if (smic_debug & SMIC_DEBUG_MSG) {
	151	printk(KERN_INFO "start_smic_transaction -");
	152	for (i = 0; i < size; i ++) {
	153	printk (" %02x", (unsigned char) (data [i]));
	154	}
	155	printk ("\n");
	156	}
	157	smic->error_retries = 0;
158	memcpy(smic->write_data, data, size);
159	smic->write_count = size;
160	smic->orig_write_count = size;
161	smic->write_pos = 0;
162	smic->read_pos = 0;
163	smic->state = SMIC_START_OP;
164	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
165	return 0;
166	}
167
168	static int smic_get_result(struct si_sm_data *smic,
169	unsigned char *data, unsigned int length)
170	{
171	int i;
172
173	if (smic_debug & SMIC_DEBUG_MSG) {
174	printk (KERN_INFO "smic_get result -");
175	for (i = 0; i < smic->read_pos; i ++) {
176	printk (" %02x", (smic->read_data [i]));
177	}
178	printk ("\n");
179	}
180	if (length < smic->read_pos) {
181	smic->read_pos = length;
182	smic->truncated = 1;
183	}
184	memcpy(data, smic->read_data, smic->read_pos);
185
186	if ((length >= 3) && (smic->read_pos < 3)) {
187	data[2] = IPMI_ERR_UNSPECIFIED;
188	smic->read_pos = 3;
189	}
190	if (smic->truncated) {
191	data[2] = IPMI_ERR_MSG_TRUNCATED;
192	smic->truncated = 0;
193	}
194	return smic->read_pos;
195	}
196
197	static inline unsigned char read_smic_flags(struct si_sm_data *smic)
198	{
199	return smic->io->inputb(smic->io, 2);
200	}
201
202	static inline unsigned char read_smic_status(struct si_sm_data *smic)
203	{
204	return smic->io->inputb(smic->io, 1);
205	}
206
207	static inline unsigned char read_smic_data(struct si_sm_data *smic)
208	{
209	return smic->io->inputb(smic->io, 0);
210	}
211
212	static inline void write_smic_flags(struct si_sm_data *smic,
213	unsigned char flags)
214	{
215	smic->io->outputb(smic->io, 2, flags);
216	}
217
218	static inline void write_smic_control(struct si_sm_data *smic,
219	unsigned char control)
220	{
221	smic->io->outputb(smic->io, 1, control);
222	}
223
224	static inline void write_si_sm_data (struct si_sm_data *smic,
225	unsigned char data)
226	{
227	smic->io->outputb(smic->io, 0, data);
228	}
229
230	static inline void start_error_recovery(struct si_sm_data smic, char reason)
231	{
232	(smic->error_retries)++;
233	if (smic->error_retries > SMIC_MAX_ERROR_RETRIES) {
234	if (smic_debug & SMIC_DEBUG_ENABLE) {
235	printk(KERN_WARNING
236	"ipmi_smic_drv: smic hosed: %s\n", reason);
237	}
238	smic->state = SMIC_HOSED;
239	} else {
240	smic->write_count = smic->orig_write_count;
241	smic->write_pos = 0;
242	smic->read_pos = 0;
243	smic->state = SMIC_START_OP;
244	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
245	}
246	}
247
248	static inline void write_next_byte(struct si_sm_data *smic)
249	{
250	write_si_sm_data(smic, smic->write_data[smic->write_pos]);
251	(smic->write_pos)++;
252	(smic->write_count)--;
253	}
254
255	static inline void read_next_byte (struct si_sm_data *smic)
256	{
257	if (smic->read_pos >= MAX_SMIC_READ_SIZE) {
258	read_smic_data (smic);
259	smic->truncated = 1;
260	} else {
261	smic->read_data[smic->read_pos] = read_smic_data(smic);
262	(smic->read_pos)++;
263	}
264	}
265
266	/* SMIC Control/Status Code Components */
267	#define SMIC_GET_STATUS 0x00 /* Control form's name */
268	#define SMIC_READY 0x00 /* Status form's name */
269	#define SMIC_WR_START 0x01 /* Unified Control/Status names... */
270	#define SMIC_WR_NEXT 0x02
271	#define SMIC_WR_END 0x03
272	#define SMIC_RD_START 0x04
273	#define SMIC_RD_NEXT 0x05
274	#define SMIC_RD_END 0x06
275	#define SMIC_CODE_MASK 0x0f
276
277	#define SMIC_CONTROL 0x00
278	#define SMIC_STATUS 0x80
279	#define SMIC_CS_MASK 0x80
280
281	#define SMIC_SMS 0x40
282	#define SMIC_SMM 0x60
283	#define SMIC_STREAM_MASK 0x60
284
285	/* SMIC Control Codes */
286	#define SMIC_CC_SMS_GET_STATUS (SMIC_CONTROL\|SMIC_SMS\|SMIC_GET_STATUS)
287	#define SMIC_CC_SMS_WR_START (SMIC_CONTROL\|SMIC_SMS\|SMIC_WR_START)
288	#define SMIC_CC_SMS_WR_NEXT (SMIC_CONTROL\|SMIC_SMS\|SMIC_WR_NEXT)
289	#define SMIC_CC_SMS_WR_END (SMIC_CONTROL\|SMIC_SMS\|SMIC_WR_END)
290	#define SMIC_CC_SMS_RD_START (SMIC_CONTROL\|SMIC_SMS\|SMIC_RD_START)
291	#define SMIC_CC_SMS_RD_NEXT (SMIC_CONTROL\|SMIC_SMS\|SMIC_RD_NEXT)
292	#define SMIC_CC_SMS_RD_END (SMIC_CONTROL\|SMIC_SMS\|SMIC_RD_END)
293
294	#define SMIC_CC_SMM_GET_STATUS (SMIC_CONTROL\|SMIC_SMM\|SMIC_GET_STATUS)
295	#define SMIC_CC_SMM_WR_START (SMIC_CONTROL\|SMIC_SMM\|SMIC_WR_START)
296	#define SMIC_CC_SMM_WR_NEXT (SMIC_CONTROL\|SMIC_SMM\|SMIC_WR_NEXT)
297	#define SMIC_CC_SMM_WR_END (SMIC_CONTROL\|SMIC_SMM\|SMIC_WR_END)
298	#define SMIC_CC_SMM_RD_START (SMIC_CONTROL\|SMIC_SMM\|SMIC_RD_START)
299	#define SMIC_CC_SMM_RD_NEXT (SMIC_CONTROL\|SMIC_SMM\|SMIC_RD_NEXT)
300	#define SMIC_CC_SMM_RD_END (SMIC_CONTROL\|SMIC_SMM\|SMIC_RD_END)
301
302	/* SMIC Status Codes */
303	#define SMIC_SC_SMS_READY (SMIC_STATUS\|SMIC_SMS\|SMIC_READY)
304	#define SMIC_SC_SMS_WR_START (SMIC_STATUS\|SMIC_SMS\|SMIC_WR_START)
305	#define SMIC_SC_SMS_WR_NEXT (SMIC_STATUS\|SMIC_SMS\|SMIC_WR_NEXT)
306	#define SMIC_SC_SMS_WR_END (SMIC_STATUS\|SMIC_SMS\|SMIC_WR_END)
307	#define SMIC_SC_SMS_RD_START (SMIC_STATUS\|SMIC_SMS\|SMIC_RD_START)
308	#define SMIC_SC_SMS_RD_NEXT (SMIC_STATUS\|SMIC_SMS\|SMIC_RD_NEXT)
309	#define SMIC_SC_SMS_RD_END (SMIC_STATUS\|SMIC_SMS\|SMIC_RD_END)
310
311	#define SMIC_SC_SMM_READY (SMIC_STATUS\|SMIC_SMM\|SMIC_READY)
312	#define SMIC_SC_SMM_WR_START (SMIC_STATUS\|SMIC_SMM\|SMIC_WR_START)
313	#define SMIC_SC_SMM_WR_NEXT (SMIC_STATUS\|SMIC_SMM\|SMIC_WR_NEXT)
314	#define SMIC_SC_SMM_WR_END (SMIC_STATUS\|SMIC_SMM\|SMIC_WR_END)
315	#define SMIC_SC_SMM_RD_START (SMIC_STATUS\|SMIC_SMM\|SMIC_RD_START)
316	#define SMIC_SC_SMM_RD_NEXT (SMIC_STATUS\|SMIC_SMM\|SMIC_RD_NEXT)
317	#define SMIC_SC_SMM_RD_END (SMIC_STATUS\|SMIC_SMM\|SMIC_RD_END)
318
319	/* these are the control/status codes we actually use
320	SMIC_CC_SMS_GET_STATUS 0x40
321	SMIC_CC_SMS_WR_START 0x41
322	SMIC_CC_SMS_WR_NEXT 0x42
323	SMIC_CC_SMS_WR_END 0x43
324	SMIC_CC_SMS_RD_START 0x44
325	SMIC_CC_SMS_RD_NEXT 0x45
326	SMIC_CC_SMS_RD_END 0x46
327
328	SMIC_SC_SMS_READY 0xC0
329	SMIC_SC_SMS_WR_START 0xC1
330	SMIC_SC_SMS_WR_NEXT 0xC2
331	SMIC_SC_SMS_WR_END 0xC3
332	SMIC_SC_SMS_RD_START 0xC4
333	SMIC_SC_SMS_RD_NEXT 0xC5
334	SMIC_SC_SMS_RD_END 0xC6
335	*/
336
337	static enum si_sm_result smic_event (struct si_sm_data *smic, long time)
338	{
339	unsigned char status;
340	unsigned char flags;
341	unsigned char data;
342
343	if (smic->state == SMIC_HOSED) {
344	init_smic_data(smic, smic->io);
345	return SI_SM_HOSED;
346	}
347	if (smic->state != SMIC_IDLE) {
348	if (smic_debug & SMIC_DEBUG_STATES) {
349	printk(KERN_INFO
350	"smic_event - smic->smic_timeout = %ld,"
351	" time = %ld\n",
352	smic->smic_timeout, time);
353	}
354	/* FIXME: smic_event is sometimes called with time > SMIC_RETRY_TIMEOUT */
355	if (time < SMIC_RETRY_TIMEOUT) {
356	smic->smic_timeout -= time;
357	if (smic->smic_timeout < 0) {
358	start_error_recovery(smic, "smic timed out.");
359	return SI_SM_CALL_WITH_DELAY;
360	}
361	}
362	}
363	flags = read_smic_flags(smic);
364	if (flags & SMIC_FLAG_BSY)
365	return SI_SM_CALL_WITH_DELAY;
366
367	status = read_smic_status (smic);
368	if (smic_debug & SMIC_DEBUG_STATES)
369	printk(KERN_INFO
370	"smic_event - state = %d, flags = 0x%02x,"
371	" status = 0x%02x\n",
372	smic->state, flags, status);
373
374	switch (smic->state) {
375	case SMIC_IDLE:
376	/* in IDLE we check for available messages */
d5a2b89a	377	if (flags & SMIC_SMS_DATA_AVAIL)
1da177e4 LT	378	{
	379	return SI_SM_ATTN;
	380	}
	381	return SI_SM_IDLE;
	382
	383	case SMIC_START_OP:
	384	/* sanity check whether smic is really idle */
	385	write_smic_control(smic, SMIC_CC_SMS_GET_STATUS);
	386	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
	387	smic->state = SMIC_OP_OK;
	388	break;
	389
	390	case SMIC_OP_OK:
	391	if (status != SMIC_SC_SMS_READY) {
	392	/* this should not happen */
	393	start_error_recovery(smic,
	394	"state = SMIC_OP_OK,"
	395	" status != SMIC_SC_SMS_READY");
	396	return SI_SM_CALL_WITH_DELAY;
	397	}
	398	/* OK so far; smic is idle let us start ... */
	399	write_smic_control(smic, SMIC_CC_SMS_WR_START);
	400	write_next_byte(smic);
	401	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
	402	smic->state = SMIC_WRITE_START;
	403	break;
	404
	405	case SMIC_WRITE_START:
	406	if (status != SMIC_SC_SMS_WR_START) {
	407	start_error_recovery(smic,
	408	"state = SMIC_WRITE_START, "
	409	"status != SMIC_SC_SMS_WR_START");
	410	return SI_SM_CALL_WITH_DELAY;
	411	}
	412	/* we must not issue WR_(NEXT\|END) unless
	413	TX_DATA_READY is set */
	414	if (flags & SMIC_TX_DATA_READY) {
	415	if (smic->write_count == 1) {
	416	/* last byte */
	417	write_smic_control(smic, SMIC_CC_SMS_WR_END);
	418	smic->state = SMIC_WRITE_END;
	419	} else {
	420	write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
	421	smic->state = SMIC_WRITE_NEXT;
	422	}
	423	write_next_byte(smic);
	424	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
	425	}
	426	else {
	427	return SI_SM_CALL_WITH_DELAY;
	428	}
	429	break;
	430
	431	case SMIC_WRITE_NEXT:
	432	if (status != SMIC_SC_SMS_WR_NEXT) {
	433	start_error_recovery(smic,
	434	"state = SMIC_WRITE_NEXT, "
	435	"status != SMIC_SC_SMS_WR_NEXT");
	436	return SI_SM_CALL_WITH_DELAY;
	437	}
	438	/* this is the same code as in SMIC_WRITE_START */
	439	if (flags & SMIC_TX_DATA_READY) {
	440	if (smic->write_count == 1) {
	441	write_smic_control(smic, SMIC_CC_SMS_WR_END);
442	smic->state = SMIC_WRITE_END;
443	}
444	else {
445	write_smic_control(smic, SMIC_CC_SMS_WR_NEXT);
446	smic->state = SMIC_WRITE_NEXT;
447	}
448	write_next_byte(smic);
449	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
450	}
451	else {
452	return SI_SM_CALL_WITH_DELAY;
453	}
454	break;
455
456	case SMIC_WRITE_END:
457	if (status != SMIC_SC_SMS_WR_END) {
458	start_error_recovery (smic,
459	"state = SMIC_WRITE_END, "
460	"status != SMIC_SC_SMS_WR_END");
461	return SI_SM_CALL_WITH_DELAY;
462	}
463	/* data register holds an error code */
464	data = read_smic_data(smic);
465	if (data != 0) {
466	if (smic_debug & SMIC_DEBUG_ENABLE) {
467	printk(KERN_INFO
468	"SMIC_WRITE_END: data = %02x\n", data);
469	}
470	start_error_recovery(smic,
471	"state = SMIC_WRITE_END, "
472	"data != SUCCESS");
473	return SI_SM_CALL_WITH_DELAY;
474	} else {
475	smic->state = SMIC_WRITE2READ;
476	}
477	break;
478
479	case SMIC_WRITE2READ:
480	/* we must wait for RX_DATA_READY to be set before we
481	can continue */
482	if (flags & SMIC_RX_DATA_READY) {
483	write_smic_control(smic, SMIC_CC_SMS_RD_START);
484	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
485	smic->state = SMIC_READ_START;
486	} else {
487	return SI_SM_CALL_WITH_DELAY;
488	}
489	break;
490
491	case SMIC_READ_START:
492	if (status != SMIC_SC_SMS_RD_START) {
493	start_error_recovery(smic,
494	"state = SMIC_READ_START, "
495	"status != SMIC_SC_SMS_RD_START");
496	return SI_SM_CALL_WITH_DELAY;
497	}
498	if (flags & SMIC_RX_DATA_READY) {
499	read_next_byte(smic);
500	write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
501	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
502	smic->state = SMIC_READ_NEXT;
503	} else {
504	return SI_SM_CALL_WITH_DELAY;
505	}
506	break;
507
508	case SMIC_READ_NEXT:
509	switch (status) {
510	/* smic tells us that this is the last byte to be read
511	--> clean up */
512	case SMIC_SC_SMS_RD_END:
513	read_next_byte(smic);
514	write_smic_control(smic, SMIC_CC_SMS_RD_END);
515	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
516	smic->state = SMIC_READ_END;
517	break;
518	case SMIC_SC_SMS_RD_NEXT:
519	if (flags & SMIC_RX_DATA_READY) {
520	read_next_byte(smic);
521	write_smic_control(smic, SMIC_CC_SMS_RD_NEXT);
522	write_smic_flags(smic, flags \| SMIC_FLAG_BSY);
523	smic->state = SMIC_READ_NEXT;
524	} else {
525	return SI_SM_CALL_WITH_DELAY;
526	}
527	break;
528	default:
529	start_error_recovery(
530	smic,
531	"state = SMIC_READ_NEXT, "
532	"status != SMIC_SC_SMS_RD_(NEXT\|END)");
533	return SI_SM_CALL_WITH_DELAY;
534	}
535	break;
536
537	case SMIC_READ_END:
538	if (status != SMIC_SC_SMS_READY) {
539	start_error_recovery(smic,
540	"state = SMIC_READ_END, "
541	"status != SMIC_SC_SMS_READY");
542	return SI_SM_CALL_WITH_DELAY;
543	}
544	data = read_smic_data(smic);
545	/* data register holds an error code */
546	if (data != 0) {
547	if (smic_debug & SMIC_DEBUG_ENABLE) {
548	printk(KERN_INFO
549	"SMIC_READ_END: data = %02x\n", data);
550	}
551	start_error_recovery(smic,
552	"state = SMIC_READ_END, "
553	"data != SUCCESS");
554	return SI_SM_CALL_WITH_DELAY;
555	} else {
556	smic->state = SMIC_IDLE;
557	return SI_SM_TRANSACTION_COMPLETE;
558	}
559
560	case SMIC_HOSED:
561	init_smic_data(smic, smic->io);
562	return SI_SM_HOSED;
563
564	default:
565	if (smic_debug & SMIC_DEBUG_ENABLE) {
566	printk(KERN_WARNING "smic->state = %d\n", smic->state);
567	start_error_recovery(smic, "state = UNKNOWN");
568	return SI_SM_CALL_WITH_DELAY;
569	}
570	}
571	smic->smic_timeout = SMIC_RETRY_TIMEOUT;
572	return SI_SM_CALL_WITHOUT_DELAY;
573	}
574
575	static int smic_detect(struct si_sm_data *smic)
576	{
577	/* It's impossible for the SMIC fnags register to be all 1's,
578	(assuming a properly functioning, self-initialized BMC)
579	but that's what you get from reading a bogus address, so we
580	test that first. */
581	if (read_smic_flags(smic) == 0xff)
582	return 1;
583
584	return 0;
585	}
586
587	static void smic_cleanup(struct si_sm_data *kcs)
588	{
589	}
590
591	static int smic_size(void)
592	{
593	return sizeof(struct si_sm_data);
594	}
595
596	struct si_sm_handlers smic_smi_handlers =
597	{
1da177e4 LT	598	.init_data = init_smic_data,
	599	.start_transaction = start_smic_transaction,
	600	.get_result = smic_get_result,
	601	.event = smic_event,
	602	.detect = smic_detect,
	603	.cleanup = smic_cleanup,
	604	.size = smic_size,
	605	};