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d985c108 DA |
1 | /* radeon_state.c -- State support for Radeon -*- linux-c -*- */ |
2 | /* | |
1da177e4 LT |
3 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Gareth Hughes <gareth@valinux.com> | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
32 | #include "drm_sarea.h" | |
33 | #include "radeon_drm.h" | |
34 | #include "radeon_drv.h" | |
35 | ||
36 | /* ================================================================ | |
37 | * Helper functions for client state checking and fixup | |
38 | */ | |
39 | ||
b5e89ed5 DA |
40 | static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t * |
41 | dev_priv, | |
6c340eac | 42 | struct drm_file * file_priv, |
b3a83639 | 43 | u32 *offset) |
b5e89ed5 | 44 | { |
214ff13d | 45 | u64 off = *offset; |
1d6bb8e5 | 46 | u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1; |
1da177e4 LT |
47 | struct drm_radeon_driver_file_fields *radeon_priv; |
48 | ||
d5ea702f DA |
49 | /* Hrm ... the story of the offset ... So this function converts |
50 | * the various ideas of what userland clients might have for an | |
51 | * offset in the card address space into an offset into the card | |
52 | * address space :) So with a sane client, it should just keep | |
53 | * the value intact and just do some boundary checking. However, | |
54 | * not all clients are sane. Some older clients pass us 0 based | |
55 | * offsets relative to the start of the framebuffer and some may | |
56 | * assume the AGP aperture it appended to the framebuffer, so we | |
57 | * try to detect those cases and fix them up. | |
58 | * | |
59 | * Note: It might be a good idea here to make sure the offset lands | |
60 | * in some "allowed" area to protect things like the PCIE GART... | |
61 | */ | |
1da177e4 | 62 | |
d5ea702f DA |
63 | /* First, the best case, the offset already lands in either the |
64 | * framebuffer or the GART mapped space | |
65 | */ | |
1d6bb8e5 | 66 | if (radeon_check_offset(dev_priv, off)) |
d5ea702f | 67 | return 0; |
1da177e4 | 68 | |
d5ea702f DA |
69 | /* Ok, that didn't happen... now check if we have a zero based |
70 | * offset that fits in the framebuffer + gart space, apply the | |
71 | * magic offset we get from SETPARAM or calculated from fb_location | |
72 | */ | |
73 | if (off < (dev_priv->fb_size + dev_priv->gart_size)) { | |
6c340eac | 74 | radeon_priv = file_priv->driver_priv; |
d5ea702f DA |
75 | off += radeon_priv->radeon_fb_delta; |
76 | } | |
1da177e4 | 77 | |
d5ea702f | 78 | /* Finally, assume we aimed at a GART offset if beyond the fb */ |
214ff13d | 79 | if (off > fb_end) |
1d6bb8e5 | 80 | off = off - fb_end - 1 + dev_priv->gart_vm_start; |
1da177e4 | 81 | |
d5ea702f | 82 | /* Now recheck and fail if out of bounds */ |
1d6bb8e5 | 83 | if (radeon_check_offset(dev_priv, off)) { |
214ff13d | 84 | DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off); |
d5ea702f DA |
85 | *offset = off; |
86 | return 0; | |
87 | } | |
20caafa6 | 88 | return -EINVAL; |
1da177e4 LT |
89 | } |
90 | ||
b5e89ed5 DA |
91 | static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * |
92 | dev_priv, | |
6c340eac | 93 | struct drm_file *file_priv, |
b3a83639 | 94 | int id, u32 *data) |
b5e89ed5 DA |
95 | { |
96 | switch (id) { | |
1da177e4 LT |
97 | |
98 | case RADEON_EMIT_PP_MISC: | |
6c340eac | 99 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
d985c108 | 100 | &data[(RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4])) { |
b5e89ed5 | 101 | DRM_ERROR("Invalid depth buffer offset\n"); |
20caafa6 | 102 | return -EINVAL; |
1da177e4 LT |
103 | } |
104 | break; | |
105 | ||
106 | case RADEON_EMIT_PP_CNTL: | |
6c340eac | 107 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
d985c108 | 108 | &data[(RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4])) { |
b5e89ed5 | 109 | DRM_ERROR("Invalid colour buffer offset\n"); |
20caafa6 | 110 | return -EINVAL; |
1da177e4 LT |
111 | } |
112 | break; | |
113 | ||
114 | case R200_EMIT_PP_TXOFFSET_0: | |
115 | case R200_EMIT_PP_TXOFFSET_1: | |
116 | case R200_EMIT_PP_TXOFFSET_2: | |
117 | case R200_EMIT_PP_TXOFFSET_3: | |
118 | case R200_EMIT_PP_TXOFFSET_4: | |
119 | case R200_EMIT_PP_TXOFFSET_5: | |
6c340eac | 120 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
b5e89ed5 DA |
121 | &data[0])) { |
122 | DRM_ERROR("Invalid R200 texture offset\n"); | |
20caafa6 | 123 | return -EINVAL; |
1da177e4 LT |
124 | } |
125 | break; | |
126 | ||
127 | case RADEON_EMIT_PP_TXFILTER_0: | |
128 | case RADEON_EMIT_PP_TXFILTER_1: | |
129 | case RADEON_EMIT_PP_TXFILTER_2: | |
6c340eac | 130 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
d985c108 | 131 | &data[(RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4])) { |
b5e89ed5 | 132 | DRM_ERROR("Invalid R100 texture offset\n"); |
20caafa6 | 133 | return -EINVAL; |
1da177e4 LT |
134 | } |
135 | break; | |
136 | ||
137 | case R200_EMIT_PP_CUBIC_OFFSETS_0: | |
138 | case R200_EMIT_PP_CUBIC_OFFSETS_1: | |
139 | case R200_EMIT_PP_CUBIC_OFFSETS_2: | |
140 | case R200_EMIT_PP_CUBIC_OFFSETS_3: | |
141 | case R200_EMIT_PP_CUBIC_OFFSETS_4: | |
b5e89ed5 DA |
142 | case R200_EMIT_PP_CUBIC_OFFSETS_5:{ |
143 | int i; | |
144 | for (i = 0; i < 5; i++) { | |
d985c108 | 145 | if (radeon_check_and_fixup_offset(dev_priv, |
6c340eac | 146 | file_priv, |
d985c108 | 147 | &data[i])) { |
b5e89ed5 DA |
148 | DRM_ERROR |
149 | ("Invalid R200 cubic texture offset\n"); | |
20caafa6 | 150 | return -EINVAL; |
b5e89ed5 | 151 | } |
1da177e4 | 152 | } |
b5e89ed5 | 153 | break; |
1da177e4 | 154 | } |
1da177e4 LT |
155 | |
156 | case RADEON_EMIT_PP_CUBIC_OFFSETS_T0: | |
157 | case RADEON_EMIT_PP_CUBIC_OFFSETS_T1: | |
158 | case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{ | |
159 | int i; | |
160 | for (i = 0; i < 5; i++) { | |
161 | if (radeon_check_and_fixup_offset(dev_priv, | |
6c340eac | 162 | file_priv, |
1da177e4 LT |
163 | &data[i])) { |
164 | DRM_ERROR | |
165 | ("Invalid R100 cubic texture offset\n"); | |
20caafa6 | 166 | return -EINVAL; |
1da177e4 LT |
167 | } |
168 | } | |
169 | } | |
170 | break; | |
171 | ||
18f2905f RS |
172 | case R200_EMIT_VAP_CTL:{ |
173 | RING_LOCALS; | |
174 | BEGIN_RING(2); | |
175 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); | |
176 | ADVANCE_RING(); | |
177 | } | |
178 | break; | |
179 | ||
1da177e4 LT |
180 | case RADEON_EMIT_RB3D_COLORPITCH: |
181 | case RADEON_EMIT_RE_LINE_PATTERN: | |
182 | case RADEON_EMIT_SE_LINE_WIDTH: | |
183 | case RADEON_EMIT_PP_LUM_MATRIX: | |
184 | case RADEON_EMIT_PP_ROT_MATRIX_0: | |
185 | case RADEON_EMIT_RB3D_STENCILREFMASK: | |
186 | case RADEON_EMIT_SE_VPORT_XSCALE: | |
187 | case RADEON_EMIT_SE_CNTL: | |
188 | case RADEON_EMIT_SE_CNTL_STATUS: | |
189 | case RADEON_EMIT_RE_MISC: | |
190 | case RADEON_EMIT_PP_BORDER_COLOR_0: | |
191 | case RADEON_EMIT_PP_BORDER_COLOR_1: | |
192 | case RADEON_EMIT_PP_BORDER_COLOR_2: | |
193 | case RADEON_EMIT_SE_ZBIAS_FACTOR: | |
194 | case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT: | |
195 | case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED: | |
196 | case R200_EMIT_PP_TXCBLEND_0: | |
197 | case R200_EMIT_PP_TXCBLEND_1: | |
198 | case R200_EMIT_PP_TXCBLEND_2: | |
199 | case R200_EMIT_PP_TXCBLEND_3: | |
200 | case R200_EMIT_PP_TXCBLEND_4: | |
201 | case R200_EMIT_PP_TXCBLEND_5: | |
202 | case R200_EMIT_PP_TXCBLEND_6: | |
203 | case R200_EMIT_PP_TXCBLEND_7: | |
204 | case R200_EMIT_TCL_LIGHT_MODEL_CTL_0: | |
205 | case R200_EMIT_TFACTOR_0: | |
206 | case R200_EMIT_VTX_FMT_0: | |
1da177e4 LT |
207 | case R200_EMIT_MATRIX_SELECT_0: |
208 | case R200_EMIT_TEX_PROC_CTL_2: | |
209 | case R200_EMIT_TCL_UCP_VERT_BLEND_CTL: | |
210 | case R200_EMIT_PP_TXFILTER_0: | |
211 | case R200_EMIT_PP_TXFILTER_1: | |
212 | case R200_EMIT_PP_TXFILTER_2: | |
213 | case R200_EMIT_PP_TXFILTER_3: | |
214 | case R200_EMIT_PP_TXFILTER_4: | |
215 | case R200_EMIT_PP_TXFILTER_5: | |
216 | case R200_EMIT_VTE_CNTL: | |
217 | case R200_EMIT_OUTPUT_VTX_COMP_SEL: | |
218 | case R200_EMIT_PP_TAM_DEBUG3: | |
219 | case R200_EMIT_PP_CNTL_X: | |
220 | case R200_EMIT_RB3D_DEPTHXY_OFFSET: | |
221 | case R200_EMIT_RE_AUX_SCISSOR_CNTL: | |
222 | case R200_EMIT_RE_SCISSOR_TL_0: | |
223 | case R200_EMIT_RE_SCISSOR_TL_1: | |
224 | case R200_EMIT_RE_SCISSOR_TL_2: | |
225 | case R200_EMIT_SE_VAP_CNTL_STATUS: | |
226 | case R200_EMIT_SE_VTX_STATE_CNTL: | |
227 | case R200_EMIT_RE_POINTSIZE: | |
228 | case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0: | |
229 | case R200_EMIT_PP_CUBIC_FACES_0: | |
230 | case R200_EMIT_PP_CUBIC_FACES_1: | |
231 | case R200_EMIT_PP_CUBIC_FACES_2: | |
232 | case R200_EMIT_PP_CUBIC_FACES_3: | |
233 | case R200_EMIT_PP_CUBIC_FACES_4: | |
234 | case R200_EMIT_PP_CUBIC_FACES_5: | |
235 | case RADEON_EMIT_PP_TEX_SIZE_0: | |
236 | case RADEON_EMIT_PP_TEX_SIZE_1: | |
237 | case RADEON_EMIT_PP_TEX_SIZE_2: | |
238 | case R200_EMIT_RB3D_BLENDCOLOR: | |
239 | case R200_EMIT_TCL_POINT_SPRITE_CNTL: | |
240 | case RADEON_EMIT_PP_CUBIC_FACES_0: | |
241 | case RADEON_EMIT_PP_CUBIC_FACES_1: | |
242 | case RADEON_EMIT_PP_CUBIC_FACES_2: | |
243 | case R200_EMIT_PP_TRI_PERF_CNTL: | |
9d17601c DA |
244 | case R200_EMIT_PP_AFS_0: |
245 | case R200_EMIT_PP_AFS_1: | |
246 | case R200_EMIT_ATF_TFACTOR: | |
247 | case R200_EMIT_PP_TXCTLALL_0: | |
248 | case R200_EMIT_PP_TXCTLALL_1: | |
249 | case R200_EMIT_PP_TXCTLALL_2: | |
250 | case R200_EMIT_PP_TXCTLALL_3: | |
251 | case R200_EMIT_PP_TXCTLALL_4: | |
252 | case R200_EMIT_PP_TXCTLALL_5: | |
d6fece05 | 253 | case R200_EMIT_VAP_PVS_CNTL: |
1da177e4 LT |
254 | /* These packets don't contain memory offsets */ |
255 | break; | |
256 | ||
257 | default: | |
b5e89ed5 | 258 | DRM_ERROR("Unknown state packet ID %d\n", id); |
20caafa6 | 259 | return -EINVAL; |
1da177e4 LT |
260 | } |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
b5e89ed5 DA |
265 | static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t * |
266 | dev_priv, | |
6c340eac | 267 | struct drm_file *file_priv, |
d985c108 DA |
268 | drm_radeon_kcmd_buffer_t * |
269 | cmdbuf, | |
b5e89ed5 DA |
270 | unsigned int *cmdsz) |
271 | { | |
1da177e4 | 272 | u32 *cmd = (u32 *) cmdbuf->buf; |
a1aa2897 RS |
273 | u32 offset, narrays; |
274 | int count, i, k; | |
1da177e4 | 275 | |
b5e89ed5 | 276 | *cmdsz = 2 + ((cmd[0] & RADEON_CP_PACKET_COUNT_MASK) >> 16); |
1da177e4 | 277 | |
b5e89ed5 DA |
278 | if ((cmd[0] & 0xc0000000) != RADEON_CP_PACKET3) { |
279 | DRM_ERROR("Not a type 3 packet\n"); | |
20caafa6 | 280 | return -EINVAL; |
1da177e4 LT |
281 | } |
282 | ||
b5e89ed5 DA |
283 | if (4 * *cmdsz > cmdbuf->bufsz) { |
284 | DRM_ERROR("Packet size larger than size of data provided\n"); | |
20caafa6 | 285 | return -EINVAL; |
1da177e4 LT |
286 | } |
287 | ||
a1aa2897 RS |
288 | switch(cmd[0] & 0xff00) { |
289 | /* XXX Are there old drivers needing other packets? */ | |
1da177e4 | 290 | |
a1aa2897 RS |
291 | case RADEON_3D_DRAW_IMMD: |
292 | case RADEON_3D_DRAW_VBUF: | |
293 | case RADEON_3D_DRAW_INDX: | |
294 | case RADEON_WAIT_FOR_IDLE: | |
295 | case RADEON_CP_NOP: | |
296 | case RADEON_3D_CLEAR_ZMASK: | |
297 | /* case RADEON_CP_NEXT_CHAR: | |
298 | case RADEON_CP_PLY_NEXTSCAN: | |
299 | case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */ | |
300 | /* these packets are safe */ | |
301 | break; | |
302 | ||
303 | case RADEON_CP_3D_DRAW_IMMD_2: | |
304 | case RADEON_CP_3D_DRAW_VBUF_2: | |
305 | case RADEON_CP_3D_DRAW_INDX_2: | |
306 | case RADEON_3D_CLEAR_HIZ: | |
307 | /* safe but r200 only */ | |
308 | if (dev_priv->microcode_version != UCODE_R200) { | |
309 | DRM_ERROR("Invalid 3d packet for r100-class chip\n"); | |
20caafa6 | 310 | return -EINVAL; |
a1aa2897 RS |
311 | } |
312 | break; | |
313 | ||
314 | case RADEON_3D_LOAD_VBPNTR: | |
315 | count = (cmd[0] >> 16) & 0x3fff; | |
316 | ||
317 | if (count > 18) { /* 12 arrays max */ | |
318 | DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n", | |
319 | count); | |
20caafa6 | 320 | return -EINVAL; |
a1aa2897 RS |
321 | } |
322 | ||
323 | /* carefully check packet contents */ | |
324 | narrays = cmd[1] & ~0xc000; | |
325 | k = 0; | |
326 | i = 2; | |
327 | while ((k < narrays) && (i < (count + 2))) { | |
328 | i++; /* skip attribute field */ | |
6c340eac EA |
329 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
330 | &cmd[i])) { | |
a1aa2897 RS |
331 | DRM_ERROR |
332 | ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", | |
333 | k, i); | |
20caafa6 | 334 | return -EINVAL; |
a1aa2897 RS |
335 | } |
336 | k++; | |
337 | i++; | |
338 | if (k == narrays) | |
339 | break; | |
340 | /* have one more to process, they come in pairs */ | |
6c340eac EA |
341 | if (radeon_check_and_fixup_offset(dev_priv, |
342 | file_priv, &cmd[i])) | |
343 | { | |
a1aa2897 RS |
344 | DRM_ERROR |
345 | ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n", | |
346 | k, i); | |
20caafa6 | 347 | return -EINVAL; |
a1aa2897 RS |
348 | } |
349 | k++; | |
350 | i++; | |
351 | } | |
352 | /* do the counts match what we expect ? */ | |
353 | if ((k != narrays) || (i != (count + 2))) { | |
354 | DRM_ERROR | |
355 | ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n", | |
356 | k, i, narrays, count + 1); | |
20caafa6 | 357 | return -EINVAL; |
a1aa2897 RS |
358 | } |
359 | break; | |
360 | ||
361 | case RADEON_3D_RNDR_GEN_INDX_PRIM: | |
362 | if (dev_priv->microcode_version != UCODE_R100) { | |
363 | DRM_ERROR("Invalid 3d packet for r200-class chip\n"); | |
20caafa6 | 364 | return -EINVAL; |
a1aa2897 | 365 | } |
6c340eac | 366 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[1])) { |
a1aa2897 | 367 | DRM_ERROR("Invalid rndr_gen_indx offset\n"); |
20caafa6 | 368 | return -EINVAL; |
a1aa2897 RS |
369 | } |
370 | break; | |
371 | ||
372 | case RADEON_CP_INDX_BUFFER: | |
373 | if (dev_priv->microcode_version != UCODE_R200) { | |
374 | DRM_ERROR("Invalid 3d packet for r100-class chip\n"); | |
20caafa6 | 375 | return -EINVAL; |
a1aa2897 RS |
376 | } |
377 | if ((cmd[1] & 0x8000ffff) != 0x80000810) { | |
378 | DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]); | |
20caafa6 | 379 | return -EINVAL; |
a1aa2897 | 380 | } |
6c340eac | 381 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, &cmd[2])) { |
a1aa2897 | 382 | DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]); |
20caafa6 | 383 | return -EINVAL; |
a1aa2897 RS |
384 | } |
385 | break; | |
386 | ||
387 | case RADEON_CNTL_HOSTDATA_BLT: | |
388 | case RADEON_CNTL_PAINT_MULTI: | |
389 | case RADEON_CNTL_BITBLT_MULTI: | |
390 | /* MSB of opcode: next DWORD GUI_CNTL */ | |
b5e89ed5 DA |
391 | if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
392 | | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { | |
1da177e4 | 393 | offset = cmd[2] << 10; |
b5e89ed5 | 394 | if (radeon_check_and_fixup_offset |
6c340eac | 395 | (dev_priv, file_priv, &offset)) { |
b5e89ed5 | 396 | DRM_ERROR("Invalid first packet offset\n"); |
20caafa6 | 397 | return -EINVAL; |
1da177e4 | 398 | } |
b5e89ed5 | 399 | cmd[2] = (cmd[2] & 0xffc00000) | offset >> 10; |
1da177e4 LT |
400 | } |
401 | ||
b5e89ed5 DA |
402 | if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) && |
403 | (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) { | |
1da177e4 | 404 | offset = cmd[3] << 10; |
b5e89ed5 | 405 | if (radeon_check_and_fixup_offset |
6c340eac | 406 | (dev_priv, file_priv, &offset)) { |
b5e89ed5 | 407 | DRM_ERROR("Invalid second packet offset\n"); |
20caafa6 | 408 | return -EINVAL; |
1da177e4 | 409 | } |
b5e89ed5 | 410 | cmd[3] = (cmd[3] & 0xffc00000) | offset >> 10; |
1da177e4 | 411 | } |
a1aa2897 RS |
412 | break; |
413 | ||
414 | default: | |
415 | DRM_ERROR("Invalid packet type %x\n", cmd[0] & 0xff00); | |
20caafa6 | 416 | return -EINVAL; |
1da177e4 LT |
417 | } |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
1da177e4 LT |
422 | /* ================================================================ |
423 | * CP hardware state programming functions | |
424 | */ | |
425 | ||
b5e89ed5 | 426 | static __inline__ void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv, |
c60ce623 | 427 | struct drm_clip_rect * box) |
1da177e4 LT |
428 | { |
429 | RING_LOCALS; | |
430 | ||
b5e89ed5 DA |
431 | DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n", |
432 | box->x1, box->y1, box->x2, box->y2); | |
1da177e4 | 433 | |
b5e89ed5 DA |
434 | BEGIN_RING(4); |
435 | OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); | |
436 | OUT_RING((box->y1 << 16) | box->x1); | |
437 | OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); | |
438 | OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1)); | |
1da177e4 LT |
439 | ADVANCE_RING(); |
440 | } | |
441 | ||
442 | /* Emit 1.1 state | |
443 | */ | |
b5e89ed5 | 444 | static int radeon_emit_state(drm_radeon_private_t * dev_priv, |
6c340eac | 445 | struct drm_file *file_priv, |
b5e89ed5 DA |
446 | drm_radeon_context_regs_t * ctx, |
447 | drm_radeon_texture_regs_t * tex, | |
448 | unsigned int dirty) | |
1da177e4 LT |
449 | { |
450 | RING_LOCALS; | |
b5e89ed5 | 451 | DRM_DEBUG("dirty=0x%08x\n", dirty); |
1da177e4 | 452 | |
b5e89ed5 | 453 | if (dirty & RADEON_UPLOAD_CONTEXT) { |
6c340eac | 454 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
b5e89ed5 DA |
455 | &ctx->rb3d_depthoffset)) { |
456 | DRM_ERROR("Invalid depth buffer offset\n"); | |
20caafa6 | 457 | return -EINVAL; |
1da177e4 LT |
458 | } |
459 | ||
6c340eac | 460 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
b5e89ed5 DA |
461 | &ctx->rb3d_coloroffset)) { |
462 | DRM_ERROR("Invalid depth buffer offset\n"); | |
20caafa6 | 463 | return -EINVAL; |
1da177e4 LT |
464 | } |
465 | ||
b5e89ed5 DA |
466 | BEGIN_RING(14); |
467 | OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6)); | |
468 | OUT_RING(ctx->pp_misc); | |
469 | OUT_RING(ctx->pp_fog_color); | |
470 | OUT_RING(ctx->re_solid_color); | |
471 | OUT_RING(ctx->rb3d_blendcntl); | |
472 | OUT_RING(ctx->rb3d_depthoffset); | |
473 | OUT_RING(ctx->rb3d_depthpitch); | |
474 | OUT_RING(ctx->rb3d_zstencilcntl); | |
475 | OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2)); | |
476 | OUT_RING(ctx->pp_cntl); | |
477 | OUT_RING(ctx->rb3d_cntl); | |
478 | OUT_RING(ctx->rb3d_coloroffset); | |
479 | OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0)); | |
480 | OUT_RING(ctx->rb3d_colorpitch); | |
1da177e4 LT |
481 | ADVANCE_RING(); |
482 | } | |
483 | ||
b5e89ed5 DA |
484 | if (dirty & RADEON_UPLOAD_VERTFMT) { |
485 | BEGIN_RING(2); | |
486 | OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0)); | |
487 | OUT_RING(ctx->se_coord_fmt); | |
1da177e4 LT |
488 | ADVANCE_RING(); |
489 | } | |
490 | ||
b5e89ed5 DA |
491 | if (dirty & RADEON_UPLOAD_LINE) { |
492 | BEGIN_RING(5); | |
493 | OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1)); | |
494 | OUT_RING(ctx->re_line_pattern); | |
495 | OUT_RING(ctx->re_line_state); | |
496 | OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0)); | |
497 | OUT_RING(ctx->se_line_width); | |
1da177e4 LT |
498 | ADVANCE_RING(); |
499 | } | |
500 | ||
b5e89ed5 DA |
501 | if (dirty & RADEON_UPLOAD_BUMPMAP) { |
502 | BEGIN_RING(5); | |
503 | OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0)); | |
504 | OUT_RING(ctx->pp_lum_matrix); | |
505 | OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1)); | |
506 | OUT_RING(ctx->pp_rot_matrix_0); | |
507 | OUT_RING(ctx->pp_rot_matrix_1); | |
1da177e4 LT |
508 | ADVANCE_RING(); |
509 | } | |
510 | ||
b5e89ed5 DA |
511 | if (dirty & RADEON_UPLOAD_MASKS) { |
512 | BEGIN_RING(4); | |
513 | OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2)); | |
514 | OUT_RING(ctx->rb3d_stencilrefmask); | |
515 | OUT_RING(ctx->rb3d_ropcntl); | |
516 | OUT_RING(ctx->rb3d_planemask); | |
1da177e4 LT |
517 | ADVANCE_RING(); |
518 | } | |
519 | ||
b5e89ed5 DA |
520 | if (dirty & RADEON_UPLOAD_VIEWPORT) { |
521 | BEGIN_RING(7); | |
522 | OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5)); | |
523 | OUT_RING(ctx->se_vport_xscale); | |
524 | OUT_RING(ctx->se_vport_xoffset); | |
525 | OUT_RING(ctx->se_vport_yscale); | |
526 | OUT_RING(ctx->se_vport_yoffset); | |
527 | OUT_RING(ctx->se_vport_zscale); | |
528 | OUT_RING(ctx->se_vport_zoffset); | |
1da177e4 LT |
529 | ADVANCE_RING(); |
530 | } | |
531 | ||
b5e89ed5 DA |
532 | if (dirty & RADEON_UPLOAD_SETUP) { |
533 | BEGIN_RING(4); | |
534 | OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0)); | |
535 | OUT_RING(ctx->se_cntl); | |
536 | OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0)); | |
537 | OUT_RING(ctx->se_cntl_status); | |
1da177e4 LT |
538 | ADVANCE_RING(); |
539 | } | |
540 | ||
b5e89ed5 DA |
541 | if (dirty & RADEON_UPLOAD_MISC) { |
542 | BEGIN_RING(2); | |
543 | OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0)); | |
544 | OUT_RING(ctx->re_misc); | |
1da177e4 LT |
545 | ADVANCE_RING(); |
546 | } | |
547 | ||
b5e89ed5 | 548 | if (dirty & RADEON_UPLOAD_TEX0) { |
6c340eac | 549 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
b5e89ed5 DA |
550 | &tex[0].pp_txoffset)) { |
551 | DRM_ERROR("Invalid texture offset for unit 0\n"); | |
20caafa6 | 552 | return -EINVAL; |
1da177e4 LT |
553 | } |
554 | ||
b5e89ed5 DA |
555 | BEGIN_RING(9); |
556 | OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5)); | |
557 | OUT_RING(tex[0].pp_txfilter); | |
558 | OUT_RING(tex[0].pp_txformat); | |
559 | OUT_RING(tex[0].pp_txoffset); | |
560 | OUT_RING(tex[0].pp_txcblend); | |
561 | OUT_RING(tex[0].pp_txablend); | |
562 | OUT_RING(tex[0].pp_tfactor); | |
563 | OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0)); | |
564 | OUT_RING(tex[0].pp_border_color); | |
1da177e4 LT |
565 | ADVANCE_RING(); |
566 | } | |
567 | ||
b5e89ed5 | 568 | if (dirty & RADEON_UPLOAD_TEX1) { |
6c340eac | 569 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
b5e89ed5 DA |
570 | &tex[1].pp_txoffset)) { |
571 | DRM_ERROR("Invalid texture offset for unit 1\n"); | |
20caafa6 | 572 | return -EINVAL; |
1da177e4 LT |
573 | } |
574 | ||
b5e89ed5 DA |
575 | BEGIN_RING(9); |
576 | OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5)); | |
577 | OUT_RING(tex[1].pp_txfilter); | |
578 | OUT_RING(tex[1].pp_txformat); | |
579 | OUT_RING(tex[1].pp_txoffset); | |
580 | OUT_RING(tex[1].pp_txcblend); | |
581 | OUT_RING(tex[1].pp_txablend); | |
582 | OUT_RING(tex[1].pp_tfactor); | |
583 | OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0)); | |
584 | OUT_RING(tex[1].pp_border_color); | |
1da177e4 LT |
585 | ADVANCE_RING(); |
586 | } | |
587 | ||
b5e89ed5 | 588 | if (dirty & RADEON_UPLOAD_TEX2) { |
6c340eac | 589 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, |
b5e89ed5 DA |
590 | &tex[2].pp_txoffset)) { |
591 | DRM_ERROR("Invalid texture offset for unit 2\n"); | |
20caafa6 | 592 | return -EINVAL; |
1da177e4 LT |
593 | } |
594 | ||
b5e89ed5 DA |
595 | BEGIN_RING(9); |
596 | OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5)); | |
597 | OUT_RING(tex[2].pp_txfilter); | |
598 | OUT_RING(tex[2].pp_txformat); | |
599 | OUT_RING(tex[2].pp_txoffset); | |
600 | OUT_RING(tex[2].pp_txcblend); | |
601 | OUT_RING(tex[2].pp_txablend); | |
602 | OUT_RING(tex[2].pp_tfactor); | |
603 | OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0)); | |
604 | OUT_RING(tex[2].pp_border_color); | |
1da177e4 LT |
605 | ADVANCE_RING(); |
606 | } | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | /* Emit 1.2 state | |
612 | */ | |
b5e89ed5 | 613 | static int radeon_emit_state2(drm_radeon_private_t * dev_priv, |
6c340eac | 614 | struct drm_file *file_priv, |
b5e89ed5 | 615 | drm_radeon_state_t * state) |
1da177e4 LT |
616 | { |
617 | RING_LOCALS; | |
618 | ||
619 | if (state->dirty & RADEON_UPLOAD_ZBIAS) { | |
b5e89ed5 DA |
620 | BEGIN_RING(3); |
621 | OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1)); | |
622 | OUT_RING(state->context2.se_zbias_factor); | |
623 | OUT_RING(state->context2.se_zbias_constant); | |
1da177e4 LT |
624 | ADVANCE_RING(); |
625 | } | |
626 | ||
6c340eac | 627 | return radeon_emit_state(dev_priv, file_priv, &state->context, |
b5e89ed5 | 628 | state->tex, state->dirty); |
1da177e4 LT |
629 | } |
630 | ||
631 | /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in | |
632 | * 1.3 cmdbuffers allow all previous state to be updated as well as | |
b5e89ed5 | 633 | * the tcl scalar and vector areas. |
1da177e4 | 634 | */ |
b5e89ed5 DA |
635 | static struct { |
636 | int start; | |
637 | int len; | |
1da177e4 LT |
638 | const char *name; |
639 | } packet[RADEON_MAX_STATE_PACKETS] = { | |
b5e89ed5 DA |
640 | {RADEON_PP_MISC, 7, "RADEON_PP_MISC"}, |
641 | {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"}, | |
642 | {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"}, | |
643 | {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"}, | |
644 | {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"}, | |
645 | {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"}, | |
646 | {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"}, | |
647 | {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"}, | |
648 | {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"}, | |
649 | {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"}, | |
650 | {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"}, | |
651 | {RADEON_RE_MISC, 1, "RADEON_RE_MISC"}, | |
652 | {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"}, | |
653 | {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"}, | |
654 | {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"}, | |
655 | {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"}, | |
656 | {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"}, | |
657 | {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"}, | |
658 | {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"}, | |
659 | {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"}, | |
660 | {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17, | |
661 | "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"}, | |
662 | {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"}, | |
663 | {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"}, | |
664 | {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"}, | |
665 | {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"}, | |
666 | {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"}, | |
667 | {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"}, | |
668 | {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"}, | |
669 | {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"}, | |
670 | {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"}, | |
671 | {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"}, | |
672 | {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"}, | |
673 | {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"}, | |
674 | {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"}, | |
675 | {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"}, | |
676 | {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"}, | |
677 | {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"}, | |
678 | {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"}, | |
679 | {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"}, | |
680 | {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"}, | |
681 | {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"}, | |
682 | {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"}, | |
683 | {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"}, | |
684 | {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"}, | |
685 | {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"}, | |
686 | {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"}, | |
687 | {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"}, | |
688 | {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"}, | |
689 | {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"}, | |
d985c108 DA |
690 | {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, |
691 | "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"}, | |
b5e89ed5 DA |
692 | {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"}, |
693 | {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"}, | |
694 | {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"}, | |
695 | {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"}, | |
696 | {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"}, | |
697 | {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"}, | |
698 | {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"}, | |
699 | {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"}, | |
700 | {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"}, | |
701 | {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"}, | |
702 | {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, | |
703 | "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"}, | |
704 | {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */ | |
d985c108 | 705 | {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */ |
b5e89ed5 DA |
706 | {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"}, |
707 | {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"}, | |
708 | {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"}, | |
709 | {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"}, | |
710 | {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"}, | |
711 | {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"}, | |
712 | {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"}, | |
713 | {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"}, | |
714 | {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"}, | |
715 | {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"}, | |
716 | {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"}, | |
717 | {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"}, | |
718 | {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, | |
719 | {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, | |
720 | {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"}, | |
721 | {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, | |
722 | {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, | |
723 | {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, | |
724 | {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, | |
725 | {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, | |
726 | {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"}, | |
727 | {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"}, | |
d985c108 | 728 | {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */ |
b5e89ed5 DA |
729 | {R200_PP_AFS_1, 32, "R200_PP_AFS_1"}, |
730 | {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"}, | |
731 | {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"}, | |
732 | {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"}, | |
733 | {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"}, | |
734 | {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, | |
735 | {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, | |
736 | {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, | |
d6fece05 | 737 | {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, |
1da177e4 LT |
738 | }; |
739 | ||
1da177e4 LT |
740 | /* ================================================================ |
741 | * Performance monitoring functions | |
742 | */ | |
743 | ||
b5e89ed5 DA |
744 | static void radeon_clear_box(drm_radeon_private_t * dev_priv, |
745 | int x, int y, int w, int h, int r, int g, int b) | |
1da177e4 LT |
746 | { |
747 | u32 color; | |
748 | RING_LOCALS; | |
749 | ||
750 | x += dev_priv->sarea_priv->boxes[0].x1; | |
751 | y += dev_priv->sarea_priv->boxes[0].y1; | |
752 | ||
b5e89ed5 | 753 | switch (dev_priv->color_fmt) { |
1da177e4 LT |
754 | case RADEON_COLOR_FORMAT_RGB565: |
755 | color = (((r & 0xf8) << 8) | | |
b5e89ed5 | 756 | ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); |
1da177e4 LT |
757 | break; |
758 | case RADEON_COLOR_FORMAT_ARGB8888: | |
759 | default: | |
b5e89ed5 | 760 | color = (((0xff) << 24) | (r << 16) | (g << 8) | b); |
1da177e4 LT |
761 | break; |
762 | } | |
763 | ||
b5e89ed5 DA |
764 | BEGIN_RING(4); |
765 | RADEON_WAIT_UNTIL_3D_IDLE(); | |
766 | OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); | |
767 | OUT_RING(0xffffffff); | |
1da177e4 LT |
768 | ADVANCE_RING(); |
769 | ||
b5e89ed5 | 770 | BEGIN_RING(6); |
1da177e4 | 771 | |
b5e89ed5 DA |
772 | OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
773 | OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
774 | RADEON_GMC_BRUSH_SOLID_COLOR | | |
775 | (dev_priv->color_fmt << 8) | | |
776 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
777 | RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS); | |
1da177e4 | 778 | |
453ff94c | 779 | if (dev_priv->sarea_priv->pfCurrentPage == 1) { |
b5e89ed5 DA |
780 | OUT_RING(dev_priv->front_pitch_offset); |
781 | } else { | |
782 | OUT_RING(dev_priv->back_pitch_offset); | |
783 | } | |
1da177e4 | 784 | |
b5e89ed5 | 785 | OUT_RING(color); |
1da177e4 | 786 | |
b5e89ed5 DA |
787 | OUT_RING((x << 16) | y); |
788 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
789 | |
790 | ADVANCE_RING(); | |
791 | } | |
792 | ||
b5e89ed5 | 793 | static void radeon_cp_performance_boxes(drm_radeon_private_t * dev_priv) |
1da177e4 LT |
794 | { |
795 | /* Collapse various things into a wait flag -- trying to | |
796 | * guess if userspase slept -- better just to have them tell us. | |
797 | */ | |
798 | if (dev_priv->stats.last_frame_reads > 1 || | |
799 | dev_priv->stats.last_clear_reads > dev_priv->stats.clears) { | |
800 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
801 | } | |
802 | ||
803 | if (dev_priv->stats.freelist_loops) { | |
804 | dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; | |
805 | } | |
806 | ||
807 | /* Purple box for page flipping | |
808 | */ | |
b5e89ed5 DA |
809 | if (dev_priv->stats.boxes & RADEON_BOX_FLIP) |
810 | radeon_clear_box(dev_priv, 4, 4, 8, 8, 255, 0, 255); | |
1da177e4 LT |
811 | |
812 | /* Red box if we have to wait for idle at any point | |
813 | */ | |
b5e89ed5 DA |
814 | if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE) |
815 | radeon_clear_box(dev_priv, 16, 4, 8, 8, 255, 0, 0); | |
1da177e4 LT |
816 | |
817 | /* Blue box: lost context? | |
818 | */ | |
819 | ||
820 | /* Yellow box for texture swaps | |
821 | */ | |
b5e89ed5 DA |
822 | if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD) |
823 | radeon_clear_box(dev_priv, 40, 4, 8, 8, 255, 255, 0); | |
1da177e4 LT |
824 | |
825 | /* Green box if hardware never idles (as far as we can tell) | |
826 | */ | |
b5e89ed5 DA |
827 | if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) |
828 | radeon_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); | |
1da177e4 | 829 | |
b5e89ed5 | 830 | /* Draw bars indicating number of buffers allocated |
1da177e4 LT |
831 | * (not a great measure, easily confused) |
832 | */ | |
833 | if (dev_priv->stats.requested_bufs) { | |
834 | if (dev_priv->stats.requested_bufs > 100) | |
835 | dev_priv->stats.requested_bufs = 100; | |
836 | ||
b5e89ed5 DA |
837 | radeon_clear_box(dev_priv, 4, 16, |
838 | dev_priv->stats.requested_bufs, 4, | |
839 | 196, 128, 128); | |
1da177e4 LT |
840 | } |
841 | ||
b5e89ed5 | 842 | memset(&dev_priv->stats, 0, sizeof(dev_priv->stats)); |
1da177e4 LT |
843 | |
844 | } | |
b5e89ed5 | 845 | |
1da177e4 LT |
846 | /* ================================================================ |
847 | * CP command dispatch functions | |
848 | */ | |
849 | ||
84b1fd10 | 850 | static void radeon_cp_dispatch_clear(struct drm_device * dev, |
b5e89ed5 DA |
851 | drm_radeon_clear_t * clear, |
852 | drm_radeon_clear_rect_t * depth_boxes) | |
1da177e4 LT |
853 | { |
854 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
855 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
856 | drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear; | |
857 | int nbox = sarea_priv->nbox; | |
c60ce623 | 858 | struct drm_clip_rect *pbox = sarea_priv->boxes; |
1da177e4 | 859 | unsigned int flags = clear->flags; |
b5e89ed5 | 860 | u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0; |
1da177e4 LT |
861 | int i; |
862 | RING_LOCALS; | |
b5e89ed5 | 863 | DRM_DEBUG("flags = 0x%x\n", flags); |
1da177e4 LT |
864 | |
865 | dev_priv->stats.clears++; | |
866 | ||
453ff94c | 867 | if (dev_priv->sarea_priv->pfCurrentPage == 1) { |
1da177e4 LT |
868 | unsigned int tmp = flags; |
869 | ||
870 | flags &= ~(RADEON_FRONT | RADEON_BACK); | |
b5e89ed5 DA |
871 | if (tmp & RADEON_FRONT) |
872 | flags |= RADEON_BACK; | |
873 | if (tmp & RADEON_BACK) | |
874 | flags |= RADEON_FRONT; | |
1da177e4 LT |
875 | } |
876 | ||
b5e89ed5 | 877 | if (flags & (RADEON_FRONT | RADEON_BACK)) { |
1da177e4 | 878 | |
b5e89ed5 | 879 | BEGIN_RING(4); |
1da177e4 LT |
880 | |
881 | /* Ensure the 3D stream is idle before doing a | |
882 | * 2D fill to clear the front or back buffer. | |
883 | */ | |
884 | RADEON_WAIT_UNTIL_3D_IDLE(); | |
b5e89ed5 DA |
885 | |
886 | OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0)); | |
887 | OUT_RING(clear->color_mask); | |
1da177e4 LT |
888 | |
889 | ADVANCE_RING(); | |
890 | ||
891 | /* Make sure we restore the 3D state next time. | |
892 | */ | |
893 | dev_priv->sarea_priv->ctx_owner = 0; | |
894 | ||
b5e89ed5 | 895 | for (i = 0; i < nbox; i++) { |
1da177e4 LT |
896 | int x = pbox[i].x1; |
897 | int y = pbox[i].y1; | |
898 | int w = pbox[i].x2 - x; | |
899 | int h = pbox[i].y2 - y; | |
900 | ||
3e684eae | 901 | DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n", |
b5e89ed5 DA |
902 | x, y, w, h, flags); |
903 | ||
904 | if (flags & RADEON_FRONT) { | |
905 | BEGIN_RING(6); | |
906 | ||
907 | OUT_RING(CP_PACKET3 | |
908 | (RADEON_CNTL_PAINT_MULTI, 4)); | |
909 | OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
910 | RADEON_GMC_BRUSH_SOLID_COLOR | | |
911 | (dev_priv-> | |
912 | color_fmt << 8) | | |
913 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
914 | RADEON_ROP3_P | | |
915 | RADEON_GMC_CLR_CMP_CNTL_DIS); | |
916 | ||
917 | OUT_RING(dev_priv->front_pitch_offset); | |
918 | OUT_RING(clear->clear_color); | |
919 | ||
920 | OUT_RING((x << 16) | y); | |
921 | OUT_RING((w << 16) | h); | |
922 | ||
1da177e4 LT |
923 | ADVANCE_RING(); |
924 | } | |
b5e89ed5 DA |
925 | |
926 | if (flags & RADEON_BACK) { | |
927 | BEGIN_RING(6); | |
928 | ||
929 | OUT_RING(CP_PACKET3 | |
930 | (RADEON_CNTL_PAINT_MULTI, 4)); | |
931 | OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
932 | RADEON_GMC_BRUSH_SOLID_COLOR | | |
933 | (dev_priv-> | |
934 | color_fmt << 8) | | |
935 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
936 | RADEON_ROP3_P | | |
937 | RADEON_GMC_CLR_CMP_CNTL_DIS); | |
938 | ||
939 | OUT_RING(dev_priv->back_pitch_offset); | |
940 | OUT_RING(clear->clear_color); | |
941 | ||
942 | OUT_RING((x << 16) | y); | |
943 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
944 | |
945 | ADVANCE_RING(); | |
946 | } | |
947 | } | |
948 | } | |
b5e89ed5 | 949 | |
1da177e4 LT |
950 | /* hyper z clear */ |
951 | /* no docs available, based on reverse engeneering by Stephane Marchesin */ | |
b5e89ed5 DA |
952 | if ((flags & (RADEON_DEPTH | RADEON_STENCIL)) |
953 | && (flags & RADEON_CLEAR_FASTZ)) { | |
1da177e4 LT |
954 | |
955 | int i; | |
b5e89ed5 DA |
956 | int depthpixperline = |
957 | dev_priv->depth_fmt == | |
958 | RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch / | |
959 | 2) : (dev_priv-> | |
960 | depth_pitch / 4); | |
961 | ||
1da177e4 LT |
962 | u32 clearmask; |
963 | ||
964 | u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth | | |
b5e89ed5 DA |
965 | ((clear->depth_mask & 0xff) << 24); |
966 | ||
1da177e4 LT |
967 | /* Make sure we restore the 3D state next time. |
968 | * we haven't touched any "normal" state - still need this? | |
969 | */ | |
970 | dev_priv->sarea_priv->ctx_owner = 0; | |
971 | ||
54a56ac5 | 972 | if ((dev_priv->flags & RADEON_HAS_HIERZ) |
b5e89ed5 DA |
973 | && (flags & RADEON_USE_HIERZ)) { |
974 | /* FIXME : reverse engineer that for Rx00 cards */ | |
975 | /* FIXME : the mask supposedly contains low-res z values. So can't set | |
976 | just to the max (0xff? or actually 0x3fff?), need to take z clear | |
977 | value into account? */ | |
978 | /* pattern seems to work for r100, though get slight | |
979 | rendering errors with glxgears. If hierz is not enabled for r100, | |
980 | only 4 bits which indicate clear (15,16,31,32, all zero) matter, the | |
981 | other ones are ignored, and the same clear mask can be used. That's | |
982 | very different behaviour than R200 which needs different clear mask | |
983 | and different number of tiles to clear if hierz is enabled or not !?! | |
984 | */ | |
985 | clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f; | |
986 | } else { | |
987 | /* clear mask : chooses the clearing pattern. | |
988 | rv250: could be used to clear only parts of macrotiles | |
989 | (but that would get really complicated...)? | |
990 | bit 0 and 1 (either or both of them ?!?!) are used to | |
991 | not clear tile (or maybe one of the bits indicates if the tile is | |
992 | compressed or not), bit 2 and 3 to not clear tile 1,...,. | |
993 | Pattern is as follows: | |
994 | | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29| | |
995 | bits ------------------------------------------------- | |
996 | | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31| | |
997 | rv100: clearmask covers 2x8 4x1 tiles, but one clear still | |
998 | covers 256 pixels ?!? | |
999 | */ | |
1da177e4 LT |
1000 | clearmask = 0x0; |
1001 | } | |
1002 | ||
b5e89ed5 | 1003 | BEGIN_RING(8); |
1da177e4 | 1004 | RADEON_WAIT_UNTIL_2D_IDLE(); |
b5e89ed5 DA |
1005 | OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE, |
1006 | tempRB3D_DEPTHCLEARVALUE); | |
1da177e4 | 1007 | /* what offset is this exactly ? */ |
b5e89ed5 | 1008 | OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0); |
1da177e4 | 1009 | /* need ctlstat, otherwise get some strange black flickering */ |
b5e89ed5 DA |
1010 | OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT, |
1011 | RADEON_RB3D_ZC_FLUSH_ALL); | |
1da177e4 LT |
1012 | ADVANCE_RING(); |
1013 | ||
1014 | for (i = 0; i < nbox; i++) { | |
1015 | int tileoffset, nrtilesx, nrtilesy, j; | |
1016 | /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */ | |
54a56ac5 | 1017 | if ((dev_priv->flags & RADEON_HAS_HIERZ) |
b5e89ed5 | 1018 | && !(dev_priv->microcode_version == UCODE_R200)) { |
1da177e4 LT |
1019 | /* FIXME : figure this out for r200 (when hierz is enabled). Or |
1020 | maybe r200 actually doesn't need to put the low-res z value into | |
1021 | the tile cache like r100, but just needs to clear the hi-level z-buffer? | |
1022 | Works for R100, both with hierz and without. | |
1023 | R100 seems to operate on 2x1 8x8 tiles, but... | |
1024 | odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially | |
1025 | problematic with resolutions which are not 64 pix aligned? */ | |
b5e89ed5 DA |
1026 | tileoffset = |
1027 | ((pbox[i].y1 >> 3) * depthpixperline + | |
1028 | pbox[i].x1) >> 6; | |
1029 | nrtilesx = | |
1030 | ((pbox[i].x2 & ~63) - | |
1031 | (pbox[i].x1 & ~63)) >> 4; | |
1032 | nrtilesy = | |
1033 | (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); | |
1da177e4 | 1034 | for (j = 0; j <= nrtilesy; j++) { |
b5e89ed5 DA |
1035 | BEGIN_RING(4); |
1036 | OUT_RING(CP_PACKET3 | |
1037 | (RADEON_3D_CLEAR_ZMASK, 2)); | |
1da177e4 | 1038 | /* first tile */ |
b5e89ed5 | 1039 | OUT_RING(tileoffset * 8); |
1da177e4 | 1040 | /* the number of tiles to clear */ |
b5e89ed5 | 1041 | OUT_RING(nrtilesx + 4); |
1da177e4 | 1042 | /* clear mask : chooses the clearing pattern. */ |
b5e89ed5 | 1043 | OUT_RING(clearmask); |
1da177e4 LT |
1044 | ADVANCE_RING(); |
1045 | tileoffset += depthpixperline >> 6; | |
1046 | } | |
b5e89ed5 | 1047 | } else if (dev_priv->microcode_version == UCODE_R200) { |
1da177e4 LT |
1048 | /* works for rv250. */ |
1049 | /* find first macro tile (8x2 4x4 z-pixels on rv250) */ | |
b5e89ed5 DA |
1050 | tileoffset = |
1051 | ((pbox[i].y1 >> 3) * depthpixperline + | |
1052 | pbox[i].x1) >> 5; | |
1053 | nrtilesx = | |
1054 | (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5); | |
1055 | nrtilesy = | |
1056 | (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3); | |
1da177e4 | 1057 | for (j = 0; j <= nrtilesy; j++) { |
b5e89ed5 DA |
1058 | BEGIN_RING(4); |
1059 | OUT_RING(CP_PACKET3 | |
1060 | (RADEON_3D_CLEAR_ZMASK, 2)); | |
1da177e4 LT |
1061 | /* first tile */ |
1062 | /* judging by the first tile offset needed, could possibly | |
1063 | directly address/clear 4x4 tiles instead of 8x2 * 4x4 | |
1064 | macro tiles, though would still need clear mask for | |
1065 | right/bottom if truely 4x4 granularity is desired ? */ | |
b5e89ed5 | 1066 | OUT_RING(tileoffset * 16); |
1da177e4 | 1067 | /* the number of tiles to clear */ |
b5e89ed5 | 1068 | OUT_RING(nrtilesx + 1); |
1da177e4 | 1069 | /* clear mask : chooses the clearing pattern. */ |
b5e89ed5 | 1070 | OUT_RING(clearmask); |
1da177e4 LT |
1071 | ADVANCE_RING(); |
1072 | tileoffset += depthpixperline >> 5; | |
1073 | } | |
b5e89ed5 | 1074 | } else { /* rv 100 */ |
1da177e4 LT |
1075 | /* rv100 might not need 64 pix alignment, who knows */ |
1076 | /* offsets are, hmm, weird */ | |
b5e89ed5 DA |
1077 | tileoffset = |
1078 | ((pbox[i].y1 >> 4) * depthpixperline + | |
1079 | pbox[i].x1) >> 6; | |
1080 | nrtilesx = | |
1081 | ((pbox[i].x2 & ~63) - | |
1082 | (pbox[i].x1 & ~63)) >> 4; | |
1083 | nrtilesy = | |
1084 | (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4); | |
1da177e4 | 1085 | for (j = 0; j <= nrtilesy; j++) { |
b5e89ed5 DA |
1086 | BEGIN_RING(4); |
1087 | OUT_RING(CP_PACKET3 | |
1088 | (RADEON_3D_CLEAR_ZMASK, 2)); | |
1089 | OUT_RING(tileoffset * 128); | |
1da177e4 | 1090 | /* the number of tiles to clear */ |
b5e89ed5 | 1091 | OUT_RING(nrtilesx + 4); |
1da177e4 | 1092 | /* clear mask : chooses the clearing pattern. */ |
b5e89ed5 | 1093 | OUT_RING(clearmask); |
1da177e4 LT |
1094 | ADVANCE_RING(); |
1095 | tileoffset += depthpixperline >> 6; | |
1096 | } | |
1097 | } | |
1098 | } | |
1099 | ||
1100 | /* TODO don't always clear all hi-level z tiles */ | |
54a56ac5 | 1101 | if ((dev_priv->flags & RADEON_HAS_HIERZ) |
b5e89ed5 DA |
1102 | && (dev_priv->microcode_version == UCODE_R200) |
1103 | && (flags & RADEON_USE_HIERZ)) | |
1104 | /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */ | |
1105 | /* FIXME : the mask supposedly contains low-res z values. So can't set | |
1106 | just to the max (0xff? or actually 0x3fff?), need to take z clear | |
1107 | value into account? */ | |
1da177e4 | 1108 | { |
b5e89ed5 DA |
1109 | BEGIN_RING(4); |
1110 | OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2)); | |
1111 | OUT_RING(0x0); /* First tile */ | |
1112 | OUT_RING(0x3cc0); | |
1113 | OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f); | |
1da177e4 LT |
1114 | ADVANCE_RING(); |
1115 | } | |
1116 | } | |
1117 | ||
1118 | /* We have to clear the depth and/or stencil buffers by | |
1119 | * rendering a quad into just those buffers. Thus, we have to | |
1120 | * make sure the 3D engine is configured correctly. | |
1121 | */ | |
d985c108 DA |
1122 | else if ((dev_priv->microcode_version == UCODE_R200) && |
1123 | (flags & (RADEON_DEPTH | RADEON_STENCIL))) { | |
1da177e4 LT |
1124 | |
1125 | int tempPP_CNTL; | |
1126 | int tempRE_CNTL; | |
1127 | int tempRB3D_CNTL; | |
1128 | int tempRB3D_ZSTENCILCNTL; | |
1129 | int tempRB3D_STENCILREFMASK; | |
1130 | int tempRB3D_PLANEMASK; | |
1131 | int tempSE_CNTL; | |
1132 | int tempSE_VTE_CNTL; | |
1133 | int tempSE_VTX_FMT_0; | |
1134 | int tempSE_VTX_FMT_1; | |
1135 | int tempSE_VAP_CNTL; | |
1136 | int tempRE_AUX_SCISSOR_CNTL; | |
1137 | ||
1138 | tempPP_CNTL = 0; | |
1139 | tempRE_CNTL = 0; | |
1140 | ||
1141 | tempRB3D_CNTL = depth_clear->rb3d_cntl; | |
1142 | ||
1143 | tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; | |
1144 | tempRB3D_STENCILREFMASK = 0x0; | |
1145 | ||
1146 | tempSE_CNTL = depth_clear->se_cntl; | |
1147 | ||
1da177e4 LT |
1148 | /* Disable TCL */ |
1149 | ||
b5e89ed5 DA |
1150 | tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */ |
1151 | (0x9 << | |
1152 | SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT)); | |
1da177e4 LT |
1153 | |
1154 | tempRB3D_PLANEMASK = 0x0; | |
1155 | ||
1156 | tempRE_AUX_SCISSOR_CNTL = 0x0; | |
1157 | ||
1158 | tempSE_VTE_CNTL = | |
b5e89ed5 | 1159 | SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK; |
1da177e4 | 1160 | |
b5e89ed5 | 1161 | /* Vertex format (X, Y, Z, W) */ |
1da177e4 | 1162 | tempSE_VTX_FMT_0 = |
b5e89ed5 DA |
1163 | SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK | |
1164 | SE_VTX_FMT_0__VTX_W0_PRESENT_MASK; | |
1da177e4 LT |
1165 | tempSE_VTX_FMT_1 = 0x0; |
1166 | ||
b5e89ed5 DA |
1167 | /* |
1168 | * Depth buffer specific enables | |
1da177e4 LT |
1169 | */ |
1170 | if (flags & RADEON_DEPTH) { | |
1171 | /* Enable depth buffer */ | |
1172 | tempRB3D_CNTL |= RADEON_Z_ENABLE; | |
1173 | } else { | |
1174 | /* Disable depth buffer */ | |
1175 | tempRB3D_CNTL &= ~RADEON_Z_ENABLE; | |
1176 | } | |
1177 | ||
b5e89ed5 | 1178 | /* |
1da177e4 LT |
1179 | * Stencil buffer specific enables |
1180 | */ | |
b5e89ed5 DA |
1181 | if (flags & RADEON_STENCIL) { |
1182 | tempRB3D_CNTL |= RADEON_STENCIL_ENABLE; | |
1183 | tempRB3D_STENCILREFMASK = clear->depth_mask; | |
1da177e4 LT |
1184 | } else { |
1185 | tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE; | |
1186 | tempRB3D_STENCILREFMASK = 0x00000000; | |
1187 | } | |
1188 | ||
1189 | if (flags & RADEON_USE_COMP_ZBUF) { | |
1190 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | | |
b5e89ed5 | 1191 | RADEON_Z_DECOMPRESSION_ENABLE; |
1da177e4 LT |
1192 | } |
1193 | if (flags & RADEON_USE_HIERZ) { | |
1194 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; | |
1195 | } | |
1196 | ||
b5e89ed5 | 1197 | BEGIN_RING(26); |
1da177e4 LT |
1198 | RADEON_WAIT_UNTIL_2D_IDLE(); |
1199 | ||
b5e89ed5 DA |
1200 | OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL); |
1201 | OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL); | |
1202 | OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL); | |
1203 | OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); | |
1204 | OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, | |
1205 | tempRB3D_STENCILREFMASK); | |
1206 | OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK); | |
1207 | OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL); | |
1208 | OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL); | |
1209 | OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0); | |
1210 | OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1); | |
1211 | OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL); | |
1212 | OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL); | |
1da177e4 LT |
1213 | ADVANCE_RING(); |
1214 | ||
1215 | /* Make sure we restore the 3D state next time. | |
1216 | */ | |
1217 | dev_priv->sarea_priv->ctx_owner = 0; | |
1218 | ||
b5e89ed5 DA |
1219 | for (i = 0; i < nbox; i++) { |
1220 | ||
1221 | /* Funny that this should be required -- | |
1da177e4 LT |
1222 | * sets top-left? |
1223 | */ | |
b5e89ed5 DA |
1224 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); |
1225 | ||
1226 | BEGIN_RING(14); | |
1227 | OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12)); | |
1228 | OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | | |
1229 | RADEON_PRIM_WALK_RING | | |
1230 | (3 << RADEON_NUM_VERTICES_SHIFT))); | |
1231 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); | |
1232 | OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); | |
1233 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); | |
1234 | OUT_RING(0x3f800000); | |
1235 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); | |
1236 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); | |
1237 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); | |
1238 | OUT_RING(0x3f800000); | |
1239 | OUT_RING(depth_boxes[i].ui[CLEAR_X2]); | |
1240 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); | |
1241 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); | |
1242 | OUT_RING(0x3f800000); | |
1da177e4 LT |
1243 | ADVANCE_RING(); |
1244 | } | |
b5e89ed5 | 1245 | } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) { |
1da177e4 LT |
1246 | |
1247 | int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl; | |
1248 | ||
1249 | rb3d_cntl = depth_clear->rb3d_cntl; | |
1250 | ||
b5e89ed5 DA |
1251 | if (flags & RADEON_DEPTH) { |
1252 | rb3d_cntl |= RADEON_Z_ENABLE; | |
1da177e4 LT |
1253 | } else { |
1254 | rb3d_cntl &= ~RADEON_Z_ENABLE; | |
1255 | } | |
1256 | ||
b5e89ed5 DA |
1257 | if (flags & RADEON_STENCIL) { |
1258 | rb3d_cntl |= RADEON_STENCIL_ENABLE; | |
1259 | rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */ | |
1da177e4 LT |
1260 | } else { |
1261 | rb3d_cntl &= ~RADEON_STENCIL_ENABLE; | |
1262 | rb3d_stencilrefmask = 0x00000000; | |
1263 | } | |
1264 | ||
1265 | if (flags & RADEON_USE_COMP_ZBUF) { | |
1266 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE | | |
b5e89ed5 | 1267 | RADEON_Z_DECOMPRESSION_ENABLE; |
1da177e4 LT |
1268 | } |
1269 | if (flags & RADEON_USE_HIERZ) { | |
1270 | tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE; | |
1271 | } | |
1272 | ||
b5e89ed5 | 1273 | BEGIN_RING(13); |
1da177e4 LT |
1274 | RADEON_WAIT_UNTIL_2D_IDLE(); |
1275 | ||
b5e89ed5 DA |
1276 | OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1)); |
1277 | OUT_RING(0x00000000); | |
1278 | OUT_RING(rb3d_cntl); | |
1279 | ||
1280 | OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL); | |
1281 | OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask); | |
1282 | OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000); | |
1283 | OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl); | |
1da177e4 LT |
1284 | ADVANCE_RING(); |
1285 | ||
1286 | /* Make sure we restore the 3D state next time. | |
1287 | */ | |
1288 | dev_priv->sarea_priv->ctx_owner = 0; | |
1289 | ||
b5e89ed5 DA |
1290 | for (i = 0; i < nbox; i++) { |
1291 | ||
1292 | /* Funny that this should be required -- | |
1da177e4 LT |
1293 | * sets top-left? |
1294 | */ | |
b5e89ed5 DA |
1295 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); |
1296 | ||
1297 | BEGIN_RING(15); | |
1298 | ||
1299 | OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13)); | |
1300 | OUT_RING(RADEON_VTX_Z_PRESENT | | |
1301 | RADEON_VTX_PKCOLOR_PRESENT); | |
1302 | OUT_RING((RADEON_PRIM_TYPE_RECT_LIST | | |
1303 | RADEON_PRIM_WALK_RING | | |
1304 | RADEON_MAOS_ENABLE | | |
1305 | RADEON_VTX_FMT_RADEON_MODE | | |
1306 | (3 << RADEON_NUM_VERTICES_SHIFT))); | |
1307 | ||
1308 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); | |
1309 | OUT_RING(depth_boxes[i].ui[CLEAR_Y1]); | |
1310 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); | |
1311 | OUT_RING(0x0); | |
1312 | ||
1313 | OUT_RING(depth_boxes[i].ui[CLEAR_X1]); | |
1314 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); | |
1315 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); | |
1316 | OUT_RING(0x0); | |
1317 | ||
1318 | OUT_RING(depth_boxes[i].ui[CLEAR_X2]); | |
1319 | OUT_RING(depth_boxes[i].ui[CLEAR_Y2]); | |
1320 | OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]); | |
1321 | OUT_RING(0x0); | |
1da177e4 LT |
1322 | |
1323 | ADVANCE_RING(); | |
1324 | } | |
1325 | } | |
1326 | ||
1327 | /* Increment the clear counter. The client-side 3D driver must | |
1328 | * wait on this value before performing the clear ioctl. We | |
1329 | * need this because the card's so damned fast... | |
1330 | */ | |
1331 | dev_priv->sarea_priv->last_clear++; | |
1332 | ||
b5e89ed5 | 1333 | BEGIN_RING(4); |
1da177e4 | 1334 | |
b5e89ed5 | 1335 | RADEON_CLEAR_AGE(dev_priv->sarea_priv->last_clear); |
1da177e4 LT |
1336 | RADEON_WAIT_UNTIL_IDLE(); |
1337 | ||
1338 | ADVANCE_RING(); | |
1339 | } | |
1340 | ||
84b1fd10 | 1341 | static void radeon_cp_dispatch_swap(struct drm_device * dev) |
1da177e4 LT |
1342 | { |
1343 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1344 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1345 | int nbox = sarea_priv->nbox; | |
c60ce623 | 1346 | struct drm_clip_rect *pbox = sarea_priv->boxes; |
1da177e4 LT |
1347 | int i; |
1348 | RING_LOCALS; | |
b5e89ed5 | 1349 | DRM_DEBUG("\n"); |
1da177e4 LT |
1350 | |
1351 | /* Do some trivial performance monitoring... | |
1352 | */ | |
1353 | if (dev_priv->do_boxes) | |
b5e89ed5 | 1354 | radeon_cp_performance_boxes(dev_priv); |
1da177e4 LT |
1355 | |
1356 | /* Wait for the 3D stream to idle before dispatching the bitblt. | |
1357 | * This will prevent data corruption between the two streams. | |
1358 | */ | |
b5e89ed5 | 1359 | BEGIN_RING(2); |
1da177e4 LT |
1360 | |
1361 | RADEON_WAIT_UNTIL_3D_IDLE(); | |
1362 | ||
1363 | ADVANCE_RING(); | |
1364 | ||
b5e89ed5 | 1365 | for (i = 0; i < nbox; i++) { |
1da177e4 LT |
1366 | int x = pbox[i].x1; |
1367 | int y = pbox[i].y1; | |
1368 | int w = pbox[i].x2 - x; | |
1369 | int h = pbox[i].y2 - y; | |
1370 | ||
3e684eae | 1371 | DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); |
b5e89ed5 | 1372 | |
3e14a286 | 1373 | BEGIN_RING(9); |
b5e89ed5 | 1374 | |
3e14a286 | 1375 | OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0)); |
b5e89ed5 DA |
1376 | OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
1377 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
1378 | RADEON_GMC_BRUSH_NONE | | |
1379 | (dev_priv->color_fmt << 8) | | |
1380 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
1381 | RADEON_ROP3_S | | |
1382 | RADEON_DP_SRC_SOURCE_MEMORY | | |
1383 | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); | |
1384 | ||
1da177e4 LT |
1385 | /* Make this work even if front & back are flipped: |
1386 | */ | |
3e14a286 | 1387 | OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1)); |
453ff94c | 1388 | if (dev_priv->sarea_priv->pfCurrentPage == 0) { |
b5e89ed5 DA |
1389 | OUT_RING(dev_priv->back_pitch_offset); |
1390 | OUT_RING(dev_priv->front_pitch_offset); | |
1391 | } else { | |
1392 | OUT_RING(dev_priv->front_pitch_offset); | |
1393 | OUT_RING(dev_priv->back_pitch_offset); | |
1da177e4 LT |
1394 | } |
1395 | ||
3e14a286 | 1396 | OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2)); |
b5e89ed5 DA |
1397 | OUT_RING((x << 16) | y); |
1398 | OUT_RING((x << 16) | y); | |
1399 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
1400 | |
1401 | ADVANCE_RING(); | |
1402 | } | |
1403 | ||
1404 | /* Increment the frame counter. The client-side 3D driver must | |
1405 | * throttle the framerate by waiting for this value before | |
1406 | * performing the swapbuffer ioctl. | |
1407 | */ | |
1408 | dev_priv->sarea_priv->last_frame++; | |
1409 | ||
b5e89ed5 | 1410 | BEGIN_RING(4); |
1da177e4 | 1411 | |
b5e89ed5 | 1412 | RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
1413 | RADEON_WAIT_UNTIL_2D_IDLE(); |
1414 | ||
1415 | ADVANCE_RING(); | |
1416 | } | |
1417 | ||
84b1fd10 | 1418 | static void radeon_cp_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
1419 | { |
1420 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
bd63cb52 | 1421 | struct drm_sarea *sarea = (struct drm_sarea *) dev_priv->sarea->handle; |
453ff94c | 1422 | int offset = (dev_priv->sarea_priv->pfCurrentPage == 1) |
b5e89ed5 | 1423 | ? dev_priv->front_offset : dev_priv->back_offset; |
1da177e4 | 1424 | RING_LOCALS; |
3e684eae | 1425 | DRM_DEBUG("pfCurrentPage=%d\n", |
453ff94c | 1426 | dev_priv->sarea_priv->pfCurrentPage); |
1da177e4 LT |
1427 | |
1428 | /* Do some trivial performance monitoring... | |
1429 | */ | |
1430 | if (dev_priv->do_boxes) { | |
1431 | dev_priv->stats.boxes |= RADEON_BOX_FLIP; | |
b5e89ed5 | 1432 | radeon_cp_performance_boxes(dev_priv); |
1da177e4 LT |
1433 | } |
1434 | ||
1435 | /* Update the frame offsets for both CRTCs | |
1436 | */ | |
b5e89ed5 | 1437 | BEGIN_RING(6); |
1da177e4 LT |
1438 | |
1439 | RADEON_WAIT_UNTIL_3D_IDLE(); | |
b5e89ed5 DA |
1440 | OUT_RING_REG(RADEON_CRTC_OFFSET, |
1441 | ((sarea->frame.y * dev_priv->front_pitch + | |
1442 | sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7) | |
1443 | + offset); | |
1444 | OUT_RING_REG(RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base | |
1445 | + offset); | |
1da177e4 LT |
1446 | |
1447 | ADVANCE_RING(); | |
1448 | ||
1449 | /* Increment the frame counter. The client-side 3D driver must | |
1450 | * throttle the framerate by waiting for this value before | |
1451 | * performing the swapbuffer ioctl. | |
1452 | */ | |
1453 | dev_priv->sarea_priv->last_frame++; | |
453ff94c MD |
1454 | dev_priv->sarea_priv->pfCurrentPage = |
1455 | 1 - dev_priv->sarea_priv->pfCurrentPage; | |
1da177e4 | 1456 | |
b5e89ed5 | 1457 | BEGIN_RING(2); |
1da177e4 | 1458 | |
b5e89ed5 | 1459 | RADEON_FRAME_AGE(dev_priv->sarea_priv->last_frame); |
1da177e4 LT |
1460 | |
1461 | ADVANCE_RING(); | |
1462 | } | |
1463 | ||
b5e89ed5 | 1464 | static int bad_prim_vertex_nr(int primitive, int nr) |
1da177e4 LT |
1465 | { |
1466 | switch (primitive & RADEON_PRIM_TYPE_MASK) { | |
1467 | case RADEON_PRIM_TYPE_NONE: | |
1468 | case RADEON_PRIM_TYPE_POINT: | |
1469 | return nr < 1; | |
1470 | case RADEON_PRIM_TYPE_LINE: | |
1471 | return (nr & 1) || nr == 0; | |
1472 | case RADEON_PRIM_TYPE_LINE_STRIP: | |
1473 | return nr < 2; | |
1474 | case RADEON_PRIM_TYPE_TRI_LIST: | |
1475 | case RADEON_PRIM_TYPE_3VRT_POINT_LIST: | |
1476 | case RADEON_PRIM_TYPE_3VRT_LINE_LIST: | |
1477 | case RADEON_PRIM_TYPE_RECT_LIST: | |
1478 | return nr % 3 || nr == 0; | |
1479 | case RADEON_PRIM_TYPE_TRI_FAN: | |
1480 | case RADEON_PRIM_TYPE_TRI_STRIP: | |
1481 | return nr < 3; | |
1482 | default: | |
1483 | return 1; | |
b5e89ed5 | 1484 | } |
1da177e4 LT |
1485 | } |
1486 | ||
1da177e4 LT |
1487 | typedef struct { |
1488 | unsigned int start; | |
1489 | unsigned int finish; | |
1490 | unsigned int prim; | |
1491 | unsigned int numverts; | |
b5e89ed5 DA |
1492 | unsigned int offset; |
1493 | unsigned int vc_format; | |
1da177e4 LT |
1494 | } drm_radeon_tcl_prim_t; |
1495 | ||
84b1fd10 | 1496 | static void radeon_cp_dispatch_vertex(struct drm_device * dev, |
056219e2 | 1497 | struct drm_buf * buf, |
b5e89ed5 | 1498 | drm_radeon_tcl_prim_t * prim) |
1da177e4 LT |
1499 | { |
1500 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1501 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1502 | int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start; | |
1503 | int numverts = (int)prim->numverts; | |
1504 | int nbox = sarea_priv->nbox; | |
1505 | int i = 0; | |
1506 | RING_LOCALS; | |
1507 | ||
1508 | DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n", | |
1509 | prim->prim, | |
b5e89ed5 | 1510 | prim->vc_format, prim->start, prim->finish, prim->numverts); |
1da177e4 | 1511 | |
b5e89ed5 DA |
1512 | if (bad_prim_vertex_nr(prim->prim, prim->numverts)) { |
1513 | DRM_ERROR("bad prim %x numverts %d\n", | |
1514 | prim->prim, prim->numverts); | |
1da177e4 LT |
1515 | return; |
1516 | } | |
1517 | ||
1518 | do { | |
1519 | /* Emit the next cliprect */ | |
b5e89ed5 DA |
1520 | if (i < nbox) { |
1521 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); | |
1da177e4 LT |
1522 | } |
1523 | ||
1524 | /* Emit the vertex buffer rendering commands */ | |
b5e89ed5 | 1525 | BEGIN_RING(5); |
1da177e4 | 1526 | |
b5e89ed5 DA |
1527 | OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3)); |
1528 | OUT_RING(offset); | |
1529 | OUT_RING(numverts); | |
1530 | OUT_RING(prim->vc_format); | |
1531 | OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST | | |
1532 | RADEON_COLOR_ORDER_RGBA | | |
1533 | RADEON_VTX_FMT_RADEON_MODE | | |
1534 | (numverts << RADEON_NUM_VERTICES_SHIFT)); | |
1da177e4 LT |
1535 | |
1536 | ADVANCE_RING(); | |
1537 | ||
1538 | i++; | |
b5e89ed5 | 1539 | } while (i < nbox); |
1da177e4 LT |
1540 | } |
1541 | ||
056219e2 | 1542 | static void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf) |
1da177e4 LT |
1543 | { |
1544 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1545 | drm_radeon_buf_priv_t *buf_priv = buf->dev_private; | |
1546 | RING_LOCALS; | |
1547 | ||
1548 | buf_priv->age = ++dev_priv->sarea_priv->last_dispatch; | |
1549 | ||
1550 | /* Emit the vertex buffer age */ | |
b5e89ed5 DA |
1551 | BEGIN_RING(2); |
1552 | RADEON_DISPATCH_AGE(buf_priv->age); | |
1da177e4 LT |
1553 | ADVANCE_RING(); |
1554 | ||
1555 | buf->pending = 1; | |
1556 | buf->used = 0; | |
1557 | } | |
1558 | ||
84b1fd10 | 1559 | static void radeon_cp_dispatch_indirect(struct drm_device * dev, |
056219e2 | 1560 | struct drm_buf * buf, int start, int end) |
1da177e4 LT |
1561 | { |
1562 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1563 | RING_LOCALS; | |
3e684eae | 1564 | DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); |
1da177e4 | 1565 | |
b5e89ed5 | 1566 | if (start != end) { |
1da177e4 LT |
1567 | int offset = (dev_priv->gart_buffers_offset |
1568 | + buf->offset + start); | |
1569 | int dwords = (end - start + 3) / sizeof(u32); | |
1570 | ||
1571 | /* Indirect buffer data must be an even number of | |
1572 | * dwords, so if we've been given an odd number we must | |
1573 | * pad the data with a Type-2 CP packet. | |
1574 | */ | |
b5e89ed5 | 1575 | if (dwords & 1) { |
1da177e4 | 1576 | u32 *data = (u32 *) |
b5e89ed5 DA |
1577 | ((char *)dev->agp_buffer_map->handle |
1578 | + buf->offset + start); | |
1da177e4 LT |
1579 | data[dwords++] = RADEON_CP_PACKET2; |
1580 | } | |
1581 | ||
1582 | /* Fire off the indirect buffer */ | |
b5e89ed5 | 1583 | BEGIN_RING(3); |
1da177e4 | 1584 | |
b5e89ed5 DA |
1585 | OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1)); |
1586 | OUT_RING(offset); | |
1587 | OUT_RING(dwords); | |
1da177e4 LT |
1588 | |
1589 | ADVANCE_RING(); | |
1590 | } | |
1591 | } | |
1592 | ||
84b1fd10 | 1593 | static void radeon_cp_dispatch_indices(struct drm_device * dev, |
056219e2 | 1594 | struct drm_buf * elt_buf, |
b5e89ed5 | 1595 | drm_radeon_tcl_prim_t * prim) |
1da177e4 LT |
1596 | { |
1597 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1598 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1599 | int offset = dev_priv->gart_buffers_offset + prim->offset; | |
1600 | u32 *data; | |
1601 | int dwords; | |
1602 | int i = 0; | |
1603 | int start = prim->start + RADEON_INDEX_PRIM_OFFSET; | |
1604 | int count = (prim->finish - start) / sizeof(u16); | |
1605 | int nbox = sarea_priv->nbox; | |
1606 | ||
1607 | DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n", | |
1608 | prim->prim, | |
1609 | prim->vc_format, | |
b5e89ed5 DA |
1610 | prim->start, prim->finish, prim->offset, prim->numverts); |
1611 | ||
1612 | if (bad_prim_vertex_nr(prim->prim, count)) { | |
1613 | DRM_ERROR("bad prim %x count %d\n", prim->prim, count); | |
1da177e4 LT |
1614 | return; |
1615 | } | |
1616 | ||
b5e89ed5 DA |
1617 | if (start >= prim->finish || (prim->start & 0x7)) { |
1618 | DRM_ERROR("buffer prim %d\n", prim->prim); | |
1da177e4 LT |
1619 | return; |
1620 | } | |
1621 | ||
1622 | dwords = (prim->finish - prim->start + 3) / sizeof(u32); | |
1623 | ||
b5e89ed5 DA |
1624 | data = (u32 *) ((char *)dev->agp_buffer_map->handle + |
1625 | elt_buf->offset + prim->start); | |
1da177e4 | 1626 | |
b5e89ed5 | 1627 | data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2); |
1da177e4 LT |
1628 | data[1] = offset; |
1629 | data[2] = prim->numverts; | |
1630 | data[3] = prim->vc_format; | |
1631 | data[4] = (prim->prim | | |
1632 | RADEON_PRIM_WALK_IND | | |
1633 | RADEON_COLOR_ORDER_RGBA | | |
1634 | RADEON_VTX_FMT_RADEON_MODE | | |
b5e89ed5 | 1635 | (count << RADEON_NUM_VERTICES_SHIFT)); |
1da177e4 LT |
1636 | |
1637 | do { | |
b5e89ed5 DA |
1638 | if (i < nbox) |
1639 | radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]); | |
1da177e4 | 1640 | |
b5e89ed5 DA |
1641 | radeon_cp_dispatch_indirect(dev, elt_buf, |
1642 | prim->start, prim->finish); | |
1da177e4 LT |
1643 | |
1644 | i++; | |
b5e89ed5 | 1645 | } while (i < nbox); |
1da177e4 LT |
1646 | |
1647 | } | |
1648 | ||
ffbbf7a3 | 1649 | #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE |
1da177e4 | 1650 | |
6c340eac EA |
1651 | static int radeon_cp_dispatch_texture(struct drm_device * dev, |
1652 | struct drm_file *file_priv, | |
b5e89ed5 DA |
1653 | drm_radeon_texture_t * tex, |
1654 | drm_radeon_tex_image_t * image) | |
1da177e4 LT |
1655 | { |
1656 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
056219e2 | 1657 | struct drm_buf *buf; |
1da177e4 LT |
1658 | u32 format; |
1659 | u32 *buffer; | |
1660 | const u8 __user *data; | |
ffbbf7a3 | 1661 | int size, dwords, tex_width, blit_width, spitch; |
1da177e4 LT |
1662 | u32 height; |
1663 | int i; | |
1664 | u32 texpitch, microtile; | |
ffbbf7a3 | 1665 | u32 offset; |
1da177e4 LT |
1666 | RING_LOCALS; |
1667 | ||
6c340eac | 1668 | if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) { |
b5e89ed5 | 1669 | DRM_ERROR("Invalid destination offset\n"); |
20caafa6 | 1670 | return -EINVAL; |
1da177e4 LT |
1671 | } |
1672 | ||
1673 | dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD; | |
1674 | ||
1675 | /* Flush the pixel cache. This ensures no pixel data gets mixed | |
1676 | * up with the texture data from the host data blit, otherwise | |
1677 | * part of the texture image may be corrupted. | |
1678 | */ | |
b5e89ed5 | 1679 | BEGIN_RING(4); |
1da177e4 LT |
1680 | RADEON_FLUSH_CACHE(); |
1681 | RADEON_WAIT_UNTIL_IDLE(); | |
1682 | ADVANCE_RING(); | |
1683 | ||
1da177e4 LT |
1684 | /* The compiler won't optimize away a division by a variable, |
1685 | * even if the only legal values are powers of two. Thus, we'll | |
1686 | * use a shift instead. | |
1687 | */ | |
b5e89ed5 | 1688 | switch (tex->format) { |
1da177e4 LT |
1689 | case RADEON_TXFORMAT_ARGB8888: |
1690 | case RADEON_TXFORMAT_RGBA8888: | |
1691 | format = RADEON_COLOR_FORMAT_ARGB8888; | |
1692 | tex_width = tex->width * 4; | |
1693 | blit_width = image->width * 4; | |
1694 | break; | |
1695 | case RADEON_TXFORMAT_AI88: | |
1696 | case RADEON_TXFORMAT_ARGB1555: | |
1697 | case RADEON_TXFORMAT_RGB565: | |
1698 | case RADEON_TXFORMAT_ARGB4444: | |
1699 | case RADEON_TXFORMAT_VYUY422: | |
1700 | case RADEON_TXFORMAT_YVYU422: | |
1701 | format = RADEON_COLOR_FORMAT_RGB565; | |
1702 | tex_width = tex->width * 2; | |
1703 | blit_width = image->width * 2; | |
1704 | break; | |
1705 | case RADEON_TXFORMAT_I8: | |
1706 | case RADEON_TXFORMAT_RGB332: | |
1707 | format = RADEON_COLOR_FORMAT_CI8; | |
1708 | tex_width = tex->width * 1; | |
1709 | blit_width = image->width * 1; | |
1710 | break; | |
1711 | default: | |
b5e89ed5 | 1712 | DRM_ERROR("invalid texture format %d\n", tex->format); |
20caafa6 | 1713 | return -EINVAL; |
1da177e4 | 1714 | } |
ffbbf7a3 DA |
1715 | spitch = blit_width >> 6; |
1716 | if (spitch == 0 && image->height > 1) | |
20caafa6 | 1717 | return -EINVAL; |
ffbbf7a3 | 1718 | |
1da177e4 LT |
1719 | texpitch = tex->pitch; |
1720 | if ((texpitch << 22) & RADEON_DST_TILE_MICRO) { | |
1721 | microtile = 1; | |
1722 | if (tex_width < 64) { | |
1723 | texpitch &= ~(RADEON_DST_TILE_MICRO >> 22); | |
1724 | /* we got tiled coordinates, untile them */ | |
1725 | image->x *= 2; | |
1726 | } | |
b5e89ed5 DA |
1727 | } else |
1728 | microtile = 0; | |
1da177e4 | 1729 | |
b5e89ed5 | 1730 | DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width); |
1da177e4 LT |
1731 | |
1732 | do { | |
b5e89ed5 DA |
1733 | DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n", |
1734 | tex->offset >> 10, tex->pitch, tex->format, | |
1735 | image->x, image->y, image->width, image->height); | |
1da177e4 LT |
1736 | |
1737 | /* Make a copy of some parameters in case we have to | |
1738 | * update them for a multi-pass texture blit. | |
1739 | */ | |
1740 | height = image->height; | |
1741 | data = (const u8 __user *)image->data; | |
b5e89ed5 | 1742 | |
1da177e4 LT |
1743 | size = height * blit_width; |
1744 | ||
b5e89ed5 | 1745 | if (size > RADEON_MAX_TEXTURE_SIZE) { |
1da177e4 LT |
1746 | height = RADEON_MAX_TEXTURE_SIZE / blit_width; |
1747 | size = height * blit_width; | |
b5e89ed5 | 1748 | } else if (size < 4 && size > 0) { |
1da177e4 | 1749 | size = 4; |
b5e89ed5 | 1750 | } else if (size == 0) { |
1da177e4 LT |
1751 | return 0; |
1752 | } | |
1753 | ||
b5e89ed5 DA |
1754 | buf = radeon_freelist_get(dev); |
1755 | if (0 && !buf) { | |
1756 | radeon_do_cp_idle(dev_priv); | |
1757 | buf = radeon_freelist_get(dev); | |
1da177e4 | 1758 | } |
b5e89ed5 | 1759 | if (!buf) { |
3e684eae | 1760 | DRM_DEBUG("EAGAIN\n"); |
b5e89ed5 | 1761 | if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) |
20caafa6 EA |
1762 | return -EFAULT; |
1763 | return -EAGAIN; | |
1da177e4 LT |
1764 | } |
1765 | ||
1da177e4 LT |
1766 | /* Dispatch the indirect buffer. |
1767 | */ | |
b5e89ed5 DA |
1768 | buffer = |
1769 | (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); | |
1da177e4 | 1770 | dwords = size / 4; |
1da177e4 | 1771 | |
d985c108 DA |
1772 | #define RADEON_COPY_MT(_buf, _data, _width) \ |
1773 | do { \ | |
1774 | if (DRM_COPY_FROM_USER(_buf, _data, (_width))) {\ | |
1775 | DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \ | |
20caafa6 | 1776 | return -EFAULT; \ |
d985c108 DA |
1777 | } \ |
1778 | } while(0) | |
1779 | ||
1da177e4 LT |
1780 | if (microtile) { |
1781 | /* texture micro tiling in use, minimum texture width is thus 16 bytes. | |
1782 | however, we cannot use blitter directly for texture width < 64 bytes, | |
1783 | since minimum tex pitch is 64 bytes and we need this to match | |
1784 | the texture width, otherwise the blitter will tile it wrong. | |
1785 | Thus, tiling manually in this case. Additionally, need to special | |
1786 | case tex height = 1, since our actual image will have height 2 | |
1787 | and we need to ensure we don't read beyond the texture size | |
1788 | from user space. */ | |
1789 | if (tex->height == 1) { | |
1790 | if (tex_width >= 64 || tex_width <= 16) { | |
d985c108 | 1791 | RADEON_COPY_MT(buffer, data, |
f8e0f290 | 1792 | (int)(tex_width * sizeof(u32))); |
1da177e4 | 1793 | } else if (tex_width == 32) { |
d985c108 DA |
1794 | RADEON_COPY_MT(buffer, data, 16); |
1795 | RADEON_COPY_MT(buffer + 8, | |
1796 | data + 16, 16); | |
1da177e4 LT |
1797 | } |
1798 | } else if (tex_width >= 64 || tex_width == 16) { | |
d985c108 | 1799 | RADEON_COPY_MT(buffer, data, |
f8e0f290 | 1800 | (int)(dwords * sizeof(u32))); |
1da177e4 LT |
1801 | } else if (tex_width < 16) { |
1802 | for (i = 0; i < tex->height; i++) { | |
d985c108 | 1803 | RADEON_COPY_MT(buffer, data, tex_width); |
1da177e4 LT |
1804 | buffer += 4; |
1805 | data += tex_width; | |
1806 | } | |
1807 | } else if (tex_width == 32) { | |
1808 | /* TODO: make sure this works when not fitting in one buffer | |
1809 | (i.e. 32bytes x 2048...) */ | |
1810 | for (i = 0; i < tex->height; i += 2) { | |
d985c108 | 1811 | RADEON_COPY_MT(buffer, data, 16); |
1da177e4 | 1812 | data += 16; |
d985c108 | 1813 | RADEON_COPY_MT(buffer + 8, data, 16); |
1da177e4 | 1814 | data += 16; |
d985c108 | 1815 | RADEON_COPY_MT(buffer + 4, data, 16); |
1da177e4 | 1816 | data += 16; |
d985c108 | 1817 | RADEON_COPY_MT(buffer + 12, data, 16); |
1da177e4 LT |
1818 | data += 16; |
1819 | buffer += 16; | |
1820 | } | |
1821 | } | |
b5e89ed5 | 1822 | } else { |
1da177e4 LT |
1823 | if (tex_width >= 32) { |
1824 | /* Texture image width is larger than the minimum, so we | |
1825 | * can upload it directly. | |
1826 | */ | |
d985c108 | 1827 | RADEON_COPY_MT(buffer, data, |
f8e0f290 | 1828 | (int)(dwords * sizeof(u32))); |
1da177e4 LT |
1829 | } else { |
1830 | /* Texture image width is less than the minimum, so we | |
1831 | * need to pad out each image scanline to the minimum | |
1832 | * width. | |
1833 | */ | |
b5e89ed5 | 1834 | for (i = 0; i < tex->height; i++) { |
d985c108 | 1835 | RADEON_COPY_MT(buffer, data, tex_width); |
1da177e4 LT |
1836 | buffer += 8; |
1837 | data += tex_width; | |
1838 | } | |
1839 | } | |
1840 | } | |
1841 | ||
d985c108 | 1842 | #undef RADEON_COPY_MT |
6c340eac | 1843 | buf->file_priv = file_priv; |
ffbbf7a3 DA |
1844 | buf->used = size; |
1845 | offset = dev_priv->gart_buffers_offset + buf->offset; | |
1846 | BEGIN_RING(9); | |
1847 | OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5)); | |
1848 | OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | | |
1849 | RADEON_GMC_DST_PITCH_OFFSET_CNTL | | |
1850 | RADEON_GMC_BRUSH_NONE | | |
1851 | (format << 8) | | |
1852 | RADEON_GMC_SRC_DATATYPE_COLOR | | |
1853 | RADEON_ROP3_S | | |
1854 | RADEON_DP_SRC_SOURCE_MEMORY | | |
b5e89ed5 | 1855 | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); |
ffbbf7a3 DA |
1856 | OUT_RING((spitch << 22) | (offset >> 10)); |
1857 | OUT_RING((texpitch << 22) | (tex->offset >> 10)); | |
1858 | OUT_RING(0); | |
1859 | OUT_RING((image->x << 16) | image->y); | |
1860 | OUT_RING((image->width << 16) | height); | |
1861 | RADEON_WAIT_UNTIL_2D_IDLE(); | |
1862 | ADVANCE_RING(); | |
eed0f722 | 1863 | COMMIT_RING(); |
ffbbf7a3 DA |
1864 | |
1865 | radeon_cp_discard_buffer(dev, buf); | |
1da177e4 LT |
1866 | |
1867 | /* Update the input parameters for next time */ | |
1868 | image->y += height; | |
1869 | image->height -= height; | |
1870 | image->data = (const u8 __user *)image->data + size; | |
1871 | } while (image->height > 0); | |
1872 | ||
1873 | /* Flush the pixel cache after the blit completes. This ensures | |
1874 | * the texture data is written out to memory before rendering | |
1875 | * continues. | |
1876 | */ | |
b5e89ed5 | 1877 | BEGIN_RING(4); |
1da177e4 LT |
1878 | RADEON_FLUSH_CACHE(); |
1879 | RADEON_WAIT_UNTIL_2D_IDLE(); | |
1880 | ADVANCE_RING(); | |
eed0f722 | 1881 | COMMIT_RING(); |
1882 | ||
1da177e4 LT |
1883 | return 0; |
1884 | } | |
1885 | ||
84b1fd10 | 1886 | static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple) |
1da177e4 LT |
1887 | { |
1888 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
1889 | int i; | |
1890 | RING_LOCALS; | |
b5e89ed5 | 1891 | DRM_DEBUG("\n"); |
1da177e4 | 1892 | |
b5e89ed5 | 1893 | BEGIN_RING(35); |
1da177e4 | 1894 | |
b5e89ed5 DA |
1895 | OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0)); |
1896 | OUT_RING(0x00000000); | |
1da177e4 | 1897 | |
b5e89ed5 DA |
1898 | OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31)); |
1899 | for (i = 0; i < 32; i++) { | |
1900 | OUT_RING(stipple[i]); | |
1da177e4 LT |
1901 | } |
1902 | ||
1903 | ADVANCE_RING(); | |
1904 | } | |
1905 | ||
b5e89ed5 | 1906 | static void radeon_apply_surface_regs(int surf_index, |
d985c108 | 1907 | drm_radeon_private_t *dev_priv) |
1da177e4 LT |
1908 | { |
1909 | if (!dev_priv->mmio) | |
1910 | return; | |
1911 | ||
1912 | radeon_do_cp_idle(dev_priv); | |
1913 | ||
b5e89ed5 DA |
1914 | RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index, |
1915 | dev_priv->surfaces[surf_index].flags); | |
1916 | RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index, | |
1917 | dev_priv->surfaces[surf_index].lower); | |
1918 | RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index, | |
1919 | dev_priv->surfaces[surf_index].upper); | |
1da177e4 LT |
1920 | } |
1921 | ||
1da177e4 | 1922 | /* Allocates a virtual surface |
b5e89ed5 | 1923 | * doesn't always allocate a real surface, will stretch an existing |
1da177e4 LT |
1924 | * surface when possible. |
1925 | * | |
1926 | * Note that refcount can be at most 2, since during a free refcount=3 | |
1927 | * might mean we have to allocate a new surface which might not always | |
1928 | * be available. | |
b5e89ed5 | 1929 | * For example : we allocate three contigous surfaces ABC. If B is |
1da177e4 LT |
1930 | * freed, we suddenly need two surfaces to store A and C, which might |
1931 | * not always be available. | |
1932 | */ | |
d985c108 | 1933 | static int alloc_surface(drm_radeon_surface_alloc_t *new, |
6c340eac EA |
1934 | drm_radeon_private_t *dev_priv, |
1935 | struct drm_file *file_priv) | |
1da177e4 LT |
1936 | { |
1937 | struct radeon_virt_surface *s; | |
1938 | int i; | |
1939 | int virt_surface_index; | |
1940 | uint32_t new_upper, new_lower; | |
1941 | ||
1942 | new_lower = new->address; | |
1943 | new_upper = new_lower + new->size - 1; | |
1944 | ||
1945 | /* sanity check */ | |
1946 | if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) || | |
b5e89ed5 DA |
1947 | ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) != |
1948 | RADEON_SURF_ADDRESS_FIXED_MASK) | |
1949 | || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0)) | |
1da177e4 LT |
1950 | return -1; |
1951 | ||
1952 | /* make sure there is no overlap with existing surfaces */ | |
1953 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { | |
1954 | if ((dev_priv->surfaces[i].refcount != 0) && | |
b5e89ed5 DA |
1955 | (((new_lower >= dev_priv->surfaces[i].lower) && |
1956 | (new_lower < dev_priv->surfaces[i].upper)) || | |
1957 | ((new_lower < dev_priv->surfaces[i].lower) && | |
1958 | (new_upper > dev_priv->surfaces[i].lower)))) { | |
1959 | return -1; | |
1960 | } | |
1da177e4 LT |
1961 | } |
1962 | ||
1963 | /* find a virtual surface */ | |
b5e89ed5 | 1964 | for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) |
6c340eac | 1965 | if (dev_priv->virt_surfaces[i].file_priv == 0) |
1da177e4 | 1966 | break; |
b5e89ed5 DA |
1967 | if (i == 2 * RADEON_MAX_SURFACES) { |
1968 | return -1; | |
1969 | } | |
1da177e4 LT |
1970 | virt_surface_index = i; |
1971 | ||
1972 | /* try to reuse an existing surface */ | |
1973 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { | |
1974 | /* extend before */ | |
1975 | if ((dev_priv->surfaces[i].refcount == 1) && | |
b5e89ed5 DA |
1976 | (new->flags == dev_priv->surfaces[i].flags) && |
1977 | (new_upper + 1 == dev_priv->surfaces[i].lower)) { | |
1da177e4 LT |
1978 | s = &(dev_priv->virt_surfaces[virt_surface_index]); |
1979 | s->surface_index = i; | |
1980 | s->lower = new_lower; | |
1981 | s->upper = new_upper; | |
1982 | s->flags = new->flags; | |
6c340eac | 1983 | s->file_priv = file_priv; |
1da177e4 LT |
1984 | dev_priv->surfaces[i].refcount++; |
1985 | dev_priv->surfaces[i].lower = s->lower; | |
1986 | radeon_apply_surface_regs(s->surface_index, dev_priv); | |
1987 | return virt_surface_index; | |
1988 | } | |
1989 | ||
1990 | /* extend after */ | |
1991 | if ((dev_priv->surfaces[i].refcount == 1) && | |
b5e89ed5 DA |
1992 | (new->flags == dev_priv->surfaces[i].flags) && |
1993 | (new_lower == dev_priv->surfaces[i].upper + 1)) { | |
1da177e4 LT |
1994 | s = &(dev_priv->virt_surfaces[virt_surface_index]); |
1995 | s->surface_index = i; | |
1996 | s->lower = new_lower; | |
1997 | s->upper = new_upper; | |
1998 | s->flags = new->flags; | |
6c340eac | 1999 | s->file_priv = file_priv; |
1da177e4 LT |
2000 | dev_priv->surfaces[i].refcount++; |
2001 | dev_priv->surfaces[i].upper = s->upper; | |
2002 | radeon_apply_surface_regs(s->surface_index, dev_priv); | |
2003 | return virt_surface_index; | |
2004 | } | |
2005 | } | |
2006 | ||
2007 | /* okay, we need a new one */ | |
2008 | for (i = 0; i < RADEON_MAX_SURFACES; i++) { | |
2009 | if (dev_priv->surfaces[i].refcount == 0) { | |
2010 | s = &(dev_priv->virt_surfaces[virt_surface_index]); | |
2011 | s->surface_index = i; | |
2012 | s->lower = new_lower; | |
2013 | s->upper = new_upper; | |
2014 | s->flags = new->flags; | |
6c340eac | 2015 | s->file_priv = file_priv; |
1da177e4 LT |
2016 | dev_priv->surfaces[i].refcount = 1; |
2017 | dev_priv->surfaces[i].lower = s->lower; | |
2018 | dev_priv->surfaces[i].upper = s->upper; | |
2019 | dev_priv->surfaces[i].flags = s->flags; | |
2020 | radeon_apply_surface_regs(s->surface_index, dev_priv); | |
2021 | return virt_surface_index; | |
2022 | } | |
2023 | } | |
2024 | ||
2025 | /* we didn't find anything */ | |
2026 | return -1; | |
2027 | } | |
2028 | ||
6c340eac EA |
2029 | static int free_surface(struct drm_file *file_priv, |
2030 | drm_radeon_private_t * dev_priv, | |
b5e89ed5 | 2031 | int lower) |
1da177e4 LT |
2032 | { |
2033 | struct radeon_virt_surface *s; | |
2034 | int i; | |
2035 | /* find the virtual surface */ | |
b5e89ed5 | 2036 | for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { |
1da177e4 | 2037 | s = &(dev_priv->virt_surfaces[i]); |
6c340eac EA |
2038 | if (s->file_priv) { |
2039 | if ((lower == s->lower) && (file_priv == s->file_priv)) | |
2040 | { | |
b5e89ed5 DA |
2041 | if (dev_priv->surfaces[s->surface_index]. |
2042 | lower == s->lower) | |
2043 | dev_priv->surfaces[s->surface_index]. | |
2044 | lower = s->upper; | |
1da177e4 | 2045 | |
b5e89ed5 DA |
2046 | if (dev_priv->surfaces[s->surface_index]. |
2047 | upper == s->upper) | |
2048 | dev_priv->surfaces[s->surface_index]. | |
2049 | upper = s->lower; | |
1da177e4 LT |
2050 | |
2051 | dev_priv->surfaces[s->surface_index].refcount--; | |
b5e89ed5 DA |
2052 | if (dev_priv->surfaces[s->surface_index]. |
2053 | refcount == 0) | |
2054 | dev_priv->surfaces[s->surface_index]. | |
2055 | flags = 0; | |
6c340eac | 2056 | s->file_priv = NULL; |
b5e89ed5 DA |
2057 | radeon_apply_surface_regs(s->surface_index, |
2058 | dev_priv); | |
1da177e4 LT |
2059 | return 0; |
2060 | } | |
2061 | } | |
2062 | } | |
2063 | return 1; | |
2064 | } | |
2065 | ||
6c340eac | 2066 | static void radeon_surfaces_release(struct drm_file *file_priv, |
b5e89ed5 | 2067 | drm_radeon_private_t * dev_priv) |
1da177e4 LT |
2068 | { |
2069 | int i; | |
b5e89ed5 | 2070 | for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) { |
6c340eac EA |
2071 | if (dev_priv->virt_surfaces[i].file_priv == file_priv) |
2072 | free_surface(file_priv, dev_priv, | |
b5e89ed5 | 2073 | dev_priv->virt_surfaces[i].lower); |
1da177e4 LT |
2074 | } |
2075 | } | |
2076 | ||
2077 | /* ================================================================ | |
2078 | * IOCTL functions | |
2079 | */ | |
c153f45f | 2080 | static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2081 | { |
1da177e4 | 2082 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 2083 | drm_radeon_surface_alloc_t *alloc = data; |
1da177e4 | 2084 | |
c153f45f | 2085 | if (alloc_surface(alloc, dev_priv, file_priv) == -1) |
20caafa6 | 2086 | return -EINVAL; |
1da177e4 LT |
2087 | else |
2088 | return 0; | |
2089 | } | |
2090 | ||
c153f45f | 2091 | static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2092 | { |
1da177e4 | 2093 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 2094 | drm_radeon_surface_free_t *memfree = data; |
1da177e4 | 2095 | |
c153f45f | 2096 | if (free_surface(file_priv, dev_priv, memfree->address)) |
20caafa6 | 2097 | return -EINVAL; |
1da177e4 LT |
2098 | else |
2099 | return 0; | |
2100 | } | |
2101 | ||
c153f45f | 2102 | static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2103 | { |
1da177e4 LT |
2104 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2105 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
c153f45f | 2106 | drm_radeon_clear_t *clear = data; |
1da177e4 | 2107 | drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS]; |
b5e89ed5 | 2108 | DRM_DEBUG("\n"); |
1da177e4 | 2109 | |
6c340eac | 2110 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2111 | |
b5e89ed5 | 2112 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 2113 | |
b5e89ed5 | 2114 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
1da177e4 LT |
2115 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; |
2116 | ||
c153f45f | 2117 | if (DRM_COPY_FROM_USER(&depth_boxes, clear->depth_boxes, |
b5e89ed5 | 2118 | sarea_priv->nbox * sizeof(depth_boxes[0]))) |
20caafa6 | 2119 | return -EFAULT; |
1da177e4 | 2120 | |
c153f45f | 2121 | radeon_cp_dispatch_clear(dev, clear, depth_boxes); |
1da177e4 LT |
2122 | |
2123 | COMMIT_RING(); | |
2124 | return 0; | |
2125 | } | |
2126 | ||
1da177e4 | 2127 | /* Not sure why this isn't set all the time: |
b5e89ed5 | 2128 | */ |
84b1fd10 | 2129 | static int radeon_do_init_pageflip(struct drm_device * dev) |
1da177e4 LT |
2130 | { |
2131 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2132 | RING_LOCALS; | |
2133 | ||
b5e89ed5 | 2134 | DRM_DEBUG("\n"); |
1da177e4 | 2135 | |
b5e89ed5 | 2136 | BEGIN_RING(6); |
1da177e4 | 2137 | RADEON_WAIT_UNTIL_3D_IDLE(); |
b5e89ed5 DA |
2138 | OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0)); |
2139 | OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) | | |
2140 | RADEON_CRTC_OFFSET_FLIP_CNTL); | |
2141 | OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0)); | |
2142 | OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) | | |
2143 | RADEON_CRTC_OFFSET_FLIP_CNTL); | |
1da177e4 LT |
2144 | ADVANCE_RING(); |
2145 | ||
2146 | dev_priv->page_flipping = 1; | |
1da177e4 | 2147 | |
453ff94c MD |
2148 | if (dev_priv->sarea_priv->pfCurrentPage != 1) |
2149 | dev_priv->sarea_priv->pfCurrentPage = 0; | |
1da177e4 | 2150 | |
1da177e4 LT |
2151 | return 0; |
2152 | } | |
2153 | ||
2154 | /* Swapping and flipping are different operations, need different ioctls. | |
b5e89ed5 | 2155 | * They can & should be intermixed to support multiple 3d windows. |
1da177e4 | 2156 | */ |
c153f45f | 2157 | static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2158 | { |
1da177e4 | 2159 | drm_radeon_private_t *dev_priv = dev->dev_private; |
b5e89ed5 DA |
2160 | DRM_DEBUG("\n"); |
2161 | ||
6c340eac | 2162 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2163 | |
b5e89ed5 | 2164 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 2165 | |
b5e89ed5 DA |
2166 | if (!dev_priv->page_flipping) |
2167 | radeon_do_init_pageflip(dev); | |
1da177e4 | 2168 | |
b5e89ed5 | 2169 | radeon_cp_dispatch_flip(dev); |
1da177e4 LT |
2170 | |
2171 | COMMIT_RING(); | |
2172 | return 0; | |
2173 | } | |
2174 | ||
c153f45f | 2175 | static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2176 | { |
1da177e4 LT |
2177 | drm_radeon_private_t *dev_priv = dev->dev_private; |
2178 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
b5e89ed5 | 2179 | DRM_DEBUG("\n"); |
1da177e4 | 2180 | |
6c340eac | 2181 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2182 | |
b5e89ed5 | 2183 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 2184 | |
b5e89ed5 | 2185 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
1da177e4 LT |
2186 | sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS; |
2187 | ||
b5e89ed5 | 2188 | radeon_cp_dispatch_swap(dev); |
1da177e4 LT |
2189 | dev_priv->sarea_priv->ctx_owner = 0; |
2190 | ||
2191 | COMMIT_RING(); | |
2192 | return 0; | |
2193 | } | |
2194 | ||
c153f45f | 2195 | static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2196 | { |
1da177e4 | 2197 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1da177e4 | 2198 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
cdd55a29 | 2199 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 2200 | struct drm_buf *buf; |
c153f45f | 2201 | drm_radeon_vertex_t *vertex = data; |
1da177e4 LT |
2202 | drm_radeon_tcl_prim_t prim; |
2203 | ||
6c340eac | 2204 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2205 | |
b5e89ed5 | 2206 | DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", |
c153f45f | 2207 | DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard); |
1da177e4 | 2208 | |
c153f45f | 2209 | if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { |
b5e89ed5 | 2210 | DRM_ERROR("buffer index %d (of %d max)\n", |
c153f45f | 2211 | vertex->idx, dma->buf_count - 1); |
20caafa6 | 2212 | return -EINVAL; |
1da177e4 | 2213 | } |
c153f45f EA |
2214 | if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
2215 | DRM_ERROR("buffer prim %d\n", vertex->prim); | |
20caafa6 | 2216 | return -EINVAL; |
1da177e4 LT |
2217 | } |
2218 | ||
b5e89ed5 DA |
2219 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2220 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 | 2221 | |
c153f45f | 2222 | buf = dma->buflist[vertex->idx]; |
1da177e4 | 2223 | |
6c340eac | 2224 | if (buf->file_priv != file_priv) { |
b5e89ed5 | 2225 | DRM_ERROR("process %d using buffer owned by %p\n", |
6c340eac | 2226 | DRM_CURRENTPID, buf->file_priv); |
20caafa6 | 2227 | return -EINVAL; |
1da177e4 | 2228 | } |
b5e89ed5 | 2229 | if (buf->pending) { |
c153f45f | 2230 | DRM_ERROR("sending pending buffer %d\n", vertex->idx); |
20caafa6 | 2231 | return -EINVAL; |
1da177e4 LT |
2232 | } |
2233 | ||
2234 | /* Build up a prim_t record: | |
2235 | */ | |
c153f45f EA |
2236 | if (vertex->count) { |
2237 | buf->used = vertex->count; /* not used? */ | |
b5e89ed5 DA |
2238 | |
2239 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { | |
6c340eac | 2240 | if (radeon_emit_state(dev_priv, file_priv, |
b5e89ed5 DA |
2241 | &sarea_priv->context_state, |
2242 | sarea_priv->tex_state, | |
2243 | sarea_priv->dirty)) { | |
2244 | DRM_ERROR("radeon_emit_state failed\n"); | |
20caafa6 | 2245 | return -EINVAL; |
1da177e4 LT |
2246 | } |
2247 | ||
2248 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | | |
2249 | RADEON_UPLOAD_TEX1IMAGES | | |
2250 | RADEON_UPLOAD_TEX2IMAGES | | |
2251 | RADEON_REQUIRE_QUIESCENCE); | |
2252 | } | |
2253 | ||
2254 | prim.start = 0; | |
c153f45f EA |
2255 | prim.finish = vertex->count; /* unused */ |
2256 | prim.prim = vertex->prim; | |
2257 | prim.numverts = vertex->count; | |
1da177e4 | 2258 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
b5e89ed5 DA |
2259 | |
2260 | radeon_cp_dispatch_vertex(dev, buf, &prim); | |
1da177e4 LT |
2261 | } |
2262 | ||
c153f45f | 2263 | if (vertex->discard) { |
b5e89ed5 | 2264 | radeon_cp_discard_buffer(dev, buf); |
1da177e4 LT |
2265 | } |
2266 | ||
2267 | COMMIT_RING(); | |
2268 | return 0; | |
2269 | } | |
2270 | ||
c153f45f | 2271 | static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2272 | { |
1da177e4 | 2273 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1da177e4 | 2274 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
cdd55a29 | 2275 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 2276 | struct drm_buf *buf; |
c153f45f | 2277 | drm_radeon_indices_t *elts = data; |
1da177e4 LT |
2278 | drm_radeon_tcl_prim_t prim; |
2279 | int count; | |
2280 | ||
6c340eac | 2281 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2282 | |
b5e89ed5 | 2283 | DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n", |
c153f45f EA |
2284 | DRM_CURRENTPID, elts->idx, elts->start, elts->end, |
2285 | elts->discard); | |
1da177e4 | 2286 | |
c153f45f | 2287 | if (elts->idx < 0 || elts->idx >= dma->buf_count) { |
b5e89ed5 | 2288 | DRM_ERROR("buffer index %d (of %d max)\n", |
c153f45f | 2289 | elts->idx, dma->buf_count - 1); |
20caafa6 | 2290 | return -EINVAL; |
1da177e4 | 2291 | } |
c153f45f EA |
2292 | if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) { |
2293 | DRM_ERROR("buffer prim %d\n", elts->prim); | |
20caafa6 | 2294 | return -EINVAL; |
1da177e4 LT |
2295 | } |
2296 | ||
b5e89ed5 DA |
2297 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2298 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 | 2299 | |
c153f45f | 2300 | buf = dma->buflist[elts->idx]; |
1da177e4 | 2301 | |
6c340eac | 2302 | if (buf->file_priv != file_priv) { |
b5e89ed5 | 2303 | DRM_ERROR("process %d using buffer owned by %p\n", |
6c340eac | 2304 | DRM_CURRENTPID, buf->file_priv); |
20caafa6 | 2305 | return -EINVAL; |
1da177e4 | 2306 | } |
b5e89ed5 | 2307 | if (buf->pending) { |
c153f45f | 2308 | DRM_ERROR("sending pending buffer %d\n", elts->idx); |
20caafa6 | 2309 | return -EINVAL; |
1da177e4 LT |
2310 | } |
2311 | ||
c153f45f EA |
2312 | count = (elts->end - elts->start) / sizeof(u16); |
2313 | elts->start -= RADEON_INDEX_PRIM_OFFSET; | |
1da177e4 | 2314 | |
c153f45f EA |
2315 | if (elts->start & 0x7) { |
2316 | DRM_ERROR("misaligned buffer 0x%x\n", elts->start); | |
20caafa6 | 2317 | return -EINVAL; |
1da177e4 | 2318 | } |
c153f45f EA |
2319 | if (elts->start < buf->used) { |
2320 | DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used); | |
20caafa6 | 2321 | return -EINVAL; |
1da177e4 LT |
2322 | } |
2323 | ||
c153f45f | 2324 | buf->used = elts->end; |
1da177e4 | 2325 | |
b5e89ed5 | 2326 | if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) { |
6c340eac | 2327 | if (radeon_emit_state(dev_priv, file_priv, |
b5e89ed5 DA |
2328 | &sarea_priv->context_state, |
2329 | sarea_priv->tex_state, | |
2330 | sarea_priv->dirty)) { | |
2331 | DRM_ERROR("radeon_emit_state failed\n"); | |
20caafa6 | 2332 | return -EINVAL; |
1da177e4 LT |
2333 | } |
2334 | ||
2335 | sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES | | |
2336 | RADEON_UPLOAD_TEX1IMAGES | | |
2337 | RADEON_UPLOAD_TEX2IMAGES | | |
2338 | RADEON_REQUIRE_QUIESCENCE); | |
2339 | } | |
2340 | ||
1da177e4 LT |
2341 | /* Build up a prim_t record: |
2342 | */ | |
c153f45f EA |
2343 | prim.start = elts->start; |
2344 | prim.finish = elts->end; | |
2345 | prim.prim = elts->prim; | |
1da177e4 | 2346 | prim.offset = 0; /* offset from start of dma buffers */ |
b5e89ed5 | 2347 | prim.numverts = RADEON_MAX_VB_VERTS; /* duh */ |
1da177e4 | 2348 | prim.vc_format = dev_priv->sarea_priv->vc_format; |
b5e89ed5 DA |
2349 | |
2350 | radeon_cp_dispatch_indices(dev, buf, &prim); | |
c153f45f | 2351 | if (elts->discard) { |
b5e89ed5 | 2352 | radeon_cp_discard_buffer(dev, buf); |
1da177e4 LT |
2353 | } |
2354 | ||
2355 | COMMIT_RING(); | |
2356 | return 0; | |
2357 | } | |
2358 | ||
c153f45f | 2359 | static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2360 | { |
1da177e4 | 2361 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 2362 | drm_radeon_texture_t *tex = data; |
1da177e4 LT |
2363 | drm_radeon_tex_image_t image; |
2364 | int ret; | |
2365 | ||
6c340eac | 2366 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2367 | |
c153f45f | 2368 | if (tex->image == NULL) { |
b5e89ed5 | 2369 | DRM_ERROR("null texture image!\n"); |
20caafa6 | 2370 | return -EINVAL; |
1da177e4 LT |
2371 | } |
2372 | ||
b5e89ed5 | 2373 | if (DRM_COPY_FROM_USER(&image, |
c153f45f | 2374 | (drm_radeon_tex_image_t __user *) tex->image, |
b5e89ed5 | 2375 | sizeof(image))) |
20caafa6 | 2376 | return -EFAULT; |
1da177e4 | 2377 | |
b5e89ed5 DA |
2378 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2379 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 | 2380 | |
c153f45f | 2381 | ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image); |
1da177e4 | 2382 | |
1da177e4 LT |
2383 | return ret; |
2384 | } | |
2385 | ||
c153f45f | 2386 | static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2387 | { |
1da177e4 | 2388 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 2389 | drm_radeon_stipple_t *stipple = data; |
1da177e4 LT |
2390 | u32 mask[32]; |
2391 | ||
6c340eac | 2392 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2393 | |
c153f45f | 2394 | if (DRM_COPY_FROM_USER(&mask, stipple->mask, 32 * sizeof(u32))) |
20caafa6 | 2395 | return -EFAULT; |
1da177e4 | 2396 | |
b5e89ed5 | 2397 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 2398 | |
b5e89ed5 | 2399 | radeon_cp_dispatch_stipple(dev, mask); |
1da177e4 LT |
2400 | |
2401 | COMMIT_RING(); | |
2402 | return 0; | |
2403 | } | |
2404 | ||
c153f45f | 2405 | static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2406 | { |
1da177e4 | 2407 | drm_radeon_private_t *dev_priv = dev->dev_private; |
cdd55a29 | 2408 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 2409 | struct drm_buf *buf; |
c153f45f | 2410 | drm_radeon_indirect_t *indirect = data; |
1da177e4 LT |
2411 | RING_LOCALS; |
2412 | ||
6c340eac | 2413 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2414 | |
3e684eae | 2415 | DRM_DEBUG("idx=%d s=%d e=%d d=%d\n", |
c153f45f EA |
2416 | indirect->idx, indirect->start, indirect->end, |
2417 | indirect->discard); | |
1da177e4 | 2418 | |
c153f45f | 2419 | if (indirect->idx < 0 || indirect->idx >= dma->buf_count) { |
b5e89ed5 | 2420 | DRM_ERROR("buffer index %d (of %d max)\n", |
c153f45f | 2421 | indirect->idx, dma->buf_count - 1); |
20caafa6 | 2422 | return -EINVAL; |
1da177e4 LT |
2423 | } |
2424 | ||
c153f45f | 2425 | buf = dma->buflist[indirect->idx]; |
1da177e4 | 2426 | |
6c340eac | 2427 | if (buf->file_priv != file_priv) { |
b5e89ed5 | 2428 | DRM_ERROR("process %d using buffer owned by %p\n", |
6c340eac | 2429 | DRM_CURRENTPID, buf->file_priv); |
20caafa6 | 2430 | return -EINVAL; |
1da177e4 | 2431 | } |
b5e89ed5 | 2432 | if (buf->pending) { |
c153f45f | 2433 | DRM_ERROR("sending pending buffer %d\n", indirect->idx); |
20caafa6 | 2434 | return -EINVAL; |
1da177e4 LT |
2435 | } |
2436 | ||
c153f45f | 2437 | if (indirect->start < buf->used) { |
b5e89ed5 | 2438 | DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", |
c153f45f | 2439 | indirect->start, buf->used); |
20caafa6 | 2440 | return -EINVAL; |
1da177e4 LT |
2441 | } |
2442 | ||
b5e89ed5 DA |
2443 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2444 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 | 2445 | |
c153f45f | 2446 | buf->used = indirect->end; |
1da177e4 LT |
2447 | |
2448 | /* Wait for the 3D stream to idle before the indirect buffer | |
2449 | * containing 2D acceleration commands is processed. | |
2450 | */ | |
b5e89ed5 | 2451 | BEGIN_RING(2); |
1da177e4 LT |
2452 | |
2453 | RADEON_WAIT_UNTIL_3D_IDLE(); | |
2454 | ||
2455 | ADVANCE_RING(); | |
2456 | ||
2457 | /* Dispatch the indirect buffer full of commands from the | |
2458 | * X server. This is insecure and is thus only available to | |
2459 | * privileged clients. | |
2460 | */ | |
c153f45f EA |
2461 | radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); |
2462 | if (indirect->discard) { | |
b5e89ed5 | 2463 | radeon_cp_discard_buffer(dev, buf); |
1da177e4 LT |
2464 | } |
2465 | ||
1da177e4 LT |
2466 | COMMIT_RING(); |
2467 | return 0; | |
2468 | } | |
2469 | ||
c153f45f | 2470 | static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2471 | { |
1da177e4 | 2472 | drm_radeon_private_t *dev_priv = dev->dev_private; |
1da177e4 | 2473 | drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; |
cdd55a29 | 2474 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 2475 | struct drm_buf *buf; |
c153f45f | 2476 | drm_radeon_vertex2_t *vertex = data; |
1da177e4 LT |
2477 | int i; |
2478 | unsigned char laststate; | |
2479 | ||
6c340eac | 2480 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2481 | |
b5e89ed5 | 2482 | DRM_DEBUG("pid=%d index=%d discard=%d\n", |
c153f45f | 2483 | DRM_CURRENTPID, vertex->idx, vertex->discard); |
1da177e4 | 2484 | |
c153f45f | 2485 | if (vertex->idx < 0 || vertex->idx >= dma->buf_count) { |
b5e89ed5 | 2486 | DRM_ERROR("buffer index %d (of %d max)\n", |
c153f45f | 2487 | vertex->idx, dma->buf_count - 1); |
20caafa6 | 2488 | return -EINVAL; |
1da177e4 LT |
2489 | } |
2490 | ||
b5e89ed5 DA |
2491 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2492 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 | 2493 | |
c153f45f | 2494 | buf = dma->buflist[vertex->idx]; |
1da177e4 | 2495 | |
6c340eac | 2496 | if (buf->file_priv != file_priv) { |
b5e89ed5 | 2497 | DRM_ERROR("process %d using buffer owned by %p\n", |
6c340eac | 2498 | DRM_CURRENTPID, buf->file_priv); |
20caafa6 | 2499 | return -EINVAL; |
1da177e4 LT |
2500 | } |
2501 | ||
b5e89ed5 | 2502 | if (buf->pending) { |
c153f45f | 2503 | DRM_ERROR("sending pending buffer %d\n", vertex->idx); |
20caafa6 | 2504 | return -EINVAL; |
1da177e4 | 2505 | } |
b5e89ed5 | 2506 | |
1da177e4 | 2507 | if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS) |
20caafa6 | 2508 | return -EINVAL; |
1da177e4 | 2509 | |
c153f45f | 2510 | for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) { |
1da177e4 LT |
2511 | drm_radeon_prim_t prim; |
2512 | drm_radeon_tcl_prim_t tclprim; | |
b5e89ed5 | 2513 | |
c153f45f | 2514 | if (DRM_COPY_FROM_USER(&prim, &vertex->prim[i], sizeof(prim))) |
20caafa6 | 2515 | return -EFAULT; |
b5e89ed5 DA |
2516 | |
2517 | if (prim.stateidx != laststate) { | |
2518 | drm_radeon_state_t state; | |
2519 | ||
2520 | if (DRM_COPY_FROM_USER(&state, | |
c153f45f | 2521 | &vertex->state[prim.stateidx], |
b5e89ed5 | 2522 | sizeof(state))) |
20caafa6 | 2523 | return -EFAULT; |
1da177e4 | 2524 | |
6c340eac | 2525 | if (radeon_emit_state2(dev_priv, file_priv, &state)) { |
b5e89ed5 | 2526 | DRM_ERROR("radeon_emit_state2 failed\n"); |
20caafa6 | 2527 | return -EINVAL; |
1da177e4 LT |
2528 | } |
2529 | ||
2530 | laststate = prim.stateidx; | |
2531 | } | |
2532 | ||
2533 | tclprim.start = prim.start; | |
2534 | tclprim.finish = prim.finish; | |
2535 | tclprim.prim = prim.prim; | |
2536 | tclprim.vc_format = prim.vc_format; | |
2537 | ||
b5e89ed5 | 2538 | if (prim.prim & RADEON_PRIM_WALK_IND) { |
1da177e4 | 2539 | tclprim.offset = prim.numverts * 64; |
b5e89ed5 | 2540 | tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */ |
1da177e4 | 2541 | |
b5e89ed5 | 2542 | radeon_cp_dispatch_indices(dev, buf, &tclprim); |
1da177e4 LT |
2543 | } else { |
2544 | tclprim.numverts = prim.numverts; | |
b5e89ed5 | 2545 | tclprim.offset = 0; /* not used */ |
1da177e4 | 2546 | |
b5e89ed5 | 2547 | radeon_cp_dispatch_vertex(dev, buf, &tclprim); |
1da177e4 | 2548 | } |
b5e89ed5 | 2549 | |
1da177e4 LT |
2550 | if (sarea_priv->nbox == 1) |
2551 | sarea_priv->nbox = 0; | |
2552 | } | |
2553 | ||
c153f45f | 2554 | if (vertex->discard) { |
b5e89ed5 | 2555 | radeon_cp_discard_buffer(dev, buf); |
1da177e4 LT |
2556 | } |
2557 | ||
2558 | COMMIT_RING(); | |
2559 | return 0; | |
2560 | } | |
2561 | ||
b5e89ed5 | 2562 | static int radeon_emit_packets(drm_radeon_private_t * dev_priv, |
6c340eac | 2563 | struct drm_file *file_priv, |
b5e89ed5 | 2564 | drm_radeon_cmd_header_t header, |
b3a83639 | 2565 | drm_radeon_kcmd_buffer_t *cmdbuf) |
1da177e4 LT |
2566 | { |
2567 | int id = (int)header.packet.packet_id; | |
2568 | int sz, reg; | |
2569 | int *data = (int *)cmdbuf->buf; | |
2570 | RING_LOCALS; | |
b5e89ed5 | 2571 | |
1da177e4 | 2572 | if (id >= RADEON_MAX_STATE_PACKETS) |
20caafa6 | 2573 | return -EINVAL; |
1da177e4 LT |
2574 | |
2575 | sz = packet[id].len; | |
2576 | reg = packet[id].start; | |
2577 | ||
2578 | if (sz * sizeof(int) > cmdbuf->bufsz) { | |
b5e89ed5 | 2579 | DRM_ERROR("Packet size provided larger than data provided\n"); |
20caafa6 | 2580 | return -EINVAL; |
1da177e4 LT |
2581 | } |
2582 | ||
6c340eac | 2583 | if (radeon_check_and_fixup_packets(dev_priv, file_priv, id, data)) { |
b5e89ed5 | 2584 | DRM_ERROR("Packet verification failed\n"); |
20caafa6 | 2585 | return -EINVAL; |
1da177e4 LT |
2586 | } |
2587 | ||
b5e89ed5 DA |
2588 | BEGIN_RING(sz + 1); |
2589 | OUT_RING(CP_PACKET0(reg, (sz - 1))); | |
2590 | OUT_RING_TABLE(data, sz); | |
1da177e4 LT |
2591 | ADVANCE_RING(); |
2592 | ||
2593 | cmdbuf->buf += sz * sizeof(int); | |
2594 | cmdbuf->bufsz -= sz * sizeof(int); | |
2595 | return 0; | |
2596 | } | |
2597 | ||
d985c108 | 2598 | static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv, |
b5e89ed5 | 2599 | drm_radeon_cmd_header_t header, |
d985c108 | 2600 | drm_radeon_kcmd_buffer_t *cmdbuf) |
1da177e4 LT |
2601 | { |
2602 | int sz = header.scalars.count; | |
2603 | int start = header.scalars.offset; | |
2604 | int stride = header.scalars.stride; | |
2605 | RING_LOCALS; | |
2606 | ||
b5e89ed5 DA |
2607 | BEGIN_RING(3 + sz); |
2608 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); | |
2609 | OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); | |
2610 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); | |
2611 | OUT_RING_TABLE(cmdbuf->buf, sz); | |
1da177e4 LT |
2612 | ADVANCE_RING(); |
2613 | cmdbuf->buf += sz * sizeof(int); | |
2614 | cmdbuf->bufsz -= sz * sizeof(int); | |
2615 | return 0; | |
2616 | } | |
2617 | ||
2618 | /* God this is ugly | |
2619 | */ | |
d985c108 | 2620 | static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv, |
b5e89ed5 | 2621 | drm_radeon_cmd_header_t header, |
d985c108 | 2622 | drm_radeon_kcmd_buffer_t *cmdbuf) |
1da177e4 LT |
2623 | { |
2624 | int sz = header.scalars.count; | |
2625 | int start = ((unsigned int)header.scalars.offset) + 0x100; | |
2626 | int stride = header.scalars.stride; | |
2627 | RING_LOCALS; | |
2628 | ||
b5e89ed5 DA |
2629 | BEGIN_RING(3 + sz); |
2630 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0)); | |
2631 | OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); | |
2632 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1)); | |
2633 | OUT_RING_TABLE(cmdbuf->buf, sz); | |
1da177e4 LT |
2634 | ADVANCE_RING(); |
2635 | cmdbuf->buf += sz * sizeof(int); | |
2636 | cmdbuf->bufsz -= sz * sizeof(int); | |
2637 | return 0; | |
2638 | } | |
2639 | ||
d985c108 | 2640 | static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv, |
b5e89ed5 | 2641 | drm_radeon_cmd_header_t header, |
d985c108 | 2642 | drm_radeon_kcmd_buffer_t *cmdbuf) |
1da177e4 LT |
2643 | { |
2644 | int sz = header.vectors.count; | |
2645 | int start = header.vectors.offset; | |
2646 | int stride = header.vectors.stride; | |
2647 | RING_LOCALS; | |
2648 | ||
f2a2279f DA |
2649 | BEGIN_RING(5 + sz); |
2650 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); | |
b5e89ed5 DA |
2651 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); |
2652 | OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); | |
2653 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); | |
2654 | OUT_RING_TABLE(cmdbuf->buf, sz); | |
1da177e4 LT |
2655 | ADVANCE_RING(); |
2656 | ||
2657 | cmdbuf->buf += sz * sizeof(int); | |
2658 | cmdbuf->bufsz -= sz * sizeof(int); | |
2659 | return 0; | |
2660 | } | |
2661 | ||
d6fece05 DA |
2662 | static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, |
2663 | drm_radeon_cmd_header_t header, | |
2664 | drm_radeon_kcmd_buffer_t *cmdbuf) | |
2665 | { | |
2666 | int sz = header.veclinear.count * 4; | |
2667 | int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8); | |
2668 | RING_LOCALS; | |
2669 | ||
2670 | if (!sz) | |
2671 | return 0; | |
2672 | if (sz * 4 > cmdbuf->bufsz) | |
20caafa6 | 2673 | return -EINVAL; |
d6fece05 DA |
2674 | |
2675 | BEGIN_RING(5 + sz); | |
2676 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); | |
2677 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); | |
2678 | OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); | |
2679 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); | |
2680 | OUT_RING_TABLE(cmdbuf->buf, sz); | |
2681 | ADVANCE_RING(); | |
2682 | ||
2683 | cmdbuf->buf += sz * sizeof(int); | |
2684 | cmdbuf->bufsz -= sz * sizeof(int); | |
2685 | return 0; | |
2686 | } | |
2687 | ||
84b1fd10 | 2688 | static int radeon_emit_packet3(struct drm_device * dev, |
6c340eac | 2689 | struct drm_file *file_priv, |
b3a83639 | 2690 | drm_radeon_kcmd_buffer_t *cmdbuf) |
1da177e4 LT |
2691 | { |
2692 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2693 | unsigned int cmdsz; | |
2694 | int ret; | |
2695 | RING_LOCALS; | |
2696 | ||
2697 | DRM_DEBUG("\n"); | |
2698 | ||
6c340eac | 2699 | if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, |
b5e89ed5 DA |
2700 | cmdbuf, &cmdsz))) { |
2701 | DRM_ERROR("Packet verification failed\n"); | |
1da177e4 LT |
2702 | return ret; |
2703 | } | |
2704 | ||
b5e89ed5 DA |
2705 | BEGIN_RING(cmdsz); |
2706 | OUT_RING_TABLE(cmdbuf->buf, cmdsz); | |
1da177e4 LT |
2707 | ADVANCE_RING(); |
2708 | ||
2709 | cmdbuf->buf += cmdsz * 4; | |
2710 | cmdbuf->bufsz -= cmdsz * 4; | |
2711 | return 0; | |
2712 | } | |
2713 | ||
84b1fd10 | 2714 | static int radeon_emit_packet3_cliprect(struct drm_device *dev, |
6c340eac | 2715 | struct drm_file *file_priv, |
b3a83639 | 2716 | drm_radeon_kcmd_buffer_t *cmdbuf, |
b5e89ed5 | 2717 | int orig_nbox) |
1da177e4 LT |
2718 | { |
2719 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
c60ce623 | 2720 | struct drm_clip_rect box; |
1da177e4 LT |
2721 | unsigned int cmdsz; |
2722 | int ret; | |
c60ce623 | 2723 | struct drm_clip_rect __user *boxes = cmdbuf->boxes; |
1da177e4 LT |
2724 | int i = 0; |
2725 | RING_LOCALS; | |
2726 | ||
2727 | DRM_DEBUG("\n"); | |
2728 | ||
6c340eac | 2729 | if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv, |
b5e89ed5 DA |
2730 | cmdbuf, &cmdsz))) { |
2731 | DRM_ERROR("Packet verification failed\n"); | |
1da177e4 LT |
2732 | return ret; |
2733 | } | |
2734 | ||
2735 | if (!orig_nbox) | |
2736 | goto out; | |
2737 | ||
2738 | do { | |
b5e89ed5 DA |
2739 | if (i < cmdbuf->nbox) { |
2740 | if (DRM_COPY_FROM_USER(&box, &boxes[i], sizeof(box))) | |
20caafa6 | 2741 | return -EFAULT; |
1da177e4 LT |
2742 | /* FIXME The second and subsequent times round |
2743 | * this loop, send a WAIT_UNTIL_3D_IDLE before | |
2744 | * calling emit_clip_rect(). This fixes a | |
2745 | * lockup on fast machines when sending | |
2746 | * several cliprects with a cmdbuf, as when | |
2747 | * waving a 2D window over a 3D | |
2748 | * window. Something in the commands from user | |
2749 | * space seems to hang the card when they're | |
2750 | * sent several times in a row. That would be | |
2751 | * the correct place to fix it but this works | |
2752 | * around it until I can figure that out - Tim | |
2753 | * Smith */ | |
b5e89ed5 DA |
2754 | if (i) { |
2755 | BEGIN_RING(2); | |
1da177e4 LT |
2756 | RADEON_WAIT_UNTIL_3D_IDLE(); |
2757 | ADVANCE_RING(); | |
2758 | } | |
b5e89ed5 | 2759 | radeon_emit_clip_rect(dev_priv, &box); |
1da177e4 | 2760 | } |
b5e89ed5 DA |
2761 | |
2762 | BEGIN_RING(cmdsz); | |
2763 | OUT_RING_TABLE(cmdbuf->buf, cmdsz); | |
1da177e4 LT |
2764 | ADVANCE_RING(); |
2765 | ||
b5e89ed5 DA |
2766 | } while (++i < cmdbuf->nbox); |
2767 | if (cmdbuf->nbox == 1) | |
1da177e4 LT |
2768 | cmdbuf->nbox = 0; |
2769 | ||
b5e89ed5 | 2770 | out: |
1da177e4 LT |
2771 | cmdbuf->buf += cmdsz * 4; |
2772 | cmdbuf->bufsz -= cmdsz * 4; | |
2773 | return 0; | |
2774 | } | |
2775 | ||
84b1fd10 | 2776 | static int radeon_emit_wait(struct drm_device * dev, int flags) |
1da177e4 LT |
2777 | { |
2778 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
2779 | RING_LOCALS; | |
2780 | ||
3e684eae | 2781 | DRM_DEBUG("%x\n", flags); |
1da177e4 LT |
2782 | switch (flags) { |
2783 | case RADEON_WAIT_2D: | |
b5e89ed5 DA |
2784 | BEGIN_RING(2); |
2785 | RADEON_WAIT_UNTIL_2D_IDLE(); | |
1da177e4 LT |
2786 | ADVANCE_RING(); |
2787 | break; | |
2788 | case RADEON_WAIT_3D: | |
b5e89ed5 DA |
2789 | BEGIN_RING(2); |
2790 | RADEON_WAIT_UNTIL_3D_IDLE(); | |
1da177e4 LT |
2791 | ADVANCE_RING(); |
2792 | break; | |
b5e89ed5 DA |
2793 | case RADEON_WAIT_2D | RADEON_WAIT_3D: |
2794 | BEGIN_RING(2); | |
2795 | RADEON_WAIT_UNTIL_IDLE(); | |
1da177e4 LT |
2796 | ADVANCE_RING(); |
2797 | break; | |
2798 | default: | |
20caafa6 | 2799 | return -EINVAL; |
1da177e4 LT |
2800 | } |
2801 | ||
2802 | return 0; | |
2803 | } | |
2804 | ||
c153f45f | 2805 | static int radeon_cp_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2806 | { |
1da177e4 | 2807 | drm_radeon_private_t *dev_priv = dev->dev_private; |
cdd55a29 | 2808 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 2809 | struct drm_buf *buf = NULL; |
1da177e4 | 2810 | int idx; |
c153f45f | 2811 | drm_radeon_kcmd_buffer_t *cmdbuf = data; |
1da177e4 LT |
2812 | drm_radeon_cmd_header_t header; |
2813 | int orig_nbox, orig_bufsz; | |
b5e89ed5 | 2814 | char *kbuf = NULL; |
1da177e4 | 2815 | |
6c340eac | 2816 | LOCK_TEST_WITH_RETURN(dev, file_priv); |
1da177e4 | 2817 | |
b5e89ed5 DA |
2818 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
2819 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 | 2820 | |
c153f45f | 2821 | if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) { |
20caafa6 | 2822 | return -EINVAL; |
1da177e4 LT |
2823 | } |
2824 | ||
2825 | /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid | |
2826 | * races between checking values and using those values in other code, | |
2827 | * and simply to avoid a lot of function calls to copy in data. | |
2828 | */ | |
c153f45f | 2829 | orig_bufsz = cmdbuf->bufsz; |
1da177e4 | 2830 | if (orig_bufsz != 0) { |
c153f45f | 2831 | kbuf = drm_alloc(cmdbuf->bufsz, DRM_MEM_DRIVER); |
1da177e4 | 2832 | if (kbuf == NULL) |
20caafa6 | 2833 | return -ENOMEM; |
c153f45f EA |
2834 | if (DRM_COPY_FROM_USER(kbuf, (void __user *)cmdbuf->buf, |
2835 | cmdbuf->bufsz)) { | |
1da177e4 | 2836 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); |
20caafa6 | 2837 | return -EFAULT; |
1da177e4 | 2838 | } |
c153f45f | 2839 | cmdbuf->buf = kbuf; |
1da177e4 LT |
2840 | } |
2841 | ||
c153f45f | 2842 | orig_nbox = cmdbuf->nbox; |
1da177e4 | 2843 | |
b5e89ed5 | 2844 | if (dev_priv->microcode_version == UCODE_R300) { |
414ed537 | 2845 | int temp; |
c153f45f | 2846 | temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf); |
b5e89ed5 | 2847 | |
414ed537 DA |
2848 | if (orig_bufsz != 0) |
2849 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); | |
b5e89ed5 | 2850 | |
414ed537 DA |
2851 | return temp; |
2852 | } | |
2853 | ||
2854 | /* microcode_version != r300 */ | |
c153f45f | 2855 | while (cmdbuf->bufsz >= sizeof(header)) { |
1da177e4 | 2856 | |
c153f45f EA |
2857 | header.i = *(int *)cmdbuf->buf; |
2858 | cmdbuf->buf += sizeof(header); | |
2859 | cmdbuf->bufsz -= sizeof(header); | |
1da177e4 LT |
2860 | |
2861 | switch (header.header.cmd_type) { | |
b5e89ed5 | 2862 | case RADEON_CMD_PACKET: |
1da177e4 | 2863 | DRM_DEBUG("RADEON_CMD_PACKET\n"); |
b5e89ed5 | 2864 | if (radeon_emit_packets |
c153f45f | 2865 | (dev_priv, file_priv, header, cmdbuf)) { |
1da177e4 LT |
2866 | DRM_ERROR("radeon_emit_packets failed\n"); |
2867 | goto err; | |
2868 | } | |
2869 | break; | |
2870 | ||
2871 | case RADEON_CMD_SCALARS: | |
2872 | DRM_DEBUG("RADEON_CMD_SCALARS\n"); | |
c153f45f | 2873 | if (radeon_emit_scalars(dev_priv, header, cmdbuf)) { |
1da177e4 LT |
2874 | DRM_ERROR("radeon_emit_scalars failed\n"); |
2875 | goto err; | |
2876 | } | |
2877 | break; | |
2878 | ||
2879 | case RADEON_CMD_VECTORS: | |
2880 | DRM_DEBUG("RADEON_CMD_VECTORS\n"); | |
c153f45f | 2881 | if (radeon_emit_vectors(dev_priv, header, cmdbuf)) { |
1da177e4 LT |
2882 | DRM_ERROR("radeon_emit_vectors failed\n"); |
2883 | goto err; | |
2884 | } | |
2885 | break; | |
2886 | ||
2887 | case RADEON_CMD_DMA_DISCARD: | |
2888 | DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n"); | |
2889 | idx = header.dma.buf_idx; | |
b5e89ed5 DA |
2890 | if (idx < 0 || idx >= dma->buf_count) { |
2891 | DRM_ERROR("buffer index %d (of %d max)\n", | |
2892 | idx, dma->buf_count - 1); | |
1da177e4 LT |
2893 | goto err; |
2894 | } | |
2895 | ||
2896 | buf = dma->buflist[idx]; | |
6c340eac | 2897 | if (buf->file_priv != file_priv || buf->pending) { |
b5e89ed5 | 2898 | DRM_ERROR("bad buffer %p %p %d\n", |
6c340eac EA |
2899 | buf->file_priv, file_priv, |
2900 | buf->pending); | |
1da177e4 LT |
2901 | goto err; |
2902 | } | |
2903 | ||
b5e89ed5 | 2904 | radeon_cp_discard_buffer(dev, buf); |
1da177e4 LT |
2905 | break; |
2906 | ||
2907 | case RADEON_CMD_PACKET3: | |
2908 | DRM_DEBUG("RADEON_CMD_PACKET3\n"); | |
c153f45f | 2909 | if (radeon_emit_packet3(dev, file_priv, cmdbuf)) { |
1da177e4 LT |
2910 | DRM_ERROR("radeon_emit_packet3 failed\n"); |
2911 | goto err; | |
2912 | } | |
2913 | break; | |
2914 | ||
2915 | case RADEON_CMD_PACKET3_CLIP: | |
2916 | DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n"); | |
b5e89ed5 | 2917 | if (radeon_emit_packet3_cliprect |
c153f45f | 2918 | (dev, file_priv, cmdbuf, orig_nbox)) { |
1da177e4 LT |
2919 | DRM_ERROR("radeon_emit_packet3_clip failed\n"); |
2920 | goto err; | |
2921 | } | |
2922 | break; | |
2923 | ||
2924 | case RADEON_CMD_SCALARS2: | |
2925 | DRM_DEBUG("RADEON_CMD_SCALARS2\n"); | |
c153f45f | 2926 | if (radeon_emit_scalars2(dev_priv, header, cmdbuf)) { |
1da177e4 LT |
2927 | DRM_ERROR("radeon_emit_scalars2 failed\n"); |
2928 | goto err; | |
2929 | } | |
2930 | break; | |
2931 | ||
2932 | case RADEON_CMD_WAIT: | |
2933 | DRM_DEBUG("RADEON_CMD_WAIT\n"); | |
b5e89ed5 | 2934 | if (radeon_emit_wait(dev, header.wait.flags)) { |
1da177e4 LT |
2935 | DRM_ERROR("radeon_emit_wait failed\n"); |
2936 | goto err; | |
2937 | } | |
2938 | break; | |
d6fece05 DA |
2939 | case RADEON_CMD_VECLINEAR: |
2940 | DRM_DEBUG("RADEON_CMD_VECLINEAR\n"); | |
c153f45f | 2941 | if (radeon_emit_veclinear(dev_priv, header, cmdbuf)) { |
d6fece05 DA |
2942 | DRM_ERROR("radeon_emit_veclinear failed\n"); |
2943 | goto err; | |
2944 | } | |
2945 | break; | |
2946 | ||
1da177e4 | 2947 | default: |
b5e89ed5 | 2948 | DRM_ERROR("bad cmd_type %d at %p\n", |
1da177e4 | 2949 | header.header.cmd_type, |
c153f45f | 2950 | cmdbuf->buf - sizeof(header)); |
1da177e4 LT |
2951 | goto err; |
2952 | } | |
2953 | } | |
2954 | ||
2955 | if (orig_bufsz != 0) | |
2956 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); | |
2957 | ||
2958 | DRM_DEBUG("DONE\n"); | |
2959 | COMMIT_RING(); | |
2960 | return 0; | |
2961 | ||
b5e89ed5 | 2962 | err: |
1da177e4 LT |
2963 | if (orig_bufsz != 0) |
2964 | drm_free(kbuf, orig_bufsz, DRM_MEM_DRIVER); | |
20caafa6 | 2965 | return -EINVAL; |
1da177e4 LT |
2966 | } |
2967 | ||
c153f45f | 2968 | static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv) |
1da177e4 | 2969 | { |
1da177e4 | 2970 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 2971 | drm_radeon_getparam_t *param = data; |
1da177e4 LT |
2972 | int value; |
2973 | ||
b5e89ed5 | 2974 | DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); |
1da177e4 | 2975 | |
c153f45f | 2976 | switch (param->param) { |
1da177e4 LT |
2977 | case RADEON_PARAM_GART_BUFFER_OFFSET: |
2978 | value = dev_priv->gart_buffers_offset; | |
2979 | break; | |
2980 | case RADEON_PARAM_LAST_FRAME: | |
2981 | dev_priv->stats.last_frame_reads++; | |
b5e89ed5 | 2982 | value = GET_SCRATCH(0); |
1da177e4 LT |
2983 | break; |
2984 | case RADEON_PARAM_LAST_DISPATCH: | |
b5e89ed5 | 2985 | value = GET_SCRATCH(1); |
1da177e4 LT |
2986 | break; |
2987 | case RADEON_PARAM_LAST_CLEAR: | |
2988 | dev_priv->stats.last_clear_reads++; | |
b5e89ed5 | 2989 | value = GET_SCRATCH(2); |
1da177e4 LT |
2990 | break; |
2991 | case RADEON_PARAM_IRQ_NR: | |
2992 | value = dev->irq; | |
2993 | break; | |
2994 | case RADEON_PARAM_GART_BASE: | |
2995 | value = dev_priv->gart_vm_start; | |
2996 | break; | |
2997 | case RADEON_PARAM_REGISTER_HANDLE: | |
d985c108 | 2998 | value = dev_priv->mmio->offset; |
1da177e4 LT |
2999 | break; |
3000 | case RADEON_PARAM_STATUS_HANDLE: | |
3001 | value = dev_priv->ring_rptr_offset; | |
3002 | break; | |
3003 | #if BITS_PER_LONG == 32 | |
b5e89ed5 DA |
3004 | /* |
3005 | * This ioctl() doesn't work on 64-bit platforms because hw_lock is a | |
3006 | * pointer which can't fit into an int-sized variable. According to | |
96de0e25 | 3007 | * Michel Dänzer, the ioctl() is only used on embedded platforms, so |
b5e89ed5 DA |
3008 | * not supporting it shouldn't be a problem. If the same functionality |
3009 | * is needed on 64-bit platforms, a new ioctl() would have to be added, | |
3010 | * so backwards-compatibility for the embedded platforms can be | |
3011 | * maintained. --davidm 4-Feb-2004. | |
3012 | */ | |
1da177e4 LT |
3013 | case RADEON_PARAM_SAREA_HANDLE: |
3014 | /* The lock is the first dword in the sarea. */ | |
3015 | value = (long)dev->lock.hw_lock; | |
3016 | break; | |
3017 | #endif | |
3018 | case RADEON_PARAM_GART_TEX_HANDLE: | |
3019 | value = dev_priv->gart_textures_offset; | |
3020 | break; | |
8624ecbf MD |
3021 | case RADEON_PARAM_SCRATCH_OFFSET: |
3022 | if (!dev_priv->writeback_works) | |
20caafa6 | 3023 | return -EINVAL; |
8624ecbf MD |
3024 | value = RADEON_SCRATCH_REG_OFFSET; |
3025 | break; | |
d985c108 | 3026 | case RADEON_PARAM_CARD_TYPE: |
54a56ac5 | 3027 | if (dev_priv->flags & RADEON_IS_PCIE) |
d985c108 | 3028 | value = RADEON_CARD_PCIE; |
54a56ac5 | 3029 | else if (dev_priv->flags & RADEON_IS_AGP) |
d985c108 DA |
3030 | value = RADEON_CARD_AGP; |
3031 | else | |
3032 | value = RADEON_CARD_PCI; | |
3033 | break; | |
ddbee333 DA |
3034 | case RADEON_PARAM_VBLANK_CRTC: |
3035 | value = radeon_vblank_crtc_get(dev); | |
3036 | break; | |
1da177e4 | 3037 | default: |
c153f45f | 3038 | DRM_DEBUG("Invalid parameter %d\n", param->param); |
20caafa6 | 3039 | return -EINVAL; |
1da177e4 LT |
3040 | } |
3041 | ||
c153f45f | 3042 | if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) { |
b5e89ed5 | 3043 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 3044 | return -EFAULT; |
1da177e4 | 3045 | } |
b5e89ed5 | 3046 | |
1da177e4 LT |
3047 | return 0; |
3048 | } | |
3049 | ||
c153f45f | 3050 | static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv) |
b5e89ed5 | 3051 | { |
1da177e4 | 3052 | drm_radeon_private_t *dev_priv = dev->dev_private; |
c153f45f | 3053 | drm_radeon_setparam_t *sp = data; |
1da177e4 LT |
3054 | struct drm_radeon_driver_file_fields *radeon_priv; |
3055 | ||
c153f45f | 3056 | switch (sp->param) { |
1da177e4 | 3057 | case RADEON_SETPARAM_FB_LOCATION: |
6c340eac | 3058 | radeon_priv = file_priv->driver_priv; |
c153f45f EA |
3059 | radeon_priv->radeon_fb_delta = dev_priv->fb_location - |
3060 | sp->value; | |
1da177e4 LT |
3061 | break; |
3062 | case RADEON_SETPARAM_SWITCH_TILING: | |
c153f45f | 3063 | if (sp->value == 0) { |
b5e89ed5 | 3064 | DRM_DEBUG("color tiling disabled\n"); |
1da177e4 LT |
3065 | dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO; |
3066 | dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO; | |
3067 | dev_priv->sarea_priv->tiling_enabled = 0; | |
c153f45f | 3068 | } else if (sp->value == 1) { |
b5e89ed5 | 3069 | DRM_DEBUG("color tiling enabled\n"); |
1da177e4 LT |
3070 | dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO; |
3071 | dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO; | |
3072 | dev_priv->sarea_priv->tiling_enabled = 1; | |
3073 | } | |
b5e89ed5 | 3074 | break; |
ea98a92f | 3075 | case RADEON_SETPARAM_PCIGART_LOCATION: |
c153f45f | 3076 | dev_priv->pcigart_offset = sp->value; |
f2b04cd2 | 3077 | dev_priv->pcigart_offset_set = 1; |
ea98a92f | 3078 | break; |
d5ea702f | 3079 | case RADEON_SETPARAM_NEW_MEMMAP: |
c153f45f | 3080 | dev_priv->new_memmap = sp->value; |
d5ea702f | 3081 | break; |
f2b04cd2 | 3082 | case RADEON_SETPARAM_PCIGART_TABLE_SIZE: |
c153f45f | 3083 | dev_priv->gart_info.table_size = sp->value; |
f2b04cd2 DA |
3084 | if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE) |
3085 | dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; | |
3086 | break; | |
ddbee333 | 3087 | case RADEON_SETPARAM_VBLANK_CRTC: |
c153f45f | 3088 | return radeon_vblank_crtc_set(dev, sp->value); |
ddbee333 | 3089 | break; |
1da177e4 | 3090 | default: |
c153f45f | 3091 | DRM_DEBUG("Invalid parameter %d\n", sp->param); |
20caafa6 | 3092 | return -EINVAL; |
1da177e4 LT |
3093 | } |
3094 | ||
3095 | return 0; | |
3096 | } | |
3097 | ||
3098 | /* When a client dies: | |
3099 | * - Check for and clean up flipped page state | |
3100 | * - Free any alloced GART memory. | |
d985c108 | 3101 | * - Free any alloced radeon surfaces. |
1da177e4 LT |
3102 | * |
3103 | * DRM infrastructure takes care of reclaiming dma buffers. | |
3104 | */ | |
6c340eac | 3105 | void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv) |
1da177e4 | 3106 | { |
b5e89ed5 DA |
3107 | if (dev->dev_private) { |
3108 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
453ff94c | 3109 | dev_priv->page_flipping = 0; |
6c340eac EA |
3110 | radeon_mem_release(file_priv, dev_priv->gart_heap); |
3111 | radeon_mem_release(file_priv, dev_priv->fb_heap); | |
3112 | radeon_surfaces_release(file_priv, dev_priv); | |
b5e89ed5 | 3113 | } |
1da177e4 LT |
3114 | } |
3115 | ||
84b1fd10 | 3116 | void radeon_driver_lastclose(struct drm_device *dev) |
1da177e4 | 3117 | { |
453ff94c MD |
3118 | if (dev->dev_private) { |
3119 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
3120 | ||
3121 | if (dev_priv->sarea_priv && | |
3122 | dev_priv->sarea_priv->pfCurrentPage != 0) | |
3123 | radeon_cp_dispatch_flip(dev); | |
3124 | } | |
3125 | ||
1da177e4 LT |
3126 | radeon_do_release(dev); |
3127 | } | |
3128 | ||
6c340eac | 3129 | int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv) |
1da177e4 LT |
3130 | { |
3131 | drm_radeon_private_t *dev_priv = dev->dev_private; | |
3132 | struct drm_radeon_driver_file_fields *radeon_priv; | |
b5e89ed5 | 3133 | |
d985c108 | 3134 | DRM_DEBUG("\n"); |
b5e89ed5 DA |
3135 | radeon_priv = |
3136 | (struct drm_radeon_driver_file_fields *) | |
3137 | drm_alloc(sizeof(*radeon_priv), DRM_MEM_FILES); | |
3138 | ||
1da177e4 LT |
3139 | if (!radeon_priv) |
3140 | return -ENOMEM; | |
3141 | ||
6c340eac | 3142 | file_priv->driver_priv = radeon_priv; |
d985c108 | 3143 | |
b5e89ed5 | 3144 | if (dev_priv) |
1da177e4 LT |
3145 | radeon_priv->radeon_fb_delta = dev_priv->fb_location; |
3146 | else | |
3147 | radeon_priv->radeon_fb_delta = 0; | |
3148 | return 0; | |
3149 | } | |
3150 | ||
6c340eac | 3151 | void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) |
1da177e4 | 3152 | { |
b5e89ed5 | 3153 | struct drm_radeon_driver_file_fields *radeon_priv = |
6c340eac | 3154 | file_priv->driver_priv; |
b5e89ed5 DA |
3155 | |
3156 | drm_free(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES); | |
1da177e4 LT |
3157 | } |
3158 | ||
c153f45f EA |
3159 | struct drm_ioctl_desc radeon_ioctls[] = { |
3160 | DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3161 | DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3162 | DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3163 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3164 | DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH), | |
3165 | DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH), | |
3166 | DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset, DRM_AUTH), | |
3167 | DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH), | |
3168 | DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap, DRM_AUTH), | |
3169 | DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear, DRM_AUTH), | |
3170 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH), | |
3171 | DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices, DRM_AUTH), | |
3172 | DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH), | |
3173 | DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH), | |
3174 | DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3175 | DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH), | |
3176 | DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH), | |
3177 | DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH), | |
3178 | DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip, DRM_AUTH), | |
3179 | DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH), | |
3180 | DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free, DRM_AUTH), | |
3181 | DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), | |
3182 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH), | |
3183 | DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH), | |
3184 | DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH), | |
3185 | DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH), | |
3186 | DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH) | |
1da177e4 LT |
3187 | }; |
3188 | ||
3189 | int radeon_max_ioctl = DRM_ARRAY_SIZE(radeon_ioctls); |