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drm/r500: add support for AGP based cards.
[net-next-2.6.git] / drivers / char / drm / radeon_drv.h
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1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
c0beb2a7 41#define DRIVER_DATE "20080528"
1da177e4
LT		 42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 71 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
d985c108 76 * (No 3D support yet - just microcode loading).
1da177e4
LT		 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 90 * 1.19- Add support for gart table in FB memory and PCIE r300
d985c108
DA		 91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
4e5e2e25 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
d5ea702f 94 * 1.23- Add new radeon memory map work from benh
ee4621f0 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
d6fece05
DA		 96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
f2b04cd2
DA		 98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
ddbee333 100 * 1.28- Add support for VBL on CRTC2
c0beb2a7 101 * 1.29- R500 3D cmd buffer support
1da177e4
LT		 102 */
103#define DRIVER_MAJOR 1
c0beb2a7 104#define DRIVER_MINOR 29
1da177e4
LT		 105#define DRIVER_PATCHLEVEL 0
106
1da177e4
LT		 107/*
108 * Radeon chip families
109 */
110enum radeon_family {
111 CHIP_R100,
1da177e4 112 CHIP_RV100,
dfab1154 113 CHIP_RS100,
1da177e4
LT		 114 CHIP_RV200,
115 CHIP_RS200,
dfab1154 116 CHIP_R200,
1da177e4 117 CHIP_RV250,
dfab1154 118 CHIP_RS300,
1da177e4
LT		 119 CHIP_RV280,
120 CHIP_R300,
414ed537 121 CHIP_R350,
1da177e4 122 CHIP_RV350,
dfab1154 123 CHIP_RV380,
414ed537 124 CHIP_R420,
dfab1154 125 CHIP_RV410,
45e51905 126 CHIP_RS480,
60f92683 127 CHIP_RS690,
3d5e2c13
DA		 128 CHIP_RV515,
129 CHIP_R520,
130 CHIP_RV530,
131 CHIP_RV560,
132 CHIP_RV570,
133 CHIP_R580,
1da177e4
LT		 134 CHIP_LAST,
135};
136
137enum radeon_cp_microcode_version {
138 UCODE_R100,
139 UCODE_R200,
140 UCODE_R300,
141};
142
143/*
144 * Chip flags
145 */
146enum radeon_chip_flags {
54a56ac5
DA		 147 RADEON_FAMILY_MASK = 0x0000ffffUL,
148 RADEON_FLAGS_MASK = 0xffff0000UL,
149 RADEON_IS_MOBILITY = 0x00010000UL,
150 RADEON_IS_IGP = 0x00020000UL,
151 RADEON_SINGLE_CRTC = 0x00040000UL,
152 RADEON_IS_AGP = 0x00080000UL,
153 RADEON_HAS_HIERZ = 0x00100000UL,
154 RADEON_IS_PCIE = 0x00200000UL,
155 RADEON_NEW_MEMMAP = 0x00400000UL,
156 RADEON_IS_PCI = 0x00800000UL,
f2b04cd2 157 RADEON_IS_IGPGART = 0x01000000UL,
1da177e4
LT		 158};
159
d5ea702f
DA		 160#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
161 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
d985c108
DA		 162#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
163
1da177e4 164typedef struct drm_radeon_freelist {
b5e89ed5 165 unsigned int age;
056219e2 166 struct drm_buf *buf;
b5e89ed5
DA		 167 struct drm_radeon_freelist *next;
168 struct drm_radeon_freelist *prev;
1da177e4
LT		 169} drm_radeon_freelist_t;
170
171typedef struct drm_radeon_ring_buffer {
172 u32 *start;
173 u32 *end;
174 int size;
175 int size_l2qw;
176
576cc458
RS		 177 int rptr_update; /* Double Words */
178 int rptr_update_l2qw; /* log2 Quad Words */
179
180 int fetch_size; /* Double Words */
181 int fetch_size_l2ow; /* log2 Oct Words */
182
1da177e4
LT		 183 u32 tail;
184 u32 tail_mask;
185 int space;
186
187 int high_mark;
188} drm_radeon_ring_buffer_t;
189
190typedef struct drm_radeon_depth_clear_t {
191 u32 rb3d_cntl;
192 u32 rb3d_zstencilcntl;
193 u32 se_cntl;
194} drm_radeon_depth_clear_t;
195
196struct drm_radeon_driver_file_fields {
197 int64_t radeon_fb_delta;
198};
199
200struct mem_block {
201 struct mem_block *next;
202 struct mem_block *prev;
203 int start;
204 int size;
6c340eac 205 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 206};
207
208struct radeon_surface {
209 int refcount;
210 u32 lower;
211 u32 upper;
212 u32 flags;
213};
214
215struct radeon_virt_surface {
216 int surface_index;
217 u32 lower;
218 u32 upper;
219 u32 flags;
6c340eac 220 struct drm_file *file_priv;
1da177e4
LT		 221};
222
223typedef struct drm_radeon_private {
224 drm_radeon_ring_buffer_t ring;
225 drm_radeon_sarea_t *sarea_priv;
226
227 u32 fb_location;
d5ea702f
DA		 228 u32 fb_size;
229 int new_memmap;
1da177e4
LT		 230
231 int gart_size;
232 u32 gart_vm_start;
233 unsigned long gart_buffers_offset;
234
235 int cp_mode;
236 int cp_running;
237
b5e89ed5
DA		 238 drm_radeon_freelist_t *head;
239 drm_radeon_freelist_t *tail;
1da177e4
LT		 240 int last_buf;
241 volatile u32 *scratch;
242 int writeback_works;
243
244 int usec_timeout;
245
246 int microcode_version;
247
1da177e4
LT		 248 struct {
249 u32 boxes;
250 int freelist_timeouts;
251 int freelist_loops;
252 int requested_bufs;
253 int last_frame_reads;
254 int last_clear_reads;
255 int clears;
256 int texture_uploads;
257 } stats;
258
259 int do_boxes;
260 int page_flipping;
1da177e4
LT		 261
262 u32 color_fmt;
263 unsigned int front_offset;
264 unsigned int front_pitch;
265 unsigned int back_offset;
266 unsigned int back_pitch;
267
268 u32 depth_fmt;
269 unsigned int depth_offset;
270 unsigned int depth_pitch;
271
272 u32 front_pitch_offset;
273 u32 back_pitch_offset;
274 u32 depth_pitch_offset;
275
276 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 277
1da177e4
LT		 278 unsigned long ring_offset;
279 unsigned long ring_rptr_offset;
280 unsigned long buffers_offset;
281 unsigned long gart_textures_offset;
282
283 drm_local_map_t *sarea;
284 drm_local_map_t *mmio;
285 drm_local_map_t *cp_ring;
286 drm_local_map_t *ring_rptr;
287 drm_local_map_t *gart_textures;
288
289 struct mem_block *gart_heap;
290 struct mem_block *fb_heap;
291
292 /* SW interrupt */
b5e89ed5
DA		 293 wait_queue_head_t swi_queue;
294 atomic_t swi_emitted;
ddbee333
DA		 295 int vblank_crtc;
296 uint32_t irq_enable_reg;
297 int irq_enabled;
c0beb2a7 298 uint32_t r500_disp_irq_reg;
1da177e4
LT		 299
300 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 301 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 302
b5e89ed5 303 unsigned long pcigart_offset;
f2b04cd2 304 unsigned int pcigart_offset_set;
55910517 305 struct drm_ati_pcigart_info gart_info;
ea98a92f 306
ee4621f0
DA		 307 u32 scratch_ages[5];
308
1da177e4
LT		 309 /* starting from here on, data is preserved accross an open */
310 uint32_t flags; /* see radeon_chip_flags */
7fc86860 311 unsigned long fb_aper_offset;
5b92c404
AD		 312
313 int num_gb_pipes;
1da177e4
LT		 314} drm_radeon_private_t;
315
316typedef struct drm_radeon_buf_priv {
317 u32 age;
318} drm_radeon_buf_priv_t;
319
b3a83639
DA		 320typedef struct drm_radeon_kcmd_buffer {
321 int bufsz;
322 char *buf;
323 int nbox;
c60ce623 324 struct drm_clip_rect __user *boxes;
b3a83639
DA		 325} drm_radeon_kcmd_buffer_t;
326
689b9d74 327extern int radeon_no_wb;
c153f45f 328extern struct drm_ioctl_desc radeon_ioctls[];
b3a83639
DA		 329extern int radeon_max_ioctl;
330
1d6bb8e5
MD		 331/* Check whether the given hardware address is inside the framebuffer or the
332 * GART area.
333 */
334static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
335 u64 off)
336{
337 u32 fb_start = dev_priv->fb_location;
338 u32 fb_end = fb_start + dev_priv->fb_size - 1;
339 u32 gart_start = dev_priv->gart_vm_start;
340 u32 gart_end = gart_start + dev_priv->gart_size - 1;
341
342 return ((off >= fb_start && off <= fb_end) ||
343 (off >= gart_start && off <= gart_end));
344}
345
1da177e4 346 /* radeon_cp.c */
c153f45f
EA		 347extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
348extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
349extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
350extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
351extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
352extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
353extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
354extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
355extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
3d5e2c13 356extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
1da177e4 357
84b1fd10 358extern void radeon_freelist_reset(struct drm_device * dev);
056219e2 359extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
1da177e4 360
b5e89ed5 361extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 362
b5e89ed5 363extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 364
365extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 366extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 367extern int radeon_driver_postcleanup(struct drm_device *dev);
368
c153f45f
EA		 369extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
370extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
371extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 372extern void radeon_mem_takedown(struct mem_block **heap);
6c340eac
EA		 373extern void radeon_mem_release(struct drm_file *file_priv,
374 struct mem_block *heap);
1da177e4
LT		 375
376 /* radeon_irq.c */
c153f45f
EA		 377extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
378extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
b5e89ed5 379
84b1fd10 380extern void radeon_do_release(struct drm_device * dev);
af6061af
DA		 381extern int radeon_driver_vblank_wait(struct drm_device * dev,
382 unsigned int *sequence);
383extern int radeon_driver_vblank_wait2(struct drm_device * dev,
384 unsigned int *sequence);
b5e89ed5 385extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 386extern void radeon_driver_irq_preinstall(struct drm_device * dev);
af6061af 387extern void radeon_driver_irq_postinstall(struct drm_device * dev);
84b1fd10
DA		 388extern void radeon_driver_irq_uninstall(struct drm_device * dev);
389extern int radeon_vblank_crtc_get(struct drm_device *dev);
390extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
1da177e4 391
22eae947
DA		 392extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
393extern int radeon_driver_unload(struct drm_device *dev);
394extern int radeon_driver_firstopen(struct drm_device *dev);
6c340eac 395extern void radeon_driver_preclose(struct drm_device * dev, struct drm_file *file_priv);
84b1fd10
DA		 396extern void radeon_driver_postclose(struct drm_device * dev, struct drm_file * filp);
397extern void radeon_driver_lastclose(struct drm_device * dev);
398extern int radeon_driver_open(struct drm_device * dev, struct drm_file * filp_priv);
9a186645
DA		 399extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
400 unsigned long arg);
401
414ed537 402/* r300_cmdbuf.c */
3d5e2c13 403extern void r300_init_reg_flags(struct drm_device *dev);
414ed537 404
6c340eac
EA		 405extern int r300_do_cp_cmdbuf(struct drm_device * dev,
406 struct drm_file *file_priv,
b3a83639 407 drm_radeon_kcmd_buffer_t * cmdbuf);
414ed537 408
1da177e4
LT		 409/* Flags for stats.boxes
410 */
411#define RADEON_BOX_DMA_IDLE 0x1
412#define RADEON_BOX_RING_FULL 0x2
413#define RADEON_BOX_FLIP 0x4
414#define RADEON_BOX_WAIT_IDLE 0x8
415#define RADEON_BOX_TEXTURE_LOAD 0x10
416
1da177e4
LT		 417/* Register definitions, register access macros and drmAddMap constants
418 * for Radeon kernel driver.
419 */
420
421#define RADEON_AGP_COMMAND 0x0f60
d985c108
DA		 422#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
423# define RADEON_AGP_ENABLE (1<<8)
1da177e4
LT		 424#define RADEON_AUX_SCISSOR_CNTL 0x26f0
425# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
426# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
427# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
428# define RADEON_SCISSOR_0_ENABLE (1 << 28)
429# define RADEON_SCISSOR_1_ENABLE (1 << 29)
430# define RADEON_SCISSOR_2_ENABLE (1 << 30)
431
432#define RADEON_BUS_CNTL 0x0030
433# define RADEON_BUS_MASTER_DIS (1 << 6)
434
435#define RADEON_CLOCK_CNTL_DATA 0x000c
436# define RADEON_PLL_WR_EN (1 << 7)
437#define RADEON_CLOCK_CNTL_INDEX 0x0008
438#define RADEON_CONFIG_APER_SIZE 0x0108
d985c108 439#define RADEON_CONFIG_MEMSIZE 0x00f8
1da177e4
LT		 440#define RADEON_CRTC_OFFSET 0x0224
441#define RADEON_CRTC_OFFSET_CNTL 0x0228
442# define RADEON_CRTC_TILE_EN (1 << 15)
443# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
444#define RADEON_CRTC2_OFFSET 0x0324
445#define RADEON_CRTC2_OFFSET_CNTL 0x0328
446
ea98a92f
DA		 447#define RADEON_PCIE_INDEX 0x0030
448#define RADEON_PCIE_DATA 0x0034
449#define RADEON_PCIE_TX_GART_CNTL 0x10
bc5f4523 450# define RADEON_PCIE_TX_GART_EN (1 << 0)
2735977b
AD		 451# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
452# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
453# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
454# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
455# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
456# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
457# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
ea98a92f
DA		 458#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
459#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
bc5f4523 460#define RADEON_PCIE_TX_GART_BASE 0x13
ea98a92f
DA		 461#define RADEON_PCIE_TX_GART_START_LO 0x14
462#define RADEON_PCIE_TX_GART_START_HI 0x15
463#define RADEON_PCIE_TX_GART_END_LO 0x16
464#define RADEON_PCIE_TX_GART_END_HI 0x17
465
45e51905
AD		 466#define RS480_NB_MC_INDEX 0x168
467# define RS480_NB_MC_IND_WR_EN (1 << 8)
468#define RS480_NB_MC_DATA 0x16c
f2b04cd2 469
60f92683
MC		 470#define RS690_MC_INDEX 0x78
471# define RS690_MC_INDEX_MASK 0x1ff
472# define RS690_MC_INDEX_WR_EN (1 << 9)
473# define RS690_MC_INDEX_WR_ACK 0x7f
474#define RS690_MC_DATA 0x7c
475
2735977b 476/* MC indirect registers */
45e51905
AD		 477#define RS480_MC_MISC_CNTL 0x18
478# define RS480_DISABLE_GTW (1 << 1)
2735977b 479/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
45e51905 480# define RS480_GART_INDEX_REG_EN (1 << 12)
2735977b 481# define RS690_BLOCK_GFX_D3_EN (1 << 14)
45e51905
AD		 482#define RS480_K8_FB_LOCATION 0x1e
483#define RS480_GART_FEATURE_ID 0x2b
484# define RS480_HANG_EN (1 << 11)
485# define RS480_TLB_ENABLE (1 << 18)
486# define RS480_P2P_ENABLE (1 << 19)
487# define RS480_GTW_LAC_EN (1 << 25)
488# define RS480_2LEVEL_GART (0 << 30)
489# define RS480_1LEVEL_GART (1 << 30)
490# define RS480_PDC_EN (1 << 31)
491#define RS480_GART_BASE 0x2c
492#define RS480_GART_CACHE_CNTRL 0x2e
493# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
494#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
495# define RS480_GART_EN (1 << 0)
496# define RS480_VA_SIZE_32MB (0 << 1)
497# define RS480_VA_SIZE_64MB (1 << 1)
498# define RS480_VA_SIZE_128MB (2 << 1)
499# define RS480_VA_SIZE_256MB (3 << 1)
500# define RS480_VA_SIZE_512MB (4 << 1)
501# define RS480_VA_SIZE_1GB (5 << 1)
502# define RS480_VA_SIZE_2GB (6 << 1)
503#define RS480_AGP_MODE_CNTL 0x39
504# define RS480_POST_GART_Q_SIZE (1 << 18)
505# define RS480_NONGART_SNOOP (1 << 19)
506# define RS480_AGP_RD_BUF_SIZE (1 << 20)
507# define RS480_REQ_TYPE_SNOOP_SHIFT 22
508# define RS480_REQ_TYPE_SNOOP_MASK 0x3
509# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
510#define RS480_MC_MISC_UMA_CNTL 0x5f
511#define RS480_MC_MCLK_CNTL 0x7a
512#define RS480_MC_UMA_DUALCH_CNTL 0x86
2735977b 513
60f92683
MC		 514#define RS690_MC_FB_LOCATION 0x100
515#define RS690_MC_AGP_LOCATION 0x101
516#define RS690_MC_AGP_BASE 0x102
3722bfc6 517#define RS690_MC_AGP_BASE_2 0x103
60f92683 518
3d5e2c13 519#define R520_MC_IND_INDEX 0x70
2735977b 520#define R520_MC_IND_WR_EN (1 << 24)
3d5e2c13
DA		 521#define R520_MC_IND_DATA 0x74
522
523#define RV515_MC_FB_LOCATION 0x01
524#define RV515_MC_AGP_LOCATION 0x02
70b13d51
DA		 525#define RV515_MC_AGP_BASE 0x03
526#define RV515_MC_AGP_BASE_2 0x04
3d5e2c13
DA		 527
528#define R520_MC_FB_LOCATION 0x04
529#define R520_MC_AGP_LOCATION 0x05
70b13d51
DA		 530#define R520_MC_AGP_BASE 0x06
531#define R520_MC_AGP_BASE_2 0x07
3d5e2c13 532
414ed537
DA		 533#define RADEON_MPP_TB_CONFIG 0x01c0
534#define RADEON_MEM_CNTL 0x0140
535#define RADEON_MEM_SDRAM_MODE_REG 0x0158
45e51905
AD		 536#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
537#define RS480_AGP_BASE_2 0x0164
414ed537
DA		 538#define RADEON_AGP_BASE 0x0170
539
5b92c404
AD		 540/* pipe config regs */
541#define R400_GB_PIPE_SELECT 0x402c
542#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
543#define R500_SU_REG_DEST 0x42c8
544#define R300_GB_TILE_CONFIG 0x4018
545# define R300_ENABLE_TILING (1 << 0)
546# define R300_PIPE_COUNT_RV350 (0 << 1)
547# define R300_PIPE_COUNT_R300 (3 << 1)
548# define R300_PIPE_COUNT_R420_3P (6 << 1)
549# define R300_PIPE_COUNT_R420 (7 << 1)
550# define R300_TILE_SIZE_8 (0 << 4)
551# define R300_TILE_SIZE_16 (1 << 4)
552# define R300_TILE_SIZE_32 (2 << 4)
553# define R300_SUBPIXEL_1_12 (0 << 16)
554# define R300_SUBPIXEL_1_16 (1 << 16)
555#define R300_DST_PIPE_CONFIG 0x170c
556# define R300_PIPE_AUTO_CONFIG (1 << 31)
557#define R300_RB2D_DSTCACHE_MODE 0x3428
558# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
559# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
560
1da177e4
LT		 561#define RADEON_RB3D_COLOROFFSET 0x1c40
562#define RADEON_RB3D_COLORPITCH 0x1c48
563
3e14a286
MD		 564#define RADEON_SRC_X_Y 0x1590
565
1da177e4
LT		 566#define RADEON_DP_GUI_MASTER_CNTL 0x146c
567# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
568# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
569# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
570# define RADEON_GMC_BRUSH_NONE (15 << 4)
571# define RADEON_GMC_DST_16BPP (4 << 8)
572# define RADEON_GMC_DST_24BPP (5 << 8)
573# define RADEON_GMC_DST_32BPP (6 << 8)
574# define RADEON_GMC_DST_DATATYPE_SHIFT 8
575# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
576# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
577# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
578# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
579# define RADEON_GMC_WR_MSK_DIS (1 << 30)
580# define RADEON_ROP3_S 0x00cc0000
581# define RADEON_ROP3_P 0x00f00000
582#define RADEON_DP_WRITE_MASK 0x16cc
3e14a286 583#define RADEON_SRC_PITCH_OFFSET 0x1428
1da177e4
LT		 584#define RADEON_DST_PITCH_OFFSET 0x142c
585#define RADEON_DST_PITCH_OFFSET_C 0x1c80
586# define RADEON_DST_TILE_LINEAR (0 << 30)
587# define RADEON_DST_TILE_MACRO (1 << 30)
588# define RADEON_DST_TILE_MICRO (2 << 30)
589# define RADEON_DST_TILE_BOTH (3 << 30)
590
591#define RADEON_SCRATCH_REG0 0x15e0
592#define RADEON_SCRATCH_REG1 0x15e4
593#define RADEON_SCRATCH_REG2 0x15e8
594#define RADEON_SCRATCH_REG3 0x15ec
595#define RADEON_SCRATCH_REG4 0x15f0
596#define RADEON_SCRATCH_REG5 0x15f4
597#define RADEON_SCRATCH_UMSK 0x0770
598#define RADEON_SCRATCH_ADDR 0x0774
599
600#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
601
602#define GET_SCRATCH( x ) (dev_priv->writeback_works \
603 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
604 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
605
1da177e4
LT		 606#define RADEON_GEN_INT_CNTL 0x0040
607# define RADEON_CRTC_VBLANK_MASK (1 << 0)
ddbee333 608# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
1da177e4
LT		 609# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
610# define RADEON_SW_INT_ENABLE (1 << 25)
611
612#define RADEON_GEN_INT_STATUS 0x0044
613# define RADEON_CRTC_VBLANK_STAT (1 << 0)
bc5f4523 614# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
ddbee333 615# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
bc5f4523 616# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
1da177e4
LT		 617# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
618# define RADEON_SW_INT_TEST (1 << 25)
bc5f4523 619# define RADEON_SW_INT_TEST_ACK (1 << 25)
1da177e4
LT		 620# define RADEON_SW_INT_FIRE (1 << 26)
621
622#define RADEON_HOST_PATH_CNTL 0x0130
623# define RADEON_HDP_SOFT_RESET (1 << 26)
624# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
625# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
626
627#define RADEON_ISYNC_CNTL 0x1724
628# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
629# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
630# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
631# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
632# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
633# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
634
635#define RADEON_RBBM_GUICNTL 0x172c
636# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
637# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
638# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
639# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
640
641#define RADEON_MC_AGP_LOCATION 0x014c
642#define RADEON_MC_FB_LOCATION 0x0148
643#define RADEON_MCLK_CNTL 0x0012
644# define RADEON_FORCEON_MCLKA (1 << 16)
645# define RADEON_FORCEON_MCLKB (1 << 17)
646# define RADEON_FORCEON_YCLKA (1 << 18)
647# define RADEON_FORCEON_YCLKB (1 << 19)
648# define RADEON_FORCEON_MC (1 << 20)
649# define RADEON_FORCEON_AIC (1 << 21)
650
651#define RADEON_PP_BORDER_COLOR_0 0x1d40
652#define RADEON_PP_BORDER_COLOR_1 0x1d44
653#define RADEON_PP_BORDER_COLOR_2 0x1d48
654#define RADEON_PP_CNTL 0x1c38
655# define RADEON_SCISSOR_ENABLE (1 << 1)
656#define RADEON_PP_LUM_MATRIX 0x1d00
657#define RADEON_PP_MISC 0x1c14
658#define RADEON_PP_ROT_MATRIX_0 0x1d58
659#define RADEON_PP_TXFILTER_0 0x1c54
660#define RADEON_PP_TXOFFSET_0 0x1c5c
661#define RADEON_PP_TXFILTER_1 0x1c6c
662#define RADEON_PP_TXFILTER_2 0x1c84
663
664#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
665# define RADEON_RB2D_DC_FLUSH (3 << 0)
666# define RADEON_RB2D_DC_FREE (3 << 2)
667# define RADEON_RB2D_DC_FLUSH_ALL 0xf
668# define RADEON_RB2D_DC_BUSY (1 << 31)
669#define RADEON_RB3D_CNTL 0x1c3c
670# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
671# define RADEON_PLANE_MASK_ENABLE (1 << 1)
672# define RADEON_DITHER_ENABLE (1 << 2)
673# define RADEON_ROUND_ENABLE (1 << 3)
674# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
675# define RADEON_DITHER_INIT (1 << 5)
676# define RADEON_ROP_ENABLE (1 << 6)
677# define RADEON_STENCIL_ENABLE (1 << 7)
678# define RADEON_Z_ENABLE (1 << 8)
679# define RADEON_ZBLOCK16 (1 << 15)
680#define RADEON_RB3D_DEPTHOFFSET 0x1c24
681#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
682#define RADEON_RB3D_DEPTHPITCH 0x1c28
683#define RADEON_RB3D_PLANEMASK 0x1d84
684#define RADEON_RB3D_STENCILREFMASK 0x1d7c
685#define RADEON_RB3D_ZCACHE_MODE 0x3250
686#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
687# define RADEON_RB3D_ZC_FLUSH (1 << 0)
688# define RADEON_RB3D_ZC_FREE (1 << 2)
689# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
690# define RADEON_RB3D_ZC_BUSY (1 << 31)
259434ac
AD		 691#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
692# define R300_ZC_FLUSH (1 << 0)
693# define R300_ZC_FREE (1 << 1)
694# define R300_ZC_FLUSH_ALL 0x3
695# define R300_ZC_BUSY (1 << 31)
b9b603dd
MD		 696#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
697# define RADEON_RB3D_DC_FLUSH (3 << 0)
698# define RADEON_RB3D_DC_FREE (3 << 2)
699# define RADEON_RB3D_DC_FLUSH_ALL 0xf
700# define RADEON_RB3D_DC_BUSY (1 << 31)
259434ac
AD		 701#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
702# define R300_RB3D_DC_FINISH (1 << 4)
1da177e4
LT		 703#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
704# define RADEON_Z_TEST_MASK (7 << 4)
705# define RADEON_Z_TEST_ALWAYS (7 << 4)
706# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
707# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
708# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
709# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
710# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
711# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
712# define RADEON_FORCE_Z_DIRTY (1 << 29)
713# define RADEON_Z_WRITE_ENABLE (1 << 30)
714# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
715#define RADEON_RBBM_SOFT_RESET 0x00f0
716# define RADEON_SOFT_RESET_CP (1 << 0)
717# define RADEON_SOFT_RESET_HI (1 << 1)
718# define RADEON_SOFT_RESET_SE (1 << 2)
719# define RADEON_SOFT_RESET_RE (1 << 3)
720# define RADEON_SOFT_RESET_PP (1 << 4)
721# define RADEON_SOFT_RESET_E2 (1 << 5)
722# define RADEON_SOFT_RESET_RB (1 << 6)
723# define RADEON_SOFT_RESET_HDP (1 << 7)
576cc458
RS		 724/*
725 * 6:0 Available slots in the FIFO
726 * 8 Host Interface active
727 * 9 CP request active
728 * 10 FIFO request active
729 * 11 Host Interface retry active
730 * 12 CP retry active
731 * 13 FIFO retry active
732 * 14 FIFO pipeline busy
733 * 15 Event engine busy
734 * 16 CP command stream busy
735 * 17 2D engine busy
736 * 18 2D portion of render backend busy
737 * 20 3D setup engine busy
738 * 26 GA engine busy
739 * 27 CBA 2D engine busy
740 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
741 * command stream queue not empty or Ring Buffer not empty
742 */
1da177e4 743#define RADEON_RBBM_STATUS 0x0e40
576cc458
RS		 744/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
745/* #define RADEON_RBBM_STATUS 0x1740 */
746/* bits 6:0 are dword slots available in the cmd fifo */
1da177e4 747# define RADEON_RBBM_FIFOCNT_MASK 0x007f
576cc458
RS		 748# define RADEON_HIRQ_ON_RBB (1 << 8)
749# define RADEON_CPRQ_ON_RBB (1 << 9)
750# define RADEON_CFRQ_ON_RBB (1 << 10)
751# define RADEON_HIRQ_IN_RTBUF (1 << 11)
752# define RADEON_CPRQ_IN_RTBUF (1 << 12)
753# define RADEON_CFRQ_IN_RTBUF (1 << 13)
754# define RADEON_PIPE_BUSY (1 << 14)
755# define RADEON_ENG_EV_BUSY (1 << 15)
756# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
757# define RADEON_E2_BUSY (1 << 17)
758# define RADEON_RB2D_BUSY (1 << 18)
759# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
760# define RADEON_VAP_BUSY (1 << 20)
761# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
762# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
763# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
764# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
765# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
766# define RADEON_GA_BUSY (1 << 26)
767# define RADEON_CBA2D_BUSY (1 << 27)
768# define RADEON_RBBM_ACTIVE (1 << 31)
1da177e4
LT		 769#define RADEON_RE_LINE_PATTERN 0x1cd0
770#define RADEON_RE_MISC 0x26c4
771#define RADEON_RE_TOP_LEFT 0x26c0
772#define RADEON_RE_WIDTH_HEIGHT 0x1c44
773#define RADEON_RE_STIPPLE_ADDR 0x1cc8
774#define RADEON_RE_STIPPLE_DATA 0x1ccc
775
776#define RADEON_SCISSOR_TL_0 0x1cd8
777#define RADEON_SCISSOR_BR_0 0x1cdc
778#define RADEON_SCISSOR_TL_1 0x1ce0
779#define RADEON_SCISSOR_BR_1 0x1ce4
780#define RADEON_SCISSOR_TL_2 0x1ce8
781#define RADEON_SCISSOR_BR_2 0x1cec
782#define RADEON_SE_COORD_FMT 0x1c50
783#define RADEON_SE_CNTL 0x1c4c
784# define RADEON_FFACE_CULL_CW (0 << 0)
785# define RADEON_BFACE_SOLID (3 << 1)
786# define RADEON_FFACE_SOLID (3 << 3)
787# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
788# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
789# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
790# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
791# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
792# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
793# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
794# define RADEON_FOG_SHADE_FLAT (1 << 14)
795# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
796# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
797# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
798# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
799# define RADEON_ROUND_MODE_TRUNC (0 << 28)
800# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
801#define RADEON_SE_CNTL_STATUS 0x2140
802#define RADEON_SE_LINE_WIDTH 0x1db8
803#define RADEON_SE_VPORT_XSCALE 0x1d98
804#define RADEON_SE_ZBIAS_FACTOR 0x1db0
805#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
806#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
807#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
808# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
809# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
810#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
811#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
812# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
813#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
814#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
815#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
816#define RADEON_SURFACE_CNTL 0x0b00
817# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
818# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
819# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
820# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
821# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
822# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
823# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
824# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
825# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
826#define RADEON_SURFACE0_INFO 0x0b0c
827# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
828# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
829# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
830# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
831# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
832# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
833#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
834#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
835# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
836#define RADEON_SURFACE1_INFO 0x0b1c
837#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
838#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
839#define RADEON_SURFACE2_INFO 0x0b2c
840#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
841#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
842#define RADEON_SURFACE3_INFO 0x0b3c
843#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
844#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
845#define RADEON_SURFACE4_INFO 0x0b4c
846#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
847#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
848#define RADEON_SURFACE5_INFO 0x0b5c
849#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
850#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
851#define RADEON_SURFACE6_INFO 0x0b6c
852#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
853#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
854#define RADEON_SURFACE7_INFO 0x0b7c
855#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
856#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
857#define RADEON_SW_SEMAPHORE 0x013c
858
859#define RADEON_WAIT_UNTIL 0x1720
860# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
d985c108
DA		 861# define RADEON_WAIT_2D_IDLE (1 << 14)
862# define RADEON_WAIT_3D_IDLE (1 << 15)
1da177e4
LT		 863# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
864# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
865# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
866
867#define RADEON_RB3D_ZMASKOFFSET 0x3234
868#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
869# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
870# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
871
1da177e4
LT		 872/* CP registers */
873#define RADEON_CP_ME_RAM_ADDR 0x07d4
874#define RADEON_CP_ME_RAM_RADDR 0x07d8
875#define RADEON_CP_ME_RAM_DATAH 0x07dc
876#define RADEON_CP_ME_RAM_DATAL 0x07e0
877
878#define RADEON_CP_RB_BASE 0x0700
879#define RADEON_CP_RB_CNTL 0x0704
880# define RADEON_BUF_SWAP_32BIT (2 << 16)
ae1b1a48 881# define RADEON_RB_NO_UPDATE (1 << 27)
1da177e4
LT		 882#define RADEON_CP_RB_RPTR_ADDR 0x070c
883#define RADEON_CP_RB_RPTR 0x0710
884#define RADEON_CP_RB_WPTR 0x0714
885
886#define RADEON_CP_RB_WPTR_DELAY 0x0718
887# define RADEON_PRE_WRITE_TIMER_SHIFT 0
888# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
889
890#define RADEON_CP_IB_BASE 0x0738
891
892#define RADEON_CP_CSQ_CNTL 0x0740
893# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
894# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
895# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
896# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
897# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
898# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
899# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
900
901#define RADEON_AIC_CNTL 0x01d0
902# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
903#define RADEON_AIC_STAT 0x01d4
904#define RADEON_AIC_PT_BASE 0x01d8
905#define RADEON_AIC_LO_ADDR 0x01dc
906#define RADEON_AIC_HI_ADDR 0x01e0
907#define RADEON_AIC_TLB_ADDR 0x01e4
908#define RADEON_AIC_TLB_DATA 0x01e8
909
910/* CP command packets */
911#define RADEON_CP_PACKET0 0x00000000
912# define RADEON_ONE_REG_WR (1 << 15)
913#define RADEON_CP_PACKET1 0x40000000
914#define RADEON_CP_PACKET2 0x80000000
915#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 916# define RADEON_CP_NOP 0x00001000
917# define RADEON_CP_NEXT_CHAR 0x00001900
918# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
919# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 920 /* GEN_INDX_PRIM is unsupported starting with R300 */
1da177e4
LT		 921# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
922# define RADEON_WAIT_FOR_IDLE 0x00002600
923# define RADEON_3D_DRAW_VBUF 0x00002800
924# define RADEON_3D_DRAW_IMMD 0x00002900
925# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 926# define RADEON_CP_LOAD_PALETTE 0x00002C00
1da177e4
LT		 927# define RADEON_3D_LOAD_VBPNTR 0x00002F00
928# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
929# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
930# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 931# define RADEON_CP_INDX_BUFFER 0x00003300
932# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
933# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
934# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 935# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 936# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1da177e4
LT		 937# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
938# define RADEON_CNTL_PAINT_MULTI 0x00009A00
939# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
940# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
941
942#define RADEON_CP_PACKET_MASK 0xC0000000
943#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
944#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
945#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
946#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
947
948#define RADEON_VTX_Z_PRESENT (1 << 31)
949#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
950
951#define RADEON_PRIM_TYPE_NONE (0 << 0)
952#define RADEON_PRIM_TYPE_POINT (1 << 0)
953#define RADEON_PRIM_TYPE_LINE (2 << 0)
954#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
955#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
956#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
957#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
958#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
959#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
960#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
961#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
962#define RADEON_PRIM_TYPE_MASK 0xf
963#define RADEON_PRIM_WALK_IND (1 << 4)
964#define RADEON_PRIM_WALK_LIST (2 << 4)
965#define RADEON_PRIM_WALK_RING (3 << 4)
966#define RADEON_COLOR_ORDER_BGRA (0 << 6)
967#define RADEON_COLOR_ORDER_RGBA (1 << 6)
968#define RADEON_MAOS_ENABLE (1 << 7)
969#define RADEON_VTX_FMT_R128_MODE (0 << 8)
970#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
971#define RADEON_NUM_VERTICES_SHIFT 16
972
973#define RADEON_COLOR_FORMAT_CI8 2
974#define RADEON_COLOR_FORMAT_ARGB1555 3
975#define RADEON_COLOR_FORMAT_RGB565 4
976#define RADEON_COLOR_FORMAT_ARGB8888 6
977#define RADEON_COLOR_FORMAT_RGB332 7
978#define RADEON_COLOR_FORMAT_RGB8 9
979#define RADEON_COLOR_FORMAT_ARGB4444 15
980
981#define RADEON_TXFORMAT_I8 0
982#define RADEON_TXFORMAT_AI88 1
983#define RADEON_TXFORMAT_RGB332 2
984#define RADEON_TXFORMAT_ARGB1555 3
985#define RADEON_TXFORMAT_RGB565 4
986#define RADEON_TXFORMAT_ARGB4444 5
987#define RADEON_TXFORMAT_ARGB8888 6
988#define RADEON_TXFORMAT_RGBA8888 7
989#define RADEON_TXFORMAT_Y8 8
990#define RADEON_TXFORMAT_VYUY422 10
991#define RADEON_TXFORMAT_YVYU422 11
992#define RADEON_TXFORMAT_DXT1 12
993#define RADEON_TXFORMAT_DXT23 14
994#define RADEON_TXFORMAT_DXT45 15
995
996#define R200_PP_TXCBLEND_0 0x2f00
997#define R200_PP_TXCBLEND_1 0x2f10
998#define R200_PP_TXCBLEND_2 0x2f20
999#define R200_PP_TXCBLEND_3 0x2f30
1000#define R200_PP_TXCBLEND_4 0x2f40
1001#define R200_PP_TXCBLEND_5 0x2f50
1002#define R200_PP_TXCBLEND_6 0x2f60
1003#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 1004#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1da177e4
LT		 1005#define R200_PP_TFACTOR_0 0x2ee0
1006#define R200_SE_VTX_FMT_0 0x2088
1007#define R200_SE_VAP_CNTL 0x2080
1008#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 1009#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1010#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1011#define R200_PP_TXFILTER_5 0x2ca0
1012#define R200_PP_TXFILTER_4 0x2c80
1013#define R200_PP_TXFILTER_3 0x2c60
1014#define R200_PP_TXFILTER_2 0x2c40
1015#define R200_PP_TXFILTER_1 0x2c20
1016#define R200_PP_TXFILTER_0 0x2c00
1da177e4
LT		 1017#define R200_PP_TXOFFSET_5 0x2d78
1018#define R200_PP_TXOFFSET_4 0x2d60
1019#define R200_PP_TXOFFSET_3 0x2d48
1020#define R200_PP_TXOFFSET_2 0x2d30
1021#define R200_PP_TXOFFSET_1 0x2d18
1022#define R200_PP_TXOFFSET_0 0x2d00
1023
1024#define R200_PP_CUBIC_FACES_0 0x2c18
1025#define R200_PP_CUBIC_FACES_1 0x2c38
1026#define R200_PP_CUBIC_FACES_2 0x2c58
1027#define R200_PP_CUBIC_FACES_3 0x2c78
1028#define R200_PP_CUBIC_FACES_4 0x2c98
1029#define R200_PP_CUBIC_FACES_5 0x2cb8
1030#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1031#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1032#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1033#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1034#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1035#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1036#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1037#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1038#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1039#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1040#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1041#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1042#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1043#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1044#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1045#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1046#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1047#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1048#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1049#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1050#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1051#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1052#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1053#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1054#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1055#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1056#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1057#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1058#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1059#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1060
1061#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1062#define R200_SE_VTE_CNTL 0x20b0
1063#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1064#define R200_PP_TAM_DEBUG3 0x2d9c
1065#define R200_PP_CNTL_X 0x2cc4
1066#define R200_SE_VAP_CNTL_STATUS 0x2140
1067#define R200_RE_SCISSOR_TL_0 0x1cd8
1068#define R200_RE_SCISSOR_TL_1 0x1ce0
1069#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 1070#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1da177e4
LT		 1071#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1072#define R200_SE_VTX_STATE_CNTL 0x2180
1073#define R200_RE_POINTSIZE 0x2648
1074#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1075
b5e89ed5 1076#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1da177e4
LT		 1077#define RADEON_PP_TEX_SIZE_1 0x1d0c
1078#define RADEON_PP_TEX_SIZE_2 0x1d14
1079
1080#define RADEON_PP_CUBIC_FACES_0 0x1d24
1081#define RADEON_PP_CUBIC_FACES_1 0x1d28
1082#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1083#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1084#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1085#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1086
f2a2279f
DA		 1087#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1088
1da177e4
LT		 1089#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1090#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1091#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1092#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1093#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1094#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1095#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1096#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1097#define R200_3D_DRAW_IMMD_2 0xC0003500
1098#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 1099#define R200_RE_CNTL 0x1c50
1da177e4
LT		 1100
1101#define R200_RB3D_BLENDCOLOR 0x3218
1102
1103#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1104
1105#define R200_PP_TRI_PERF 0x2cf8
1106
9d17601c 1107#define R200_PP_AFS_0 0x2f80
b5e89ed5 1108#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 1109
d6fece05
DA		 1110#define R200_VAP_PVS_CNTL_1 0x22D0
1111
c0beb2a7
DA		 1112#define R500_D1CRTC_STATUS 0x609c
1113#define R500_D2CRTC_STATUS 0x689c
1114#define R500_CRTC_V_BLANK (1<<0)
1115
1116#define R500_D1CRTC_FRAME_COUNT 0x60a4
1117#define R500_D2CRTC_FRAME_COUNT 0x68a4
1118
1119#define R500_D1MODE_V_COUNTER 0x6530
1120#define R500_D2MODE_V_COUNTER 0x6d30
1121
1122#define R500_D1MODE_VBLANK_STATUS 0x6534
1123#define R500_D2MODE_VBLANK_STATUS 0x6d34
1124#define R500_VBLANK_OCCURED (1<<0)
1125#define R500_VBLANK_ACK (1<<4)
1126#define R500_VBLANK_STAT (1<<12)
1127#define R500_VBLANK_INT (1<<16)
1128
1129#define R500_DxMODE_INT_MASK 0x6540
1130#define R500_D1MODE_INT_MASK (1<<0)
1131#define R500_D2MODE_INT_MASK (1<<8)
1132
1133#define R500_DISP_INTERRUPT_STATUS 0x7edc
1134#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1135#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1136
1da177e4
LT		 1137/* Constants */
1138#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1139
1140#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1141#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1142#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1143#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1144#define RADEON_LAST_DISPATCH 1
1145
1146#define RADEON_MAX_VB_AGE 0x7fffffff
1147#define RADEON_MAX_VB_VERTS (0xffff)
1148
1149#define RADEON_RING_HIGH_MARK 128
1150
ea98a92f
DA		 1151#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1152
1da177e4
LT		 1153#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1154#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1155#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1156#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1157
2735977b 1158#define RADEON_WRITE_PLL(addr, val) \
1da177e4 1159do { \
2735977b 1160 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1da177e4 1161 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
2735977b 1162 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1da177e4
LT		 1163} while (0)
1164
2735977b 1165#define RADEON_WRITE_PCIE(addr, val) \
ea98a92f 1166do { \
2735977b 1167 RADEON_WRITE8(RADEON_PCIE_INDEX, \
ea98a92f 1168 ((addr) & 0xff)); \
2735977b 1169 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
ea98a92f
DA		 1170} while (0)
1171
45e51905
AD		 1172#define R500_WRITE_MCIND(addr, val) \
1173do { \
1174 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1175 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1176 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1177} while (0)
1178
1179#define RS480_WRITE_MCIND(addr, val) \
1180do { \
1181 RADEON_WRITE(RS480_NB_MC_INDEX, \
1182 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1183 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1184 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1185} while (0)
3d5e2c13 1186
2735977b 1187#define RS690_WRITE_MCIND(addr, val) \
60f92683
MC		 1188do { \
1189 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1190 RADEON_WRITE(RS690_MC_DATA, val); \
1191 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1192} while (0)
1193
45e51905
AD		 1194#define IGP_WRITE_MCIND(addr, val) \
1195do { \
1196 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
1197 RS690_WRITE_MCIND(addr, val); \
1198 else \
1199 RS480_WRITE_MCIND(addr, val); \
1200} while (0)
1201
1da177e4
LT		 1202#define CP_PACKET0( reg, n ) \
1203 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1204#define CP_PACKET0_TABLE( reg, n ) \
1205 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1206#define CP_PACKET1( reg0, reg1 ) \
1207 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1208#define CP_PACKET2() \
1209 (RADEON_CP_PACKET2)
1210#define CP_PACKET3( pkt, n ) \
1211 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1212
1da177e4
LT		 1213/* ================================================================
1214 * Engine control helper macros
1215 */
1216
1217#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1218 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1219 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1220 RADEON_WAIT_HOST_IDLECLEAN) ); \
1221} while (0)
1222
1223#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1224 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1225 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1226 RADEON_WAIT_HOST_IDLECLEAN) ); \
1227} while (0)
1228
1229#define RADEON_WAIT_UNTIL_IDLE() do { \
1230 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1231 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1232 RADEON_WAIT_3D_IDLECLEAN | \
1233 RADEON_WAIT_HOST_IDLECLEAN) ); \
1234} while (0)
1235
1236#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1237 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1238 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1239} while (0)
1240
1241#define RADEON_FLUSH_CACHE() do { \
259434ac
AD		 1242 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1243 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1244 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1245 } else { \
1246 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1247 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1248 } \
1da177e4
LT		 1249} while (0)
1250
1251#define RADEON_PURGE_CACHE() do { \
259434ac
AD		 1252 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1253 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1254 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1255 } else { \
1256 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1257 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
1258 } \
1da177e4
LT		 1259} while (0)
1260
1261#define RADEON_FLUSH_ZCACHE() do { \
259434ac
AD		 1262 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1263 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1264 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1265 } else { \
1266 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1267 OUT_RING(R300_ZC_FLUSH); \
1268 } \
1da177e4
LT		 1269} while (0)
1270
1271#define RADEON_PURGE_ZCACHE() do { \
259434ac
AD		 1272 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1273 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1274 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
1275 } else { \
1276 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1277 OUT_RING(R300_ZC_FLUSH_ALL); \
1278 } \
1da177e4
LT		 1279} while (0)
1280
1da177e4
LT		 1281/* ================================================================
1282 * Misc helper macros
1283 */
1284
b5e89ed5 1285/* Perfbox functionality only.
1da177e4
LT		 1286 */
1287#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1288do { \
1289 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1290 u32 head = GET_RING_HEAD( dev_priv ); \
1291 if (head == dev_priv->ring.tail) \
1292 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1293 } \
1294} while (0)
1295
1296#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1297do { \
1298 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1299 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1300 int __ret = radeon_do_cp_idle( dev_priv ); \
1301 if ( __ret ) return __ret; \
1302 sarea_priv->last_dispatch = 0; \
1303 radeon_freelist_reset( dev ); \
1304 } \
1305} while (0)
1306
1307#define RADEON_DISPATCH_AGE( age ) do { \
1308 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1309 OUT_RING( age ); \
1310} while (0)
1311
1312#define RADEON_FRAME_AGE( age ) do { \
1313 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1314 OUT_RING( age ); \
1315} while (0)
1316
1317#define RADEON_CLEAR_AGE( age ) do { \
1318 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1319 OUT_RING( age ); \
1320} while (0)
1321
1da177e4
LT		 1322/* ================================================================
1323 * Ring control
1324 */
1325
1326#define RADEON_VERBOSE 0
1327
1328#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1329
1330#define BEGIN_RING( n ) do { \
1331 if ( RADEON_VERBOSE ) { \
3e684eae 1332 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1da177e4
LT		 1333 } \
1334 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1335 COMMIT_RING(); \
1336 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1337 } \
1338 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1339 ring = dev_priv->ring.start; \
1340 write = dev_priv->ring.tail; \
1341 mask = dev_priv->ring.tail_mask; \
1342} while (0)
1343
1344#define ADVANCE_RING() do { \
1345 if ( RADEON_VERBOSE ) { \
1346 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1347 write, dev_priv->ring.tail ); \
1348 } \
1349 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
bc5f4523 1350 DRM_ERROR( \
1da177e4
LT		 1351 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1352 ((dev_priv->ring.tail + _nr) & mask), \
1353 write, __LINE__); \
1354 } else \
1355 dev_priv->ring.tail = write; \
1356} while (0)
1357
1358#define COMMIT_RING() do { \
1359 /* Flush writes to ring */ \
1360 DRM_MEMORYBARRIER(); \
1361 GET_RING_HEAD( dev_priv ); \
1362 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1363 /* read from PCI bus to ensure correct posting */ \
1364 RADEON_READ( RADEON_CP_RB_RPTR ); \
1365} while (0)
1366
1367#define OUT_RING( x ) do { \
1368 if ( RADEON_VERBOSE ) { \
1369 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1370 (unsigned int)(x), write ); \
1371 } \
1372 ring[write++] = (x); \
1373 write &= mask; \
1374} while (0)
1375
1376#define OUT_RING_REG( reg, val ) do { \
1377 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1378 OUT_RING( val ); \
1379} while (0)
1380
1da177e4
LT		 1381#define OUT_RING_TABLE( tab, sz ) do { \
1382 int _size = (sz); \
1383 int *_tab = (int *)(tab); \
1384 \
1385 if (write + _size > mask) { \
1386 int _i = (mask+1) - write; \
1387 _size -= _i; \
1388 while (_i > 0 ) { \
1389 *(int *)(ring + write) = *_tab++; \
1390 write++; \
1391 _i--; \
1392 } \
1393 write = 0; \
1394 _tab += _i; \
1395 } \
1da177e4
LT		 1396 while (_size > 0) { \
1397 *(ring + write) = *_tab++; \
1398 write++; \
1399 _size--; \
1400 } \
1401 write &= mask; \
1402} while (0)
1403
b5e89ed5 1404#endif /* __RADEON_DRV_H__ */
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