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[net-next-2.6.git] / drivers / char / drm / radeon_drv.h
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1da177e4
LT		 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#ifndef __RADEON_DRV_H__
32#define __RADEON_DRV_H__
33
34/* General customization:
35 */
36
37#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39#define DRIVER_NAME "radeon"
40#define DRIVER_DESC "ATI Radeon"
d6fece05 41#define DRIVER_DATE "20060524"
1da177e4
LT		 42
43/* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
b5e89ed5 71 * clients use to tell the DRM where they think the framebuffer is
1da177e4
LT		 72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
d985c108 76 * (No 3D support yet - just microcode loading).
1da177e4
LT		 77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
414ed537 85 * 1.17- Add initial support for R300 (3D).
9d17601c
DA		 86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
ea98a92f 90 * 1.19- Add support for gart table in FB memory and PCIE r300
d985c108
DA		 91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
4e5e2e25 93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
d5ea702f 94 * 1.23- Add new radeon memory map work from benh
ee4621f0 95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
d6fece05
DA		 96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
1da177e4
LT		 98 */
99#define DRIVER_MAJOR 1
d6fece05 100#define DRIVER_MINOR 25
1da177e4
LT		 101#define DRIVER_PATCHLEVEL 0
102
1da177e4
LT		 103/*
104 * Radeon chip families
105 */
106enum radeon_family {
107 CHIP_R100,
1da177e4 108 CHIP_RV100,
dfab1154 109 CHIP_RS100,
1da177e4
LT		 110 CHIP_RV200,
111 CHIP_RS200,
dfab1154 112 CHIP_R200,
1da177e4 113 CHIP_RV250,
dfab1154 114 CHIP_RS300,
1da177e4
LT		 115 CHIP_RV280,
116 CHIP_R300,
414ed537 117 CHIP_R350,
1da177e4 118 CHIP_RV350,
dfab1154 119 CHIP_RV380,
414ed537 120 CHIP_R420,
dfab1154
DA		 121 CHIP_RV410,
122 CHIP_RS400,
1da177e4
LT		 123 CHIP_LAST,
124};
125
126enum radeon_cp_microcode_version {
127 UCODE_R100,
128 UCODE_R200,
129 UCODE_R300,
130};
131
132/*
133 * Chip flags
134 */
135enum radeon_chip_flags {
54a56ac5
DA		 136 RADEON_FAMILY_MASK = 0x0000ffffUL,
137 RADEON_FLAGS_MASK = 0xffff0000UL,
138 RADEON_IS_MOBILITY = 0x00010000UL,
139 RADEON_IS_IGP = 0x00020000UL,
140 RADEON_SINGLE_CRTC = 0x00040000UL,
141 RADEON_IS_AGP = 0x00080000UL,
142 RADEON_HAS_HIERZ = 0x00100000UL,
143 RADEON_IS_PCIE = 0x00200000UL,
144 RADEON_NEW_MEMMAP = 0x00400000UL,
145 RADEON_IS_PCI = 0x00800000UL,
1da177e4
LT		 146};
147
d5ea702f
DA		 148#define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
149 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
d985c108
DA		 150#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
151
1da177e4 152typedef struct drm_radeon_freelist {
b5e89ed5
DA		 153 unsigned int age;
154 drm_buf_t *buf;
155 struct drm_radeon_freelist *next;
156 struct drm_radeon_freelist *prev;
1da177e4
LT		 157} drm_radeon_freelist_t;
158
159typedef struct drm_radeon_ring_buffer {
160 u32 *start;
161 u32 *end;
162 int size;
163 int size_l2qw;
164
165 u32 tail;
166 u32 tail_mask;
167 int space;
168
169 int high_mark;
170} drm_radeon_ring_buffer_t;
171
172typedef struct drm_radeon_depth_clear_t {
173 u32 rb3d_cntl;
174 u32 rb3d_zstencilcntl;
175 u32 se_cntl;
176} drm_radeon_depth_clear_t;
177
178struct drm_radeon_driver_file_fields {
179 int64_t radeon_fb_delta;
180};
181
182struct mem_block {
183 struct mem_block *next;
184 struct mem_block *prev;
185 int start;
186 int size;
187 DRMFILE filp; /* 0: free, -1: heap, other: real files */
188};
189
190struct radeon_surface {
191 int refcount;
192 u32 lower;
193 u32 upper;
194 u32 flags;
195};
196
197struct radeon_virt_surface {
198 int surface_index;
199 u32 lower;
200 u32 upper;
201 u32 flags;
202 DRMFILE filp;
203};
204
205typedef struct drm_radeon_private {
206 drm_radeon_ring_buffer_t ring;
207 drm_radeon_sarea_t *sarea_priv;
208
209 u32 fb_location;
d5ea702f
DA		 210 u32 fb_size;
211 int new_memmap;
1da177e4
LT		 212
213 int gart_size;
214 u32 gart_vm_start;
215 unsigned long gart_buffers_offset;
216
217 int cp_mode;
218 int cp_running;
219
b5e89ed5
DA		 220 drm_radeon_freelist_t *head;
221 drm_radeon_freelist_t *tail;
1da177e4
LT		 222 int last_buf;
223 volatile u32 *scratch;
224 int writeback_works;
225
226 int usec_timeout;
227
228 int microcode_version;
229
1da177e4
LT		 230 struct {
231 u32 boxes;
232 int freelist_timeouts;
233 int freelist_loops;
234 int requested_bufs;
235 int last_frame_reads;
236 int last_clear_reads;
237 int clears;
238 int texture_uploads;
239 } stats;
240
241 int do_boxes;
242 int page_flipping;
243 int current_page;
244
245 u32 color_fmt;
246 unsigned int front_offset;
247 unsigned int front_pitch;
248 unsigned int back_offset;
249 unsigned int back_pitch;
250
251 u32 depth_fmt;
252 unsigned int depth_offset;
253 unsigned int depth_pitch;
254
255 u32 front_pitch_offset;
256 u32 back_pitch_offset;
257 u32 depth_pitch_offset;
258
259 drm_radeon_depth_clear_t depth_clear;
b5e89ed5 260
1da177e4
LT		 261 unsigned long ring_offset;
262 unsigned long ring_rptr_offset;
263 unsigned long buffers_offset;
264 unsigned long gart_textures_offset;
265
266 drm_local_map_t *sarea;
267 drm_local_map_t *mmio;
268 drm_local_map_t *cp_ring;
269 drm_local_map_t *ring_rptr;
270 drm_local_map_t *gart_textures;
271
272 struct mem_block *gart_heap;
273 struct mem_block *fb_heap;
274
275 /* SW interrupt */
b5e89ed5
DA		 276 wait_queue_head_t swi_queue;
277 atomic_t swi_emitted;
1da177e4
LT		 278
279 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
b5e89ed5 280 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
1da177e4 281
b5e89ed5
DA		 282 unsigned long pcigart_offset;
283 drm_ati_pcigart_info gart_info;
ea98a92f 284
ee4621f0
DA		 285 u32 scratch_ages[5];
286
1da177e4
LT		 287 /* starting from here on, data is preserved accross an open */
288 uint32_t flags; /* see radeon_chip_flags */
289} drm_radeon_private_t;
290
291typedef struct drm_radeon_buf_priv {
292 u32 age;
293} drm_radeon_buf_priv_t;
294
b3a83639
DA		 295typedef struct drm_radeon_kcmd_buffer {
296 int bufsz;
297 char *buf;
298 int nbox;
299 drm_clip_rect_t __user *boxes;
300} drm_radeon_kcmd_buffer_t;
301
689b9d74 302extern int radeon_no_wb;
b3a83639
DA		 303extern drm_ioctl_desc_t radeon_ioctls[];
304extern int radeon_max_ioctl;
305
1d6bb8e5
MD		 306/* Check whether the given hardware address is inside the framebuffer or the
307 * GART area.
308 */
309static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
310 u64 off)
311{
312 u32 fb_start = dev_priv->fb_location;
313 u32 fb_end = fb_start + dev_priv->fb_size - 1;
314 u32 gart_start = dev_priv->gart_vm_start;
315 u32 gart_end = gart_start + dev_priv->gart_size - 1;
316
317 return ((off >= fb_start && off <= fb_end) ||
318 (off >= gart_start && off <= gart_end));
319}
320
1da177e4 321 /* radeon_cp.c */
b5e89ed5
DA		 322extern int radeon_cp_init(DRM_IOCTL_ARGS);
323extern int radeon_cp_start(DRM_IOCTL_ARGS);
324extern int radeon_cp_stop(DRM_IOCTL_ARGS);
325extern int radeon_cp_reset(DRM_IOCTL_ARGS);
326extern int radeon_cp_idle(DRM_IOCTL_ARGS);
327extern int radeon_cp_resume(DRM_IOCTL_ARGS);
328extern int radeon_engine_reset(DRM_IOCTL_ARGS);
329extern int radeon_fullscreen(DRM_IOCTL_ARGS);
330extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
1da177e4 331
b5e89ed5
DA		 332extern void radeon_freelist_reset(drm_device_t * dev);
333extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
1da177e4 334
b5e89ed5 335extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
1da177e4 336
b5e89ed5 337extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
1da177e4
LT		 338
339extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
836cf046 340extern int radeon_presetup(struct drm_device *dev);
1da177e4
LT		 341extern int radeon_driver_postcleanup(struct drm_device *dev);
342
b5e89ed5
DA		 343extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
344extern int radeon_mem_free(DRM_IOCTL_ARGS);
345extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
346extern void radeon_mem_takedown(struct mem_block **heap);
347extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
1da177e4
LT		 348
349 /* radeon_irq.c */
b5e89ed5
DA		 350extern int radeon_irq_emit(DRM_IOCTL_ARGS);
351extern int radeon_irq_wait(DRM_IOCTL_ARGS);
352
353extern void radeon_do_release(drm_device_t * dev);
354extern int radeon_driver_vblank_wait(drm_device_t * dev,
355 unsigned int *sequence);
356extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
357extern void radeon_driver_irq_preinstall(drm_device_t * dev);
358extern void radeon_driver_irq_postinstall(drm_device_t * dev);
359extern void radeon_driver_irq_uninstall(drm_device_t * dev);
1da177e4 360
22eae947
DA		 361extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
362extern int radeon_driver_unload(struct drm_device *dev);
363extern int radeon_driver_firstopen(struct drm_device *dev);
364extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
365extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
366extern void radeon_driver_lastclose(drm_device_t * dev);
367extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
9a186645
DA		 368extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
369 unsigned long arg);
370
414ed537
DA		 371/* r300_cmdbuf.c */
372extern void r300_init_reg_flags(void);
373
b5e89ed5
DA		 374extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
375 drm_file_t * filp_priv,
b3a83639 376 drm_radeon_kcmd_buffer_t * cmdbuf);
414ed537 377
1da177e4
LT		 378/* Flags for stats.boxes
379 */
380#define RADEON_BOX_DMA_IDLE 0x1
381#define RADEON_BOX_RING_FULL 0x2
382#define RADEON_BOX_FLIP 0x4
383#define RADEON_BOX_WAIT_IDLE 0x8
384#define RADEON_BOX_TEXTURE_LOAD 0x10
385
1da177e4
LT		 386/* Register definitions, register access macros and drmAddMap constants
387 * for Radeon kernel driver.
388 */
389
390#define RADEON_AGP_COMMAND 0x0f60
d985c108
DA		 391#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
392# define RADEON_AGP_ENABLE (1<<8)
1da177e4
LT		 393#define RADEON_AUX_SCISSOR_CNTL 0x26f0
394# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
395# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
396# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
397# define RADEON_SCISSOR_0_ENABLE (1 << 28)
398# define RADEON_SCISSOR_1_ENABLE (1 << 29)
399# define RADEON_SCISSOR_2_ENABLE (1 << 30)
400
401#define RADEON_BUS_CNTL 0x0030
402# define RADEON_BUS_MASTER_DIS (1 << 6)
403
404#define RADEON_CLOCK_CNTL_DATA 0x000c
405# define RADEON_PLL_WR_EN (1 << 7)
406#define RADEON_CLOCK_CNTL_INDEX 0x0008
407#define RADEON_CONFIG_APER_SIZE 0x0108
d985c108 408#define RADEON_CONFIG_MEMSIZE 0x00f8
1da177e4
LT		 409#define RADEON_CRTC_OFFSET 0x0224
410#define RADEON_CRTC_OFFSET_CNTL 0x0228
411# define RADEON_CRTC_TILE_EN (1 << 15)
412# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
413#define RADEON_CRTC2_OFFSET 0x0324
414#define RADEON_CRTC2_OFFSET_CNTL 0x0328
415
ea98a92f
DA		 416#define RADEON_PCIE_INDEX 0x0030
417#define RADEON_PCIE_DATA 0x0034
418#define RADEON_PCIE_TX_GART_CNTL 0x10
419# define RADEON_PCIE_TX_GART_EN (1 << 0)
420# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
421# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
422# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
423# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
424# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
425# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
426# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
427#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
428#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
429#define RADEON_PCIE_TX_GART_BASE 0x13
430#define RADEON_PCIE_TX_GART_START_LO 0x14
431#define RADEON_PCIE_TX_GART_START_HI 0x15
432#define RADEON_PCIE_TX_GART_END_LO 0x16
433#define RADEON_PCIE_TX_GART_END_HI 0x17
434
414ed537
DA		 435#define RADEON_MPP_TB_CONFIG 0x01c0
436#define RADEON_MEM_CNTL 0x0140
437#define RADEON_MEM_SDRAM_MODE_REG 0x0158
438#define RADEON_AGP_BASE 0x0170
439
1da177e4
LT		 440#define RADEON_RB3D_COLOROFFSET 0x1c40
441#define RADEON_RB3D_COLORPITCH 0x1c48
442
3e14a286
MD		 443#define RADEON_SRC_X_Y 0x1590
444
1da177e4
LT		 445#define RADEON_DP_GUI_MASTER_CNTL 0x146c
446# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
447# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
448# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
449# define RADEON_GMC_BRUSH_NONE (15 << 4)
450# define RADEON_GMC_DST_16BPP (4 << 8)
451# define RADEON_GMC_DST_24BPP (5 << 8)
452# define RADEON_GMC_DST_32BPP (6 << 8)
453# define RADEON_GMC_DST_DATATYPE_SHIFT 8
454# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
455# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
456# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
457# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
458# define RADEON_GMC_WR_MSK_DIS (1 << 30)
459# define RADEON_ROP3_S 0x00cc0000
460# define RADEON_ROP3_P 0x00f00000
461#define RADEON_DP_WRITE_MASK 0x16cc
3e14a286 462#define RADEON_SRC_PITCH_OFFSET 0x1428
1da177e4
LT		 463#define RADEON_DST_PITCH_OFFSET 0x142c
464#define RADEON_DST_PITCH_OFFSET_C 0x1c80
465# define RADEON_DST_TILE_LINEAR (0 << 30)
466# define RADEON_DST_TILE_MACRO (1 << 30)
467# define RADEON_DST_TILE_MICRO (2 << 30)
468# define RADEON_DST_TILE_BOTH (3 << 30)
469
470#define RADEON_SCRATCH_REG0 0x15e0
471#define RADEON_SCRATCH_REG1 0x15e4
472#define RADEON_SCRATCH_REG2 0x15e8
473#define RADEON_SCRATCH_REG3 0x15ec
474#define RADEON_SCRATCH_REG4 0x15f0
475#define RADEON_SCRATCH_REG5 0x15f4
476#define RADEON_SCRATCH_UMSK 0x0770
477#define RADEON_SCRATCH_ADDR 0x0774
478
479#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
480
481#define GET_SCRATCH( x ) (dev_priv->writeback_works \
482 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
483 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
484
1da177e4
LT		 485#define RADEON_GEN_INT_CNTL 0x0040
486# define RADEON_CRTC_VBLANK_MASK (1 << 0)
487# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
488# define RADEON_SW_INT_ENABLE (1 << 25)
489
490#define RADEON_GEN_INT_STATUS 0x0044
491# define RADEON_CRTC_VBLANK_STAT (1 << 0)
492# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
493# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
494# define RADEON_SW_INT_TEST (1 << 25)
495# define RADEON_SW_INT_TEST_ACK (1 << 25)
496# define RADEON_SW_INT_FIRE (1 << 26)
497
498#define RADEON_HOST_PATH_CNTL 0x0130
499# define RADEON_HDP_SOFT_RESET (1 << 26)
500# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
501# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
502
503#define RADEON_ISYNC_CNTL 0x1724
504# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
505# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
506# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
507# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
508# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
509# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
510
511#define RADEON_RBBM_GUICNTL 0x172c
512# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
513# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
514# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
515# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
516
517#define RADEON_MC_AGP_LOCATION 0x014c
518#define RADEON_MC_FB_LOCATION 0x0148
519#define RADEON_MCLK_CNTL 0x0012
520# define RADEON_FORCEON_MCLKA (1 << 16)
521# define RADEON_FORCEON_MCLKB (1 << 17)
522# define RADEON_FORCEON_YCLKA (1 << 18)
523# define RADEON_FORCEON_YCLKB (1 << 19)
524# define RADEON_FORCEON_MC (1 << 20)
525# define RADEON_FORCEON_AIC (1 << 21)
526
527#define RADEON_PP_BORDER_COLOR_0 0x1d40
528#define RADEON_PP_BORDER_COLOR_1 0x1d44
529#define RADEON_PP_BORDER_COLOR_2 0x1d48
530#define RADEON_PP_CNTL 0x1c38
531# define RADEON_SCISSOR_ENABLE (1 << 1)
532#define RADEON_PP_LUM_MATRIX 0x1d00
533#define RADEON_PP_MISC 0x1c14
534#define RADEON_PP_ROT_MATRIX_0 0x1d58
535#define RADEON_PP_TXFILTER_0 0x1c54
536#define RADEON_PP_TXOFFSET_0 0x1c5c
537#define RADEON_PP_TXFILTER_1 0x1c6c
538#define RADEON_PP_TXFILTER_2 0x1c84
539
540#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
541# define RADEON_RB2D_DC_FLUSH (3 << 0)
542# define RADEON_RB2D_DC_FREE (3 << 2)
543# define RADEON_RB2D_DC_FLUSH_ALL 0xf
544# define RADEON_RB2D_DC_BUSY (1 << 31)
545#define RADEON_RB3D_CNTL 0x1c3c
546# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
547# define RADEON_PLANE_MASK_ENABLE (1 << 1)
548# define RADEON_DITHER_ENABLE (1 << 2)
549# define RADEON_ROUND_ENABLE (1 << 3)
550# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
551# define RADEON_DITHER_INIT (1 << 5)
552# define RADEON_ROP_ENABLE (1 << 6)
553# define RADEON_STENCIL_ENABLE (1 << 7)
554# define RADEON_Z_ENABLE (1 << 8)
555# define RADEON_ZBLOCK16 (1 << 15)
556#define RADEON_RB3D_DEPTHOFFSET 0x1c24
557#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
558#define RADEON_RB3D_DEPTHPITCH 0x1c28
559#define RADEON_RB3D_PLANEMASK 0x1d84
560#define RADEON_RB3D_STENCILREFMASK 0x1d7c
561#define RADEON_RB3D_ZCACHE_MODE 0x3250
562#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
563# define RADEON_RB3D_ZC_FLUSH (1 << 0)
564# define RADEON_RB3D_ZC_FREE (1 << 2)
565# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
566# define RADEON_RB3D_ZC_BUSY (1 << 31)
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MD		 567#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
568# define RADEON_RB3D_DC_FLUSH (3 << 0)
569# define RADEON_RB3D_DC_FREE (3 << 2)
570# define RADEON_RB3D_DC_FLUSH_ALL 0xf
571# define RADEON_RB3D_DC_BUSY (1 << 31)
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LT		 572#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
573# define RADEON_Z_TEST_MASK (7 << 4)
574# define RADEON_Z_TEST_ALWAYS (7 << 4)
575# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
576# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
577# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
578# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
579# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
580# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
581# define RADEON_FORCE_Z_DIRTY (1 << 29)
582# define RADEON_Z_WRITE_ENABLE (1 << 30)
583# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
584#define RADEON_RBBM_SOFT_RESET 0x00f0
585# define RADEON_SOFT_RESET_CP (1 << 0)
586# define RADEON_SOFT_RESET_HI (1 << 1)
587# define RADEON_SOFT_RESET_SE (1 << 2)
588# define RADEON_SOFT_RESET_RE (1 << 3)
589# define RADEON_SOFT_RESET_PP (1 << 4)
590# define RADEON_SOFT_RESET_E2 (1 << 5)
591# define RADEON_SOFT_RESET_RB (1 << 6)
592# define RADEON_SOFT_RESET_HDP (1 << 7)
593#define RADEON_RBBM_STATUS 0x0e40
594# define RADEON_RBBM_FIFOCNT_MASK 0x007f
595# define RADEON_RBBM_ACTIVE (1 << 31)
596#define RADEON_RE_LINE_PATTERN 0x1cd0
597#define RADEON_RE_MISC 0x26c4
598#define RADEON_RE_TOP_LEFT 0x26c0
599#define RADEON_RE_WIDTH_HEIGHT 0x1c44
600#define RADEON_RE_STIPPLE_ADDR 0x1cc8
601#define RADEON_RE_STIPPLE_DATA 0x1ccc
602
603#define RADEON_SCISSOR_TL_0 0x1cd8
604#define RADEON_SCISSOR_BR_0 0x1cdc
605#define RADEON_SCISSOR_TL_1 0x1ce0
606#define RADEON_SCISSOR_BR_1 0x1ce4
607#define RADEON_SCISSOR_TL_2 0x1ce8
608#define RADEON_SCISSOR_BR_2 0x1cec
609#define RADEON_SE_COORD_FMT 0x1c50
610#define RADEON_SE_CNTL 0x1c4c
611# define RADEON_FFACE_CULL_CW (0 << 0)
612# define RADEON_BFACE_SOLID (3 << 1)
613# define RADEON_FFACE_SOLID (3 << 3)
614# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
615# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
616# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
617# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
618# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
619# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
620# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
621# define RADEON_FOG_SHADE_FLAT (1 << 14)
622# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
623# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
624# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
625# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
626# define RADEON_ROUND_MODE_TRUNC (0 << 28)
627# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
628#define RADEON_SE_CNTL_STATUS 0x2140
629#define RADEON_SE_LINE_WIDTH 0x1db8
630#define RADEON_SE_VPORT_XSCALE 0x1d98
631#define RADEON_SE_ZBIAS_FACTOR 0x1db0
632#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
633#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
634#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
635# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
636# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
637#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
638#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
639# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
640#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
641#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
642#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
643#define RADEON_SURFACE_CNTL 0x0b00
644# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
645# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
646# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
647# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
648# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
649# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
650# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
651# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
652# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
653#define RADEON_SURFACE0_INFO 0x0b0c
654# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
655# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
656# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
657# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
658# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
659# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
660#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
661#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
662# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
663#define RADEON_SURFACE1_INFO 0x0b1c
664#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
665#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
666#define RADEON_SURFACE2_INFO 0x0b2c
667#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
668#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
669#define RADEON_SURFACE3_INFO 0x0b3c
670#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
671#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
672#define RADEON_SURFACE4_INFO 0x0b4c
673#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
674#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
675#define RADEON_SURFACE5_INFO 0x0b5c
676#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
677#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
678#define RADEON_SURFACE6_INFO 0x0b6c
679#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
680#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
681#define RADEON_SURFACE7_INFO 0x0b7c
682#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
683#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
684#define RADEON_SW_SEMAPHORE 0x013c
685
686#define RADEON_WAIT_UNTIL 0x1720
687# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
d985c108
DA		 688# define RADEON_WAIT_2D_IDLE (1 << 14)
689# define RADEON_WAIT_3D_IDLE (1 << 15)
1da177e4
LT		 690# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
691# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
692# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
693
694#define RADEON_RB3D_ZMASKOFFSET 0x3234
695#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
696# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
697# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
698
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LT		 699/* CP registers */
700#define RADEON_CP_ME_RAM_ADDR 0x07d4
701#define RADEON_CP_ME_RAM_RADDR 0x07d8
702#define RADEON_CP_ME_RAM_DATAH 0x07dc
703#define RADEON_CP_ME_RAM_DATAL 0x07e0
704
705#define RADEON_CP_RB_BASE 0x0700
706#define RADEON_CP_RB_CNTL 0x0704
707# define RADEON_BUF_SWAP_32BIT (2 << 16)
ae1b1a48 708# define RADEON_RB_NO_UPDATE (1 << 27)
1da177e4
LT		 709#define RADEON_CP_RB_RPTR_ADDR 0x070c
710#define RADEON_CP_RB_RPTR 0x0710
711#define RADEON_CP_RB_WPTR 0x0714
712
713#define RADEON_CP_RB_WPTR_DELAY 0x0718
714# define RADEON_PRE_WRITE_TIMER_SHIFT 0
715# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
716
717#define RADEON_CP_IB_BASE 0x0738
718
719#define RADEON_CP_CSQ_CNTL 0x0740
720# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
721# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
722# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
723# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
724# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
725# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
726# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
727
728#define RADEON_AIC_CNTL 0x01d0
729# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
730#define RADEON_AIC_STAT 0x01d4
731#define RADEON_AIC_PT_BASE 0x01d8
732#define RADEON_AIC_LO_ADDR 0x01dc
733#define RADEON_AIC_HI_ADDR 0x01e0
734#define RADEON_AIC_TLB_ADDR 0x01e4
735#define RADEON_AIC_TLB_DATA 0x01e8
736
737/* CP command packets */
738#define RADEON_CP_PACKET0 0x00000000
739# define RADEON_ONE_REG_WR (1 << 15)
740#define RADEON_CP_PACKET1 0x40000000
741#define RADEON_CP_PACKET2 0x80000000
742#define RADEON_CP_PACKET3 0xC0000000
414ed537
DA		 743# define RADEON_CP_NOP 0x00001000
744# define RADEON_CP_NEXT_CHAR 0x00001900
745# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
746# define RADEON_CP_SET_SCISSORS 0x00001E00
b5e89ed5 747 /* GEN_INDX_PRIM is unsupported starting with R300 */
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LT		 748# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
749# define RADEON_WAIT_FOR_IDLE 0x00002600
750# define RADEON_3D_DRAW_VBUF 0x00002800
751# define RADEON_3D_DRAW_IMMD 0x00002900
752# define RADEON_3D_DRAW_INDX 0x00002A00
414ed537 753# define RADEON_CP_LOAD_PALETTE 0x00002C00
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LT		 754# define RADEON_3D_LOAD_VBPNTR 0x00002F00
755# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
756# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
757# define RADEON_3D_CLEAR_ZMASK 0x00003200
414ed537
DA		 758# define RADEON_CP_INDX_BUFFER 0x00003300
759# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
760# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
761# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1da177e4 762# define RADEON_3D_CLEAR_HIZ 0x00003700
414ed537 763# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
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LT		 764# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
765# define RADEON_CNTL_PAINT_MULTI 0x00009A00
766# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
767# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
768
769#define RADEON_CP_PACKET_MASK 0xC0000000
770#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
771#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
772#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
773#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
774
775#define RADEON_VTX_Z_PRESENT (1 << 31)
776#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
777
778#define RADEON_PRIM_TYPE_NONE (0 << 0)
779#define RADEON_PRIM_TYPE_POINT (1 << 0)
780#define RADEON_PRIM_TYPE_LINE (2 << 0)
781#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
782#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
783#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
784#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
785#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
786#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
787#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
788#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
789#define RADEON_PRIM_TYPE_MASK 0xf
790#define RADEON_PRIM_WALK_IND (1 << 4)
791#define RADEON_PRIM_WALK_LIST (2 << 4)
792#define RADEON_PRIM_WALK_RING (3 << 4)
793#define RADEON_COLOR_ORDER_BGRA (0 << 6)
794#define RADEON_COLOR_ORDER_RGBA (1 << 6)
795#define RADEON_MAOS_ENABLE (1 << 7)
796#define RADEON_VTX_FMT_R128_MODE (0 << 8)
797#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
798#define RADEON_NUM_VERTICES_SHIFT 16
799
800#define RADEON_COLOR_FORMAT_CI8 2
801#define RADEON_COLOR_FORMAT_ARGB1555 3
802#define RADEON_COLOR_FORMAT_RGB565 4
803#define RADEON_COLOR_FORMAT_ARGB8888 6
804#define RADEON_COLOR_FORMAT_RGB332 7
805#define RADEON_COLOR_FORMAT_RGB8 9
806#define RADEON_COLOR_FORMAT_ARGB4444 15
807
808#define RADEON_TXFORMAT_I8 0
809#define RADEON_TXFORMAT_AI88 1
810#define RADEON_TXFORMAT_RGB332 2
811#define RADEON_TXFORMAT_ARGB1555 3
812#define RADEON_TXFORMAT_RGB565 4
813#define RADEON_TXFORMAT_ARGB4444 5
814#define RADEON_TXFORMAT_ARGB8888 6
815#define RADEON_TXFORMAT_RGBA8888 7
816#define RADEON_TXFORMAT_Y8 8
817#define RADEON_TXFORMAT_VYUY422 10
818#define RADEON_TXFORMAT_YVYU422 11
819#define RADEON_TXFORMAT_DXT1 12
820#define RADEON_TXFORMAT_DXT23 14
821#define RADEON_TXFORMAT_DXT45 15
822
823#define R200_PP_TXCBLEND_0 0x2f00
824#define R200_PP_TXCBLEND_1 0x2f10
825#define R200_PP_TXCBLEND_2 0x2f20
826#define R200_PP_TXCBLEND_3 0x2f30
827#define R200_PP_TXCBLEND_4 0x2f40
828#define R200_PP_TXCBLEND_5 0x2f50
829#define R200_PP_TXCBLEND_6 0x2f60
830#define R200_PP_TXCBLEND_7 0x2f70
b5e89ed5 831#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
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LT		 832#define R200_PP_TFACTOR_0 0x2ee0
833#define R200_SE_VTX_FMT_0 0x2088
834#define R200_SE_VAP_CNTL 0x2080
835#define R200_SE_TCL_MATRIX_SEL_0 0x2230
b5e89ed5
DA		 836#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
837#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
838#define R200_PP_TXFILTER_5 0x2ca0
839#define R200_PP_TXFILTER_4 0x2c80
840#define R200_PP_TXFILTER_3 0x2c60
841#define R200_PP_TXFILTER_2 0x2c40
842#define R200_PP_TXFILTER_1 0x2c20
843#define R200_PP_TXFILTER_0 0x2c00
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LT		 844#define R200_PP_TXOFFSET_5 0x2d78
845#define R200_PP_TXOFFSET_4 0x2d60
846#define R200_PP_TXOFFSET_3 0x2d48
847#define R200_PP_TXOFFSET_2 0x2d30
848#define R200_PP_TXOFFSET_1 0x2d18
849#define R200_PP_TXOFFSET_0 0x2d00
850
851#define R200_PP_CUBIC_FACES_0 0x2c18
852#define R200_PP_CUBIC_FACES_1 0x2c38
853#define R200_PP_CUBIC_FACES_2 0x2c58
854#define R200_PP_CUBIC_FACES_3 0x2c78
855#define R200_PP_CUBIC_FACES_4 0x2c98
856#define R200_PP_CUBIC_FACES_5 0x2cb8
857#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
858#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
859#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
860#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
861#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
862#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
863#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
864#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
865#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
866#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
867#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
868#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
869#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
870#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
871#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
872#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
873#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
874#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
875#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
876#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
877#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
878#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
879#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
880#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
881#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
882#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
883#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
884#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
885#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
886#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
887
888#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
889#define R200_SE_VTE_CNTL 0x20b0
890#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
891#define R200_PP_TAM_DEBUG3 0x2d9c
892#define R200_PP_CNTL_X 0x2cc4
893#define R200_SE_VAP_CNTL_STATUS 0x2140
894#define R200_RE_SCISSOR_TL_0 0x1cd8
895#define R200_RE_SCISSOR_TL_1 0x1ce0
896#define R200_RE_SCISSOR_TL_2 0x1ce8
b5e89ed5 897#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
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LT		 898#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
899#define R200_SE_VTX_STATE_CNTL 0x2180
900#define R200_RE_POINTSIZE 0x2648
901#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
902
b5e89ed5 903#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
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LT		 904#define RADEON_PP_TEX_SIZE_1 0x1d0c
905#define RADEON_PP_TEX_SIZE_2 0x1d14
906
907#define RADEON_PP_CUBIC_FACES_0 0x1d24
908#define RADEON_PP_CUBIC_FACES_1 0x1d28
909#define RADEON_PP_CUBIC_FACES_2 0x1d2c
910#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
911#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
912#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
913
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DA		 914#define RADEON_SE_TCL_STATE_FLUSH 0x2284
915
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LT		 916#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
917#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
918#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
919#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
920#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
921#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
922#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
923#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
924#define R200_3D_DRAW_IMMD_2 0xC0003500
925#define R200_SE_VTX_FMT_1 0x208c
b5e89ed5 926#define R200_RE_CNTL 0x1c50
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LT		 927
928#define R200_RB3D_BLENDCOLOR 0x3218
929
930#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
931
932#define R200_PP_TRI_PERF 0x2cf8
933
9d17601c 934#define R200_PP_AFS_0 0x2f80
b5e89ed5 935#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
9d17601c 936
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DA		 937#define R200_VAP_PVS_CNTL_1 0x22D0
938
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LT		 939/* Constants */
940#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
941
942#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
943#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
944#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
945#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
946#define RADEON_LAST_DISPATCH 1
947
948#define RADEON_MAX_VB_AGE 0x7fffffff
949#define RADEON_MAX_VB_VERTS (0xffff)
950
951#define RADEON_RING_HIGH_MARK 128
952
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DA		 953#define RADEON_PCIGART_TABLE_SIZE (32*1024)
954
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LT		 955#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
956#define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
957#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
958#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
959
960#define RADEON_WRITE_PLL( addr, val ) \
961do { \
962 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
963 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
964 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
965} while (0)
966
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DA		 967#define RADEON_WRITE_PCIE( addr, val ) \
968do { \
969 RADEON_WRITE8( RADEON_PCIE_INDEX, \
970 ((addr) & 0xff)); \
971 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
972} while (0)
973
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LT		 974#define CP_PACKET0( reg, n ) \
975 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
976#define CP_PACKET0_TABLE( reg, n ) \
977 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
978#define CP_PACKET1( reg0, reg1 ) \
979 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
980#define CP_PACKET2() \
981 (RADEON_CP_PACKET2)
982#define CP_PACKET3( pkt, n ) \
983 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
984
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LT		 985/* ================================================================
986 * Engine control helper macros
987 */
988
989#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
990 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
991 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
992 RADEON_WAIT_HOST_IDLECLEAN) ); \
993} while (0)
994
995#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
996 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
997 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
998 RADEON_WAIT_HOST_IDLECLEAN) ); \
999} while (0)
1000
1001#define RADEON_WAIT_UNTIL_IDLE() do { \
1002 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1003 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1004 RADEON_WAIT_3D_IDLECLEAN | \
1005 RADEON_WAIT_HOST_IDLECLEAN) ); \
1006} while (0)
1007
1008#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1009 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1010 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1011} while (0)
1012
1013#define RADEON_FLUSH_CACHE() do { \
b9b603dd 1014 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
b15ec368 1015 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
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LT		 1016} while (0)
1017
1018#define RADEON_PURGE_CACHE() do { \
b9b603dd 1019 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
b15ec368 1020 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
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LT		 1021} while (0)
1022
1023#define RADEON_FLUSH_ZCACHE() do { \
1024 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1025 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1026} while (0)
1027
1028#define RADEON_PURGE_ZCACHE() do { \
1029 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1030 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1031} while (0)
1032
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LT		 1033/* ================================================================
1034 * Misc helper macros
1035 */
1036
b5e89ed5 1037/* Perfbox functionality only.
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LT		 1038 */
1039#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1040do { \
1041 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1042 u32 head = GET_RING_HEAD( dev_priv ); \
1043 if (head == dev_priv->ring.tail) \
1044 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1045 } \
1046} while (0)
1047
1048#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1049do { \
1050 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1051 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1052 int __ret = radeon_do_cp_idle( dev_priv ); \
1053 if ( __ret ) return __ret; \
1054 sarea_priv->last_dispatch = 0; \
1055 radeon_freelist_reset( dev ); \
1056 } \
1057} while (0)
1058
1059#define RADEON_DISPATCH_AGE( age ) do { \
1060 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1061 OUT_RING( age ); \
1062} while (0)
1063
1064#define RADEON_FRAME_AGE( age ) do { \
1065 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1066 OUT_RING( age ); \
1067} while (0)
1068
1069#define RADEON_CLEAR_AGE( age ) do { \
1070 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1071 OUT_RING( age ); \
1072} while (0)
1073
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LT		 1074/* ================================================================
1075 * Ring control
1076 */
1077
1078#define RADEON_VERBOSE 0
1079
1080#define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1081
1082#define BEGIN_RING( n ) do { \
1083 if ( RADEON_VERBOSE ) { \
1084 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1085 n, __FUNCTION__ ); \
1086 } \
1087 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1088 COMMIT_RING(); \
1089 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1090 } \
1091 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1092 ring = dev_priv->ring.start; \
1093 write = dev_priv->ring.tail; \
1094 mask = dev_priv->ring.tail_mask; \
1095} while (0)
1096
1097#define ADVANCE_RING() do { \
1098 if ( RADEON_VERBOSE ) { \
1099 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1100 write, dev_priv->ring.tail ); \
1101 } \
1102 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1103 DRM_ERROR( \
1104 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1105 ((dev_priv->ring.tail + _nr) & mask), \
1106 write, __LINE__); \
1107 } else \
1108 dev_priv->ring.tail = write; \
1109} while (0)
1110
1111#define COMMIT_RING() do { \
1112 /* Flush writes to ring */ \
1113 DRM_MEMORYBARRIER(); \
1114 GET_RING_HEAD( dev_priv ); \
1115 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1116 /* read from PCI bus to ensure correct posting */ \
1117 RADEON_READ( RADEON_CP_RB_RPTR ); \
1118} while (0)
1119
1120#define OUT_RING( x ) do { \
1121 if ( RADEON_VERBOSE ) { \
1122 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1123 (unsigned int)(x), write ); \
1124 } \
1125 ring[write++] = (x); \
1126 write &= mask; \
1127} while (0)
1128
1129#define OUT_RING_REG( reg, val ) do { \
1130 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1131 OUT_RING( val ); \
1132} while (0)
1133
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LT		 1134#define OUT_RING_TABLE( tab, sz ) do { \
1135 int _size = (sz); \
1136 int *_tab = (int *)(tab); \
1137 \
1138 if (write + _size > mask) { \
1139 int _i = (mask+1) - write; \
1140 _size -= _i; \
1141 while (_i > 0 ) { \
1142 *(int *)(ring + write) = *_tab++; \
1143 write++; \
1144 _i--; \
1145 } \
1146 write = 0; \
1147 _tab += _i; \
1148 } \
1da177e4
LT		 1149 while (_size > 0) { \
1150 *(ring + write) = *_tab++; \
1151 write++; \
1152 _size--; \
1153 } \
1154 write &= mask; \
1155} while (0)
1156
b5e89ed5 1157#endif /* __RADEON_DRV_H__ */
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