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1da177e4 LT |
1 | /* r128_state.c -- State support for r128 -*- linux-c -*- |
2 | * Created: Thu Jan 27 02:53:43 2000 by gareth@valinux.com | |
f26c473c | 3 | */ |
83a9e29b DA |
4 | /* |
5 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
1da177e4 LT |
6 | * All Rights Reserved. |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the next | |
16 | * paragraph) shall be included in all copies or substantial portions of the | |
17 | * Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
20 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
21 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
22 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
23 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
25 | * DEALINGS IN THE SOFTWARE. | |
26 | * | |
27 | * Authors: | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | */ | |
30 | ||
31 | #include "drmP.h" | |
32 | #include "drm.h" | |
33 | #include "r128_drm.h" | |
34 | #include "r128_drv.h" | |
35 | ||
1da177e4 LT |
36 | /* ================================================================ |
37 | * CCE hardware state programming functions | |
38 | */ | |
39 | ||
b5e89ed5 | 40 | static void r128_emit_clip_rects(drm_r128_private_t * dev_priv, |
eddca551 | 41 | struct drm_clip_rect * boxes, int count) |
1da177e4 LT |
42 | { |
43 | u32 aux_sc_cntl = 0x00000000; | |
44 | RING_LOCALS; | |
b5e89ed5 | 45 | DRM_DEBUG(" %s\n", __FUNCTION__); |
1da177e4 | 46 | |
b5e89ed5 | 47 | BEGIN_RING((count < 3 ? count : 3) * 5 + 2); |
1da177e4 | 48 | |
b5e89ed5 DA |
49 | if (count >= 1) { |
50 | OUT_RING(CCE_PACKET0(R128_AUX1_SC_LEFT, 3)); | |
51 | OUT_RING(boxes[0].x1); | |
52 | OUT_RING(boxes[0].x2 - 1); | |
53 | OUT_RING(boxes[0].y1); | |
54 | OUT_RING(boxes[0].y2 - 1); | |
1da177e4 LT |
55 | |
56 | aux_sc_cntl |= (R128_AUX1_SC_EN | R128_AUX1_SC_MODE_OR); | |
57 | } | |
b5e89ed5 DA |
58 | if (count >= 2) { |
59 | OUT_RING(CCE_PACKET0(R128_AUX2_SC_LEFT, 3)); | |
60 | OUT_RING(boxes[1].x1); | |
61 | OUT_RING(boxes[1].x2 - 1); | |
62 | OUT_RING(boxes[1].y1); | |
63 | OUT_RING(boxes[1].y2 - 1); | |
1da177e4 LT |
64 | |
65 | aux_sc_cntl |= (R128_AUX2_SC_EN | R128_AUX2_SC_MODE_OR); | |
66 | } | |
b5e89ed5 DA |
67 | if (count >= 3) { |
68 | OUT_RING(CCE_PACKET0(R128_AUX3_SC_LEFT, 3)); | |
69 | OUT_RING(boxes[2].x1); | |
70 | OUT_RING(boxes[2].x2 - 1); | |
71 | OUT_RING(boxes[2].y1); | |
72 | OUT_RING(boxes[2].y2 - 1); | |
1da177e4 LT |
73 | |
74 | aux_sc_cntl |= (R128_AUX3_SC_EN | R128_AUX3_SC_MODE_OR); | |
75 | } | |
76 | ||
b5e89ed5 DA |
77 | OUT_RING(CCE_PACKET0(R128_AUX_SC_CNTL, 0)); |
78 | OUT_RING(aux_sc_cntl); | |
1da177e4 LT |
79 | |
80 | ADVANCE_RING(); | |
81 | } | |
82 | ||
b5e89ed5 | 83 | static __inline__ void r128_emit_core(drm_r128_private_t * dev_priv) |
1da177e4 LT |
84 | { |
85 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
86 | drm_r128_context_regs_t *ctx = &sarea_priv->context_state; | |
87 | RING_LOCALS; | |
b5e89ed5 | 88 | DRM_DEBUG(" %s\n", __FUNCTION__); |
1da177e4 | 89 | |
b5e89ed5 | 90 | BEGIN_RING(2); |
1da177e4 | 91 | |
b5e89ed5 DA |
92 | OUT_RING(CCE_PACKET0(R128_SCALE_3D_CNTL, 0)); |
93 | OUT_RING(ctx->scale_3d_cntl); | |
1da177e4 LT |
94 | |
95 | ADVANCE_RING(); | |
96 | } | |
97 | ||
b5e89ed5 | 98 | static __inline__ void r128_emit_context(drm_r128_private_t * dev_priv) |
1da177e4 LT |
99 | { |
100 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
101 | drm_r128_context_regs_t *ctx = &sarea_priv->context_state; | |
102 | RING_LOCALS; | |
b5e89ed5 DA |
103 | DRM_DEBUG(" %s\n", __FUNCTION__); |
104 | ||
105 | BEGIN_RING(13); | |
106 | ||
107 | OUT_RING(CCE_PACKET0(R128_DST_PITCH_OFFSET_C, 11)); | |
108 | OUT_RING(ctx->dst_pitch_offset_c); | |
109 | OUT_RING(ctx->dp_gui_master_cntl_c); | |
110 | OUT_RING(ctx->sc_top_left_c); | |
111 | OUT_RING(ctx->sc_bottom_right_c); | |
112 | OUT_RING(ctx->z_offset_c); | |
113 | OUT_RING(ctx->z_pitch_c); | |
114 | OUT_RING(ctx->z_sten_cntl_c); | |
115 | OUT_RING(ctx->tex_cntl_c); | |
116 | OUT_RING(ctx->misc_3d_state_cntl_reg); | |
117 | OUT_RING(ctx->texture_clr_cmp_clr_c); | |
118 | OUT_RING(ctx->texture_clr_cmp_msk_c); | |
119 | OUT_RING(ctx->fog_color_c); | |
1da177e4 LT |
120 | |
121 | ADVANCE_RING(); | |
122 | } | |
123 | ||
b5e89ed5 | 124 | static __inline__ void r128_emit_setup(drm_r128_private_t * dev_priv) |
1da177e4 LT |
125 | { |
126 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
127 | drm_r128_context_regs_t *ctx = &sarea_priv->context_state; | |
128 | RING_LOCALS; | |
b5e89ed5 | 129 | DRM_DEBUG(" %s\n", __FUNCTION__); |
1da177e4 | 130 | |
b5e89ed5 | 131 | BEGIN_RING(3); |
1da177e4 | 132 | |
b5e89ed5 DA |
133 | OUT_RING(CCE_PACKET1(R128_SETUP_CNTL, R128_PM4_VC_FPU_SETUP)); |
134 | OUT_RING(ctx->setup_cntl); | |
135 | OUT_RING(ctx->pm4_vc_fpu_setup); | |
1da177e4 LT |
136 | |
137 | ADVANCE_RING(); | |
138 | } | |
139 | ||
b5e89ed5 | 140 | static __inline__ void r128_emit_masks(drm_r128_private_t * dev_priv) |
1da177e4 LT |
141 | { |
142 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
143 | drm_r128_context_regs_t *ctx = &sarea_priv->context_state; | |
144 | RING_LOCALS; | |
b5e89ed5 | 145 | DRM_DEBUG(" %s\n", __FUNCTION__); |
1da177e4 | 146 | |
b5e89ed5 | 147 | BEGIN_RING(5); |
1da177e4 | 148 | |
b5e89ed5 DA |
149 | OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); |
150 | OUT_RING(ctx->dp_write_mask); | |
1da177e4 | 151 | |
b5e89ed5 DA |
152 | OUT_RING(CCE_PACKET0(R128_STEN_REF_MASK_C, 1)); |
153 | OUT_RING(ctx->sten_ref_mask_c); | |
154 | OUT_RING(ctx->plane_3d_mask_c); | |
1da177e4 LT |
155 | |
156 | ADVANCE_RING(); | |
157 | } | |
158 | ||
b5e89ed5 | 159 | static __inline__ void r128_emit_window(drm_r128_private_t * dev_priv) |
1da177e4 LT |
160 | { |
161 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
162 | drm_r128_context_regs_t *ctx = &sarea_priv->context_state; | |
163 | RING_LOCALS; | |
b5e89ed5 | 164 | DRM_DEBUG(" %s\n", __FUNCTION__); |
1da177e4 | 165 | |
b5e89ed5 | 166 | BEGIN_RING(2); |
1da177e4 | 167 | |
b5e89ed5 DA |
168 | OUT_RING(CCE_PACKET0(R128_WINDOW_XY_OFFSET, 0)); |
169 | OUT_RING(ctx->window_xy_offset); | |
1da177e4 LT |
170 | |
171 | ADVANCE_RING(); | |
172 | } | |
173 | ||
b5e89ed5 | 174 | static __inline__ void r128_emit_tex0(drm_r128_private_t * dev_priv) |
1da177e4 LT |
175 | { |
176 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
177 | drm_r128_context_regs_t *ctx = &sarea_priv->context_state; | |
178 | drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[0]; | |
179 | int i; | |
180 | RING_LOCALS; | |
b5e89ed5 | 181 | DRM_DEBUG(" %s\n", __FUNCTION__); |
1da177e4 | 182 | |
b5e89ed5 | 183 | BEGIN_RING(7 + R128_MAX_TEXTURE_LEVELS); |
1da177e4 | 184 | |
b5e89ed5 DA |
185 | OUT_RING(CCE_PACKET0(R128_PRIM_TEX_CNTL_C, |
186 | 2 + R128_MAX_TEXTURE_LEVELS)); | |
187 | OUT_RING(tex->tex_cntl); | |
188 | OUT_RING(tex->tex_combine_cntl); | |
189 | OUT_RING(ctx->tex_size_pitch_c); | |
190 | for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { | |
191 | OUT_RING(tex->tex_offset[i]); | |
1da177e4 LT |
192 | } |
193 | ||
b5e89ed5 DA |
194 | OUT_RING(CCE_PACKET0(R128_CONSTANT_COLOR_C, 1)); |
195 | OUT_RING(ctx->constant_color_c); | |
196 | OUT_RING(tex->tex_border_color); | |
1da177e4 LT |
197 | |
198 | ADVANCE_RING(); | |
199 | } | |
200 | ||
b5e89ed5 | 201 | static __inline__ void r128_emit_tex1(drm_r128_private_t * dev_priv) |
1da177e4 LT |
202 | { |
203 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
204 | drm_r128_texture_regs_t *tex = &sarea_priv->tex_state[1]; | |
205 | int i; | |
206 | RING_LOCALS; | |
b5e89ed5 | 207 | DRM_DEBUG(" %s\n", __FUNCTION__); |
1da177e4 | 208 | |
b5e89ed5 | 209 | BEGIN_RING(5 + R128_MAX_TEXTURE_LEVELS); |
1da177e4 | 210 | |
b5e89ed5 DA |
211 | OUT_RING(CCE_PACKET0(R128_SEC_TEX_CNTL_C, 1 + R128_MAX_TEXTURE_LEVELS)); |
212 | OUT_RING(tex->tex_cntl); | |
213 | OUT_RING(tex->tex_combine_cntl); | |
214 | for (i = 0; i < R128_MAX_TEXTURE_LEVELS; i++) { | |
215 | OUT_RING(tex->tex_offset[i]); | |
1da177e4 LT |
216 | } |
217 | ||
b5e89ed5 DA |
218 | OUT_RING(CCE_PACKET0(R128_SEC_TEXTURE_BORDER_COLOR_C, 0)); |
219 | OUT_RING(tex->tex_border_color); | |
1da177e4 LT |
220 | |
221 | ADVANCE_RING(); | |
222 | } | |
223 | ||
858119e1 | 224 | static void r128_emit_state(drm_r128_private_t * dev_priv) |
1da177e4 LT |
225 | { |
226 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
227 | unsigned int dirty = sarea_priv->dirty; | |
228 | ||
b5e89ed5 | 229 | DRM_DEBUG("%s: dirty=0x%08x\n", __FUNCTION__, dirty); |
1da177e4 | 230 | |
b5e89ed5 DA |
231 | if (dirty & R128_UPLOAD_CORE) { |
232 | r128_emit_core(dev_priv); | |
1da177e4 LT |
233 | sarea_priv->dirty &= ~R128_UPLOAD_CORE; |
234 | } | |
235 | ||
b5e89ed5 DA |
236 | if (dirty & R128_UPLOAD_CONTEXT) { |
237 | r128_emit_context(dev_priv); | |
1da177e4 LT |
238 | sarea_priv->dirty &= ~R128_UPLOAD_CONTEXT; |
239 | } | |
240 | ||
b5e89ed5 DA |
241 | if (dirty & R128_UPLOAD_SETUP) { |
242 | r128_emit_setup(dev_priv); | |
1da177e4 LT |
243 | sarea_priv->dirty &= ~R128_UPLOAD_SETUP; |
244 | } | |
245 | ||
b5e89ed5 DA |
246 | if (dirty & R128_UPLOAD_MASKS) { |
247 | r128_emit_masks(dev_priv); | |
1da177e4 LT |
248 | sarea_priv->dirty &= ~R128_UPLOAD_MASKS; |
249 | } | |
250 | ||
b5e89ed5 DA |
251 | if (dirty & R128_UPLOAD_WINDOW) { |
252 | r128_emit_window(dev_priv); | |
1da177e4 LT |
253 | sarea_priv->dirty &= ~R128_UPLOAD_WINDOW; |
254 | } | |
255 | ||
b5e89ed5 DA |
256 | if (dirty & R128_UPLOAD_TEX0) { |
257 | r128_emit_tex0(dev_priv); | |
1da177e4 LT |
258 | sarea_priv->dirty &= ~R128_UPLOAD_TEX0; |
259 | } | |
260 | ||
b5e89ed5 DA |
261 | if (dirty & R128_UPLOAD_TEX1) { |
262 | r128_emit_tex1(dev_priv); | |
1da177e4 LT |
263 | sarea_priv->dirty &= ~R128_UPLOAD_TEX1; |
264 | } | |
265 | ||
266 | /* Turn off the texture cache flushing */ | |
267 | sarea_priv->context_state.tex_cntl_c &= ~R128_TEX_CACHE_FLUSH; | |
268 | ||
269 | sarea_priv->dirty &= ~R128_REQUIRE_QUIESCENCE; | |
270 | } | |
271 | ||
1da177e4 LT |
272 | #if R128_PERFORMANCE_BOXES |
273 | /* ================================================================ | |
274 | * Performance monitoring functions | |
275 | */ | |
276 | ||
b5e89ed5 DA |
277 | static void r128_clear_box(drm_r128_private_t * dev_priv, |
278 | int x, int y, int w, int h, int r, int g, int b) | |
1da177e4 LT |
279 | { |
280 | u32 pitch, offset; | |
281 | u32 fb_bpp, color; | |
282 | RING_LOCALS; | |
283 | ||
b5e89ed5 | 284 | switch (dev_priv->fb_bpp) { |
1da177e4 LT |
285 | case 16: |
286 | fb_bpp = R128_GMC_DST_16BPP; | |
287 | color = (((r & 0xf8) << 8) | | |
b5e89ed5 | 288 | ((g & 0xfc) << 3) | ((b & 0xf8) >> 3)); |
1da177e4 LT |
289 | break; |
290 | case 24: | |
291 | fb_bpp = R128_GMC_DST_24BPP; | |
292 | color = ((r << 16) | (g << 8) | b); | |
293 | break; | |
294 | case 32: | |
295 | fb_bpp = R128_GMC_DST_32BPP; | |
b5e89ed5 | 296 | color = (((0xff) << 24) | (r << 16) | (g << 8) | b); |
1da177e4 LT |
297 | break; |
298 | default: | |
299 | return; | |
300 | } | |
301 | ||
302 | offset = dev_priv->back_offset; | |
303 | pitch = dev_priv->back_pitch >> 3; | |
304 | ||
b5e89ed5 | 305 | BEGIN_RING(6); |
1da177e4 | 306 | |
b5e89ed5 DA |
307 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
308 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
309 | R128_GMC_BRUSH_SOLID_COLOR | | |
310 | fb_bpp | | |
311 | R128_GMC_SRC_DATATYPE_COLOR | | |
312 | R128_ROP3_P | | |
313 | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_AUX_CLIP_DIS); | |
1da177e4 | 314 | |
b5e89ed5 DA |
315 | OUT_RING((pitch << 21) | (offset >> 5)); |
316 | OUT_RING(color); | |
1da177e4 | 317 | |
b5e89ed5 DA |
318 | OUT_RING((x << 16) | y); |
319 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
320 | |
321 | ADVANCE_RING(); | |
322 | } | |
323 | ||
b5e89ed5 | 324 | static void r128_cce_performance_boxes(drm_r128_private_t * dev_priv) |
1da177e4 | 325 | { |
b5e89ed5 DA |
326 | if (atomic_read(&dev_priv->idle_count) == 0) { |
327 | r128_clear_box(dev_priv, 64, 4, 8, 8, 0, 255, 0); | |
1da177e4 | 328 | } else { |
b5e89ed5 | 329 | atomic_set(&dev_priv->idle_count, 0); |
1da177e4 LT |
330 | } |
331 | } | |
332 | ||
333 | #endif | |
334 | ||
1da177e4 LT |
335 | /* ================================================================ |
336 | * CCE command dispatch functions | |
337 | */ | |
338 | ||
b5e89ed5 | 339 | static void r128_print_dirty(const char *msg, unsigned int flags) |
1da177e4 | 340 | { |
b5e89ed5 DA |
341 | DRM_INFO("%s: (0x%x) %s%s%s%s%s%s%s%s%s\n", |
342 | msg, | |
343 | flags, | |
344 | (flags & R128_UPLOAD_CORE) ? "core, " : "", | |
345 | (flags & R128_UPLOAD_CONTEXT) ? "context, " : "", | |
346 | (flags & R128_UPLOAD_SETUP) ? "setup, " : "", | |
347 | (flags & R128_UPLOAD_TEX0) ? "tex0, " : "", | |
348 | (flags & R128_UPLOAD_TEX1) ? "tex1, " : "", | |
349 | (flags & R128_UPLOAD_MASKS) ? "masks, " : "", | |
350 | (flags & R128_UPLOAD_WINDOW) ? "window, " : "", | |
351 | (flags & R128_UPLOAD_CLIPRECTS) ? "cliprects, " : "", | |
352 | (flags & R128_REQUIRE_QUIESCENCE) ? "quiescence, " : ""); | |
1da177e4 LT |
353 | } |
354 | ||
eddca551 | 355 | static void r128_cce_dispatch_clear(struct drm_device * dev, |
b5e89ed5 | 356 | drm_r128_clear_t * clear) |
1da177e4 LT |
357 | { |
358 | drm_r128_private_t *dev_priv = dev->dev_private; | |
359 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
360 | int nbox = sarea_priv->nbox; | |
eddca551 | 361 | struct drm_clip_rect *pbox = sarea_priv->boxes; |
1da177e4 LT |
362 | unsigned int flags = clear->flags; |
363 | int i; | |
364 | RING_LOCALS; | |
b5e89ed5 | 365 | DRM_DEBUG("%s\n", __FUNCTION__); |
1da177e4 | 366 | |
b5e89ed5 | 367 | if (dev_priv->page_flipping && dev_priv->current_page == 1) { |
1da177e4 LT |
368 | unsigned int tmp = flags; |
369 | ||
370 | flags &= ~(R128_FRONT | R128_BACK); | |
b5e89ed5 DA |
371 | if (tmp & R128_FRONT) |
372 | flags |= R128_BACK; | |
373 | if (tmp & R128_BACK) | |
374 | flags |= R128_FRONT; | |
1da177e4 LT |
375 | } |
376 | ||
b5e89ed5 | 377 | for (i = 0; i < nbox; i++) { |
1da177e4 LT |
378 | int x = pbox[i].x1; |
379 | int y = pbox[i].y1; | |
380 | int w = pbox[i].x2 - x; | |
381 | int h = pbox[i].y2 - y; | |
382 | ||
b5e89ed5 DA |
383 | DRM_DEBUG("dispatch clear %d,%d-%d,%d flags 0x%x\n", |
384 | pbox[i].x1, pbox[i].y1, pbox[i].x2, | |
385 | pbox[i].y2, flags); | |
1da177e4 | 386 | |
b5e89ed5 DA |
387 | if (flags & (R128_FRONT | R128_BACK)) { |
388 | BEGIN_RING(2); | |
1da177e4 | 389 | |
b5e89ed5 DA |
390 | OUT_RING(CCE_PACKET0(R128_DP_WRITE_MASK, 0)); |
391 | OUT_RING(clear->color_mask); | |
1da177e4 LT |
392 | |
393 | ADVANCE_RING(); | |
394 | } | |
395 | ||
b5e89ed5 DA |
396 | if (flags & R128_FRONT) { |
397 | BEGIN_RING(6); | |
1da177e4 | 398 | |
b5e89ed5 DA |
399 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
400 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
401 | R128_GMC_BRUSH_SOLID_COLOR | | |
402 | (dev_priv->color_fmt << 8) | | |
403 | R128_GMC_SRC_DATATYPE_COLOR | | |
404 | R128_ROP3_P | | |
405 | R128_GMC_CLR_CMP_CNTL_DIS | | |
406 | R128_GMC_AUX_CLIP_DIS); | |
1da177e4 | 407 | |
b5e89ed5 DA |
408 | OUT_RING(dev_priv->front_pitch_offset_c); |
409 | OUT_RING(clear->clear_color); | |
1da177e4 | 410 | |
b5e89ed5 DA |
411 | OUT_RING((x << 16) | y); |
412 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
413 | |
414 | ADVANCE_RING(); | |
415 | } | |
416 | ||
b5e89ed5 DA |
417 | if (flags & R128_BACK) { |
418 | BEGIN_RING(6); | |
1da177e4 | 419 | |
b5e89ed5 DA |
420 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
421 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
422 | R128_GMC_BRUSH_SOLID_COLOR | | |
423 | (dev_priv->color_fmt << 8) | | |
424 | R128_GMC_SRC_DATATYPE_COLOR | | |
425 | R128_ROP3_P | | |
426 | R128_GMC_CLR_CMP_CNTL_DIS | | |
427 | R128_GMC_AUX_CLIP_DIS); | |
1da177e4 | 428 | |
b5e89ed5 DA |
429 | OUT_RING(dev_priv->back_pitch_offset_c); |
430 | OUT_RING(clear->clear_color); | |
1da177e4 | 431 | |
b5e89ed5 DA |
432 | OUT_RING((x << 16) | y); |
433 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
434 | |
435 | ADVANCE_RING(); | |
436 | } | |
437 | ||
b5e89ed5 DA |
438 | if (flags & R128_DEPTH) { |
439 | BEGIN_RING(6); | |
1da177e4 | 440 | |
b5e89ed5 DA |
441 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
442 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
443 | R128_GMC_BRUSH_SOLID_COLOR | | |
444 | (dev_priv->depth_fmt << 8) | | |
445 | R128_GMC_SRC_DATATYPE_COLOR | | |
446 | R128_ROP3_P | | |
447 | R128_GMC_CLR_CMP_CNTL_DIS | | |
448 | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); | |
1da177e4 | 449 | |
b5e89ed5 DA |
450 | OUT_RING(dev_priv->depth_pitch_offset_c); |
451 | OUT_RING(clear->clear_depth); | |
1da177e4 | 452 | |
b5e89ed5 DA |
453 | OUT_RING((x << 16) | y); |
454 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
455 | |
456 | ADVANCE_RING(); | |
457 | } | |
458 | } | |
459 | } | |
460 | ||
eddca551 | 461 | static void r128_cce_dispatch_swap(struct drm_device * dev) |
1da177e4 LT |
462 | { |
463 | drm_r128_private_t *dev_priv = dev->dev_private; | |
464 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
465 | int nbox = sarea_priv->nbox; | |
eddca551 | 466 | struct drm_clip_rect *pbox = sarea_priv->boxes; |
1da177e4 LT |
467 | int i; |
468 | RING_LOCALS; | |
b5e89ed5 | 469 | DRM_DEBUG("%s\n", __FUNCTION__); |
1da177e4 LT |
470 | |
471 | #if R128_PERFORMANCE_BOXES | |
472 | /* Do some trivial performance monitoring... | |
473 | */ | |
b5e89ed5 | 474 | r128_cce_performance_boxes(dev_priv); |
1da177e4 LT |
475 | #endif |
476 | ||
b5e89ed5 | 477 | for (i = 0; i < nbox; i++) { |
1da177e4 LT |
478 | int x = pbox[i].x1; |
479 | int y = pbox[i].y1; | |
480 | int w = pbox[i].x2 - x; | |
481 | int h = pbox[i].y2 - y; | |
482 | ||
b5e89ed5 | 483 | BEGIN_RING(7); |
1da177e4 | 484 | |
b5e89ed5 DA |
485 | OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); |
486 | OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | | |
487 | R128_GMC_DST_PITCH_OFFSET_CNTL | | |
488 | R128_GMC_BRUSH_NONE | | |
489 | (dev_priv->color_fmt << 8) | | |
490 | R128_GMC_SRC_DATATYPE_COLOR | | |
491 | R128_ROP3_S | | |
492 | R128_DP_SRC_SOURCE_MEMORY | | |
493 | R128_GMC_CLR_CMP_CNTL_DIS | | |
494 | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS); | |
1da177e4 LT |
495 | |
496 | /* Make this work even if front & back are flipped: | |
497 | */ | |
498 | if (dev_priv->current_page == 0) { | |
b5e89ed5 DA |
499 | OUT_RING(dev_priv->back_pitch_offset_c); |
500 | OUT_RING(dev_priv->front_pitch_offset_c); | |
501 | } else { | |
502 | OUT_RING(dev_priv->front_pitch_offset_c); | |
503 | OUT_RING(dev_priv->back_pitch_offset_c); | |
1da177e4 LT |
504 | } |
505 | ||
b5e89ed5 DA |
506 | OUT_RING((x << 16) | y); |
507 | OUT_RING((x << 16) | y); | |
508 | OUT_RING((w << 16) | h); | |
1da177e4 LT |
509 | |
510 | ADVANCE_RING(); | |
511 | } | |
512 | ||
513 | /* Increment the frame counter. The client-side 3D driver must | |
514 | * throttle the framerate by waiting for this value before | |
515 | * performing the swapbuffer ioctl. | |
516 | */ | |
517 | dev_priv->sarea_priv->last_frame++; | |
518 | ||
b5e89ed5 | 519 | BEGIN_RING(2); |
1da177e4 | 520 | |
b5e89ed5 DA |
521 | OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); |
522 | OUT_RING(dev_priv->sarea_priv->last_frame); | |
1da177e4 LT |
523 | |
524 | ADVANCE_RING(); | |
525 | } | |
526 | ||
eddca551 | 527 | static void r128_cce_dispatch_flip(struct drm_device * dev) |
1da177e4 LT |
528 | { |
529 | drm_r128_private_t *dev_priv = dev->dev_private; | |
530 | RING_LOCALS; | |
b5e89ed5 DA |
531 | DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n", |
532 | __FUNCTION__, | |
533 | dev_priv->current_page, dev_priv->sarea_priv->pfCurrentPage); | |
1da177e4 LT |
534 | |
535 | #if R128_PERFORMANCE_BOXES | |
536 | /* Do some trivial performance monitoring... | |
537 | */ | |
b5e89ed5 | 538 | r128_cce_performance_boxes(dev_priv); |
1da177e4 LT |
539 | #endif |
540 | ||
b5e89ed5 | 541 | BEGIN_RING(4); |
1da177e4 LT |
542 | |
543 | R128_WAIT_UNTIL_PAGE_FLIPPED(); | |
b5e89ed5 | 544 | OUT_RING(CCE_PACKET0(R128_CRTC_OFFSET, 0)); |
1da177e4 | 545 | |
b5e89ed5 DA |
546 | if (dev_priv->current_page == 0) { |
547 | OUT_RING(dev_priv->back_offset); | |
1da177e4 | 548 | } else { |
b5e89ed5 | 549 | OUT_RING(dev_priv->front_offset); |
1da177e4 LT |
550 | } |
551 | ||
552 | ADVANCE_RING(); | |
553 | ||
554 | /* Increment the frame counter. The client-side 3D driver must | |
555 | * throttle the framerate by waiting for this value before | |
556 | * performing the swapbuffer ioctl. | |
557 | */ | |
558 | dev_priv->sarea_priv->last_frame++; | |
559 | dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page = | |
b5e89ed5 | 560 | 1 - dev_priv->current_page; |
1da177e4 | 561 | |
b5e89ed5 | 562 | BEGIN_RING(2); |
1da177e4 | 563 | |
b5e89ed5 DA |
564 | OUT_RING(CCE_PACKET0(R128_LAST_FRAME_REG, 0)); |
565 | OUT_RING(dev_priv->sarea_priv->last_frame); | |
1da177e4 LT |
566 | |
567 | ADVANCE_RING(); | |
568 | } | |
569 | ||
056219e2 | 570 | static void r128_cce_dispatch_vertex(struct drm_device * dev, struct drm_buf * buf) |
1da177e4 LT |
571 | { |
572 | drm_r128_private_t *dev_priv = dev->dev_private; | |
573 | drm_r128_buf_priv_t *buf_priv = buf->dev_private; | |
574 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
575 | int format = sarea_priv->vc_format; | |
576 | int offset = buf->bus_address; | |
577 | int size = buf->used; | |
578 | int prim = buf_priv->prim; | |
579 | int i = 0; | |
580 | RING_LOCALS; | |
b5e89ed5 | 581 | DRM_DEBUG("buf=%d nbox=%d\n", buf->idx, sarea_priv->nbox); |
1da177e4 | 582 | |
b5e89ed5 DA |
583 | if (0) |
584 | r128_print_dirty("dispatch_vertex", sarea_priv->dirty); | |
1da177e4 | 585 | |
b5e89ed5 | 586 | if (buf->used) { |
1da177e4 LT |
587 | buf_priv->dispatched = 1; |
588 | ||
b5e89ed5 DA |
589 | if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { |
590 | r128_emit_state(dev_priv); | |
1da177e4 LT |
591 | } |
592 | ||
593 | do { | |
594 | /* Emit the next set of up to three cliprects */ | |
b5e89ed5 DA |
595 | if (i < sarea_priv->nbox) { |
596 | r128_emit_clip_rects(dev_priv, | |
597 | &sarea_priv->boxes[i], | |
598 | sarea_priv->nbox - i); | |
1da177e4 LT |
599 | } |
600 | ||
601 | /* Emit the vertex buffer rendering commands */ | |
b5e89ed5 | 602 | BEGIN_RING(5); |
1da177e4 | 603 | |
b5e89ed5 DA |
604 | OUT_RING(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, 3)); |
605 | OUT_RING(offset); | |
606 | OUT_RING(size); | |
607 | OUT_RING(format); | |
608 | OUT_RING(prim | R128_CCE_VC_CNTL_PRIM_WALK_LIST | | |
609 | (size << R128_CCE_VC_CNTL_NUM_SHIFT)); | |
1da177e4 LT |
610 | |
611 | ADVANCE_RING(); | |
612 | ||
613 | i += 3; | |
b5e89ed5 | 614 | } while (i < sarea_priv->nbox); |
1da177e4 LT |
615 | } |
616 | ||
b5e89ed5 | 617 | if (buf_priv->discard) { |
1da177e4 LT |
618 | buf_priv->age = dev_priv->sarea_priv->last_dispatch; |
619 | ||
620 | /* Emit the vertex buffer age */ | |
b5e89ed5 | 621 | BEGIN_RING(2); |
1da177e4 | 622 | |
b5e89ed5 DA |
623 | OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); |
624 | OUT_RING(buf_priv->age); | |
1da177e4 LT |
625 | |
626 | ADVANCE_RING(); | |
627 | ||
628 | buf->pending = 1; | |
629 | buf->used = 0; | |
630 | /* FIXME: Check dispatched field */ | |
631 | buf_priv->dispatched = 0; | |
632 | } | |
633 | ||
634 | dev_priv->sarea_priv->last_dispatch++; | |
635 | ||
636 | sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; | |
637 | sarea_priv->nbox = 0; | |
638 | } | |
639 | ||
eddca551 | 640 | static void r128_cce_dispatch_indirect(struct drm_device * dev, |
056219e2 | 641 | struct drm_buf * buf, int start, int end) |
1da177e4 LT |
642 | { |
643 | drm_r128_private_t *dev_priv = dev->dev_private; | |
644 | drm_r128_buf_priv_t *buf_priv = buf->dev_private; | |
645 | RING_LOCALS; | |
b5e89ed5 | 646 | DRM_DEBUG("indirect: buf=%d s=0x%x e=0x%x\n", buf->idx, start, end); |
1da177e4 | 647 | |
b5e89ed5 | 648 | if (start != end) { |
1da177e4 LT |
649 | int offset = buf->bus_address + start; |
650 | int dwords = (end - start + 3) / sizeof(u32); | |
651 | ||
652 | /* Indirect buffer data must be an even number of | |
653 | * dwords, so if we've been given an odd number we must | |
654 | * pad the data with a Type-2 CCE packet. | |
655 | */ | |
b5e89ed5 | 656 | if (dwords & 1) { |
1da177e4 | 657 | u32 *data = (u32 *) |
b5e89ed5 DA |
658 | ((char *)dev->agp_buffer_map->handle |
659 | + buf->offset + start); | |
660 | data[dwords++] = cpu_to_le32(R128_CCE_PACKET2); | |
1da177e4 LT |
661 | } |
662 | ||
663 | buf_priv->dispatched = 1; | |
664 | ||
665 | /* Fire off the indirect buffer */ | |
b5e89ed5 | 666 | BEGIN_RING(3); |
1da177e4 | 667 | |
b5e89ed5 DA |
668 | OUT_RING(CCE_PACKET0(R128_PM4_IW_INDOFF, 1)); |
669 | OUT_RING(offset); | |
670 | OUT_RING(dwords); | |
1da177e4 LT |
671 | |
672 | ADVANCE_RING(); | |
673 | } | |
674 | ||
b5e89ed5 | 675 | if (buf_priv->discard) { |
1da177e4 LT |
676 | buf_priv->age = dev_priv->sarea_priv->last_dispatch; |
677 | ||
678 | /* Emit the indirect buffer age */ | |
b5e89ed5 | 679 | BEGIN_RING(2); |
1da177e4 | 680 | |
b5e89ed5 DA |
681 | OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); |
682 | OUT_RING(buf_priv->age); | |
1da177e4 LT |
683 | |
684 | ADVANCE_RING(); | |
685 | ||
686 | buf->pending = 1; | |
687 | buf->used = 0; | |
688 | /* FIXME: Check dispatched field */ | |
689 | buf_priv->dispatched = 0; | |
690 | } | |
691 | ||
692 | dev_priv->sarea_priv->last_dispatch++; | |
693 | } | |
694 | ||
eddca551 | 695 | static void r128_cce_dispatch_indices(struct drm_device * dev, |
056219e2 | 696 | struct drm_buf * buf, |
b5e89ed5 | 697 | int start, int end, int count) |
1da177e4 LT |
698 | { |
699 | drm_r128_private_t *dev_priv = dev->dev_private; | |
700 | drm_r128_buf_priv_t *buf_priv = buf->dev_private; | |
701 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
702 | int format = sarea_priv->vc_format; | |
703 | int offset = dev->agp_buffer_map->offset - dev_priv->cce_buffers_offset; | |
704 | int prim = buf_priv->prim; | |
705 | u32 *data; | |
706 | int dwords; | |
707 | int i = 0; | |
708 | RING_LOCALS; | |
b5e89ed5 | 709 | DRM_DEBUG("indices: s=%d e=%d c=%d\n", start, end, count); |
1da177e4 | 710 | |
b5e89ed5 DA |
711 | if (0) |
712 | r128_print_dirty("dispatch_indices", sarea_priv->dirty); | |
1da177e4 | 713 | |
b5e89ed5 | 714 | if (start != end) { |
1da177e4 LT |
715 | buf_priv->dispatched = 1; |
716 | ||
b5e89ed5 DA |
717 | if (sarea_priv->dirty & ~R128_UPLOAD_CLIPRECTS) { |
718 | r128_emit_state(dev_priv); | |
1da177e4 LT |
719 | } |
720 | ||
721 | dwords = (end - start + 3) / sizeof(u32); | |
722 | ||
b5e89ed5 DA |
723 | data = (u32 *) ((char *)dev->agp_buffer_map->handle |
724 | + buf->offset + start); | |
1da177e4 | 725 | |
b5e89ed5 DA |
726 | data[0] = cpu_to_le32(CCE_PACKET3(R128_3D_RNDR_GEN_INDX_PRIM, |
727 | dwords - 2)); | |
1da177e4 | 728 | |
b5e89ed5 DA |
729 | data[1] = cpu_to_le32(offset); |
730 | data[2] = cpu_to_le32(R128_MAX_VB_VERTS); | |
731 | data[3] = cpu_to_le32(format); | |
732 | data[4] = cpu_to_le32((prim | R128_CCE_VC_CNTL_PRIM_WALK_IND | | |
733 | (count << 16))); | |
1da177e4 | 734 | |
b5e89ed5 | 735 | if (count & 0x1) { |
1da177e4 | 736 | #ifdef __LITTLE_ENDIAN |
b5e89ed5 | 737 | data[dwords - 1] &= 0x0000ffff; |
1da177e4 | 738 | #else |
b5e89ed5 | 739 | data[dwords - 1] &= 0xffff0000; |
1da177e4 LT |
740 | #endif |
741 | } | |
742 | ||
743 | do { | |
744 | /* Emit the next set of up to three cliprects */ | |
b5e89ed5 DA |
745 | if (i < sarea_priv->nbox) { |
746 | r128_emit_clip_rects(dev_priv, | |
747 | &sarea_priv->boxes[i], | |
748 | sarea_priv->nbox - i); | |
1da177e4 LT |
749 | } |
750 | ||
b5e89ed5 | 751 | r128_cce_dispatch_indirect(dev, buf, start, end); |
1da177e4 LT |
752 | |
753 | i += 3; | |
b5e89ed5 | 754 | } while (i < sarea_priv->nbox); |
1da177e4 LT |
755 | } |
756 | ||
b5e89ed5 | 757 | if (buf_priv->discard) { |
1da177e4 LT |
758 | buf_priv->age = dev_priv->sarea_priv->last_dispatch; |
759 | ||
760 | /* Emit the vertex buffer age */ | |
b5e89ed5 | 761 | BEGIN_RING(2); |
1da177e4 | 762 | |
b5e89ed5 DA |
763 | OUT_RING(CCE_PACKET0(R128_LAST_DISPATCH_REG, 0)); |
764 | OUT_RING(buf_priv->age); | |
1da177e4 LT |
765 | |
766 | ADVANCE_RING(); | |
767 | ||
768 | buf->pending = 1; | |
769 | /* FIXME: Check dispatched field */ | |
770 | buf_priv->dispatched = 0; | |
771 | } | |
772 | ||
773 | dev_priv->sarea_priv->last_dispatch++; | |
774 | ||
775 | sarea_priv->dirty &= ~R128_UPLOAD_CLIPRECTS; | |
776 | sarea_priv->nbox = 0; | |
777 | } | |
778 | ||
b5e89ed5 | 779 | static int r128_cce_dispatch_blit(DRMFILE filp, |
eddca551 | 780 | struct drm_device * dev, drm_r128_blit_t * blit) |
1da177e4 LT |
781 | { |
782 | drm_r128_private_t *dev_priv = dev->dev_private; | |
cdd55a29 | 783 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 784 | struct drm_buf *buf; |
1da177e4 LT |
785 | drm_r128_buf_priv_t *buf_priv; |
786 | u32 *data; | |
787 | int dword_shift, dwords; | |
788 | RING_LOCALS; | |
b5e89ed5 | 789 | DRM_DEBUG("\n"); |
1da177e4 LT |
790 | |
791 | /* The compiler won't optimize away a division by a variable, | |
792 | * even if the only legal values are powers of two. Thus, we'll | |
793 | * use a shift instead. | |
794 | */ | |
b5e89ed5 | 795 | switch (blit->format) { |
1da177e4 LT |
796 | case R128_DATATYPE_ARGB8888: |
797 | dword_shift = 0; | |
798 | break; | |
799 | case R128_DATATYPE_ARGB1555: | |
800 | case R128_DATATYPE_RGB565: | |
801 | case R128_DATATYPE_ARGB4444: | |
802 | case R128_DATATYPE_YVYU422: | |
803 | case R128_DATATYPE_VYUY422: | |
804 | dword_shift = 1; | |
805 | break; | |
806 | case R128_DATATYPE_CI8: | |
807 | case R128_DATATYPE_RGB8: | |
808 | dword_shift = 2; | |
809 | break; | |
810 | default: | |
b5e89ed5 | 811 | DRM_ERROR("invalid blit format %d\n", blit->format); |
20caafa6 | 812 | return -EINVAL; |
1da177e4 LT |
813 | } |
814 | ||
815 | /* Flush the pixel cache, and mark the contents as Read Invalid. | |
816 | * This ensures no pixel data gets mixed up with the texture | |
817 | * data from the host data blit, otherwise part of the texture | |
818 | * image may be corrupted. | |
819 | */ | |
b5e89ed5 | 820 | BEGIN_RING(2); |
1da177e4 | 821 | |
b5e89ed5 DA |
822 | OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); |
823 | OUT_RING(R128_PC_RI_GUI | R128_PC_FLUSH_GUI); | |
1da177e4 LT |
824 | |
825 | ADVANCE_RING(); | |
826 | ||
827 | /* Dispatch the indirect buffer. | |
828 | */ | |
829 | buf = dma->buflist[blit->idx]; | |
830 | buf_priv = buf->dev_private; | |
831 | ||
b5e89ed5 DA |
832 | if (buf->filp != filp) { |
833 | DRM_ERROR("process %d using buffer owned by %p\n", | |
834 | DRM_CURRENTPID, buf->filp); | |
20caafa6 | 835 | return -EINVAL; |
1da177e4 | 836 | } |
b5e89ed5 DA |
837 | if (buf->pending) { |
838 | DRM_ERROR("sending pending buffer %d\n", blit->idx); | |
20caafa6 | 839 | return -EINVAL; |
1da177e4 LT |
840 | } |
841 | ||
842 | buf_priv->discard = 1; | |
843 | ||
844 | dwords = (blit->width * blit->height) >> dword_shift; | |
845 | ||
b5e89ed5 DA |
846 | data = (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); |
847 | ||
848 | data[0] = cpu_to_le32(CCE_PACKET3(R128_CNTL_HOSTDATA_BLT, dwords + 6)); | |
849 | data[1] = cpu_to_le32((R128_GMC_DST_PITCH_OFFSET_CNTL | | |
850 | R128_GMC_BRUSH_NONE | | |
851 | (blit->format << 8) | | |
852 | R128_GMC_SRC_DATATYPE_COLOR | | |
853 | R128_ROP3_S | | |
854 | R128_DP_SRC_SOURCE_HOST_DATA | | |
855 | R128_GMC_CLR_CMP_CNTL_DIS | | |
856 | R128_GMC_AUX_CLIP_DIS | R128_GMC_WR_MSK_DIS)); | |
857 | ||
858 | data[2] = cpu_to_le32((blit->pitch << 21) | (blit->offset >> 5)); | |
859 | data[3] = cpu_to_le32(0xffffffff); | |
860 | data[4] = cpu_to_le32(0xffffffff); | |
861 | data[5] = cpu_to_le32((blit->y << 16) | blit->x); | |
862 | data[6] = cpu_to_le32((blit->height << 16) | blit->width); | |
863 | data[7] = cpu_to_le32(dwords); | |
1da177e4 LT |
864 | |
865 | buf->used = (dwords + 8) * sizeof(u32); | |
866 | ||
b5e89ed5 | 867 | r128_cce_dispatch_indirect(dev, buf, 0, buf->used); |
1da177e4 LT |
868 | |
869 | /* Flush the pixel cache after the blit completes. This ensures | |
870 | * the texture data is written out to memory before rendering | |
871 | * continues. | |
872 | */ | |
b5e89ed5 | 873 | BEGIN_RING(2); |
1da177e4 | 874 | |
b5e89ed5 DA |
875 | OUT_RING(CCE_PACKET0(R128_PC_GUI_CTLSTAT, 0)); |
876 | OUT_RING(R128_PC_FLUSH_GUI); | |
1da177e4 LT |
877 | |
878 | ADVANCE_RING(); | |
879 | ||
880 | return 0; | |
881 | } | |
882 | ||
1da177e4 LT |
883 | /* ================================================================ |
884 | * Tiled depth buffer management | |
885 | * | |
886 | * FIXME: These should all set the destination write mask for when we | |
887 | * have hardware stencil support. | |
888 | */ | |
889 | ||
eddca551 | 890 | static int r128_cce_dispatch_write_span(struct drm_device * dev, |
b5e89ed5 | 891 | drm_r128_depth_t * depth) |
1da177e4 LT |
892 | { |
893 | drm_r128_private_t *dev_priv = dev->dev_private; | |
894 | int count, x, y; | |
895 | u32 *buffer; | |
896 | u8 *mask; | |
897 | int i, buffer_size, mask_size; | |
898 | RING_LOCALS; | |
b5e89ed5 | 899 | DRM_DEBUG("\n"); |
1da177e4 LT |
900 | |
901 | count = depth->n; | |
902 | if (count > 4096 || count <= 0) | |
20caafa6 | 903 | return -EMSGSIZE; |
1da177e4 | 904 | |
b5e89ed5 | 905 | if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { |
20caafa6 | 906 | return -EFAULT; |
1da177e4 | 907 | } |
b5e89ed5 | 908 | if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { |
20caafa6 | 909 | return -EFAULT; |
1da177e4 LT |
910 | } |
911 | ||
912 | buffer_size = depth->n * sizeof(u32); | |
b5e89ed5 DA |
913 | buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); |
914 | if (buffer == NULL) | |
20caafa6 | 915 | return -ENOMEM; |
b5e89ed5 DA |
916 | if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { |
917 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); | |
20caafa6 | 918 | return -EFAULT; |
1da177e4 LT |
919 | } |
920 | ||
921 | mask_size = depth->n * sizeof(u8); | |
b5e89ed5 DA |
922 | if (depth->mask) { |
923 | mask = drm_alloc(mask_size, DRM_MEM_BUFS); | |
924 | if (mask == NULL) { | |
925 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); | |
20caafa6 | 926 | return -ENOMEM; |
1da177e4 | 927 | } |
b5e89ed5 DA |
928 | if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { |
929 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); | |
930 | drm_free(mask, mask_size, DRM_MEM_BUFS); | |
20caafa6 | 931 | return -EFAULT; |
1da177e4 LT |
932 | } |
933 | ||
b5e89ed5 DA |
934 | for (i = 0; i < count; i++, x++) { |
935 | if (mask[i]) { | |
936 | BEGIN_RING(6); | |
1da177e4 | 937 | |
b5e89ed5 DA |
938 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
939 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
940 | R128_GMC_BRUSH_SOLID_COLOR | | |
941 | (dev_priv->depth_fmt << 8) | | |
942 | R128_GMC_SRC_DATATYPE_COLOR | | |
943 | R128_ROP3_P | | |
944 | R128_GMC_CLR_CMP_CNTL_DIS | | |
945 | R128_GMC_WR_MSK_DIS); | |
1da177e4 | 946 | |
b5e89ed5 DA |
947 | OUT_RING(dev_priv->depth_pitch_offset_c); |
948 | OUT_RING(buffer[i]); | |
1da177e4 | 949 | |
b5e89ed5 DA |
950 | OUT_RING((x << 16) | y); |
951 | OUT_RING((1 << 16) | 1); | |
1da177e4 LT |
952 | |
953 | ADVANCE_RING(); | |
954 | } | |
955 | } | |
956 | ||
b5e89ed5 | 957 | drm_free(mask, mask_size, DRM_MEM_BUFS); |
1da177e4 | 958 | } else { |
b5e89ed5 DA |
959 | for (i = 0; i < count; i++, x++) { |
960 | BEGIN_RING(6); | |
1da177e4 | 961 | |
b5e89ed5 DA |
962 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
963 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
964 | R128_GMC_BRUSH_SOLID_COLOR | | |
965 | (dev_priv->depth_fmt << 8) | | |
966 | R128_GMC_SRC_DATATYPE_COLOR | | |
967 | R128_ROP3_P | | |
968 | R128_GMC_CLR_CMP_CNTL_DIS | | |
969 | R128_GMC_WR_MSK_DIS); | |
1da177e4 | 970 | |
b5e89ed5 DA |
971 | OUT_RING(dev_priv->depth_pitch_offset_c); |
972 | OUT_RING(buffer[i]); | |
1da177e4 | 973 | |
b5e89ed5 DA |
974 | OUT_RING((x << 16) | y); |
975 | OUT_RING((1 << 16) | 1); | |
1da177e4 LT |
976 | |
977 | ADVANCE_RING(); | |
978 | } | |
979 | } | |
980 | ||
b5e89ed5 | 981 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); |
1da177e4 LT |
982 | |
983 | return 0; | |
984 | } | |
985 | ||
eddca551 | 986 | static int r128_cce_dispatch_write_pixels(struct drm_device * dev, |
b5e89ed5 | 987 | drm_r128_depth_t * depth) |
1da177e4 LT |
988 | { |
989 | drm_r128_private_t *dev_priv = dev->dev_private; | |
990 | int count, *x, *y; | |
991 | u32 *buffer; | |
992 | u8 *mask; | |
993 | int i, xbuf_size, ybuf_size, buffer_size, mask_size; | |
994 | RING_LOCALS; | |
b5e89ed5 | 995 | DRM_DEBUG("\n"); |
1da177e4 LT |
996 | |
997 | count = depth->n; | |
998 | if (count > 4096 || count <= 0) | |
20caafa6 | 999 | return -EMSGSIZE; |
1da177e4 LT |
1000 | |
1001 | xbuf_size = count * sizeof(*x); | |
1002 | ybuf_size = count * sizeof(*y); | |
b5e89ed5 DA |
1003 | x = drm_alloc(xbuf_size, DRM_MEM_BUFS); |
1004 | if (x == NULL) { | |
20caafa6 | 1005 | return -ENOMEM; |
1da177e4 | 1006 | } |
b5e89ed5 DA |
1007 | y = drm_alloc(ybuf_size, DRM_MEM_BUFS); |
1008 | if (y == NULL) { | |
1009 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
20caafa6 | 1010 | return -ENOMEM; |
1da177e4 | 1011 | } |
b5e89ed5 DA |
1012 | if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { |
1013 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1014 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
20caafa6 | 1015 | return -EFAULT; |
1da177e4 | 1016 | } |
b5e89ed5 DA |
1017 | if (DRM_COPY_FROM_USER(y, depth->y, xbuf_size)) { |
1018 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1019 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
20caafa6 | 1020 | return -EFAULT; |
1da177e4 LT |
1021 | } |
1022 | ||
1023 | buffer_size = depth->n * sizeof(u32); | |
b5e89ed5 DA |
1024 | buffer = drm_alloc(buffer_size, DRM_MEM_BUFS); |
1025 | if (buffer == NULL) { | |
1026 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1027 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
20caafa6 | 1028 | return -ENOMEM; |
1da177e4 | 1029 | } |
b5e89ed5 DA |
1030 | if (DRM_COPY_FROM_USER(buffer, depth->buffer, buffer_size)) { |
1031 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1032 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
1033 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); | |
20caafa6 | 1034 | return -EFAULT; |
1da177e4 LT |
1035 | } |
1036 | ||
b5e89ed5 | 1037 | if (depth->mask) { |
1da177e4 | 1038 | mask_size = depth->n * sizeof(u8); |
b5e89ed5 DA |
1039 | mask = drm_alloc(mask_size, DRM_MEM_BUFS); |
1040 | if (mask == NULL) { | |
1041 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1042 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
1043 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); | |
20caafa6 | 1044 | return -ENOMEM; |
1da177e4 | 1045 | } |
b5e89ed5 DA |
1046 | if (DRM_COPY_FROM_USER(mask, depth->mask, mask_size)) { |
1047 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1048 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
1049 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); | |
1050 | drm_free(mask, mask_size, DRM_MEM_BUFS); | |
20caafa6 | 1051 | return -EFAULT; |
1da177e4 LT |
1052 | } |
1053 | ||
b5e89ed5 DA |
1054 | for (i = 0; i < count; i++) { |
1055 | if (mask[i]) { | |
1056 | BEGIN_RING(6); | |
1da177e4 | 1057 | |
b5e89ed5 DA |
1058 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
1059 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
1060 | R128_GMC_BRUSH_SOLID_COLOR | | |
1061 | (dev_priv->depth_fmt << 8) | | |
1062 | R128_GMC_SRC_DATATYPE_COLOR | | |
1063 | R128_ROP3_P | | |
1064 | R128_GMC_CLR_CMP_CNTL_DIS | | |
1065 | R128_GMC_WR_MSK_DIS); | |
1da177e4 | 1066 | |
b5e89ed5 DA |
1067 | OUT_RING(dev_priv->depth_pitch_offset_c); |
1068 | OUT_RING(buffer[i]); | |
1da177e4 | 1069 | |
b5e89ed5 DA |
1070 | OUT_RING((x[i] << 16) | y[i]); |
1071 | OUT_RING((1 << 16) | 1); | |
1da177e4 LT |
1072 | |
1073 | ADVANCE_RING(); | |
1074 | } | |
1075 | } | |
1076 | ||
b5e89ed5 | 1077 | drm_free(mask, mask_size, DRM_MEM_BUFS); |
1da177e4 | 1078 | } else { |
b5e89ed5 DA |
1079 | for (i = 0; i < count; i++) { |
1080 | BEGIN_RING(6); | |
1da177e4 | 1081 | |
b5e89ed5 DA |
1082 | OUT_RING(CCE_PACKET3(R128_CNTL_PAINT_MULTI, 4)); |
1083 | OUT_RING(R128_GMC_DST_PITCH_OFFSET_CNTL | | |
1084 | R128_GMC_BRUSH_SOLID_COLOR | | |
1085 | (dev_priv->depth_fmt << 8) | | |
1086 | R128_GMC_SRC_DATATYPE_COLOR | | |
1087 | R128_ROP3_P | | |
1088 | R128_GMC_CLR_CMP_CNTL_DIS | | |
1089 | R128_GMC_WR_MSK_DIS); | |
1da177e4 | 1090 | |
b5e89ed5 DA |
1091 | OUT_RING(dev_priv->depth_pitch_offset_c); |
1092 | OUT_RING(buffer[i]); | |
1da177e4 | 1093 | |
b5e89ed5 DA |
1094 | OUT_RING((x[i] << 16) | y[i]); |
1095 | OUT_RING((1 << 16) | 1); | |
1da177e4 LT |
1096 | |
1097 | ADVANCE_RING(); | |
1098 | } | |
1099 | } | |
1100 | ||
b5e89ed5 DA |
1101 | drm_free(x, xbuf_size, DRM_MEM_BUFS); |
1102 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
1103 | drm_free(buffer, buffer_size, DRM_MEM_BUFS); | |
1da177e4 LT |
1104 | |
1105 | return 0; | |
1106 | } | |
1107 | ||
eddca551 | 1108 | static int r128_cce_dispatch_read_span(struct drm_device * dev, |
b5e89ed5 | 1109 | drm_r128_depth_t * depth) |
1da177e4 LT |
1110 | { |
1111 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1112 | int count, x, y; | |
1113 | RING_LOCALS; | |
b5e89ed5 | 1114 | DRM_DEBUG("\n"); |
1da177e4 LT |
1115 | |
1116 | count = depth->n; | |
1117 | if (count > 4096 || count <= 0) | |
20caafa6 | 1118 | return -EMSGSIZE; |
1da177e4 | 1119 | |
b5e89ed5 | 1120 | if (DRM_COPY_FROM_USER(&x, depth->x, sizeof(x))) { |
20caafa6 | 1121 | return -EFAULT; |
1da177e4 | 1122 | } |
b5e89ed5 | 1123 | if (DRM_COPY_FROM_USER(&y, depth->y, sizeof(y))) { |
20caafa6 | 1124 | return -EFAULT; |
1da177e4 LT |
1125 | } |
1126 | ||
b5e89ed5 | 1127 | BEGIN_RING(7); |
1da177e4 | 1128 | |
b5e89ed5 DA |
1129 | OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); |
1130 | OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | | |
1131 | R128_GMC_DST_PITCH_OFFSET_CNTL | | |
1132 | R128_GMC_BRUSH_NONE | | |
1133 | (dev_priv->depth_fmt << 8) | | |
1134 | R128_GMC_SRC_DATATYPE_COLOR | | |
1135 | R128_ROP3_S | | |
1136 | R128_DP_SRC_SOURCE_MEMORY | | |
1137 | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); | |
1da177e4 | 1138 | |
b5e89ed5 DA |
1139 | OUT_RING(dev_priv->depth_pitch_offset_c); |
1140 | OUT_RING(dev_priv->span_pitch_offset_c); | |
1da177e4 | 1141 | |
b5e89ed5 DA |
1142 | OUT_RING((x << 16) | y); |
1143 | OUT_RING((0 << 16) | 0); | |
1144 | OUT_RING((count << 16) | 1); | |
1da177e4 LT |
1145 | |
1146 | ADVANCE_RING(); | |
1147 | ||
1148 | return 0; | |
1149 | } | |
1150 | ||
eddca551 | 1151 | static int r128_cce_dispatch_read_pixels(struct drm_device * dev, |
b5e89ed5 | 1152 | drm_r128_depth_t * depth) |
1da177e4 LT |
1153 | { |
1154 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1155 | int count, *x, *y; | |
1156 | int i, xbuf_size, ybuf_size; | |
1157 | RING_LOCALS; | |
b5e89ed5 | 1158 | DRM_DEBUG("%s\n", __FUNCTION__); |
1da177e4 LT |
1159 | |
1160 | count = depth->n; | |
1161 | if (count > 4096 || count <= 0) | |
20caafa6 | 1162 | return -EMSGSIZE; |
1da177e4 | 1163 | |
b5e89ed5 | 1164 | if (count > dev_priv->depth_pitch) { |
1da177e4 LT |
1165 | count = dev_priv->depth_pitch; |
1166 | } | |
1167 | ||
1168 | xbuf_size = count * sizeof(*x); | |
1169 | ybuf_size = count * sizeof(*y); | |
b5e89ed5 DA |
1170 | x = drm_alloc(xbuf_size, DRM_MEM_BUFS); |
1171 | if (x == NULL) { | |
20caafa6 | 1172 | return -ENOMEM; |
1da177e4 | 1173 | } |
b5e89ed5 DA |
1174 | y = drm_alloc(ybuf_size, DRM_MEM_BUFS); |
1175 | if (y == NULL) { | |
1176 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
20caafa6 | 1177 | return -ENOMEM; |
1da177e4 | 1178 | } |
b5e89ed5 DA |
1179 | if (DRM_COPY_FROM_USER(x, depth->x, xbuf_size)) { |
1180 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1181 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
20caafa6 | 1182 | return -EFAULT; |
1da177e4 | 1183 | } |
b5e89ed5 DA |
1184 | if (DRM_COPY_FROM_USER(y, depth->y, ybuf_size)) { |
1185 | drm_free(x, xbuf_size, DRM_MEM_BUFS); | |
1186 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
20caafa6 | 1187 | return -EFAULT; |
1da177e4 LT |
1188 | } |
1189 | ||
b5e89ed5 DA |
1190 | for (i = 0; i < count; i++) { |
1191 | BEGIN_RING(7); | |
1da177e4 | 1192 | |
b5e89ed5 DA |
1193 | OUT_RING(CCE_PACKET3(R128_CNTL_BITBLT_MULTI, 5)); |
1194 | OUT_RING(R128_GMC_SRC_PITCH_OFFSET_CNTL | | |
1195 | R128_GMC_DST_PITCH_OFFSET_CNTL | | |
1196 | R128_GMC_BRUSH_NONE | | |
1197 | (dev_priv->depth_fmt << 8) | | |
1198 | R128_GMC_SRC_DATATYPE_COLOR | | |
1199 | R128_ROP3_S | | |
1200 | R128_DP_SRC_SOURCE_MEMORY | | |
1201 | R128_GMC_CLR_CMP_CNTL_DIS | R128_GMC_WR_MSK_DIS); | |
1da177e4 | 1202 | |
b5e89ed5 DA |
1203 | OUT_RING(dev_priv->depth_pitch_offset_c); |
1204 | OUT_RING(dev_priv->span_pitch_offset_c); | |
1da177e4 | 1205 | |
b5e89ed5 DA |
1206 | OUT_RING((x[i] << 16) | y[i]); |
1207 | OUT_RING((i << 16) | 0); | |
1208 | OUT_RING((1 << 16) | 1); | |
1da177e4 LT |
1209 | |
1210 | ADVANCE_RING(); | |
1211 | } | |
1212 | ||
b5e89ed5 DA |
1213 | drm_free(x, xbuf_size, DRM_MEM_BUFS); |
1214 | drm_free(y, ybuf_size, DRM_MEM_BUFS); | |
1da177e4 LT |
1215 | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1da177e4 LT |
1219 | /* ================================================================ |
1220 | * Polygon stipple | |
1221 | */ | |
1222 | ||
eddca551 | 1223 | static void r128_cce_dispatch_stipple(struct drm_device * dev, u32 * stipple) |
1da177e4 LT |
1224 | { |
1225 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1226 | int i; | |
1227 | RING_LOCALS; | |
b5e89ed5 | 1228 | DRM_DEBUG("%s\n", __FUNCTION__); |
1da177e4 | 1229 | |
b5e89ed5 | 1230 | BEGIN_RING(33); |
1da177e4 | 1231 | |
b5e89ed5 DA |
1232 | OUT_RING(CCE_PACKET0(R128_BRUSH_DATA0, 31)); |
1233 | for (i = 0; i < 32; i++) { | |
1234 | OUT_RING(stipple[i]); | |
1da177e4 LT |
1235 | } |
1236 | ||
1237 | ADVANCE_RING(); | |
1238 | } | |
1239 | ||
1da177e4 LT |
1240 | /* ================================================================ |
1241 | * IOCTL functions | |
1242 | */ | |
1243 | ||
b5e89ed5 | 1244 | static int r128_cce_clear(DRM_IOCTL_ARGS) |
1da177e4 LT |
1245 | { |
1246 | DRM_DEVICE; | |
1247 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1248 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
1249 | drm_r128_clear_t clear; | |
b5e89ed5 | 1250 | DRM_DEBUG("\n"); |
1da177e4 | 1251 | |
b5e89ed5 | 1252 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1253 | |
b5e89ed5 DA |
1254 | DRM_COPY_FROM_USER_IOCTL(clear, (drm_r128_clear_t __user *) data, |
1255 | sizeof(clear)); | |
1da177e4 | 1256 | |
b5e89ed5 | 1257 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 1258 | |
b5e89ed5 | 1259 | if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) |
1da177e4 LT |
1260 | sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; |
1261 | ||
b5e89ed5 | 1262 | r128_cce_dispatch_clear(dev, &clear); |
1da177e4 LT |
1263 | COMMIT_RING(); |
1264 | ||
1265 | /* Make sure we restore the 3D state next time. | |
1266 | */ | |
1267 | dev_priv->sarea_priv->dirty |= R128_UPLOAD_CONTEXT | R128_UPLOAD_MASKS; | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
eddca551 | 1272 | static int r128_do_init_pageflip(struct drm_device * dev) |
1da177e4 LT |
1273 | { |
1274 | drm_r128_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1275 | DRM_DEBUG("\n"); |
1da177e4 | 1276 | |
b5e89ed5 DA |
1277 | dev_priv->crtc_offset = R128_READ(R128_CRTC_OFFSET); |
1278 | dev_priv->crtc_offset_cntl = R128_READ(R128_CRTC_OFFSET_CNTL); | |
1da177e4 | 1279 | |
b5e89ed5 DA |
1280 | R128_WRITE(R128_CRTC_OFFSET, dev_priv->front_offset); |
1281 | R128_WRITE(R128_CRTC_OFFSET_CNTL, | |
1282 | dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL); | |
1da177e4 LT |
1283 | |
1284 | dev_priv->page_flipping = 1; | |
1285 | dev_priv->current_page = 0; | |
1286 | dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page; | |
1287 | ||
1288 | return 0; | |
1289 | } | |
1290 | ||
eddca551 | 1291 | static int r128_do_cleanup_pageflip(struct drm_device * dev) |
1da177e4 LT |
1292 | { |
1293 | drm_r128_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1294 | DRM_DEBUG("\n"); |
1da177e4 | 1295 | |
b5e89ed5 DA |
1296 | R128_WRITE(R128_CRTC_OFFSET, dev_priv->crtc_offset); |
1297 | R128_WRITE(R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl); | |
1da177e4 LT |
1298 | |
1299 | if (dev_priv->current_page != 0) { | |
b5e89ed5 | 1300 | r128_cce_dispatch_flip(dev); |
1da177e4 LT |
1301 | COMMIT_RING(); |
1302 | } | |
1303 | ||
1304 | dev_priv->page_flipping = 0; | |
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | /* Swapping and flipping are different operations, need different ioctls. | |
b5e89ed5 | 1309 | * They can & should be intermixed to support multiple 3d windows. |
1da177e4 LT |
1310 | */ |
1311 | ||
b5e89ed5 | 1312 | static int r128_cce_flip(DRM_IOCTL_ARGS) |
1da177e4 LT |
1313 | { |
1314 | DRM_DEVICE; | |
1315 | drm_r128_private_t *dev_priv = dev->dev_private; | |
b5e89ed5 | 1316 | DRM_DEBUG("%s\n", __FUNCTION__); |
1da177e4 | 1317 | |
b5e89ed5 | 1318 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1319 | |
b5e89ed5 | 1320 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 1321 | |
b5e89ed5 DA |
1322 | if (!dev_priv->page_flipping) |
1323 | r128_do_init_pageflip(dev); | |
1da177e4 | 1324 | |
b5e89ed5 | 1325 | r128_cce_dispatch_flip(dev); |
1da177e4 LT |
1326 | |
1327 | COMMIT_RING(); | |
1328 | return 0; | |
1329 | } | |
1330 | ||
b5e89ed5 | 1331 | static int r128_cce_swap(DRM_IOCTL_ARGS) |
1da177e4 LT |
1332 | { |
1333 | DRM_DEVICE; | |
1334 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1335 | drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; | |
b5e89ed5 | 1336 | DRM_DEBUG("%s\n", __FUNCTION__); |
1da177e4 | 1337 | |
b5e89ed5 | 1338 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1339 | |
b5e89ed5 | 1340 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 1341 | |
b5e89ed5 | 1342 | if (sarea_priv->nbox > R128_NR_SAREA_CLIPRECTS) |
1da177e4 LT |
1343 | sarea_priv->nbox = R128_NR_SAREA_CLIPRECTS; |
1344 | ||
b5e89ed5 | 1345 | r128_cce_dispatch_swap(dev); |
1da177e4 LT |
1346 | dev_priv->sarea_priv->dirty |= (R128_UPLOAD_CONTEXT | |
1347 | R128_UPLOAD_MASKS); | |
1348 | ||
1349 | COMMIT_RING(); | |
1350 | return 0; | |
1351 | } | |
1352 | ||
b5e89ed5 | 1353 | static int r128_cce_vertex(DRM_IOCTL_ARGS) |
1da177e4 LT |
1354 | { |
1355 | DRM_DEVICE; | |
1356 | drm_r128_private_t *dev_priv = dev->dev_private; | |
cdd55a29 | 1357 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 1358 | struct drm_buf *buf; |
1da177e4 LT |
1359 | drm_r128_buf_priv_t *buf_priv; |
1360 | drm_r128_vertex_t vertex; | |
1361 | ||
b5e89ed5 | 1362 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1363 | |
b5e89ed5 DA |
1364 | if (!dev_priv) { |
1365 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
20caafa6 | 1366 | return -EINVAL; |
1da177e4 LT |
1367 | } |
1368 | ||
b5e89ed5 DA |
1369 | DRM_COPY_FROM_USER_IOCTL(vertex, (drm_r128_vertex_t __user *) data, |
1370 | sizeof(vertex)); | |
1da177e4 | 1371 | |
b5e89ed5 DA |
1372 | DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n", |
1373 | DRM_CURRENTPID, vertex.idx, vertex.count, vertex.discard); | |
1da177e4 | 1374 | |
b5e89ed5 DA |
1375 | if (vertex.idx < 0 || vertex.idx >= dma->buf_count) { |
1376 | DRM_ERROR("buffer index %d (of %d max)\n", | |
1377 | vertex.idx, dma->buf_count - 1); | |
20caafa6 | 1378 | return -EINVAL; |
1da177e4 | 1379 | } |
b5e89ed5 DA |
1380 | if (vertex.prim < 0 || |
1381 | vertex.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { | |
1382 | DRM_ERROR("buffer prim %d\n", vertex.prim); | |
20caafa6 | 1383 | return -EINVAL; |
1da177e4 LT |
1384 | } |
1385 | ||
b5e89ed5 DA |
1386 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1387 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 LT |
1388 | |
1389 | buf = dma->buflist[vertex.idx]; | |
1390 | buf_priv = buf->dev_private; | |
1391 | ||
b5e89ed5 DA |
1392 | if (buf->filp != filp) { |
1393 | DRM_ERROR("process %d using buffer owned by %p\n", | |
1394 | DRM_CURRENTPID, buf->filp); | |
20caafa6 | 1395 | return -EINVAL; |
1da177e4 | 1396 | } |
b5e89ed5 DA |
1397 | if (buf->pending) { |
1398 | DRM_ERROR("sending pending buffer %d\n", vertex.idx); | |
20caafa6 | 1399 | return -EINVAL; |
1da177e4 LT |
1400 | } |
1401 | ||
1402 | buf->used = vertex.count; | |
1403 | buf_priv->prim = vertex.prim; | |
1404 | buf_priv->discard = vertex.discard; | |
1405 | ||
b5e89ed5 | 1406 | r128_cce_dispatch_vertex(dev, buf); |
1da177e4 LT |
1407 | |
1408 | COMMIT_RING(); | |
1409 | return 0; | |
1410 | } | |
1411 | ||
b5e89ed5 | 1412 | static int r128_cce_indices(DRM_IOCTL_ARGS) |
1da177e4 LT |
1413 | { |
1414 | DRM_DEVICE; | |
1415 | drm_r128_private_t *dev_priv = dev->dev_private; | |
cdd55a29 | 1416 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 1417 | struct drm_buf *buf; |
1da177e4 LT |
1418 | drm_r128_buf_priv_t *buf_priv; |
1419 | drm_r128_indices_t elts; | |
1420 | int count; | |
1421 | ||
b5e89ed5 | 1422 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1423 | |
b5e89ed5 DA |
1424 | if (!dev_priv) { |
1425 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
20caafa6 | 1426 | return -EINVAL; |
1da177e4 LT |
1427 | } |
1428 | ||
b5e89ed5 DA |
1429 | DRM_COPY_FROM_USER_IOCTL(elts, (drm_r128_indices_t __user *) data, |
1430 | sizeof(elts)); | |
1da177e4 | 1431 | |
b5e89ed5 DA |
1432 | DRM_DEBUG("pid=%d buf=%d s=%d e=%d d=%d\n", DRM_CURRENTPID, |
1433 | elts.idx, elts.start, elts.end, elts.discard); | |
1da177e4 | 1434 | |
b5e89ed5 DA |
1435 | if (elts.idx < 0 || elts.idx >= dma->buf_count) { |
1436 | DRM_ERROR("buffer index %d (of %d max)\n", | |
1437 | elts.idx, dma->buf_count - 1); | |
20caafa6 | 1438 | return -EINVAL; |
1da177e4 | 1439 | } |
b5e89ed5 DA |
1440 | if (elts.prim < 0 || elts.prim > R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2) { |
1441 | DRM_ERROR("buffer prim %d\n", elts.prim); | |
20caafa6 | 1442 | return -EINVAL; |
1da177e4 LT |
1443 | } |
1444 | ||
b5e89ed5 DA |
1445 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1446 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 LT |
1447 | |
1448 | buf = dma->buflist[elts.idx]; | |
1449 | buf_priv = buf->dev_private; | |
1450 | ||
b5e89ed5 DA |
1451 | if (buf->filp != filp) { |
1452 | DRM_ERROR("process %d using buffer owned by %p\n", | |
1453 | DRM_CURRENTPID, buf->filp); | |
20caafa6 | 1454 | return -EINVAL; |
1da177e4 | 1455 | } |
b5e89ed5 DA |
1456 | if (buf->pending) { |
1457 | DRM_ERROR("sending pending buffer %d\n", elts.idx); | |
20caafa6 | 1458 | return -EINVAL; |
1da177e4 LT |
1459 | } |
1460 | ||
1461 | count = (elts.end - elts.start) / sizeof(u16); | |
1462 | elts.start -= R128_INDEX_PRIM_OFFSET; | |
1463 | ||
b5e89ed5 DA |
1464 | if (elts.start & 0x7) { |
1465 | DRM_ERROR("misaligned buffer 0x%x\n", elts.start); | |
20caafa6 | 1466 | return -EINVAL; |
1da177e4 | 1467 | } |
b5e89ed5 DA |
1468 | if (elts.start < buf->used) { |
1469 | DRM_ERROR("no header 0x%x - 0x%x\n", elts.start, buf->used); | |
20caafa6 | 1470 | return -EINVAL; |
1da177e4 LT |
1471 | } |
1472 | ||
1473 | buf->used = elts.end; | |
1474 | buf_priv->prim = elts.prim; | |
1475 | buf_priv->discard = elts.discard; | |
1476 | ||
b5e89ed5 | 1477 | r128_cce_dispatch_indices(dev, buf, elts.start, elts.end, count); |
1da177e4 LT |
1478 | |
1479 | COMMIT_RING(); | |
1480 | return 0; | |
1481 | } | |
1482 | ||
b5e89ed5 | 1483 | static int r128_cce_blit(DRM_IOCTL_ARGS) |
1da177e4 LT |
1484 | { |
1485 | DRM_DEVICE; | |
cdd55a29 | 1486 | struct drm_device_dma *dma = dev->dma; |
1da177e4 LT |
1487 | drm_r128_private_t *dev_priv = dev->dev_private; |
1488 | drm_r128_blit_t blit; | |
1489 | int ret; | |
1490 | ||
b5e89ed5 | 1491 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1492 | |
b5e89ed5 DA |
1493 | DRM_COPY_FROM_USER_IOCTL(blit, (drm_r128_blit_t __user *) data, |
1494 | sizeof(blit)); | |
1da177e4 | 1495 | |
b5e89ed5 | 1496 | DRM_DEBUG("pid=%d index=%d\n", DRM_CURRENTPID, blit.idx); |
1da177e4 | 1497 | |
b5e89ed5 DA |
1498 | if (blit.idx < 0 || blit.idx >= dma->buf_count) { |
1499 | DRM_ERROR("buffer index %d (of %d max)\n", | |
1500 | blit.idx, dma->buf_count - 1); | |
20caafa6 | 1501 | return -EINVAL; |
1da177e4 LT |
1502 | } |
1503 | ||
b5e89ed5 DA |
1504 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1505 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 | 1506 | |
b5e89ed5 | 1507 | ret = r128_cce_dispatch_blit(filp, dev, &blit); |
1da177e4 LT |
1508 | |
1509 | COMMIT_RING(); | |
1510 | return ret; | |
1511 | } | |
1512 | ||
b5e89ed5 | 1513 | static int r128_cce_depth(DRM_IOCTL_ARGS) |
1da177e4 LT |
1514 | { |
1515 | DRM_DEVICE; | |
1516 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1517 | drm_r128_depth_t depth; | |
1518 | int ret; | |
1519 | ||
b5e89ed5 | 1520 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1521 | |
b5e89ed5 DA |
1522 | DRM_COPY_FROM_USER_IOCTL(depth, (drm_r128_depth_t __user *) data, |
1523 | sizeof(depth)); | |
1da177e4 | 1524 | |
b5e89ed5 | 1525 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 1526 | |
20caafa6 | 1527 | ret = -EINVAL; |
b5e89ed5 | 1528 | switch (depth.func) { |
1da177e4 | 1529 | case R128_WRITE_SPAN: |
b5e89ed5 | 1530 | ret = r128_cce_dispatch_write_span(dev, &depth); |
41aac24f | 1531 | break; |
1da177e4 | 1532 | case R128_WRITE_PIXELS: |
b5e89ed5 | 1533 | ret = r128_cce_dispatch_write_pixels(dev, &depth); |
41aac24f | 1534 | break; |
1da177e4 | 1535 | case R128_READ_SPAN: |
b5e89ed5 | 1536 | ret = r128_cce_dispatch_read_span(dev, &depth); |
41aac24f | 1537 | break; |
1da177e4 | 1538 | case R128_READ_PIXELS: |
b5e89ed5 | 1539 | ret = r128_cce_dispatch_read_pixels(dev, &depth); |
41aac24f | 1540 | break; |
1da177e4 LT |
1541 | } |
1542 | ||
1543 | COMMIT_RING(); | |
1544 | return ret; | |
1545 | } | |
1546 | ||
b5e89ed5 | 1547 | static int r128_cce_stipple(DRM_IOCTL_ARGS) |
1da177e4 LT |
1548 | { |
1549 | DRM_DEVICE; | |
1550 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1551 | drm_r128_stipple_t stipple; | |
1552 | u32 mask[32]; | |
1553 | ||
b5e89ed5 | 1554 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1555 | |
b5e89ed5 DA |
1556 | DRM_COPY_FROM_USER_IOCTL(stipple, (drm_r128_stipple_t __user *) data, |
1557 | sizeof(stipple)); | |
1da177e4 | 1558 | |
b5e89ed5 | 1559 | if (DRM_COPY_FROM_USER(&mask, stipple.mask, 32 * sizeof(u32))) |
20caafa6 | 1560 | return -EFAULT; |
1da177e4 | 1561 | |
b5e89ed5 | 1562 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1da177e4 | 1563 | |
b5e89ed5 | 1564 | r128_cce_dispatch_stipple(dev, mask); |
1da177e4 LT |
1565 | |
1566 | COMMIT_RING(); | |
1567 | return 0; | |
1568 | } | |
1569 | ||
b5e89ed5 | 1570 | static int r128_cce_indirect(DRM_IOCTL_ARGS) |
1da177e4 LT |
1571 | { |
1572 | DRM_DEVICE; | |
1573 | drm_r128_private_t *dev_priv = dev->dev_private; | |
cdd55a29 | 1574 | struct drm_device_dma *dma = dev->dma; |
056219e2 | 1575 | struct drm_buf *buf; |
1da177e4 LT |
1576 | drm_r128_buf_priv_t *buf_priv; |
1577 | drm_r128_indirect_t indirect; | |
1578 | #if 0 | |
1579 | RING_LOCALS; | |
1580 | #endif | |
1581 | ||
b5e89ed5 | 1582 | LOCK_TEST_WITH_RETURN(dev, filp); |
1da177e4 | 1583 | |
b5e89ed5 DA |
1584 | if (!dev_priv) { |
1585 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
20caafa6 | 1586 | return -EINVAL; |
1da177e4 LT |
1587 | } |
1588 | ||
b5e89ed5 DA |
1589 | DRM_COPY_FROM_USER_IOCTL(indirect, (drm_r128_indirect_t __user *) data, |
1590 | sizeof(indirect)); | |
1da177e4 | 1591 | |
b5e89ed5 DA |
1592 | DRM_DEBUG("indirect: idx=%d s=%d e=%d d=%d\n", |
1593 | indirect.idx, indirect.start, indirect.end, indirect.discard); | |
1da177e4 | 1594 | |
b5e89ed5 DA |
1595 | if (indirect.idx < 0 || indirect.idx >= dma->buf_count) { |
1596 | DRM_ERROR("buffer index %d (of %d max)\n", | |
1597 | indirect.idx, dma->buf_count - 1); | |
20caafa6 | 1598 | return -EINVAL; |
1da177e4 LT |
1599 | } |
1600 | ||
1601 | buf = dma->buflist[indirect.idx]; | |
1602 | buf_priv = buf->dev_private; | |
1603 | ||
b5e89ed5 DA |
1604 | if (buf->filp != filp) { |
1605 | DRM_ERROR("process %d using buffer owned by %p\n", | |
1606 | DRM_CURRENTPID, buf->filp); | |
20caafa6 | 1607 | return -EINVAL; |
1da177e4 | 1608 | } |
b5e89ed5 DA |
1609 | if (buf->pending) { |
1610 | DRM_ERROR("sending pending buffer %d\n", indirect.idx); | |
20caafa6 | 1611 | return -EINVAL; |
1da177e4 LT |
1612 | } |
1613 | ||
b5e89ed5 DA |
1614 | if (indirect.start < buf->used) { |
1615 | DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n", | |
1616 | indirect.start, buf->used); | |
20caafa6 | 1617 | return -EINVAL; |
1da177e4 LT |
1618 | } |
1619 | ||
b5e89ed5 DA |
1620 | RING_SPACE_TEST_WITH_RETURN(dev_priv); |
1621 | VB_AGE_TEST_WITH_RETURN(dev_priv); | |
1da177e4 LT |
1622 | |
1623 | buf->used = indirect.end; | |
1624 | buf_priv->discard = indirect.discard; | |
1625 | ||
1626 | #if 0 | |
1627 | /* Wait for the 3D stream to idle before the indirect buffer | |
1628 | * containing 2D acceleration commands is processed. | |
1629 | */ | |
b5e89ed5 | 1630 | BEGIN_RING(2); |
1da177e4 LT |
1631 | RADEON_WAIT_UNTIL_3D_IDLE(); |
1632 | ADVANCE_RING(); | |
1633 | #endif | |
1634 | ||
1635 | /* Dispatch the indirect buffer full of commands from the | |
1636 | * X server. This is insecure and is thus only available to | |
1637 | * privileged clients. | |
1638 | */ | |
b5e89ed5 | 1639 | r128_cce_dispatch_indirect(dev, buf, indirect.start, indirect.end); |
1da177e4 LT |
1640 | |
1641 | COMMIT_RING(); | |
1642 | return 0; | |
1643 | } | |
1644 | ||
b5e89ed5 | 1645 | static int r128_getparam(DRM_IOCTL_ARGS) |
1da177e4 LT |
1646 | { |
1647 | DRM_DEVICE; | |
1648 | drm_r128_private_t *dev_priv = dev->dev_private; | |
1649 | drm_r128_getparam_t param; | |
1650 | int value; | |
1651 | ||
b5e89ed5 DA |
1652 | if (!dev_priv) { |
1653 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | |
20caafa6 | 1654 | return -EINVAL; |
1da177e4 LT |
1655 | } |
1656 | ||
b5e89ed5 DA |
1657 | DRM_COPY_FROM_USER_IOCTL(param, (drm_r128_getparam_t __user *) data, |
1658 | sizeof(param)); | |
1da177e4 | 1659 | |
b5e89ed5 | 1660 | DRM_DEBUG("pid=%d\n", DRM_CURRENTPID); |
1da177e4 | 1661 | |
b5e89ed5 | 1662 | switch (param.param) { |
1da177e4 LT |
1663 | case R128_PARAM_IRQ_NR: |
1664 | value = dev->irq; | |
1665 | break; | |
1666 | default: | |
20caafa6 | 1667 | return -EINVAL; |
1da177e4 LT |
1668 | } |
1669 | ||
b5e89ed5 DA |
1670 | if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) { |
1671 | DRM_ERROR("copy_to_user\n"); | |
20caafa6 | 1672 | return -EFAULT; |
1da177e4 | 1673 | } |
b5e89ed5 | 1674 | |
1da177e4 LT |
1675 | return 0; |
1676 | } | |
1677 | ||
eddca551 | 1678 | void r128_driver_preclose(struct drm_device * dev, DRMFILE filp) |
1da177e4 | 1679 | { |
b5e89ed5 | 1680 | if (dev->dev_private) { |
1da177e4 | 1681 | drm_r128_private_t *dev_priv = dev->dev_private; |
b5e89ed5 DA |
1682 | if (dev_priv->page_flipping) { |
1683 | r128_do_cleanup_pageflip(dev); | |
1da177e4 | 1684 | } |
b5e89ed5 | 1685 | } |
1da177e4 LT |
1686 | } |
1687 | ||
eddca551 | 1688 | void r128_driver_lastclose(struct drm_device * dev) |
1da177e4 | 1689 | { |
b5e89ed5 | 1690 | r128_do_cleanup_cce(dev); |
1da177e4 LT |
1691 | } |
1692 | ||
1693 | drm_ioctl_desc_t r128_ioctls[] = { | |
a7a2cc31 DA |
1694 | [DRM_IOCTL_NR(DRM_R128_INIT)] = {r128_cce_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, |
1695 | [DRM_IOCTL_NR(DRM_R128_CCE_START)] = {r128_cce_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | |
1696 | [DRM_IOCTL_NR(DRM_R128_CCE_STOP)] = {r128_cce_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | |
1697 | [DRM_IOCTL_NR(DRM_R128_CCE_RESET)] = {r128_cce_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | |
1698 | [DRM_IOCTL_NR(DRM_R128_CCE_IDLE)] = {r128_cce_idle, DRM_AUTH}, | |
1699 | [DRM_IOCTL_NR(DRM_R128_RESET)] = {r128_engine_reset, DRM_AUTH}, | |
1700 | [DRM_IOCTL_NR(DRM_R128_FULLSCREEN)] = {r128_fullscreen, DRM_AUTH}, | |
1701 | [DRM_IOCTL_NR(DRM_R128_SWAP)] = {r128_cce_swap, DRM_AUTH}, | |
1702 | [DRM_IOCTL_NR(DRM_R128_FLIP)] = {r128_cce_flip, DRM_AUTH}, | |
1703 | [DRM_IOCTL_NR(DRM_R128_CLEAR)] = {r128_cce_clear, DRM_AUTH}, | |
1704 | [DRM_IOCTL_NR(DRM_R128_VERTEX)] = {r128_cce_vertex, DRM_AUTH}, | |
1705 | [DRM_IOCTL_NR(DRM_R128_INDICES)] = {r128_cce_indices, DRM_AUTH}, | |
1706 | [DRM_IOCTL_NR(DRM_R128_BLIT)] = {r128_cce_blit, DRM_AUTH}, | |
1707 | [DRM_IOCTL_NR(DRM_R128_DEPTH)] = {r128_cce_depth, DRM_AUTH}, | |
1708 | [DRM_IOCTL_NR(DRM_R128_STIPPLE)] = {r128_cce_stipple, DRM_AUTH}, | |
1709 | [DRM_IOCTL_NR(DRM_R128_INDIRECT)] = {r128_cce_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | |
1710 | [DRM_IOCTL_NR(DRM_R128_GETPARAM)] = {r128_getparam, DRM_AUTH}, | |
1da177e4 LT |
1711 | }; |
1712 | ||
1713 | int r128_max_ioctl = DRM_ARRAY_SIZE(r128_ioctls); |