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drm: Core vsync: Don't clobber target sequence number when scheduling signal.
[net-next-2.6.git] / drivers / char / drm / i915_dma.c
CommitLineData
1da177e4
LT		 1/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4
LT		 28
29#include "drmP.h"
30#include "drm.h"
31#include "i915_drm.h"
32#include "i915_drv.h"
33
2f02cc3f
EA		 34#define IS_I965G(dev) (dev->pci_device == 0x2972 || \
35 dev->pci_device == 0x2982 || \
36 dev->pci_device == 0x2992 || \
37 dev->pci_device == 0x29A2)
c29b669c 38
1da177e4
LT		 39/* Really want an OS-independent resettable timer. Would like to have
40 * this loop run for (eg) 3 sec, but have the timer reset every time
41 * the head pointer changes, so that EBUSY only happens if the ring
42 * actually stalls for (eg) 3 seconds.
43 */
44int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
45{
46 drm_i915_private_t *dev_priv = dev->dev_private;
47 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
48 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
49 int i;
50
51 for (i = 0; i < 10000; i++) {
52 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
53 ring->space = ring->head - (ring->tail + 8);
54 if (ring->space < 0)
55 ring->space += ring->Size;
56 if (ring->space >= n)
57 return 0;
58
59 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
60
61 if (ring->head != last_head)
62 i = 0;
63
64 last_head = ring->head;
65 }
66
67 return DRM_ERR(EBUSY);
68}
69
70void i915_kernel_lost_context(drm_device_t * dev)
71{
72 drm_i915_private_t *dev_priv = dev->dev_private;
73 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
74
75 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
76 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
77 ring->space = ring->head - (ring->tail + 8);
78 if (ring->space < 0)
79 ring->space += ring->Size;
80
81 if (ring->head == ring->tail)
82 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
83}
84
c94f7029 85static int i915_dma_cleanup(drm_device_t * dev)
1da177e4
LT		 86{
87 /* Make sure interrupts are disabled here because the uninstall ioctl
88 * may not have been called from userspace and after dev_private
89 * is freed, it's too late.
90 */
91 if (dev->irq)
b5e89ed5 92 drm_irq_uninstall(dev);
1da177e4
LT		 93
94 if (dev->dev_private) {
95 drm_i915_private_t *dev_priv =
96 (drm_i915_private_t *) dev->dev_private;
97
98 if (dev_priv->ring.virtual_start) {
b5e89ed5 99 drm_core_ioremapfree(&dev_priv->ring.map, dev);
1da177e4
LT		 100 }
101
9c8da5eb
DA		 102 if (dev_priv->status_page_dmah) {
103 drm_pci_free(dev, dev_priv->status_page_dmah);
1da177e4
LT		 104 /* Need to rewrite hardware status page */
105 I915_WRITE(0x02080, 0x1ffff000);
106 }
107
b5e89ed5
DA		 108 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
109 DRM_MEM_DRIVER);
1da177e4
LT		 110
111 dev->dev_private = NULL;
112 }
113
114 return 0;
115}
116
117static int i915_initialize(drm_device_t * dev,
118 drm_i915_private_t * dev_priv,
119 drm_i915_init_t * init)
120{
121 memset(dev_priv, 0, sizeof(drm_i915_private_t));
122
123 DRM_GETSAREA();
124 if (!dev_priv->sarea) {
125 DRM_ERROR("can not find sarea!\n");
126 dev->dev_private = (void *)dev_priv;
127 i915_dma_cleanup(dev);
128 return DRM_ERR(EINVAL);
129 }
130
131 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
132 if (!dev_priv->mmio_map) {
133 dev->dev_private = (void *)dev_priv;
134 i915_dma_cleanup(dev);
135 DRM_ERROR("can not find mmio map!\n");
136 return DRM_ERR(EINVAL);
137 }
138
139 dev_priv->sarea_priv = (drm_i915_sarea_t *)
140 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
141
142 dev_priv->ring.Start = init->ring_start;
143 dev_priv->ring.End = init->ring_end;
144 dev_priv->ring.Size = init->ring_size;
145 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
146
147 dev_priv->ring.map.offset = init->ring_start;
148 dev_priv->ring.map.size = init->ring_size;
149 dev_priv->ring.map.type = 0;
150 dev_priv->ring.map.flags = 0;
151 dev_priv->ring.map.mtrr = 0;
152
b5e89ed5 153 drm_core_ioremap(&dev_priv->ring.map, dev);
1da177e4
LT		 154
155 if (dev_priv->ring.map.handle == NULL) {
156 dev->dev_private = (void *)dev_priv;
157 i915_dma_cleanup(dev);
158 DRM_ERROR("can not ioremap virtual address for"
159 " ring buffer\n");
160 return DRM_ERR(ENOMEM);
161 }
162
163 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
164
165 dev_priv->back_offset = init->back_offset;
166 dev_priv->front_offset = init->front_offset;
167 dev_priv->current_page = 0;
168 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
169
170 /* We are using separate values as placeholders for mechanisms for
171 * private backbuffer/depthbuffer usage.
172 */
173 dev_priv->use_mi_batchbuffer_start = 0;
174
175 /* Allow hardware batchbuffers unless told otherwise.
176 */
177 dev_priv->allow_batchbuffer = 1;
178
179 /* Program Hardware Status Page */
9c8da5eb
DA		 180 dev_priv->status_page_dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE,
181 0xffffffff);
1da177e4 182
9c8da5eb 183 if (!dev_priv->status_page_dmah) {
1da177e4
LT		 184 dev->dev_private = (void *)dev_priv;
185 i915_dma_cleanup(dev);
186 DRM_ERROR("Can not allocate hardware status page\n");
187 return DRM_ERR(ENOMEM);
188 }
9c8da5eb
DA		 189 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
190 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
191
1da177e4
LT		 192 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
193 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
194
195 I915_WRITE(0x02080, dev_priv->dma_status_page);
196 DRM_DEBUG("Enabled hardware status page\n");
197
198 dev->dev_private = (void *)dev_priv;
199
200 return 0;
201}
202
0d6aa60b 203static int i915_dma_resume(drm_device_t * dev)
1da177e4
LT		 204{
205 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
206
207 DRM_DEBUG("%s\n", __FUNCTION__);
208
209 if (!dev_priv->sarea) {
210 DRM_ERROR("can not find sarea!\n");
211 return DRM_ERR(EINVAL);
212 }
213
214 if (!dev_priv->mmio_map) {
215 DRM_ERROR("can not find mmio map!\n");
216 return DRM_ERR(EINVAL);
217 }
218
219 if (dev_priv->ring.map.handle == NULL) {
220 DRM_ERROR("can not ioremap virtual address for"
221 " ring buffer\n");
222 return DRM_ERR(ENOMEM);
223 }
224
225 /* Program Hardware Status Page */
226 if (!dev_priv->hw_status_page) {
227 DRM_ERROR("Can not find hardware status page\n");
228 return DRM_ERR(EINVAL);
229 }
230 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
231
232 I915_WRITE(0x02080, dev_priv->dma_status_page);
233 DRM_DEBUG("Enabled hardware status page\n");
234
235 return 0;
236}
237
c94f7029 238static int i915_dma_init(DRM_IOCTL_ARGS)
1da177e4
LT		 239{
240 DRM_DEVICE;
241 drm_i915_private_t *dev_priv;
242 drm_i915_init_t init;
243 int retcode = 0;
244
245 DRM_COPY_FROM_USER_IOCTL(init, (drm_i915_init_t __user *) data,
246 sizeof(init));
247
248 switch (init.func) {
249 case I915_INIT_DMA:
b5e89ed5
DA		 250 dev_priv = drm_alloc(sizeof(drm_i915_private_t),
251 DRM_MEM_DRIVER);
1da177e4
LT		 252 if (dev_priv == NULL)
253 return DRM_ERR(ENOMEM);
254 retcode = i915_initialize(dev, dev_priv, &init);
255 break;
256 case I915_CLEANUP_DMA:
257 retcode = i915_dma_cleanup(dev);
258 break;
259 case I915_RESUME_DMA:
0d6aa60b 260 retcode = i915_dma_resume(dev);
1da177e4
LT		 261 break;
262 default:
46acbf13 263 retcode = DRM_ERR(EINVAL);
1da177e4
LT		 264 break;
265 }
266
267 return retcode;
268}
269
270/* Implement basically the same security restrictions as hardware does
271 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
272 *
273 * Most of the calculations below involve calculating the size of a
274 * particular instruction. It's important to get the size right as
275 * that tells us where the next instruction to check is. Any illegal
276 * instruction detected will be given a size of zero, which is a
277 * signal to abort the rest of the buffer.
278 */
279static int do_validate_cmd(int cmd)
280{
281 switch (((cmd >> 29) & 0x7)) {
282 case 0x0:
283 switch ((cmd >> 23) & 0x3f) {
284 case 0x0:
285 return 1; /* MI_NOOP */
286 case 0x4:
287 return 1; /* MI_FLUSH */
288 default:
289 return 0; /* disallow everything else */
290 }
291 break;
292 case 0x1:
293 return 0; /* reserved */
294 case 0x2:
295 return (cmd & 0xff) + 2; /* 2d commands */
296 case 0x3:
297 if (((cmd >> 24) & 0x1f) <= 0x18)
298 return 1;
299
300 switch ((cmd >> 24) & 0x1f) {
301 case 0x1c:
302 return 1;
303 case 0x1d:
b5e89ed5 304 switch ((cmd >> 16) & 0xff) {
1da177e4
LT		 305 case 0x3:
306 return (cmd & 0x1f) + 2;
307 case 0x4:
308 return (cmd & 0xf) + 2;
309 default:
310 return (cmd & 0xffff) + 2;
311 }
312 case 0x1e:
313 if (cmd & (1 << 23))
314 return (cmd & 0xffff) + 1;
315 else
316 return 1;
317 case 0x1f:
318 if ((cmd & (1 << 23)) == 0) /* inline vertices */
319 return (cmd & 0x1ffff) + 2;
320 else if (cmd & (1 << 17)) /* indirect random */
321 if ((cmd & 0xffff) == 0)
322 return 0; /* unknown length, too hard */
323 else
324 return (((cmd & 0xffff) + 1) / 2) + 1;
325 else
326 return 2; /* indirect sequential */
327 default:
328 return 0;
329 }
330 default:
331 return 0;
332 }
333
334 return 0;
335}
336
337static int validate_cmd(int cmd)
338{
339 int ret = do_validate_cmd(cmd);
340
341/* printk("validate_cmd( %x ): %d\n", cmd, ret); */
342
343 return ret;
344}
345
346static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
347{
348 drm_i915_private_t *dev_priv = dev->dev_private;
349 int i;
350 RING_LOCALS;
351
de227f5f
DA		 352 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
353 return DRM_ERR(EINVAL);
354
c29b669c 355 BEGIN_LP_RING((dwords+1)&~1);
de227f5f 356
1da177e4
LT		 357 for (i = 0; i < dwords;) {
358 int cmd, sz;
359
360 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
361 return DRM_ERR(EINVAL);
362
1da177e4
LT		 363 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
364 return DRM_ERR(EINVAL);
365
1da177e4
LT		 366 OUT_RING(cmd);
367
368 while (++i, --sz) {
369 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
370 sizeof(cmd))) {
371 return DRM_ERR(EINVAL);
372 }
373 OUT_RING(cmd);
374 }
1da177e4
LT		 375 }
376
de227f5f
DA		 377 if (dwords & 1)
378 OUT_RING(0);
379
380 ADVANCE_LP_RING();
381
1da177e4
LT		 382 return 0;
383}
384
385static int i915_emit_box(drm_device_t * dev,
386 drm_clip_rect_t __user * boxes,
387 int i, int DR1, int DR4)
388{
389 drm_i915_private_t *dev_priv = dev->dev_private;
390 drm_clip_rect_t box;
391 RING_LOCALS;
392
393 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
46acbf13 394 return DRM_ERR(EFAULT);
1da177e4
LT		 395 }
396
397 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
398 DRM_ERROR("Bad box %d,%d..%d,%d\n",
399 box.x1, box.y1, box.x2, box.y2);
400 return DRM_ERR(EINVAL);
401 }
402
c29b669c
AH		 403 if (IS_I965G(dev)) {
404 BEGIN_LP_RING(4);
405 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
406 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
78eca43d 407 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
c29b669c
AH		 408 OUT_RING(DR4);
409 ADVANCE_LP_RING();
410 } else {
411 BEGIN_LP_RING(6);
412 OUT_RING(GFX_OP_DRAWRECT_INFO);
413 OUT_RING(DR1);
414 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
415 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
416 OUT_RING(DR4);
417 OUT_RING(0);
418 ADVANCE_LP_RING();
419 }
1da177e4
LT		 420
421 return 0;
422}
423
c29b669c
AH		 424/* XXX: Emitting the counter should really be moved to part of the IRQ
425 * emit. For now, do it in both places:
426 */
427
de227f5f
DA		 428static void i915_emit_breadcrumb(drm_device_t *dev)
429{
430 drm_i915_private_t *dev_priv = dev->dev_private;
431 RING_LOCALS;
432
c29b669c
AH		 433 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
434
435 if (dev_priv->counter > 0x7FFFFFFFUL)
436 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
de227f5f
DA		 437
438 BEGIN_LP_RING(4);
439 OUT_RING(CMD_STORE_DWORD_IDX);
440 OUT_RING(20);
441 OUT_RING(dev_priv->counter);
442 OUT_RING(0);
443 ADVANCE_LP_RING();
444}
445
1da177e4
LT		 446static int i915_dispatch_cmdbuffer(drm_device_t * dev,
447 drm_i915_cmdbuffer_t * cmd)
448{
449 int nbox = cmd->num_cliprects;
450 int i = 0, count, ret;
451
452 if (cmd->sz & 0x3) {
453 DRM_ERROR("alignment");
454 return DRM_ERR(EINVAL);
455 }
456
457 i915_kernel_lost_context(dev);
458
459 count = nbox ? nbox : 1;
460
461 for (i = 0; i < count; i++) {
462 if (i < nbox) {
463 ret = i915_emit_box(dev, cmd->cliprects, i,
464 cmd->DR1, cmd->DR4);
465 if (ret)
466 return ret;
467 }
468
469 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
470 if (ret)
471 return ret;
472 }
473
de227f5f 474 i915_emit_breadcrumb(dev);
1da177e4
LT		 475 return 0;
476}
477
478static int i915_dispatch_batchbuffer(drm_device_t * dev,
479 drm_i915_batchbuffer_t * batch)
480{
481 drm_i915_private_t *dev_priv = dev->dev_private;
482 drm_clip_rect_t __user *boxes = batch->cliprects;
483 int nbox = batch->num_cliprects;
484 int i = 0, count;
485 RING_LOCALS;
486
487 if ((batch->start | batch->used) & 0x7) {
488 DRM_ERROR("alignment");
489 return DRM_ERR(EINVAL);
490 }
491
492 i915_kernel_lost_context(dev);
493
494 count = nbox ? nbox : 1;
495
496 for (i = 0; i < count; i++) {
497 if (i < nbox) {
498 int ret = i915_emit_box(dev, boxes, i,
499 batch->DR1, batch->DR4);
500 if (ret)
501 return ret;
502 }
503
504 if (dev_priv->use_mi_batchbuffer_start) {
505 BEGIN_LP_RING(2);
506 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
507 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
508 ADVANCE_LP_RING();
509 } else {
510 BEGIN_LP_RING(4);
511 OUT_RING(MI_BATCH_BUFFER);
512 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
513 OUT_RING(batch->start + batch->used - 4);
514 OUT_RING(0);
515 ADVANCE_LP_RING();
516 }
517 }
518
de227f5f 519 i915_emit_breadcrumb(dev);
1da177e4
LT		 520
521 return 0;
522}
523
524static int i915_dispatch_flip(drm_device_t * dev)
525{
526 drm_i915_private_t *dev_priv = dev->dev_private;
527 RING_LOCALS;
528
529 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
530 __FUNCTION__,
531 dev_priv->current_page,
532 dev_priv->sarea_priv->pf_current_page);
533
534 i915_kernel_lost_context(dev);
535
536 BEGIN_LP_RING(2);
537 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
538 OUT_RING(0);
539 ADVANCE_LP_RING();
540
541 BEGIN_LP_RING(6);
542 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
543 OUT_RING(0);
544 if (dev_priv->current_page == 0) {
545 OUT_RING(dev_priv->back_offset);
546 dev_priv->current_page = 1;
547 } else {
548 OUT_RING(dev_priv->front_offset);
549 dev_priv->current_page = 0;
550 }
551 OUT_RING(0);
552 ADVANCE_LP_RING();
553
554 BEGIN_LP_RING(2);
555 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
556 OUT_RING(0);
557 ADVANCE_LP_RING();
558
559 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
560
561 BEGIN_LP_RING(4);
562 OUT_RING(CMD_STORE_DWORD_IDX);
563 OUT_RING(20);
564 OUT_RING(dev_priv->counter);
565 OUT_RING(0);
566 ADVANCE_LP_RING();
567
568 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
569 return 0;
570}
571
572static int i915_quiescent(drm_device_t * dev)
573{
574 drm_i915_private_t *dev_priv = dev->dev_private;
575
576 i915_kernel_lost_context(dev);
577 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
578}
579
c94f7029 580static int i915_flush_ioctl(DRM_IOCTL_ARGS)
1da177e4
LT		 581{
582 DRM_DEVICE;
583
584 LOCK_TEST_WITH_RETURN(dev, filp);
585
586 return i915_quiescent(dev);
587}
588
c94f7029 589static int i915_batchbuffer(DRM_IOCTL_ARGS)
1da177e4
LT		 590{
591 DRM_DEVICE;
592 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
593 u32 *hw_status = dev_priv->hw_status_page;
594 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
595 dev_priv->sarea_priv;
596 drm_i915_batchbuffer_t batch;
597 int ret;
598
599 if (!dev_priv->allow_batchbuffer) {
600 DRM_ERROR("Batchbuffer ioctl disabled\n");
601 return DRM_ERR(EINVAL);
602 }
603
604 DRM_COPY_FROM_USER_IOCTL(batch, (drm_i915_batchbuffer_t __user *) data,
605 sizeof(batch));
606
607 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
608 batch.start, batch.used, batch.num_cliprects);
609
610 LOCK_TEST_WITH_RETURN(dev, filp);
611
612 if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
613 batch.num_cliprects *
614 sizeof(drm_clip_rect_t)))
615 return DRM_ERR(EFAULT);
616
617 ret = i915_dispatch_batchbuffer(dev, &batch);
618
619 sarea_priv->last_dispatch = (int)hw_status[5];
620 return ret;
621}
622
c94f7029 623static int i915_cmdbuffer(DRM_IOCTL_ARGS)
1da177e4
LT		 624{
625 DRM_DEVICE;
626 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
627 u32 *hw_status = dev_priv->hw_status_page;
628 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
629 dev_priv->sarea_priv;
630 drm_i915_cmdbuffer_t cmdbuf;
631 int ret;
632
633 DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_i915_cmdbuffer_t __user *) data,
634 sizeof(cmdbuf));
635
636 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
637 cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
638
639 LOCK_TEST_WITH_RETURN(dev, filp);
640
641 if (cmdbuf.num_cliprects &&
642 DRM_VERIFYAREA_READ(cmdbuf.cliprects,
643 cmdbuf.num_cliprects *
644 sizeof(drm_clip_rect_t))) {
645 DRM_ERROR("Fault accessing cliprects\n");
646 return DRM_ERR(EFAULT);
647 }
648
649 ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
650 if (ret) {
651 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
652 return ret;
653 }
654
655 sarea_priv->last_dispatch = (int)hw_status[5];
656 return 0;
657}
658
c94f7029 659static int i915_flip_bufs(DRM_IOCTL_ARGS)
1da177e4
LT		 660{
661 DRM_DEVICE;
662
663 DRM_DEBUG("%s\n", __FUNCTION__);
664
665 LOCK_TEST_WITH_RETURN(dev, filp);
666
667 return i915_dispatch_flip(dev);
668}
669
c94f7029 670static int i915_getparam(DRM_IOCTL_ARGS)
1da177e4
LT		 671{
672 DRM_DEVICE;
673 drm_i915_private_t *dev_priv = dev->dev_private;
674 drm_i915_getparam_t param;
675 int value;
676
677 if (!dev_priv) {
678 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
679 return DRM_ERR(EINVAL);
680 }
681
682 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_getparam_t __user *) data,
683 sizeof(param));
684
685 switch (param.param) {
686 case I915_PARAM_IRQ_ACTIVE:
687 value = dev->irq ? 1 : 0;
688 break;
689 case I915_PARAM_ALLOW_BATCHBUFFER:
690 value = dev_priv->allow_batchbuffer ? 1 : 0;
691 break;
0d6aa60b
DA		 692 case I915_PARAM_LAST_DISPATCH:
693 value = READ_BREADCRUMB(dev_priv);
694 break;
1da177e4 695 default:
de227f5f 696 DRM_ERROR("Unknown parameter %d\n", param.param);
1da177e4
LT		 697 return DRM_ERR(EINVAL);
698 }
699
700 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
701 DRM_ERROR("DRM_COPY_TO_USER failed\n");
702 return DRM_ERR(EFAULT);
703 }
704
705 return 0;
706}
707
c94f7029 708static int i915_setparam(DRM_IOCTL_ARGS)
1da177e4
LT		 709{
710 DRM_DEVICE;
711 drm_i915_private_t *dev_priv = dev->dev_private;
712 drm_i915_setparam_t param;
713
714 if (!dev_priv) {
715 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
716 return DRM_ERR(EINVAL);
717 }
718
719 DRM_COPY_FROM_USER_IOCTL(param, (drm_i915_setparam_t __user *) data,
720 sizeof(param));
721
722 switch (param.param) {
723 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
724 dev_priv->use_mi_batchbuffer_start = param.value;
725 break;
726 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
727 dev_priv->tex_lru_log_granularity = param.value;
728 break;
729 case I915_SETPARAM_ALLOW_BATCHBUFFER:
730 dev_priv->allow_batchbuffer = param.value;
731 break;
732 default:
733 DRM_ERROR("unknown parameter %d\n", param.param);
734 return DRM_ERR(EINVAL);
735 }
736
737 return 0;
738}
739
22eae947
DA		 740int i915_driver_load(drm_device_t *dev, unsigned long flags)
741{
742 /* i915 has 4 more counters */
743 dev->counters += 4;
744 dev->types[6] = _DRM_STAT_IRQ;
745 dev->types[7] = _DRM_STAT_PRIMARY;
746 dev->types[8] = _DRM_STAT_SECONDARY;
747 dev->types[9] = _DRM_STAT_DMA;
748
749 return 0;
750}
751
752void i915_driver_lastclose(drm_device_t * dev)
1da177e4 753{
b5e89ed5 754 if (dev->dev_private) {
1da177e4 755 drm_i915_private_t *dev_priv = dev->dev_private;
b5e89ed5
DA		 756 i915_mem_takedown(&(dev_priv->agp_heap));
757 }
758 i915_dma_cleanup(dev);
1da177e4
LT		 759}
760
22eae947 761void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
1da177e4 762{
b5e89ed5 763 if (dev->dev_private) {
1da177e4 764 drm_i915_private_t *dev_priv = dev->dev_private;
b5e89ed5 765 i915_mem_release(dev, filp, dev_priv->agp_heap);
1da177e4
LT		 766 }
767}
768
c94f7029 769drm_ioctl_desc_t i915_ioctls[] = {
a7a2cc31
DA		 770 [DRM_IOCTL_NR(DRM_I915_INIT)] = {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
771 [DRM_IOCTL_NR(DRM_I915_FLUSH)] = {i915_flush_ioctl, DRM_AUTH},
772 [DRM_IOCTL_NR(DRM_I915_FLIP)] = {i915_flip_bufs, DRM_AUTH},
773 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] = {i915_batchbuffer, DRM_AUTH},
774 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] = {i915_irq_emit, DRM_AUTH},
775 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] = {i915_irq_wait, DRM_AUTH},
776 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] = {i915_getparam, DRM_AUTH},
777 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] = {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
778 [DRM_IOCTL_NR(DRM_I915_ALLOC)] = {i915_mem_alloc, DRM_AUTH},
779 [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH},
780 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
de227f5f 781 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH},
702880f2
DA		 782 [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
783 [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY },
784 [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH },
c94f7029
DA		 785};
786
787int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
cda17380
DA		 788
789/**
790 * Determine if the device really is AGP or not.
791 *
792 * All Intel graphics chipsets are treated as AGP, even if they are really
793 * PCI-e.
794 *
795 * \param dev The device to be tested.
796 *
797 * \returns
798 * A value of 1 is always retured to indictate every i9x5 is AGP.
799 */
800int i915_driver_device_is_agp(drm_device_t * dev)
801{
802 return 1;
803}
Clone of davem's net-next-2.6 tree