git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /************************************************************************* |
| 2 | * Defines and structure definitions for PCI BIOS Interface | |
| 3 | *************************************************************************/ | |
| 4 | #define PCIMAX 32 /* maximum number of PCI boards */ | |
| 5 | ||
| 6 | ||
| 7 | #define PCI_VENDOR_DIGI 0x114F | |
| 8 | #define PCI_DEVICE_EPC 0x0002 | |
| 9 | #define PCI_DEVICE_RIGHTSWITCH 0x0003 /* For testing */ | |
| 10 | #define PCI_DEVICE_XEM 0x0004 | |
| 11 | #define PCI_DEVICE_XR 0x0005 | |
| 12 | #define PCI_DEVICE_CX 0x0006 | |
| 13 | #define PCI_DEVICE_XRJ 0x0009 /* Jupiter boards with */ | |
| 14 | #define PCI_DEVICE_EPCJ 0x000a /* PLX 9060 chip for PCI */ | |
| 15 | ||
| 16 | ||
| 17 | /* | |
| 18 | * On the PCI boards, there is no IO space allocated | |
| 19 | * The I/O registers will be in the first 3 bytes of the | |
| 20 | * upper 2MB of the 4MB memory space. The board memory | |
| 21 | * will be mapped into the low 2MB of the 4MB memory space | |
| 22 | */ | |
| 23 | ||
| 24 | /* Potential location of PCI Bios from E0000 to FFFFF*/ | |
| 25 | #define PCI_BIOS_SIZE 0x00020000 | |
| 26 | ||
| 27 | /* Size of Memory and I/O for PCI (4MB) */ | |
| 28 | #define PCI_RAM_SIZE 0x00400000 | |
| 29 | ||
| 30 | /* Size of Memory (2MB) */ | |
| 31 | #define PCI_MEM_SIZE 0x00200000 | |
| 32 | ||
| 33 | /* Offset of I/0 in Memory (2MB) */ | |
| 34 | #define PCI_IO_OFFSET 0x00200000 | |
| 35 | ||
| 36 | #define MEMOUTB(basemem, pnum, setmemval) *(caddr_t)((basemem) + ( PCI_IO_OFFSET | pnum << 4 | pnum )) = (setmemval) | |
| 37 | #define MEMINB(basemem, pnum) *(caddr_t)((basemem) + (PCI_IO_OFFSET | pnum << 4 | pnum )) /* for PCI I/O */ | |
| 38 | ||
| 39 | ||
| 40 | ||
| 41 | ||
| 42 |