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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * UniNorth AGPGART routines. | |
3 | */ | |
4 | #include <linux/module.h> | |
5 | #include <linux/pci.h> | |
5a0e3ad6 | 6 | #include <linux/slab.h> |
1da177e4 LT |
7 | #include <linux/init.h> |
8 | #include <linux/pagemap.h> | |
9 | #include <linux/agp_backend.h> | |
10 | #include <linux/delay.h> | |
e8a5f900 | 11 | #include <linux/vmalloc.h> |
1da177e4 LT |
12 | #include <asm/uninorth.h> |
13 | #include <asm/pci-bridge.h> | |
14 | #include <asm/prom.h> | |
0c541b44 | 15 | #include <asm/pmac_feature.h> |
1da177e4 LT |
16 | #include "agp.h" |
17 | ||
18 | /* | |
19 | * NOTES for uninorth3 (G5 AGP) supports : | |
20 | * | |
21 | * There maybe also possibility to have bigger cache line size for | |
22 | * agp (see pmac_pci.c and look for cache line). Need to be investigated | |
23 | * by someone. | |
24 | * | |
25 | * PAGE size are hardcoded but this may change, see asm/page.h. | |
26 | * | |
27 | * Jerome Glisse <j.glisse@gmail.com> | |
28 | */ | |
29 | static int uninorth_rev; | |
30 | static int is_u3; | |
61cf0593 | 31 | static u32 scratch_value; |
1da177e4 | 32 | |
52f072cb MD |
33 | #define DEFAULT_APERTURE_SIZE 256 |
34 | #define DEFAULT_APERTURE_STRING "256" | |
b0385146 | 35 | static char *aperture = NULL; |
0c541b44 | 36 | |
1da177e4 LT |
37 | static int uninorth_fetch_size(void) |
38 | { | |
18088748 MD |
39 | int i, size = 0; |
40 | struct aper_size_info_32 *values = | |
41 | A_SIZE_32(agp_bridge->driver->aperture_sizes); | |
42 | ||
43 | if (aperture) { | |
44 | char *save = aperture; | |
45 | ||
46 | size = memparse(aperture, &aperture) >> 20; | |
47 | aperture = save; | |
48 | ||
49 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) | |
50 | if (size == values[i].size) | |
51 | break; | |
52 | ||
53 | if (i == agp_bridge->driver->num_aperture_sizes) { | |
e3cf6951 BH |
54 | dev_err(&agp_bridge->dev->dev, "invalid aperture size, " |
55 | "using default\n"); | |
18088748 MD |
56 | size = 0; |
57 | aperture = NULL; | |
1da177e4 LT |
58 | } |
59 | } | |
60 | ||
18088748 MD |
61 | if (!size) { |
62 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) | |
52f072cb | 63 | if (values[i].size == DEFAULT_APERTURE_SIZE) |
18088748 MD |
64 | break; |
65 | } | |
1da177e4 | 66 | |
18088748 MD |
67 | agp_bridge->previous_size = |
68 | agp_bridge->current_size = (void *)(values + i); | |
69 | agp_bridge->aperture_size_idx = i; | |
70 | return values[i].size; | |
1da177e4 LT |
71 | } |
72 | ||
73 | static void uninorth_tlbflush(struct agp_memory *mem) | |
74 | { | |
75 | u32 ctrl = UNI_N_CFG_GART_ENABLE; | |
76 | ||
77 | if (is_u3) | |
78 | ctrl |= U3_N_CFG_GART_PERFRD; | |
79 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, | |
80 | ctrl | UNI_N_CFG_GART_INVAL); | |
81 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); | |
82 | ||
83 | if (uninorth_rev <= 0x30) { | |
84 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, | |
85 | ctrl | UNI_N_CFG_GART_2xRESET); | |
86 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, | |
87 | ctrl); | |
88 | } | |
89 | } | |
90 | ||
91 | static void uninorth_cleanup(void) | |
92 | { | |
93 | u32 tmp; | |
94 | ||
95 | pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); | |
96 | if (!(tmp & UNI_N_CFG_GART_ENABLE)) | |
97 | return; | |
98 | tmp |= UNI_N_CFG_GART_INVAL; | |
99 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); | |
100 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); | |
101 | ||
102 | if (uninorth_rev <= 0x30) { | |
103 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, | |
104 | UNI_N_CFG_GART_2xRESET); | |
105 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, | |
106 | 0); | |
107 | } | |
108 | } | |
109 | ||
110 | static int uninorth_configure(void) | |
111 | { | |
112 | struct aper_size_info_32 *current_size; | |
6a92a4e0 | 113 | |
1da177e4 LT |
114 | current_size = A_SIZE_32(agp_bridge->current_size); |
115 | ||
e3cf6951 BH |
116 | dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n", |
117 | current_size->size_value); | |
6a92a4e0 | 118 | |
1da177e4 LT |
119 | /* aperture size and gatt addr */ |
120 | pci_write_config_dword(agp_bridge->dev, | |
121 | UNI_N_CFG_GART_BASE, | |
122 | (agp_bridge->gatt_bus_addr & 0xfffff000) | |
123 | | current_size->size_value); | |
124 | ||
125 | /* HACK ALERT | |
126 | * UniNorth seem to be buggy enough not to handle properly when | |
127 | * the AGP aperture isn't mapped at bus physical address 0 | |
128 | */ | |
129 | agp_bridge->gart_bus_addr = 0; | |
130 | #ifdef CONFIG_PPC64 | |
131 | /* Assume U3 or later on PPC64 systems */ | |
132 | /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ | |
133 | pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, | |
134 | (agp_bridge->gatt_bus_addr >> 32) & 0xf); | |
135 | #else | |
136 | pci_write_config_dword(agp_bridge->dev, | |
137 | UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); | |
138 | #endif | |
139 | ||
140 | if (is_u3) { | |
141 | pci_write_config_dword(agp_bridge->dev, | |
142 | UNI_N_CFG_GART_DUMMY_PAGE, | |
5e8d6b8b | 143 | page_to_phys(agp_bridge->scratch_page_page) >> 12); |
1da177e4 | 144 | } |
6a92a4e0 | 145 | |
1da177e4 LT |
146 | return 0; |
147 | } | |
148 | ||
37580f3f | 149 | static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type) |
1da177e4 LT |
150 | { |
151 | int i, num_entries; | |
152 | void *temp; | |
153 | u32 *gp; | |
62369028 | 154 | int mask_type; |
1da177e4 | 155 | |
62369028 MD |
156 | if (type != mem->type) |
157 | return -EINVAL; | |
158 | ||
159 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
160 | if (mask_type != 0) { | |
1da177e4 LT |
161 | /* We know nothing of memory types */ |
162 | return -EINVAL; | |
62369028 MD |
163 | } |
164 | ||
3fc3a6b4 MD |
165 | if (mem->page_count == 0) |
166 | return 0; | |
167 | ||
168 | temp = agp_bridge->current_size; | |
169 | num_entries = A_SIZE_32(temp)->num_entries; | |
170 | ||
1da177e4 LT |
171 | if ((pg_start + mem->page_count) > num_entries) |
172 | return -EINVAL; | |
173 | ||
174 | gp = (u32 *) &agp_bridge->gatt_table[pg_start]; | |
175 | for (i = 0; i < mem->page_count; ++i) { | |
61cf0593 | 176 | if (gp[i] != scratch_value) { |
e3cf6951 | 177 | dev_info(&agp_bridge->dev->dev, |
37580f3f | 178 | "uninorth_insert_memory: entry 0x%x occupied (%x)\n", |
e3cf6951 | 179 | i, gp[i]); |
1da177e4 LT |
180 | return -EBUSY; |
181 | } | |
182 | } | |
183 | ||
184 | for (i = 0; i < mem->page_count; i++) { | |
37580f3f MD |
185 | if (is_u3) |
186 | gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL; | |
187 | else | |
188 | gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | | |
189 | 0x1UL); | |
07613ba2 DA |
190 | flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])), |
191 | (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000); | |
1da177e4 LT |
192 | } |
193 | mb(); | |
1da177e4 LT |
194 | uninorth_tlbflush(mem); |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
37580f3f | 199 | int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type) |
1da177e4 LT |
200 | { |
201 | size_t i; | |
202 | u32 *gp; | |
3fc3a6b4 | 203 | int mask_type; |
1da177e4 | 204 | |
3fc3a6b4 MD |
205 | if (type != mem->type) |
206 | return -EINVAL; | |
207 | ||
208 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
209 | if (mask_type != 0) { | |
1da177e4 LT |
210 | /* We know nothing of memory types */ |
211 | return -EINVAL; | |
3fc3a6b4 MD |
212 | } |
213 | ||
214 | if (mem->page_count == 0) | |
215 | return 0; | |
1da177e4 LT |
216 | |
217 | gp = (u32 *) &agp_bridge->gatt_table[pg_start]; | |
61cf0593 JG |
218 | for (i = 0; i < mem->page_count; ++i) { |
219 | gp[i] = scratch_value; | |
220 | } | |
1da177e4 | 221 | mb(); |
1da177e4 LT |
222 | uninorth_tlbflush(mem); |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
228 | { | |
229 | u32 command, scratch, status; | |
230 | int timeout; | |
231 | ||
232 | pci_read_config_dword(bridge->dev, | |
233 | bridge->capndx + PCI_AGP_STATUS, | |
234 | &status); | |
235 | ||
236 | command = agp_collect_device_status(bridge, mode, status); | |
237 | command |= PCI_AGP_COMMAND_AGP; | |
6a92a4e0 | 238 | |
1da177e4 LT |
239 | if (uninorth_rev == 0x21) { |
240 | /* | |
241 | * Darwin disable AGP 4x on this revision, thus we | |
242 | * may assume it's broken. This is an AGP2 controller. | |
243 | */ | |
244 | command &= ~AGPSTAT2_4X; | |
245 | } | |
246 | ||
247 | if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { | |
248 | /* | |
fd589a8f | 249 | * We need to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, |
1da177e4 LT |
250 | * 2.2 and 2.3, Darwin do so. |
251 | */ | |
252 | if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) | |
253 | command = (command & ~AGPSTAT_RQ_DEPTH) | |
254 | | (7 << AGPSTAT_RQ_DEPTH_SHIFT); | |
255 | } | |
256 | ||
257 | uninorth_tlbflush(NULL); | |
258 | ||
259 | timeout = 0; | |
260 | do { | |
261 | pci_write_config_dword(bridge->dev, | |
262 | bridge->capndx + PCI_AGP_COMMAND, | |
263 | command); | |
264 | pci_read_config_dword(bridge->dev, | |
265 | bridge->capndx + PCI_AGP_COMMAND, | |
266 | &scratch); | |
267 | } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); | |
268 | if ((scratch & PCI_AGP_COMMAND_AGP) == 0) | |
e3cf6951 BH |
269 | dev_err(&bridge->dev->dev, "can't write UniNorth AGP " |
270 | "command register\n"); | |
1da177e4 LT |
271 | |
272 | if (uninorth_rev >= 0x30) { | |
273 | /* This is an AGP V3 */ | |
c7258012 | 274 | agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0); |
1da177e4 LT |
275 | } else { |
276 | /* AGP V2 */ | |
c7258012 | 277 | agp_device_command(command, false); |
1da177e4 LT |
278 | } |
279 | ||
280 | uninorth_tlbflush(NULL); | |
281 | } | |
282 | ||
283 | #ifdef CONFIG_PM | |
0c541b44 BH |
284 | /* |
285 | * These Power Management routines are _not_ called by the normal PCI PM layer, | |
286 | * but directly by the video driver through function pointers in the device | |
287 | * tree. | |
288 | */ | |
289 | static int agp_uninorth_suspend(struct pci_dev *pdev) | |
1da177e4 | 290 | { |
0c541b44 | 291 | struct agp_bridge_data *bridge; |
1da177e4 LT |
292 | u32 cmd; |
293 | u8 agp; | |
294 | struct pci_dev *device = NULL; | |
295 | ||
0c541b44 BH |
296 | bridge = agp_find_bridge(pdev); |
297 | if (bridge == NULL) | |
298 | return -ENODEV; | |
299 | ||
300 | /* Only one suspend supported */ | |
301 | if (bridge->dev_private_data) | |
1da177e4 LT |
302 | return 0; |
303 | ||
304 | /* turn off AGP on the video chip, if it was enabled */ | |
305 | for_each_pci_dev(device) { | |
306 | /* Don't touch the bridge yet, device first */ | |
307 | if (device == pdev) | |
308 | continue; | |
309 | /* Only deal with devices on the same bus here, no Mac has a P2P | |
310 | * bridge on the AGP port, and mucking around the entire PCI | |
311 | * tree is source of problems on some machines because of a bug | |
312 | * in some versions of pci_find_capability() when hitting a dead | |
313 | * device | |
314 | */ | |
315 | if (device->bus != pdev->bus) | |
316 | continue; | |
317 | agp = pci_find_capability(device, PCI_CAP_ID_AGP); | |
318 | if (!agp) | |
319 | continue; | |
320 | pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); | |
321 | if (!(cmd & PCI_AGP_COMMAND_AGP)) | |
322 | continue; | |
e3cf6951 BH |
323 | dev_info(&pdev->dev, "disabling AGP on device %s\n", |
324 | pci_name(device)); | |
1da177e4 LT |
325 | cmd &= ~PCI_AGP_COMMAND_AGP; |
326 | pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); | |
327 | } | |
328 | ||
329 | /* turn off AGP on the bridge */ | |
330 | agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
331 | pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); | |
b07cd518 | 332 | bridge->dev_private_data = (void *)(long)cmd; |
1da177e4 | 333 | if (cmd & PCI_AGP_COMMAND_AGP) { |
e3cf6951 | 334 | dev_info(&pdev->dev, "disabling AGP on bridge\n"); |
1da177e4 LT |
335 | cmd &= ~PCI_AGP_COMMAND_AGP; |
336 | pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); | |
337 | } | |
338 | /* turn off the GART */ | |
339 | uninorth_cleanup(); | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
344 | static int agp_uninorth_resume(struct pci_dev *pdev) | |
345 | { | |
0c541b44 BH |
346 | struct agp_bridge_data *bridge; |
347 | u32 command; | |
348 | ||
349 | bridge = agp_find_bridge(pdev); | |
350 | if (bridge == NULL) | |
351 | return -ENODEV; | |
352 | ||
b07cd518 | 353 | command = (long)bridge->dev_private_data; |
0c541b44 BH |
354 | bridge->dev_private_data = NULL; |
355 | if (!(command & PCI_AGP_COMMAND_AGP)) | |
356 | return 0; | |
357 | ||
358 | uninorth_agp_enable(bridge, command); | |
359 | ||
1da177e4 LT |
360 | return 0; |
361 | } | |
0c541b44 | 362 | #endif /* CONFIG_PM */ |
1da177e4 LT |
363 | |
364 | static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) | |
365 | { | |
366 | char *table; | |
367 | char *table_end; | |
368 | int size; | |
369 | int page_order; | |
370 | int num_entries; | |
371 | int i; | |
372 | void *temp; | |
373 | struct page *page; | |
e8a5f900 | 374 | struct page **pages; |
1da177e4 LT |
375 | |
376 | /* We can't handle 2 level gatt's */ | |
377 | if (bridge->driver->size_type == LVL2_APER_SIZE) | |
378 | return -EINVAL; | |
379 | ||
380 | table = NULL; | |
381 | i = bridge->aperture_size_idx; | |
382 | temp = bridge->current_size; | |
383 | size = page_order = num_entries = 0; | |
384 | ||
385 | do { | |
386 | size = A_SIZE_32(temp)->size; | |
387 | page_order = A_SIZE_32(temp)->page_order; | |
388 | num_entries = A_SIZE_32(temp)->num_entries; | |
389 | ||
390 | table = (char *) __get_free_pages(GFP_KERNEL, page_order); | |
391 | ||
392 | if (table == NULL) { | |
393 | i++; | |
394 | bridge->current_size = A_IDX32(bridge); | |
395 | } else { | |
396 | bridge->aperture_size_idx = i; | |
397 | } | |
398 | } while (!table && (i < bridge->driver->num_aperture_sizes)); | |
399 | ||
400 | if (table == NULL) | |
401 | return -ENOMEM; | |
402 | ||
e8a5f900 MD |
403 | pages = kmalloc((1 << page_order) * sizeof(struct page*), GFP_KERNEL); |
404 | if (pages == NULL) | |
405 | goto enomem; | |
406 | ||
1da177e4 LT |
407 | table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); |
408 | ||
e8a5f900 MD |
409 | for (page = virt_to_page(table), i = 0; page <= virt_to_page(table_end); |
410 | page++, i++) { | |
1da177e4 | 411 | SetPageReserved(page); |
e8a5f900 MD |
412 | pages[i] = page; |
413 | } | |
1da177e4 LT |
414 | |
415 | bridge->gatt_table_real = (u32 *) table; | |
e8a5f900 MD |
416 | /* Need to clear out any dirty data still sitting in caches */ |
417 | flush_dcache_range((unsigned long)table, | |
418 | (unsigned long)(table_end + PAGE_SIZE)); | |
419 | bridge->gatt_table = vmap(pages, (1 << page_order), 0, PAGE_KERNEL_NCG); | |
420 | ||
421 | if (bridge->gatt_table == NULL) | |
422 | goto enomem; | |
423 | ||
6a12235c | 424 | bridge->gatt_bus_addr = virt_to_phys(table); |
1da177e4 | 425 | |
61cf0593 JG |
426 | if (is_u3) |
427 | scratch_value = (page_to_phys(agp_bridge->scratch_page_page) >> PAGE_SHIFT) | 0x80000000UL; | |
428 | else | |
429 | scratch_value = cpu_to_le32((page_to_phys(agp_bridge->scratch_page_page) & 0xFFFFF000UL) | | |
430 | 0x1UL); | |
1da177e4 | 431 | for (i = 0; i < num_entries; i++) |
61cf0593 | 432 | bridge->gatt_table[i] = scratch_value; |
1da177e4 | 433 | |
1da177e4 | 434 | return 0; |
e8a5f900 MD |
435 | |
436 | enomem: | |
437 | kfree(pages); | |
438 | if (table) | |
439 | free_pages((unsigned long)table, page_order); | |
440 | return -ENOMEM; | |
1da177e4 LT |
441 | } |
442 | ||
443 | static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) | |
444 | { | |
445 | int page_order; | |
446 | char *table, *table_end; | |
447 | void *temp; | |
448 | struct page *page; | |
449 | ||
450 | temp = bridge->current_size; | |
451 | page_order = A_SIZE_32(temp)->page_order; | |
452 | ||
453 | /* Do not worry about freeing memory, because if this is | |
454 | * called, then all agp memory is deallocated and removed | |
455 | * from the table. | |
456 | */ | |
457 | ||
e8a5f900 | 458 | vunmap(bridge->gatt_table); |
1da177e4 LT |
459 | table = (char *) bridge->gatt_table_real; |
460 | table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); | |
461 | ||
462 | for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) | |
463 | ClearPageReserved(page); | |
464 | ||
465 | free_pages((unsigned long) bridge->gatt_table_real, page_order); | |
466 | ||
467 | return 0; | |
468 | } | |
469 | ||
470 | void null_cache_flush(void) | |
471 | { | |
472 | mb(); | |
473 | } | |
474 | ||
475 | /* Setup function */ | |
476 | ||
52f072cb | 477 | static const struct aper_size_info_32 uninorth_sizes[] = |
1da177e4 | 478 | { |
1da177e4 LT |
479 | {256, 65536, 6, 64}, |
480 | {128, 32768, 5, 32}, | |
481 | {64, 16384, 4, 16}, | |
1da177e4 LT |
482 | {32, 8192, 3, 8}, |
483 | {16, 4096, 2, 4}, | |
484 | {8, 2048, 1, 2}, | |
485 | {4, 1024, 0, 1} | |
486 | }; | |
487 | ||
488 | /* | |
489 | * Not sure that u3 supports that high aperture sizes but it | |
490 | * would strange if it did not :) | |
491 | */ | |
52f072cb | 492 | static const struct aper_size_info_32 u3_sizes[] = |
1da177e4 LT |
493 | { |
494 | {512, 131072, 7, 128}, | |
495 | {256, 65536, 6, 64}, | |
496 | {128, 32768, 5, 32}, | |
497 | {64, 16384, 4, 16}, | |
498 | {32, 8192, 3, 8}, | |
499 | {16, 4096, 2, 4}, | |
500 | {8, 2048, 1, 2}, | |
501 | {4, 1024, 0, 1} | |
502 | }; | |
503 | ||
e047d1cf | 504 | const struct agp_bridge_driver uninorth_agp_driver = { |
1da177e4 LT |
505 | .owner = THIS_MODULE, |
506 | .aperture_sizes = (void *)uninorth_sizes, | |
507 | .size_type = U32_APER_SIZE, | |
52f072cb | 508 | .num_aperture_sizes = ARRAY_SIZE(uninorth_sizes), |
1da177e4 LT |
509 | .configure = uninorth_configure, |
510 | .fetch_size = uninorth_fetch_size, | |
511 | .cleanup = uninorth_cleanup, | |
512 | .tlb_flush = uninorth_tlbflush, | |
513 | .mask_memory = agp_generic_mask_memory, | |
514 | .masks = NULL, | |
515 | .cache_flush = null_cache_flush, | |
516 | .agp_enable = uninorth_agp_enable, | |
517 | .create_gatt_table = uninorth_create_gatt_table, | |
518 | .free_gatt_table = uninorth_free_gatt_table, | |
519 | .insert_memory = uninorth_insert_memory, | |
37580f3f | 520 | .remove_memory = uninorth_remove_memory, |
1da177e4 LT |
521 | .alloc_by_type = agp_generic_alloc_by_type, |
522 | .free_by_type = agp_generic_free_by_type, | |
523 | .agp_alloc_page = agp_generic_alloc_page, | |
5f310b63 | 524 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 525 | .agp_destroy_page = agp_generic_destroy_page, |
5f310b63 | 526 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 527 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
c7258012 | 528 | .cant_use_aperture = true, |
61cf0593 | 529 | .needs_scratch_page = true, |
1da177e4 LT |
530 | }; |
531 | ||
e047d1cf | 532 | const struct agp_bridge_driver u3_agp_driver = { |
1da177e4 LT |
533 | .owner = THIS_MODULE, |
534 | .aperture_sizes = (void *)u3_sizes, | |
535 | .size_type = U32_APER_SIZE, | |
52f072cb | 536 | .num_aperture_sizes = ARRAY_SIZE(u3_sizes), |
1da177e4 LT |
537 | .configure = uninorth_configure, |
538 | .fetch_size = uninorth_fetch_size, | |
539 | .cleanup = uninorth_cleanup, | |
540 | .tlb_flush = uninorth_tlbflush, | |
541 | .mask_memory = agp_generic_mask_memory, | |
542 | .masks = NULL, | |
543 | .cache_flush = null_cache_flush, | |
544 | .agp_enable = uninorth_agp_enable, | |
545 | .create_gatt_table = uninorth_create_gatt_table, | |
546 | .free_gatt_table = uninorth_free_gatt_table, | |
37580f3f MD |
547 | .insert_memory = uninorth_insert_memory, |
548 | .remove_memory = uninorth_remove_memory, | |
1da177e4 LT |
549 | .alloc_by_type = agp_generic_alloc_by_type, |
550 | .free_by_type = agp_generic_free_by_type, | |
551 | .agp_alloc_page = agp_generic_alloc_page, | |
5f310b63 | 552 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 553 | .agp_destroy_page = agp_generic_destroy_page, |
c09ff7e1 | 554 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 555 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
c7258012 JP |
556 | .cant_use_aperture = true, |
557 | .needs_scratch_page = true, | |
1da177e4 LT |
558 | }; |
559 | ||
560 | static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { | |
561 | { | |
562 | .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, | |
563 | .chipset_name = "UniNorth", | |
564 | }, | |
565 | { | |
566 | .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, | |
567 | .chipset_name = "UniNorth/Pangea", | |
568 | }, | |
569 | { | |
570 | .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, | |
571 | .chipset_name = "UniNorth 1.5", | |
572 | }, | |
573 | { | |
574 | .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, | |
575 | .chipset_name = "UniNorth 2", | |
576 | }, | |
577 | { | |
578 | .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, | |
579 | .chipset_name = "U3", | |
580 | }, | |
581 | { | |
582 | .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, | |
583 | .chipset_name = "U3L", | |
584 | }, | |
585 | { | |
586 | .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, | |
587 | .chipset_name = "U3H", | |
588 | }, | |
7fce260a OJ |
589 | { |
590 | .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP, | |
591 | .chipset_name = "UniNorth/Intrepid2", | |
592 | }, | |
1da177e4 LT |
593 | }; |
594 | ||
595 | static int __devinit agp_uninorth_probe(struct pci_dev *pdev, | |
596 | const struct pci_device_id *ent) | |
597 | { | |
598 | struct agp_device_ids *devs = uninorth_agp_device_ids; | |
599 | struct agp_bridge_data *bridge; | |
600 | struct device_node *uninorth_node; | |
601 | u8 cap_ptr; | |
602 | int j; | |
603 | ||
604 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
605 | if (cap_ptr == 0) | |
606 | return -ENODEV; | |
607 | ||
608 | /* probe for known chipsets */ | |
609 | for (j = 0; devs[j].chipset_name != NULL; ++j) { | |
610 | if (pdev->device == devs[j].device_id) { | |
e3cf6951 BH |
611 | dev_info(&pdev->dev, "Apple %s chipset\n", |
612 | devs[j].chipset_name); | |
1da177e4 LT |
613 | goto found; |
614 | } | |
615 | } | |
616 | ||
e3cf6951 BH |
617 | dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n", |
618 | pdev->vendor, pdev->device); | |
1da177e4 LT |
619 | return -ENODEV; |
620 | ||
621 | found: | |
622 | /* Set revision to 0 if we could not read it. */ | |
623 | uninorth_rev = 0; | |
624 | is_u3 = 0; | |
625 | /* Locate core99 Uni-N */ | |
626 | uninorth_node = of_find_node_by_name(NULL, "uni-n"); | |
627 | /* Locate G5 u3 */ | |
628 | if (uninorth_node == NULL) { | |
629 | is_u3 = 1; | |
630 | uninorth_node = of_find_node_by_name(NULL, "u3"); | |
631 | } | |
632 | if (uninorth_node) { | |
40cd3a45 | 633 | const int *revprop = of_get_property(uninorth_node, |
b04e3dd4 | 634 | "device-rev", NULL); |
1da177e4 LT |
635 | if (revprop != NULL) |
636 | uninorth_rev = *revprop & 0x3f; | |
637 | of_node_put(uninorth_node); | |
638 | } | |
639 | ||
0c541b44 BH |
640 | #ifdef CONFIG_PM |
641 | /* Inform platform of our suspend/resume caps */ | |
642 | pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume); | |
643 | #endif | |
644 | ||
645 | /* Allocate & setup our driver */ | |
1da177e4 LT |
646 | bridge = agp_alloc_bridge(); |
647 | if (!bridge) | |
648 | return -ENOMEM; | |
649 | ||
650 | if (is_u3) | |
651 | bridge->driver = &u3_agp_driver; | |
652 | else | |
653 | bridge->driver = &uninorth_agp_driver; | |
654 | ||
655 | bridge->dev = pdev; | |
656 | bridge->capndx = cap_ptr; | |
657 | bridge->flags = AGP_ERRATA_FASTWRITES; | |
658 | ||
659 | /* Fill in the mode register */ | |
660 | pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); | |
661 | ||
662 | pci_set_drvdata(pdev, bridge); | |
663 | return agp_add_bridge(bridge); | |
664 | } | |
665 | ||
666 | static void __devexit agp_uninorth_remove(struct pci_dev *pdev) | |
667 | { | |
668 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
669 | ||
0c541b44 BH |
670 | #ifdef CONFIG_PM |
671 | /* Inform platform of our suspend/resume caps */ | |
672 | pmac_register_agp_pm(pdev, NULL, NULL); | |
673 | #endif | |
674 | ||
1da177e4 LT |
675 | agp_remove_bridge(bridge); |
676 | agp_put_bridge(bridge); | |
677 | } | |
678 | ||
679 | static struct pci_device_id agp_uninorth_pci_table[] = { | |
680 | { | |
681 | .class = (PCI_CLASS_BRIDGE_HOST << 8), | |
682 | .class_mask = ~0, | |
683 | .vendor = PCI_VENDOR_ID_APPLE, | |
684 | .device = PCI_ANY_ID, | |
685 | .subvendor = PCI_ANY_ID, | |
686 | .subdevice = PCI_ANY_ID, | |
687 | }, | |
688 | { } | |
689 | }; | |
690 | ||
691 | MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); | |
692 | ||
693 | static struct pci_driver agp_uninorth_pci_driver = { | |
694 | .name = "agpgart-uninorth", | |
695 | .id_table = agp_uninorth_pci_table, | |
696 | .probe = agp_uninorth_probe, | |
697 | .remove = agp_uninorth_remove, | |
1da177e4 LT |
698 | }; |
699 | ||
700 | static int __init agp_uninorth_init(void) | |
701 | { | |
702 | if (agp_off) | |
703 | return -EINVAL; | |
704 | return pci_register_driver(&agp_uninorth_pci_driver); | |
705 | } | |
706 | ||
707 | static void __exit agp_uninorth_cleanup(void) | |
708 | { | |
709 | pci_unregister_driver(&agp_uninorth_pci_driver); | |
710 | } | |
711 | ||
712 | module_init(agp_uninorth_init); | |
713 | module_exit(agp_uninorth_cleanup); | |
714 | ||
18088748 MD |
715 | module_param(aperture, charp, 0); |
716 | MODULE_PARM_DESC(aperture, | |
717 | "Aperture size, must be power of two between 4MB and an\n" | |
718 | "\t\tupper limit specific to the UniNorth revision.\n" | |
52f072cb | 719 | "\t\tDefault: " DEFAULT_APERTURE_STRING "M"); |
18088748 | 720 | |
1da177e4 LT |
721 | MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); |
722 | MODULE_LICENSE("GPL"); |