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ff7cdd69 DV |
1 | /* |
2 | * Common Intel AGPGART and GTT definitions. | |
3 | */ | |
93f5f7f1 ZW |
4 | #ifndef _INTEL_AGP_H |
5 | #define _INTEL_AGP_H | |
ff7cdd69 DV |
6 | |
7 | /* Intel registers */ | |
8 | #define INTEL_APSIZE 0xb4 | |
9 | #define INTEL_ATTBASE 0xb8 | |
10 | #define INTEL_AGPCTRL 0xb0 | |
11 | #define INTEL_NBXCFG 0x50 | |
12 | #define INTEL_ERRSTS 0x91 | |
13 | ||
14 | /* Intel i830 registers */ | |
15 | #define I830_GMCH_CTRL 0x52 | |
16 | #define I830_GMCH_ENABLED 0x4 | |
17 | #define I830_GMCH_MEM_MASK 0x1 | |
18 | #define I830_GMCH_MEM_64M 0x1 | |
19 | #define I830_GMCH_MEM_128M 0 | |
20 | #define I830_GMCH_GMS_MASK 0x70 | |
21 | #define I830_GMCH_GMS_DISABLED 0x00 | |
22 | #define I830_GMCH_GMS_LOCAL 0x10 | |
23 | #define I830_GMCH_GMS_STOLEN_512 0x20 | |
24 | #define I830_GMCH_GMS_STOLEN_1024 0x30 | |
25 | #define I830_GMCH_GMS_STOLEN_8192 0x40 | |
26 | #define I830_RDRAM_CHANNEL_TYPE 0x03010 | |
27 | #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) | |
28 | #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) | |
29 | ||
30 | /* This one is for I830MP w. an external graphic card */ | |
31 | #define INTEL_I830_ERRSTS 0x92 | |
32 | ||
33 | /* Intel 855GM/852GM registers */ | |
34 | #define I855_GMCH_GMS_MASK 0xF0 | |
35 | #define I855_GMCH_GMS_STOLEN_0M 0x0 | |
36 | #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) | |
37 | #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) | |
38 | #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) | |
39 | #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) | |
40 | #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) | |
41 | #define I85X_CAPID 0x44 | |
42 | #define I85X_VARIANT_MASK 0x7 | |
43 | #define I85X_VARIANT_SHIFT 5 | |
44 | #define I855_GME 0x0 | |
45 | #define I855_GM 0x4 | |
46 | #define I852_GME 0x2 | |
47 | #define I852_GM 0x5 | |
48 | ||
49 | /* Intel i845 registers */ | |
50 | #define INTEL_I845_AGPM 0x51 | |
51 | #define INTEL_I845_ERRSTS 0xc8 | |
52 | ||
53 | /* Intel i860 registers */ | |
54 | #define INTEL_I860_MCHCFG 0x50 | |
55 | #define INTEL_I860_ERRSTS 0xc8 | |
56 | ||
57 | /* Intel i810 registers */ | |
58 | #define I810_GMADDR 0x10 | |
59 | #define I810_MMADDR 0x14 | |
60 | #define I810_PTE_BASE 0x10000 | |
61 | #define I810_PTE_MAIN_UNCACHED 0x00000000 | |
62 | #define I810_PTE_LOCAL 0x00000002 | |
63 | #define I810_PTE_VALID 0x00000001 | |
64 | #define I830_PTE_SYSTEM_CACHED 0x00000006 | |
a2757b6f ZW |
65 | /* GT PTE cache control fields */ |
66 | #define GEN6_PTE_UNCACHED 0x00000002 | |
67 | #define GEN6_PTE_LLC 0x00000004 | |
68 | #define GEN6_PTE_LLC_MLC 0x00000006 | |
69 | #define GEN6_PTE_GFDT 0x00000008 | |
70 | ||
ff7cdd69 DV |
71 | #define I810_SMRAM_MISCC 0x70 |
72 | #define I810_GFX_MEM_WIN_SIZE 0x00010000 | |
73 | #define I810_GFX_MEM_WIN_32M 0x00010000 | |
74 | #define I810_GMS 0x000000c0 | |
75 | #define I810_GMS_DISABLE 0x00000000 | |
76 | #define I810_PGETBL_CTL 0x2020 | |
77 | #define I810_PGETBL_ENABLED 0x00000001 | |
78 | #define I965_PGETBL_SIZE_MASK 0x0000000e | |
79 | #define I965_PGETBL_SIZE_512KB (0 << 1) | |
80 | #define I965_PGETBL_SIZE_256KB (1 << 1) | |
81 | #define I965_PGETBL_SIZE_128KB (2 << 1) | |
82 | #define I965_PGETBL_SIZE_1MB (3 << 1) | |
83 | #define I965_PGETBL_SIZE_2MB (4 << 1) | |
84 | #define I965_PGETBL_SIZE_1_5MB (5 << 1) | |
85 | #define G33_PGETBL_SIZE_MASK (3 << 8) | |
86 | #define G33_PGETBL_SIZE_1M (1 << 8) | |
87 | #define G33_PGETBL_SIZE_2M (2 << 8) | |
88 | ||
89 | #define I810_DRAM_CTL 0x3000 | |
90 | #define I810_DRAM_ROW_0 0x00000001 | |
91 | #define I810_DRAM_ROW_0_SDRAM 0x00000001 | |
92 | ||
93 | /* Intel 815 register */ | |
94 | #define INTEL_815_APCONT 0x51 | |
95 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
96 | ||
97 | /* Intel i820 registers */ | |
98 | #define INTEL_I820_RDCR 0x51 | |
99 | #define INTEL_I820_ERRSTS 0xc8 | |
100 | ||
101 | /* Intel i840 registers */ | |
102 | #define INTEL_I840_MCHCFG 0x50 | |
103 | #define INTEL_I840_ERRSTS 0xc8 | |
104 | ||
105 | /* Intel i850 registers */ | |
106 | #define INTEL_I850_MCHCFG 0x50 | |
107 | #define INTEL_I850_ERRSTS 0xc8 | |
108 | ||
109 | /* intel 915G registers */ | |
110 | #define I915_GMADDR 0x18 | |
111 | #define I915_MMADDR 0x10 | |
112 | #define I915_PTEADDR 0x1C | |
113 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
114 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
115 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) | |
116 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
117 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
118 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
119 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
120 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
121 | ||
122 | #define I915_IFPADDR 0x60 | |
123 | ||
124 | /* Intel 965G registers */ | |
125 | #define I965_MSAC 0x62 | |
126 | #define I965_IFPADDR 0x70 | |
127 | ||
128 | /* Intel 7505 registers */ | |
129 | #define INTEL_I7505_APSIZE 0x74 | |
130 | #define INTEL_I7505_NCAPID 0x60 | |
131 | #define INTEL_I7505_NISTAT 0x6c | |
132 | #define INTEL_I7505_ATTBASE 0x78 | |
133 | #define INTEL_I7505_ERRSTS 0x42 | |
134 | #define INTEL_I7505_AGPCTRL 0x70 | |
135 | #define INTEL_I7505_MCHCFG 0x50 | |
136 | ||
137 | #define SNB_GMCH_CTRL 0x50 | |
138 | #define SNB_GMCH_GMS_STOLEN_MASK 0xF8 | |
139 | #define SNB_GMCH_GMS_STOLEN_32M (1 << 3) | |
140 | #define SNB_GMCH_GMS_STOLEN_64M (2 << 3) | |
141 | #define SNB_GMCH_GMS_STOLEN_96M (3 << 3) | |
142 | #define SNB_GMCH_GMS_STOLEN_128M (4 << 3) | |
143 | #define SNB_GMCH_GMS_STOLEN_160M (5 << 3) | |
144 | #define SNB_GMCH_GMS_STOLEN_192M (6 << 3) | |
145 | #define SNB_GMCH_GMS_STOLEN_224M (7 << 3) | |
146 | #define SNB_GMCH_GMS_STOLEN_256M (8 << 3) | |
147 | #define SNB_GMCH_GMS_STOLEN_288M (9 << 3) | |
148 | #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) | |
149 | #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) | |
150 | #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) | |
151 | #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) | |
152 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) | |
153 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) | |
154 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) | |
155 | #define SNB_GTT_SIZE_0M (0 << 8) | |
156 | #define SNB_GTT_SIZE_1M (1 << 8) | |
157 | #define SNB_GTT_SIZE_2M (2 << 8) | |
158 | #define SNB_GTT_SIZE_MASK (3 << 8) | |
159 | ||
160 | /* pci devices ids */ | |
161 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 | |
162 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
163 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 | |
164 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
165 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 | |
166 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
167 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 | |
168 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
169 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
170 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
171 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 | |
172 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
173 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 | |
174 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 | |
175 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC | |
176 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE | |
177 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 | |
178 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 | |
179 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 | |
180 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 | |
181 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 | |
182 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
183 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
184 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
185 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
186 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
187 | #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 | |
188 | #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 | |
41a51428 CW |
189 | #define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90 |
190 | #define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92 | |
ff7cdd69 DV |
191 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
192 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
193 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 | |
194 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 | |
195 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 | |
196 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
197 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
198 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
199 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 | |
200 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
201 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 | |
202 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 | |
203 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 | |
204 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 | |
205 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a | |
206 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 | |
85540480 ZW |
207 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */ |
208 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102 | |
209 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112 | |
210 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122 | |
211 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */ | |
212 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106 | |
213 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116 | |
214 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126 | |
215 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */ | |
216 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A | |
ff7cdd69 DV |
217 | |
218 | /* cover 915 and 945 variants */ | |
219 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
220 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
221 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
222 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
223 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
224 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
225 | ||
226 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ | |
227 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ | |
228 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
229 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
230 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
231 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) | |
232 | ||
233 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ | |
234 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
235 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ | |
236 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ | |
237 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
238 | ||
239 | #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ | |
240 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
241 | ||
242 | #define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \ | |
85540480 ZW |
243 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \ |
244 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB) | |
ff7cdd69 DV |
245 | |
246 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ | |
247 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ | |
248 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ | |
249 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ | |
250 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ | |
251 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ | |
252 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \ | |
253 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ | |
254 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ | |
255 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ | |
256 | IS_SNB) | |
93f5f7f1 ZW |
257 | |
258 | #endif |