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agp: two-stage page destruction issue
[net-next-2.6.git] / drivers / char / agp / intel-agp.c
CommitLineData
1da177e4
LT		 1/*
2 * Intel AGPGART routines.
3 */
4
1da177e4
LT		 5#include <linux/module.h>
6#include <linux/pci.h>
7#include <linux/init.h>
1eaf122c 8#include <linux/kernel.h>
1da177e4
LT		 9#include <linux/pagemap.h>
10#include <linux/agp_backend.h>
11#include "agp.h"
12
e914a36a
CM		 13#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
65c25aad
EA		 15#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
9119f85a
ZW		 17#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
65c25aad
EA		 19#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
4598af33
WZ		 23#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
dde47876 25#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
c8eebfd6 26#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
dde47876 27#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
df80b148 28#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
874808c6
WZ		 29#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
30#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
31#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
32#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
33#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
34#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
4e8b6e25
ZW		 35#define PCI_DEVICE_ID_INTEL_IGD_HB 0x2A40
36#define PCI_DEVICE_ID_INTEL_IGD_IG 0x2A42
65c25aad 37
f011ae74
DA		 38/* cover 915 and 945 variants */
39#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
40 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
41 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
42 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
43 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
44 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
45
65c25aad 46#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
f011ae74
DA		 47 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
48 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
49 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
50 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
4e8b6e25
ZW		 51 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB || \
52 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
65c25aad 53
874808c6
WZ		 54#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
55 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
56 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
65c25aad 57
a030ce44
TH		 58extern int agp_memory_reserved;
59
60
1da177e4
LT		 61/* Intel 815 register */
62#define INTEL_815_APCONT 0x51
63#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
64
65/* Intel i820 registers */
66#define INTEL_I820_RDCR 0x51
67#define INTEL_I820_ERRSTS 0xc8
68
69/* Intel i840 registers */
70#define INTEL_I840_MCHCFG 0x50
71#define INTEL_I840_ERRSTS 0xc8
72
73/* Intel i850 registers */
74#define INTEL_I850_MCHCFG 0x50
75#define INTEL_I850_ERRSTS 0xc8
76
77/* intel 915G registers */
78#define I915_GMADDR 0x18
79#define I915_MMADDR 0x10
80#define I915_PTEADDR 0x1C
81#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
82#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
874808c6
WZ		 83#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
84#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
6c00a61e 85#define I915_IFPADDR 0x60
1da177e4 86
65c25aad
EA		 87/* Intel 965G registers */
88#define I965_MSAC 0x62
6c00a61e 89#define I965_IFPADDR 0x70
1da177e4
LT		 90
91/* Intel 7505 registers */
92#define INTEL_I7505_APSIZE 0x74
93#define INTEL_I7505_NCAPID 0x60
94#define INTEL_I7505_NISTAT 0x6c
95#define INTEL_I7505_ATTBASE 0x78
96#define INTEL_I7505_ERRSTS 0x42
97#define INTEL_I7505_AGPCTRL 0x70
98#define INTEL_I7505_MCHCFG 0x50
99
e5524f35 100static const struct aper_size_info_fixed intel_i810_sizes[] =
1da177e4
LT		 101{
102 {64, 16384, 4},
103 /* The 32M mode still requires a 64k gatt */
104 {32, 8192, 4}
105};
106
107#define AGP_DCACHE_MEMORY 1
108#define AGP_PHYS_MEMORY 2
a030ce44 109#define INTEL_AGP_CACHED_MEMORY 3
1da177e4
LT		 110
111static struct gatt_mask intel_i810_masks[] =
112{
113 {.mask = I810_PTE_VALID, .type = 0},
114 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
a030ce44
TH		 115 {.mask = I810_PTE_VALID, .type = 0},
116 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
117 .type = INTEL_AGP_CACHED_MEMORY}
1da177e4
LT		 118};
119
c4ca8817
WZ		 120static struct _intel_private {
121 struct pci_dev *pcidev; /* device one */
122 u8 __iomem *registers;
123 u32 __iomem *gtt; /* I915G */
1da177e4 124 int num_dcache_entries;
c4ca8817
WZ		 125 /* gtt_entries is the number of gtt entries that are already mapped
126 * to stolen memory. Stolen memory is larger than the memory mapped
127 * through gtt_entries, as it includes some reserved space for the BIOS
128 * popup and for the GTT.
129 */
130 int gtt_entries; /* i830+ */
2162e6a2
DA		 131 union {
132 void __iomem *i9xx_flush_page;
133 void *i8xx_flush_page;
134 };
135 struct page *i8xx_page;
6c00a61e 136 struct resource ifp_resource;
4d64dd9e 137 int resource_valid;
c4ca8817 138} intel_private;
1da177e4
LT		 139
140static int intel_i810_fetch_size(void)
141{
142 u32 smram_miscc;
143 struct aper_size_info_fixed *values;
144
145 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
146 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
147
148 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
149 printk(KERN_WARNING PFX "i810 is disabled\n");
150 return 0;
151 }
152 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
153 agp_bridge->previous_size =
154 agp_bridge->current_size = (void *) (values + 1);
155 agp_bridge->aperture_size_idx = 1;
156 return values[1].size;
157 } else {
158 agp_bridge->previous_size =
159 agp_bridge->current_size = (void *) (values);
160 agp_bridge->aperture_size_idx = 0;
161 return values[0].size;
162 }
163
164 return 0;
165}
166
167static int intel_i810_configure(void)
168{
169 struct aper_size_info_fixed *current_size;
170 u32 temp;
171 int i;
172
173 current_size = A_SIZE_FIX(agp_bridge->current_size);
174
c4ca8817
WZ		 175 if (!intel_private.registers) {
176 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
e4ac5e4f
DJ		 177 temp &= 0xfff80000;
178
c4ca8817
WZ		 179 intel_private.registers = ioremap(temp, 128 * 4096);
180 if (!intel_private.registers) {
e4ac5e4f
DJ		 181 printk(KERN_ERR PFX "Unable to remap memory.\n");
182 return -ENOMEM;
183 }
1da177e4
LT		 184 }
185
c4ca8817 186 if ((readl(intel_private.registers+I810_DRAM_CTL)
1da177e4
LT		 187 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
188 /* This will need to be dynamically assigned */
189 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
c4ca8817 190 intel_private.num_dcache_entries = 1024;
1da177e4 191 }
c4ca8817 192 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
1da177e4 193 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
c4ca8817
WZ		 194 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
195 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1da177e4
LT		 196
197 if (agp_bridge->driver->needs_scratch_page) {
198 for (i = 0; i < current_size->num_entries; i++) {
c4ca8817
WZ		 199 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
200 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
1da177e4
LT		 201 }
202 }
203 global_cache_flush();
204 return 0;
205}
206
207static void intel_i810_cleanup(void)
208{
c4ca8817
WZ		 209 writel(0, intel_private.registers+I810_PGETBL_CTL);
210 readl(intel_private.registers); /* PCI Posting. */
211 iounmap(intel_private.registers);
1da177e4
LT		 212}
213
214static void intel_i810_tlbflush(struct agp_memory *mem)
215{
216 return;
217}
218
219static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
220{
221 return;
222}
223
224/* Exists to support ARGB cursors */
225static void *i8xx_alloc_pages(void)
226{
f011ae74 227 struct page *page;
1da177e4 228
66c669ba 229 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
1da177e4
LT		 230 if (page == NULL)
231 return NULL;
232
6d238cc4
AV		 233 if (set_pages_uc(page, 4) < 0) {
234 set_pages_wb(page, 4);
89cf7ccc 235 __free_pages(page, 2);
1da177e4
LT		 236 return NULL;
237 }
1da177e4 238 get_page(page);
1da177e4
LT		 239 atomic_inc(&agp_bridge->current_memory_agp);
240 return page_address(page);
241}
242
243static void i8xx_destroy_pages(void *addr)
244{
245 struct page *page;
246
247 if (addr == NULL)
248 return;
249
250 page = virt_to_page(addr);
6d238cc4 251 set_pages_wb(page, 4);
1da177e4 252 put_page(page);
89cf7ccc 253 __free_pages(page, 2);
1da177e4
LT		 254 atomic_dec(&agp_bridge->current_memory_agp);
255}
256
a030ce44
TH		 257static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
258 int type)
259{
260 if (type < AGP_USER_TYPES)
261 return type;
262 else if (type == AGP_USER_CACHED_MEMORY)
263 return INTEL_AGP_CACHED_MEMORY;
264 else
265 return 0;
266}
267
1da177e4
LT		 268static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
269 int type)
270{
271 int i, j, num_entries;
272 void *temp;
a030ce44
TH		 273 int ret = -EINVAL;
274 int mask_type;
1da177e4 275
5aa80c72 276 if (mem->page_count == 0)
a030ce44 277 goto out;
5aa80c72 278
1da177e4
LT		 279 temp = agp_bridge->current_size;
280 num_entries = A_SIZE_FIX(temp)->num_entries;
281
6a92a4e0 282 if ((pg_start + mem->page_count) > num_entries)
a030ce44 283 goto out_err;
6a92a4e0 284
1da177e4 285
a030ce44
TH		 286 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
287 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
288 ret = -EBUSY;
289 goto out_err;
1da177e4 290 }
1da177e4
LT		 291 }
292
a030ce44
TH		 293 if (type != mem->type)
294 goto out_err;
5aa80c72 295
a030ce44
TH		 296 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
297
298 switch (mask_type) {
299 case AGP_DCACHE_MEMORY:
300 if (!mem->is_flushed)
301 global_cache_flush();
302 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
303 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
c4ca8817 304 intel_private.registers+I810_PTE_BASE+(i*4));
a030ce44 305 }
c4ca8817 306 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
a030ce44
TH		 307 break;
308 case AGP_PHYS_MEMORY:
309 case AGP_NORMAL_MEMORY:
310 if (!mem->is_flushed)
311 global_cache_flush();
312 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
313 writel(agp_bridge->driver->mask_memory(agp_bridge,
314 mem->memory[i],
315 mask_type),
c4ca8817 316 intel_private.registers+I810_PTE_BASE+(j*4));
a030ce44 317 }
c4ca8817 318 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
a030ce44
TH		 319 break;
320 default:
321 goto out_err;
1da177e4 322 }
1da177e4
LT		 323
324 agp_bridge->driver->tlb_flush(mem);
a030ce44
TH		 325out:
326 ret = 0;
327out_err:
328 mem->is_flushed = 1;
329 return ret;
1da177e4
LT		 330}
331
332static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
333 int type)
334{
335 int i;
336
5aa80c72
TH		 337 if (mem->page_count == 0)
338 return 0;
339
1da177e4 340 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
c4ca8817 341 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1da177e4 342 }
c4ca8817 343 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1da177e4 344
1da177e4
LT		 345 agp_bridge->driver->tlb_flush(mem);
346 return 0;
347}
348
349/*
350 * The i810/i830 requires a physical address to program its mouse
351 * pointer into hardware.
352 * However the Xserver still writes to it through the agp aperture.
353 */
354static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
355{
356 struct agp_memory *new;
357 void *addr;
358
1da177e4
LT		 359 switch (pg_count) {
360 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
361 break;
362 case 4:
363 /* kludge to get 4 physical pages for ARGB cursor */
364 addr = i8xx_alloc_pages();
365 break;
366 default:
367 return NULL;
368 }
369
370 if (addr == NULL)
371 return NULL;
372
373 new = agp_create_memory(pg_count);
374 if (new == NULL)
375 return NULL;
376
07eee78e 377 new->memory[0] = virt_to_gart(addr);
1da177e4
LT		 378 if (pg_count == 4) {
379 /* kludge to get 4 physical pages for ARGB cursor */
380 new->memory[1] = new->memory[0] + PAGE_SIZE;
381 new->memory[2] = new->memory[1] + PAGE_SIZE;
382 new->memory[3] = new->memory[2] + PAGE_SIZE;
383 }
384 new->page_count = pg_count;
385 new->num_scratch_pages = pg_count;
386 new->type = AGP_PHYS_MEMORY;
387 new->physical = new->memory[0];
388 return new;
389}
390
391static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
392{
393 struct agp_memory *new;
394
395 if (type == AGP_DCACHE_MEMORY) {
c4ca8817 396 if (pg_count != intel_private.num_dcache_entries)
1da177e4
LT		 397 return NULL;
398
399 new = agp_create_memory(1);
400 if (new == NULL)
401 return NULL;
402
403 new->type = AGP_DCACHE_MEMORY;
404 new->page_count = pg_count;
405 new->num_scratch_pages = 0;
a030ce44 406 agp_free_page_array(new);
1da177e4
LT		 407 return new;
408 }
409 if (type == AGP_PHYS_MEMORY)
410 return alloc_agpphysmem_i8xx(pg_count, type);
1da177e4
LT		 411 return NULL;
412}
413
414static void intel_i810_free_by_type(struct agp_memory *curr)
415{
416 agp_free_key(curr->key);
6a92a4e0 417 if (curr->type == AGP_PHYS_MEMORY) {
1da177e4 418 if (curr->page_count == 4)
07eee78e 419 i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
88d51967 420 else {
da503fa6
JB		 421 void *va = gart_to_virt(curr->memory[0]);
422
423 agp_bridge->driver->agp_destroy_page(va,
a2721e99 424 AGP_PAGE_DESTROY_UNMAP);
da503fa6 425 agp_bridge->driver->agp_destroy_page(va,
a2721e99 426 AGP_PAGE_DESTROY_FREE);
88d51967 427 }
a030ce44 428 agp_free_page_array(curr);
1da177e4
LT		 429 }
430 kfree(curr);
431}
432
433static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
434 unsigned long addr, int type)
435{
436 /* Type checking must be done elsewhere */
437 return addr | bridge->driver->masks[type].mask;
438}
439
440static struct aper_size_info_fixed intel_i830_sizes[] =
441{
442 {128, 32768, 5},
443 /* The 64M mode still requires a 128k gatt */
444 {64, 16384, 5},
445 {256, 65536, 6},
65c25aad 446 {512, 131072, 7},
1da177e4
LT		 447};
448
1da177e4
LT		 449static void intel_i830_init_gtt_entries(void)
450{
451 u16 gmch_ctrl;
452 int gtt_entries;
453 u8 rdct;
454 int local = 0;
455 static const int ddt[4] = { 0, 16, 32, 64 };
c41e0deb 456 int size; /* reserved space (in kb) at the top of stolen memory */
1da177e4 457
f011ae74 458 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1da177e4 459
c41e0deb
EA		 460 if (IS_I965) {
461 u32 pgetbl_ctl;
c4ca8817 462 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
c41e0deb 463
c41e0deb
EA		 464 /* The 965 has a field telling us the size of the GTT,
465 * which may be larger than what is necessary to map the
466 * aperture.
467 */
468 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
469 case I965_PGETBL_SIZE_128KB:
470 size = 128;
471 break;
472 case I965_PGETBL_SIZE_256KB:
473 size = 256;
474 break;
475 case I965_PGETBL_SIZE_512KB:
476 size = 512;
477 break;
4e8b6e25
ZW		 478 case I965_PGETBL_SIZE_1MB:
479 size = 1024;
480 break;
481 case I965_PGETBL_SIZE_2MB:
482 size = 2048;
483 break;
484 case I965_PGETBL_SIZE_1_5MB:
485 size = 1024 + 512;
486 break;
c41e0deb
EA		 487 default:
488 printk(KERN_INFO PFX "Unknown page table size, "
489 "assuming 512KB\n");
490 size = 512;
491 }
492 size += 4; /* add in BIOS popup space */
874808c6
WZ		 493 } else if (IS_G33) {
494 /* G33's GTT size defined in gmch_ctrl */
495 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
496 case G33_PGETBL_SIZE_1M:
497 size = 1024;
498 break;
499 case G33_PGETBL_SIZE_2M:
500 size = 2048;
501 break;
502 default:
503 printk(KERN_INFO PFX "Unknown page table size 0x%x, "
504 "assuming 512KB\n",
505 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
506 size = 512;
507 }
508 size += 4;
c41e0deb
EA		 509 } else {
510 /* On previous hardware, the GTT size was just what was
511 * required to map the aperture.
512 */
513 size = agp_bridge->driver->fetch_size() + 4;
514 }
1da177e4
LT		 515
516 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
517 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
518 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
519 case I830_GMCH_GMS_STOLEN_512:
520 gtt_entries = KB(512) - KB(size);
521 break;
522 case I830_GMCH_GMS_STOLEN_1024:
523 gtt_entries = MB(1) - KB(size);
524 break;
525 case I830_GMCH_GMS_STOLEN_8192:
526 gtt_entries = MB(8) - KB(size);
527 break;
528 case I830_GMCH_GMS_LOCAL:
c4ca8817 529 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
1da177e4
LT		 530 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
531 MB(ddt[I830_RDRAM_DDT(rdct)]);
532 local = 1;
533 break;
534 default:
535 gtt_entries = 0;
536 break;
537 }
538 } else {
e67aa27a 539 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
1da177e4
LT		 540 case I855_GMCH_GMS_STOLEN_1M:
541 gtt_entries = MB(1) - KB(size);
542 break;
543 case I855_GMCH_GMS_STOLEN_4M:
544 gtt_entries = MB(4) - KB(size);
545 break;
546 case I855_GMCH_GMS_STOLEN_8M:
547 gtt_entries = MB(8) - KB(size);
548 break;
549 case I855_GMCH_GMS_STOLEN_16M:
550 gtt_entries = MB(16) - KB(size);
551 break;
552 case I855_GMCH_GMS_STOLEN_32M:
553 gtt_entries = MB(32) - KB(size);
554 break;
555 case I915_GMCH_GMS_STOLEN_48M:
556 /* Check it's really I915G */
f011ae74 557 if (IS_I915 || IS_I965 || IS_G33)
1da177e4
LT		 558 gtt_entries = MB(48) - KB(size);
559 else
560 gtt_entries = 0;
561 break;
562 case I915_GMCH_GMS_STOLEN_64M:
563 /* Check it's really I915G */
f011ae74 564 if (IS_I915 || IS_I965 || IS_G33)
1da177e4
LT		 565 gtt_entries = MB(64) - KB(size);
566 else
567 gtt_entries = 0;
874808c6
WZ		 568 break;
569 case G33_GMCH_GMS_STOLEN_128M:
570 if (IS_G33)
571 gtt_entries = MB(128) - KB(size);
572 else
573 gtt_entries = 0;
574 break;
575 case G33_GMCH_GMS_STOLEN_256M:
576 if (IS_G33)
577 gtt_entries = MB(256) - KB(size);
578 else
579 gtt_entries = 0;
580 break;
1da177e4
LT		 581 default:
582 gtt_entries = 0;
583 break;
584 }
585 }
586 if (gtt_entries > 0)
587 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
588 gtt_entries / KB(1), local ? "local" : "stolen");
589 else
590 printk(KERN_INFO PFX
591 "No pre-allocated video memory detected.\n");
592 gtt_entries /= KB(4);
593
c4ca8817 594 intel_private.gtt_entries = gtt_entries;
1da177e4
LT		 595}
596
2162e6a2
DA		 597static void intel_i830_fini_flush(void)
598{
599 kunmap(intel_private.i8xx_page);
600 intel_private.i8xx_flush_page = NULL;
601 unmap_page_from_agp(intel_private.i8xx_page);
2162e6a2
DA		 602
603 __free_page(intel_private.i8xx_page);
4d64dd9e 604 intel_private.i8xx_page = NULL;
2162e6a2
DA		 605}
606
607static void intel_i830_setup_flush(void)
608{
4d64dd9e
DA		 609 /* return if we've already set the flush mechanism up */
610 if (intel_private.i8xx_page)
611 return;
2162e6a2
DA		 612
613 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
f011ae74 614 if (!intel_private.i8xx_page)
2162e6a2 615 return;
2162e6a2
DA		 616
617 /* make page uncached */
618 map_page_into_agp(intel_private.i8xx_page);
2162e6a2
DA		 619
620 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
621 if (!intel_private.i8xx_flush_page)
622 intel_i830_fini_flush();
623}
624
625static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
626{
627 unsigned int *pg = intel_private.i8xx_flush_page;
628 int i;
629
f011ae74 630 for (i = 0; i < 256; i += 2)
2162e6a2 631 *(pg + i) = i;
f011ae74 632
2162e6a2
DA		 633 wmb();
634}
635
1da177e4
LT		 636/* The intel i830 automatically initializes the agp aperture during POST.
637 * Use the memory already set aside for in the GTT.
638 */
639static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
640{
641 int page_order;
642 struct aper_size_info_fixed *size;
643 int num_entries;
644 u32 temp;
645
646 size = agp_bridge->current_size;
647 page_order = size->page_order;
648 num_entries = size->num_entries;
649 agp_bridge->gatt_table_real = NULL;
650
f011ae74 651 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
1da177e4
LT		 652 temp &= 0xfff80000;
653
f011ae74 654 intel_private.registers = ioremap(temp, 128 * 4096);
c4ca8817 655 if (!intel_private.registers)
1da177e4
LT		 656 return -ENOMEM;
657
c4ca8817 658 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1da177e4
LT		 659 global_cache_flush(); /* FIXME: ?? */
660
661 /* we have to call this as early as possible after the MMIO base address is known */
662 intel_i830_init_gtt_entries();
663
664 agp_bridge->gatt_table = NULL;
665
666 agp_bridge->gatt_bus_addr = temp;
667
668 return 0;
669}
670
671/* Return the gatt table to a sane state. Use the top of stolen
672 * memory for the GTT.
673 */
674static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
675{
676 return 0;
677}
678
679static int intel_i830_fetch_size(void)
680{
681 u16 gmch_ctrl;
682 struct aper_size_info_fixed *values;
683
684 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
685
686 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
687 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
688 /* 855GM/852GM/865G has 128MB aperture size */
689 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
690 agp_bridge->aperture_size_idx = 0;
691 return values[0].size;
692 }
693
f011ae74 694 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1da177e4
LT		 695
696 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
697 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
698 agp_bridge->aperture_size_idx = 0;
699 return values[0].size;
700 } else {
701 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
702 agp_bridge->aperture_size_idx = 1;
703 return values[1].size;
704 }
705
706 return 0;
707}
708
709static int intel_i830_configure(void)
710{
711 struct aper_size_info_fixed *current_size;
712 u32 temp;
713 u16 gmch_ctrl;
714 int i;
715
716 current_size = A_SIZE_FIX(agp_bridge->current_size);
717
f011ae74 718 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
1da177e4
LT		 719 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
720
f011ae74 721 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1da177e4 722 gmch_ctrl |= I830_GMCH_ENABLED;
f011ae74 723 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1da177e4 724
c4ca8817
WZ		 725 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
726 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1da177e4
LT		 727
728 if (agp_bridge->driver->needs_scratch_page) {
c4ca8817
WZ		 729 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
730 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
731 readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
1da177e4
LT		 732 }
733 }
734
735 global_cache_flush();
2162e6a2
DA		 736
737 intel_i830_setup_flush();
1da177e4
LT		 738 return 0;
739}
740
741static void intel_i830_cleanup(void)
742{
c4ca8817 743 iounmap(intel_private.registers);
1da177e4
LT		 744}
745
f011ae74
DA		 746static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
747 int type)
1da177e4 748{
f011ae74 749 int i, j, num_entries;
1da177e4 750 void *temp;
a030ce44
TH		 751 int ret = -EINVAL;
752 int mask_type;
1da177e4 753
5aa80c72 754 if (mem->page_count == 0)
a030ce44 755 goto out;
5aa80c72 756
1da177e4
LT		 757 temp = agp_bridge->current_size;
758 num_entries = A_SIZE_FIX(temp)->num_entries;
759
c4ca8817 760 if (pg_start < intel_private.gtt_entries) {
f011ae74
DA		 761 printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
762 pg_start, intel_private.gtt_entries);
1da177e4 763
f011ae74 764 printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n");
a030ce44 765 goto out_err;
1da177e4
LT		 766 }
767
768 if ((pg_start + mem->page_count) > num_entries)
a030ce44 769 goto out_err;
1da177e4
LT		 770
771 /* The i830 can't check the GTT for entries since its read only,
772 * depend on the caller to make the correct offset decisions.
773 */
774
a030ce44
TH		 775 if (type != mem->type)
776 goto out_err;
777
778 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1da177e4 779
a030ce44
TH		 780 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
781 mask_type != INTEL_AGP_CACHED_MEMORY)
782 goto out_err;
783
784 if (!mem->is_flushed)
5aa80c72 785 global_cache_flush();
1da177e4
LT		 786
787 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
788 writel(agp_bridge->driver->mask_memory(agp_bridge,
a030ce44 789 mem->memory[i], mask_type),
c4ca8817 790 intel_private.registers+I810_PTE_BASE+(j*4));
1da177e4 791 }
c4ca8817 792 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
1da177e4 793 agp_bridge->driver->tlb_flush(mem);
a030ce44
TH		 794
795out:
796 ret = 0;
797out_err:
798 mem->is_flushed = 1;
799 return ret;
1da177e4
LT		 800}
801
f011ae74
DA		 802static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
803 int type)
1da177e4
LT		 804{
805 int i;
806
5aa80c72
TH		 807 if (mem->page_count == 0)
808 return 0;
1da177e4 809
c4ca8817 810 if (pg_start < intel_private.gtt_entries) {
f011ae74 811 printk(KERN_INFO PFX "Trying to disable local/stolen memory\n");
1da177e4
LT		 812 return -EINVAL;
813 }
814
815 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
c4ca8817 816 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1da177e4 817 }
c4ca8817 818 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1da177e4 819
1da177e4
LT		 820 agp_bridge->driver->tlb_flush(mem);
821 return 0;
822}
823
f011ae74 824static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1da177e4
LT		 825{
826 if (type == AGP_PHYS_MEMORY)
827 return alloc_agpphysmem_i8xx(pg_count, type);
1da177e4
LT		 828 /* always return NULL for other allocation types for now */
829 return NULL;
830}
831
6c00a61e
DA		 832static int intel_alloc_chipset_flush_resource(void)
833{
834 int ret;
835 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
836 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
837 pcibios_align_resource, agp_bridge->dev);
6c00a61e 838
2162e6a2 839 return ret;
6c00a61e
DA		 840}
841
842static void intel_i915_setup_chipset_flush(void)
843{
844 int ret;
845 u32 temp;
846
847 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
848 if (!(temp & 0x1)) {
849 intel_alloc_chipset_flush_resource();
4d64dd9e 850 intel_private.resource_valid = 1;
6c00a61e
DA		 851 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
852 } else {
853 temp &= ~1;
854
4d64dd9e 855 intel_private.resource_valid = 1;
6c00a61e
DA		 856 intel_private.ifp_resource.start = temp;
857 intel_private.ifp_resource.end = temp + PAGE_SIZE;
858 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
4d64dd9e
DA		 859 /* some BIOSes reserve this area in a pnp some don't */
860 if (ret)
861 intel_private.resource_valid = 0;
6c00a61e
DA		 862 }
863}
864
865static void intel_i965_g33_setup_chipset_flush(void)
866{
867 u32 temp_hi, temp_lo;
868 int ret;
869
870 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
871 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
872
873 if (!(temp_lo & 0x1)) {
874
875 intel_alloc_chipset_flush_resource();
876
4d64dd9e 877 intel_private.resource_valid = 1;
1fa4db7d
AM		 878 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
879 upper_32_bits(intel_private.ifp_resource.start));
6c00a61e 880 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
6c00a61e
DA		 881 } else {
882 u64 l64;
f011ae74 883
6c00a61e
DA		 884 temp_lo &= ~0x1;
885 l64 = ((u64)temp_hi << 32) | temp_lo;
886
4d64dd9e 887 intel_private.resource_valid = 1;
6c00a61e
DA		 888 intel_private.ifp_resource.start = l64;
889 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
890 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
4d64dd9e
DA		 891 /* some BIOSes reserve this area in a pnp some don't */
892 if (ret)
893 intel_private.resource_valid = 0;
6c00a61e
DA		 894 }
895}
896
2162e6a2
DA		 897static void intel_i9xx_setup_flush(void)
898{
4d64dd9e
DA		 899 /* return if already configured */
900 if (intel_private.ifp_resource.start)
901 return;
2162e6a2 902
4d64dd9e 903 /* setup a resource for this object */
2162e6a2
DA		 904 intel_private.ifp_resource.name = "Intel Flush Page";
905 intel_private.ifp_resource.flags = IORESOURCE_MEM;
906
907 /* Setup chipset flush for 915 */
908 if (IS_I965 || IS_G33) {
909 intel_i965_g33_setup_chipset_flush();
910 } else {
911 intel_i915_setup_chipset_flush();
912 }
913
914 if (intel_private.ifp_resource.start) {
915 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
916 if (!intel_private.i9xx_flush_page)
f011ae74 917 printk(KERN_INFO "unable to ioremap flush page - no chipset flushing");
2162e6a2
DA		 918 }
919}
920
1da177e4
LT		 921static int intel_i915_configure(void)
922{
923 struct aper_size_info_fixed *current_size;
924 u32 temp;
925 u16 gmch_ctrl;
926 int i;
927
928 current_size = A_SIZE_FIX(agp_bridge->current_size);
929
c4ca8817 930 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1da177e4
LT		 931
932 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
933
f011ae74 934 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1da177e4 935 gmch_ctrl |= I830_GMCH_ENABLED;
f011ae74 936 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1da177e4 937
c4ca8817
WZ		 938 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
939 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1da177e4
LT		 940
941 if (agp_bridge->driver->needs_scratch_page) {
c4ca8817
WZ		 942 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
943 writel(agp_bridge->scratch_page, intel_private.gtt+i);
944 readl(intel_private.gtt+i); /* PCI Posting. */
1da177e4
LT		 945 }
946 }
947
948 global_cache_flush();
6c00a61e 949
2162e6a2 950 intel_i9xx_setup_flush();
f011ae74 951
1da177e4
LT		 952 return 0;
953}
954
955static void intel_i915_cleanup(void)
956{
2162e6a2
DA		 957 if (intel_private.i9xx_flush_page)
958 iounmap(intel_private.i9xx_flush_page);
4d64dd9e
DA		 959 if (intel_private.resource_valid)
960 release_resource(&intel_private.ifp_resource);
961 intel_private.ifp_resource.start = 0;
962 intel_private.resource_valid = 0;
c4ca8817
WZ		 963 iounmap(intel_private.gtt);
964 iounmap(intel_private.registers);
1da177e4
LT		 965}
966
6c00a61e
DA		 967static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
968{
2162e6a2
DA		 969 if (intel_private.i9xx_flush_page)
970 writel(1, intel_private.i9xx_flush_page);
6c00a61e
DA		 971}
972
f011ae74
DA		 973static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
974 int type)
1da177e4 975{
f011ae74 976 int i, j, num_entries;
1da177e4 977 void *temp;
a030ce44
TH		 978 int ret = -EINVAL;
979 int mask_type;
1da177e4 980
5aa80c72 981 if (mem->page_count == 0)
a030ce44 982 goto out;
5aa80c72 983
1da177e4
LT		 984 temp = agp_bridge->current_size;
985 num_entries = A_SIZE_FIX(temp)->num_entries;
986
c4ca8817 987 if (pg_start < intel_private.gtt_entries) {
f011ae74
DA		 988 printk(KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
989 pg_start, intel_private.gtt_entries);
1da177e4 990
f011ae74 991 printk(KERN_INFO PFX "Trying to insert into local/stolen memory\n");
a030ce44 992 goto out_err;
1da177e4
LT		 993 }
994
995 if ((pg_start + mem->page_count) > num_entries)
a030ce44 996 goto out_err;
1da177e4 997
a030ce44 998 /* The i915 can't check the GTT for entries since its read only,
1da177e4
LT		 999 * depend on the caller to make the correct offset decisions.
1000 */
1001
a030ce44
TH		 1002 if (type != mem->type)
1003 goto out_err;
1004
1005 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1da177e4 1006
a030ce44
TH		 1007 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1008 mask_type != INTEL_AGP_CACHED_MEMORY)
1009 goto out_err;
1010
1011 if (!mem->is_flushed)
5aa80c72 1012 global_cache_flush();
1da177e4
LT		 1013
1014 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1015 writel(agp_bridge->driver->mask_memory(agp_bridge,
c4ca8817 1016 mem->memory[i], mask_type), intel_private.gtt+j);
1da177e4
LT		 1017 }
1018
c4ca8817 1019 readl(intel_private.gtt+j-1);
1da177e4 1020 agp_bridge->driver->tlb_flush(mem);
a030ce44
TH		 1021
1022 out:
1023 ret = 0;
1024 out_err:
1025 mem->is_flushed = 1;
1026 return ret;
1da177e4
LT		 1027}
1028
f011ae74
DA		 1029static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1030 int type)
1da177e4
LT		 1031{
1032 int i;
1033
5aa80c72
TH		 1034 if (mem->page_count == 0)
1035 return 0;
1da177e4 1036
c4ca8817 1037 if (pg_start < intel_private.gtt_entries) {
f011ae74 1038 printk(KERN_INFO PFX "Trying to disable local/stolen memory\n");
1da177e4
LT		 1039 return -EINVAL;
1040 }
1041
f011ae74 1042 for (i = pg_start; i < (mem->page_count + pg_start); i++)
c4ca8817 1043 writel(agp_bridge->scratch_page, intel_private.gtt+i);
f011ae74 1044
c4ca8817 1045 readl(intel_private.gtt+i-1);
1da177e4 1046
1da177e4
LT		 1047 agp_bridge->driver->tlb_flush(mem);
1048 return 0;
1049}
1050
c41e0deb
EA		 1051/* Return the aperture size by just checking the resource length. The effect
1052 * described in the spec of the MSAC registers is just changing of the
1053 * resource size.
1054 */
1055static int intel_i9xx_fetch_size(void)
1da177e4 1056{
1eaf122c 1057 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
c41e0deb
EA		 1058 int aper_size; /* size in megabytes */
1059 int i;
1da177e4 1060
c4ca8817 1061 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1da177e4 1062
c41e0deb
EA		 1063 for (i = 0; i < num_sizes; i++) {
1064 if (aper_size == intel_i830_sizes[i].size) {
1065 agp_bridge->current_size = intel_i830_sizes + i;
1066 agp_bridge->previous_size = agp_bridge->current_size;
1067 return aper_size;
1068 }
1069 }
1da177e4 1070
c41e0deb 1071 return 0;
1da177e4
LT		 1072}
1073
1074/* The intel i915 automatically initializes the agp aperture during POST.
1075 * Use the memory already set aside for in the GTT.
1076 */
1077static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1078{
1079 int page_order;
1080 struct aper_size_info_fixed *size;
1081 int num_entries;
1082 u32 temp, temp2;
4740622c 1083 int gtt_map_size = 256 * 1024;
1da177e4
LT		 1084
1085 size = agp_bridge->current_size;
1086 page_order = size->page_order;
1087 num_entries = size->num_entries;
1088 agp_bridge->gatt_table_real = NULL;
1089
c4ca8817 1090 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
f011ae74 1091 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1da177e4 1092
4740622c
ZW		 1093 if (IS_G33)
1094 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1095 intel_private.gtt = ioremap(temp2, gtt_map_size);
c4ca8817 1096 if (!intel_private.gtt)
1da177e4
LT		 1097 return -ENOMEM;
1098
1099 temp &= 0xfff80000;
1100
f011ae74 1101 intel_private.registers = ioremap(temp, 128 * 4096);
5bdbc7dc
ST		 1102 if (!intel_private.registers) {
1103 iounmap(intel_private.gtt);
1da177e4 1104 return -ENOMEM;
5bdbc7dc 1105 }
1da177e4 1106
c4ca8817 1107 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1da177e4
LT		 1108 global_cache_flush(); /* FIXME: ? */
1109
1110 /* we have to call this as early as possible after the MMIO base address is known */
1111 intel_i830_init_gtt_entries();
1112
1113 agp_bridge->gatt_table = NULL;
1114
1115 agp_bridge->gatt_bus_addr = temp;
1116
1117 return 0;
1118}
7d915a38
LT		 1119
1120/*
1121 * The i965 supports 36-bit physical addresses, but to keep
1122 * the format of the GTT the same, the bits that don't fit
1123 * in a 32-bit word are shifted down to bits 4..7.
1124 *
1125 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1126 * is always zero on 32-bit architectures, so no need to make
1127 * this conditional.
1128 */
1129static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1130 unsigned long addr, int type)
1131{
1132 /* Shift high bits down */
1133 addr |= (addr >> 28) & 0xf0;
1134
1135 /* Type checking must be done elsewhere */
1136 return addr | bridge->driver->masks[type].mask;
1137}
1138
65c25aad 1139/* The intel i965 automatically initializes the agp aperture during POST.
c41e0deb
EA		 1140 * Use the memory already set aside for in the GTT.
1141 */
65c25aad
EA		 1142static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1143{
1144 int page_order;
1145 struct aper_size_info_fixed *size;
1146 int num_entries;
1147 u32 temp;
4e8b6e25 1148 int gtt_offset, gtt_size;
65c25aad
EA		 1149
1150 size = agp_bridge->current_size;
1151 page_order = size->page_order;
1152 num_entries = size->num_entries;
1153 agp_bridge->gatt_table_real = NULL;
1154
c4ca8817 1155 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
65c25aad
EA		 1156
1157 temp &= 0xfff00000;
65c25aad 1158
4e8b6e25
ZW		 1159 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_HB)
1160 gtt_offset = gtt_size = MB(2);
1161 else
1162 gtt_offset = gtt_size = KB(512);
1163
1164 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
65c25aad 1165
4e8b6e25
ZW		 1166 if (!intel_private.gtt)
1167 return -ENOMEM;
65c25aad 1168
4e8b6e25 1169 intel_private.registers = ioremap(temp, 128 * 4096);
5bdbc7dc
ST		 1170 if (!intel_private.registers) {
1171 iounmap(intel_private.gtt);
1172 return -ENOMEM;
1173 }
65c25aad 1174
c4ca8817 1175 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
65c25aad
EA		 1176 global_cache_flush(); /* FIXME: ? */
1177
1178 /* we have to call this as early as possible after the MMIO base address is known */
1179 intel_i830_init_gtt_entries();
1180
1181 agp_bridge->gatt_table = NULL;
1182
1183 agp_bridge->gatt_bus_addr = temp;
1184
1185 return 0;
1186}
1187
1da177e4
LT		 1188
1189static int intel_fetch_size(void)
1190{
1191 int i;
1192 u16 temp;
1193 struct aper_size_info_16 *values;
1194
1195 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1196 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1197
1198 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1199 if (temp == values[i].size_value) {
1200 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1201 agp_bridge->aperture_size_idx = i;
1202 return values[i].size;
1203 }
1204 }
1205
1206 return 0;
1207}
1208
1209static int __intel_8xx_fetch_size(u8 temp)
1210{
1211 int i;
1212 struct aper_size_info_8 *values;
1213
1214 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1215
1216 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1217 if (temp == values[i].size_value) {
1218 agp_bridge->previous_size =
1219 agp_bridge->current_size = (void *) (values + i);
1220 agp_bridge->aperture_size_idx = i;
1221 return values[i].size;
1222 }
1223 }
1224 return 0;
1225}
1226
1227static int intel_8xx_fetch_size(void)
1228{
1229 u8 temp;
1230
1231 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1232 return __intel_8xx_fetch_size(temp);
1233}
1234
1235static int intel_815_fetch_size(void)
1236{
1237 u8 temp;
1238
1239 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1240 * one non-reserved bit, so mask the others out ... */
1241 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1242 temp &= (1 << 3);
1243
1244 return __intel_8xx_fetch_size(temp);
1245}
1246
1247static void intel_tlbflush(struct agp_memory *mem)
1248{
1249 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1250 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1251}
1252
1253
1254static void intel_8xx_tlbflush(struct agp_memory *mem)
1255{
1256 u32 temp;
1257 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1258 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1259 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1260 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1261}
1262
1263
1264static void intel_cleanup(void)
1265{
1266 u16 temp;
1267 struct aper_size_info_16 *previous_size;
1268
1269 previous_size = A_SIZE_16(agp_bridge->previous_size);
1270 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1271 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1272 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1273}
1274
1275
1276static void intel_8xx_cleanup(void)
1277{
1278 u16 temp;
1279 struct aper_size_info_8 *previous_size;
1280
1281 previous_size = A_SIZE_8(agp_bridge->previous_size);
1282 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1283 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1284 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1285}
1286
1287
1288static int intel_configure(void)
1289{
1290 u32 temp;
1291 u16 temp2;
1292 struct aper_size_info_16 *current_size;
1293
1294 current_size = A_SIZE_16(agp_bridge->current_size);
1295
1296 /* aperture size */
1297 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1298
1299 /* address to map to */
1300 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1301 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1302
1303 /* attbase - aperture base */
1304 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1305
1306 /* agpctrl */
1307 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1308
1309 /* paccfg/nbxcfg */
1310 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1311 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1312 (temp2 & ~(1 << 10)) | (1 << 9));
1313 /* clear any possible error conditions */
1314 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1315 return 0;
1316}
1317
1318static int intel_815_configure(void)
1319{
1320 u32 temp, addr;
1321 u8 temp2;
1322 struct aper_size_info_8 *current_size;
1323
1324 /* attbase - aperture base */
1325 /* the Intel 815 chipset spec. says that bits 29-31 in the
1326 * ATTBASE register are reserved -> try not to write them */
1327 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
f011ae74 1328 printk(KERN_EMERG PFX "gatt bus addr too high");
1da177e4
LT		 1329 return -EINVAL;
1330 }
1331
1332 current_size = A_SIZE_8(agp_bridge->current_size);
1333
1334 /* aperture size */
1335 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1336 current_size->size_value);
1337
1338 /* address to map to */
1339 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1340 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1341
1342 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1343 addr &= INTEL_815_ATTBASE_MASK;
1344 addr |= agp_bridge->gatt_bus_addr;
1345 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1346
1347 /* agpctrl */
1348 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1349
1350 /* apcont */
1351 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1352 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1353
1354 /* clear any possible error conditions */
1355 /* Oddness : this chipset seems to have no ERRSTS register ! */
1356 return 0;
1357}
1358
1359static void intel_820_tlbflush(struct agp_memory *mem)
1360{
1361 return;
1362}
1363
1364static void intel_820_cleanup(void)
1365{
1366 u8 temp;
1367 struct aper_size_info_8 *previous_size;
1368
1369 previous_size = A_SIZE_8(agp_bridge->previous_size);
1370 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1371 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1372 temp & ~(1 << 1));
1373 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1374 previous_size->size_value);
1375}
1376
1377
1378static int intel_820_configure(void)
1379{
1380 u32 temp;
1381 u8 temp2;
1382 struct aper_size_info_8 *current_size;
1383
1384 current_size = A_SIZE_8(agp_bridge->current_size);
1385
1386 /* aperture size */
1387 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1388
1389 /* address to map to */
1390 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1391 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1392
1393 /* attbase - aperture base */
1394 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1395
1396 /* agpctrl */
1397 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1398
1399 /* global enable aperture access */
1400 /* This flag is not accessed through MCHCFG register as in */
1401 /* i850 chipset. */
1402 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1403 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1404 /* clear any possible AGP-related error conditions */
1405 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1406 return 0;
1407}
1408
1409static int intel_840_configure(void)
1410{
1411 u32 temp;
1412 u16 temp2;
1413 struct aper_size_info_8 *current_size;
1414
1415 current_size = A_SIZE_8(agp_bridge->current_size);
1416
1417 /* aperture size */
1418 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1419
1420 /* address to map to */
1421 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1422 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1423
1424 /* attbase - aperture base */
1425 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1426
1427 /* agpctrl */
1428 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1429
1430 /* mcgcfg */
1431 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1432 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1433 /* clear any possible error conditions */
1434 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1435 return 0;
1436}
1437
1438static int intel_845_configure(void)
1439{
1440 u32 temp;
1441 u8 temp2;
1442 struct aper_size_info_8 *current_size;
1443
1444 current_size = A_SIZE_8(agp_bridge->current_size);
1445
1446 /* aperture size */
1447 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1448
b0825488
MG		 1449 if (agp_bridge->apbase_config != 0) {
1450 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1451 agp_bridge->apbase_config);
1452 } else {
1453 /* address to map to */
1454 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1455 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1456 agp_bridge->apbase_config = temp;
1457 }
1da177e4
LT		 1458
1459 /* attbase - aperture base */
1460 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1461
1462 /* agpctrl */
1463 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1464
1465 /* agpm */
1466 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1467 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1468 /* clear any possible error conditions */
1469 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
2162e6a2
DA		 1470
1471 intel_i830_setup_flush();
1da177e4
LT		 1472 return 0;
1473}
1474
1475static int intel_850_configure(void)
1476{
1477 u32 temp;
1478 u16 temp2;
1479 struct aper_size_info_8 *current_size;
1480
1481 current_size = A_SIZE_8(agp_bridge->current_size);
1482
1483 /* aperture size */
1484 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1485
1486 /* address to map to */
1487 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1488 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1489
1490 /* attbase - aperture base */
1491 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1492
1493 /* agpctrl */
1494 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1495
1496 /* mcgcfg */
1497 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1498 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1499 /* clear any possible AGP-related error conditions */
1500 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1501 return 0;
1502}
1503
1504static int intel_860_configure(void)
1505{
1506 u32 temp;
1507 u16 temp2;
1508 struct aper_size_info_8 *current_size;
1509
1510 current_size = A_SIZE_8(agp_bridge->current_size);
1511
1512 /* aperture size */
1513 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1514
1515 /* address to map to */
1516 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1517 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1518
1519 /* attbase - aperture base */
1520 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1521
1522 /* agpctrl */
1523 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1524
1525 /* mcgcfg */
1526 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1527 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1528 /* clear any possible AGP-related error conditions */
1529 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1530 return 0;
1531}
1532
1533static int intel_830mp_configure(void)
1534{
1535 u32 temp;
1536 u16 temp2;
1537 struct aper_size_info_8 *current_size;
1538
1539 current_size = A_SIZE_8(agp_bridge->current_size);
1540
1541 /* aperture size */
1542 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1543
1544 /* address to map to */
1545 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1546 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1547
1548 /* attbase - aperture base */
1549 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1550
1551 /* agpctrl */
1552 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1553
1554 /* gmch */
1555 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1556 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1557 /* clear any possible AGP-related error conditions */
1558 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1559 return 0;
1560}
1561
1562static int intel_7505_configure(void)
1563{
1564 u32 temp;
1565 u16 temp2;
1566 struct aper_size_info_8 *current_size;
1567
1568 current_size = A_SIZE_8(agp_bridge->current_size);
1569
1570 /* aperture size */
1571 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1572
1573 /* address to map to */
1574 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1575 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1576
1577 /* attbase - aperture base */
1578 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1579
1580 /* agpctrl */
1581 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1582
1583 /* mchcfg */
1584 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1585 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1586
1587 return 0;
1588}
1589
1590/* Setup function */
e5524f35 1591static const struct gatt_mask intel_generic_masks[] =
1da177e4
LT		 1592{
1593 {.mask = 0x00000017, .type = 0}
1594};
1595
e5524f35 1596static const struct aper_size_info_8 intel_815_sizes[2] =
1da177e4
LT		 1597{
1598 {64, 16384, 4, 0},
1599 {32, 8192, 3, 8},
1600};
1601
e5524f35 1602static const struct aper_size_info_8 intel_8xx_sizes[7] =
1da177e4
LT		 1603{
1604 {256, 65536, 6, 0},
1605 {128, 32768, 5, 32},
1606 {64, 16384, 4, 48},
1607 {32, 8192, 3, 56},
1608 {16, 4096, 2, 60},
1609 {8, 2048, 1, 62},
1610 {4, 1024, 0, 63}
1611};
1612
e5524f35 1613static const struct aper_size_info_16 intel_generic_sizes[7] =
1da177e4
LT		 1614{
1615 {256, 65536, 6, 0},
1616 {128, 32768, 5, 32},
1617 {64, 16384, 4, 48},
1618 {32, 8192, 3, 56},
1619 {16, 4096, 2, 60},
1620 {8, 2048, 1, 62},
1621 {4, 1024, 0, 63}
1622};
1623
e5524f35 1624static const struct aper_size_info_8 intel_830mp_sizes[4] =
1da177e4
LT		 1625{
1626 {256, 65536, 6, 0},
1627 {128, 32768, 5, 32},
1628 {64, 16384, 4, 48},
1629 {32, 8192, 3, 56}
1630};
1631
e5524f35 1632static const struct agp_bridge_driver intel_generic_driver = {
1da177e4
LT		 1633 .owner = THIS_MODULE,
1634 .aperture_sizes = intel_generic_sizes,
1635 .size_type = U16_APER_SIZE,
1636 .num_aperture_sizes = 7,
1637 .configure = intel_configure,
1638 .fetch_size = intel_fetch_size,
1639 .cleanup = intel_cleanup,
1640 .tlb_flush = intel_tlbflush,
1641 .mask_memory = agp_generic_mask_memory,
1642 .masks = intel_generic_masks,
1643 .agp_enable = agp_generic_enable,
1644 .cache_flush = global_cache_flush,
1645 .create_gatt_table = agp_generic_create_gatt_table,
1646 .free_gatt_table = agp_generic_free_gatt_table,
1647 .insert_memory = agp_generic_insert_memory,
1648 .remove_memory = agp_generic_remove_memory,
1649 .alloc_by_type = agp_generic_alloc_by_type,
1650 .free_by_type = agp_generic_free_by_type,
1651 .agp_alloc_page = agp_generic_alloc_page,
1652 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1653 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1654};
1655
e5524f35 1656static const struct agp_bridge_driver intel_810_driver = {
1da177e4
LT		 1657 .owner = THIS_MODULE,
1658 .aperture_sizes = intel_i810_sizes,
1659 .size_type = FIXED_APER_SIZE,
1660 .num_aperture_sizes = 2,
1661 .needs_scratch_page = TRUE,
1662 .configure = intel_i810_configure,
1663 .fetch_size = intel_i810_fetch_size,
1664 .cleanup = intel_i810_cleanup,
1665 .tlb_flush = intel_i810_tlbflush,
1666 .mask_memory = intel_i810_mask_memory,
1667 .masks = intel_i810_masks,
1668 .agp_enable = intel_i810_agp_enable,
1669 .cache_flush = global_cache_flush,
1670 .create_gatt_table = agp_generic_create_gatt_table,
1671 .free_gatt_table = agp_generic_free_gatt_table,
1672 .insert_memory = intel_i810_insert_entries,
1673 .remove_memory = intel_i810_remove_entries,
1674 .alloc_by_type = intel_i810_alloc_by_type,
1675 .free_by_type = intel_i810_free_by_type,
1676 .agp_alloc_page = agp_generic_alloc_page,
1677 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1678 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1679};
1680
e5524f35 1681static const struct agp_bridge_driver intel_815_driver = {
1da177e4
LT		 1682 .owner = THIS_MODULE,
1683 .aperture_sizes = intel_815_sizes,
1684 .size_type = U8_APER_SIZE,
1685 .num_aperture_sizes = 2,
1686 .configure = intel_815_configure,
1687 .fetch_size = intel_815_fetch_size,
1688 .cleanup = intel_8xx_cleanup,
1689 .tlb_flush = intel_8xx_tlbflush,
1690 .mask_memory = agp_generic_mask_memory,
1691 .masks = intel_generic_masks,
1692 .agp_enable = agp_generic_enable,
1693 .cache_flush = global_cache_flush,
1694 .create_gatt_table = agp_generic_create_gatt_table,
1695 .free_gatt_table = agp_generic_free_gatt_table,
1696 .insert_memory = agp_generic_insert_memory,
1697 .remove_memory = agp_generic_remove_memory,
1698 .alloc_by_type = agp_generic_alloc_by_type,
1699 .free_by_type = agp_generic_free_by_type,
1700 .agp_alloc_page = agp_generic_alloc_page,
1701 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1702 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1703};
1704
e5524f35 1705static const struct agp_bridge_driver intel_830_driver = {
1da177e4
LT		 1706 .owner = THIS_MODULE,
1707 .aperture_sizes = intel_i830_sizes,
1708 .size_type = FIXED_APER_SIZE,
c14635eb 1709 .num_aperture_sizes = 4,
1da177e4
LT		 1710 .needs_scratch_page = TRUE,
1711 .configure = intel_i830_configure,
1712 .fetch_size = intel_i830_fetch_size,
1713 .cleanup = intel_i830_cleanup,
1714 .tlb_flush = intel_i810_tlbflush,
1715 .mask_memory = intel_i810_mask_memory,
1716 .masks = intel_i810_masks,
1717 .agp_enable = intel_i810_agp_enable,
1718 .cache_flush = global_cache_flush,
1719 .create_gatt_table = intel_i830_create_gatt_table,
1720 .free_gatt_table = intel_i830_free_gatt_table,
1721 .insert_memory = intel_i830_insert_entries,
1722 .remove_memory = intel_i830_remove_entries,
1723 .alloc_by_type = intel_i830_alloc_by_type,
1724 .free_by_type = intel_i810_free_by_type,
1725 .agp_alloc_page = agp_generic_alloc_page,
1726 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1727 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2162e6a2 1728 .chipset_flush = intel_i830_chipset_flush,
1da177e4
LT		 1729};
1730
e5524f35 1731static const struct agp_bridge_driver intel_820_driver = {
1da177e4
LT		 1732 .owner = THIS_MODULE,
1733 .aperture_sizes = intel_8xx_sizes,
1734 .size_type = U8_APER_SIZE,
1735 .num_aperture_sizes = 7,
1736 .configure = intel_820_configure,
1737 .fetch_size = intel_8xx_fetch_size,
1738 .cleanup = intel_820_cleanup,
1739 .tlb_flush = intel_820_tlbflush,
1740 .mask_memory = agp_generic_mask_memory,
1741 .masks = intel_generic_masks,
1742 .agp_enable = agp_generic_enable,
1743 .cache_flush = global_cache_flush,
1744 .create_gatt_table = agp_generic_create_gatt_table,
1745 .free_gatt_table = agp_generic_free_gatt_table,
1746 .insert_memory = agp_generic_insert_memory,
1747 .remove_memory = agp_generic_remove_memory,
1748 .alloc_by_type = agp_generic_alloc_by_type,
1749 .free_by_type = agp_generic_free_by_type,
1750 .agp_alloc_page = agp_generic_alloc_page,
1751 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1752 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1753};
1754
e5524f35 1755static const struct agp_bridge_driver intel_830mp_driver = {
1da177e4
LT		 1756 .owner = THIS_MODULE,
1757 .aperture_sizes = intel_830mp_sizes,
1758 .size_type = U8_APER_SIZE,
1759 .num_aperture_sizes = 4,
1760 .configure = intel_830mp_configure,
1761 .fetch_size = intel_8xx_fetch_size,
1762 .cleanup = intel_8xx_cleanup,
1763 .tlb_flush = intel_8xx_tlbflush,
1764 .mask_memory = agp_generic_mask_memory,
1765 .masks = intel_generic_masks,
1766 .agp_enable = agp_generic_enable,
1767 .cache_flush = global_cache_flush,
1768 .create_gatt_table = agp_generic_create_gatt_table,
1769 .free_gatt_table = agp_generic_free_gatt_table,
1770 .insert_memory = agp_generic_insert_memory,
1771 .remove_memory = agp_generic_remove_memory,
1772 .alloc_by_type = agp_generic_alloc_by_type,
1773 .free_by_type = agp_generic_free_by_type,
1774 .agp_alloc_page = agp_generic_alloc_page,
1775 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1776 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1777};
1778
e5524f35 1779static const struct agp_bridge_driver intel_840_driver = {
1da177e4
LT		 1780 .owner = THIS_MODULE,
1781 .aperture_sizes = intel_8xx_sizes,
1782 .size_type = U8_APER_SIZE,
1783 .num_aperture_sizes = 7,
1784 .configure = intel_840_configure,
1785 .fetch_size = intel_8xx_fetch_size,
1786 .cleanup = intel_8xx_cleanup,
1787 .tlb_flush = intel_8xx_tlbflush,
1788 .mask_memory = agp_generic_mask_memory,
1789 .masks = intel_generic_masks,
1790 .agp_enable = agp_generic_enable,
1791 .cache_flush = global_cache_flush,
1792 .create_gatt_table = agp_generic_create_gatt_table,
1793 .free_gatt_table = agp_generic_free_gatt_table,
1794 .insert_memory = agp_generic_insert_memory,
1795 .remove_memory = agp_generic_remove_memory,
1796 .alloc_by_type = agp_generic_alloc_by_type,
1797 .free_by_type = agp_generic_free_by_type,
1798 .agp_alloc_page = agp_generic_alloc_page,
1799 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1800 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1801};
1802
e5524f35 1803static const struct agp_bridge_driver intel_845_driver = {
1da177e4
LT		 1804 .owner = THIS_MODULE,
1805 .aperture_sizes = intel_8xx_sizes,
1806 .size_type = U8_APER_SIZE,
1807 .num_aperture_sizes = 7,
1808 .configure = intel_845_configure,
1809 .fetch_size = intel_8xx_fetch_size,
1810 .cleanup = intel_8xx_cleanup,
1811 .tlb_flush = intel_8xx_tlbflush,
1812 .mask_memory = agp_generic_mask_memory,
1813 .masks = intel_generic_masks,
1814 .agp_enable = agp_generic_enable,
1815 .cache_flush = global_cache_flush,
1816 .create_gatt_table = agp_generic_create_gatt_table,
1817 .free_gatt_table = agp_generic_free_gatt_table,
1818 .insert_memory = agp_generic_insert_memory,
1819 .remove_memory = agp_generic_remove_memory,
1820 .alloc_by_type = agp_generic_alloc_by_type,
1821 .free_by_type = agp_generic_free_by_type,
1822 .agp_alloc_page = agp_generic_alloc_page,
1823 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1824 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2162e6a2 1825 .chipset_flush = intel_i830_chipset_flush,
1da177e4
LT		 1826};
1827
e5524f35 1828static const struct agp_bridge_driver intel_850_driver = {
1da177e4
LT		 1829 .owner = THIS_MODULE,
1830 .aperture_sizes = intel_8xx_sizes,
1831 .size_type = U8_APER_SIZE,
1832 .num_aperture_sizes = 7,
1833 .configure = intel_850_configure,
1834 .fetch_size = intel_8xx_fetch_size,
1835 .cleanup = intel_8xx_cleanup,
1836 .tlb_flush = intel_8xx_tlbflush,
1837 .mask_memory = agp_generic_mask_memory,
1838 .masks = intel_generic_masks,
1839 .agp_enable = agp_generic_enable,
1840 .cache_flush = global_cache_flush,
1841 .create_gatt_table = agp_generic_create_gatt_table,
1842 .free_gatt_table = agp_generic_free_gatt_table,
1843 .insert_memory = agp_generic_insert_memory,
1844 .remove_memory = agp_generic_remove_memory,
1845 .alloc_by_type = agp_generic_alloc_by_type,
1846 .free_by_type = agp_generic_free_by_type,
1847 .agp_alloc_page = agp_generic_alloc_page,
1848 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1849 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1850};
1851
e5524f35 1852static const struct agp_bridge_driver intel_860_driver = {
1da177e4
LT		 1853 .owner = THIS_MODULE,
1854 .aperture_sizes = intel_8xx_sizes,
1855 .size_type = U8_APER_SIZE,
1856 .num_aperture_sizes = 7,
1857 .configure = intel_860_configure,
1858 .fetch_size = intel_8xx_fetch_size,
1859 .cleanup = intel_8xx_cleanup,
1860 .tlb_flush = intel_8xx_tlbflush,
1861 .mask_memory = agp_generic_mask_memory,
1862 .masks = intel_generic_masks,
1863 .agp_enable = agp_generic_enable,
1864 .cache_flush = global_cache_flush,
1865 .create_gatt_table = agp_generic_create_gatt_table,
1866 .free_gatt_table = agp_generic_free_gatt_table,
1867 .insert_memory = agp_generic_insert_memory,
1868 .remove_memory = agp_generic_remove_memory,
1869 .alloc_by_type = agp_generic_alloc_by_type,
1870 .free_by_type = agp_generic_free_by_type,
1871 .agp_alloc_page = agp_generic_alloc_page,
1872 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1873 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1874};
1875
e5524f35 1876static const struct agp_bridge_driver intel_915_driver = {
1da177e4
LT		 1877 .owner = THIS_MODULE,
1878 .aperture_sizes = intel_i830_sizes,
1879 .size_type = FIXED_APER_SIZE,
c14635eb 1880 .num_aperture_sizes = 4,
1da177e4
LT		 1881 .needs_scratch_page = TRUE,
1882 .configure = intel_i915_configure,
c41e0deb 1883 .fetch_size = intel_i9xx_fetch_size,
1da177e4
LT		 1884 .cleanup = intel_i915_cleanup,
1885 .tlb_flush = intel_i810_tlbflush,
1886 .mask_memory = intel_i810_mask_memory,
1887 .masks = intel_i810_masks,
1888 .agp_enable = intel_i810_agp_enable,
1889 .cache_flush = global_cache_flush,
1890 .create_gatt_table = intel_i915_create_gatt_table,
1891 .free_gatt_table = intel_i830_free_gatt_table,
1892 .insert_memory = intel_i915_insert_entries,
1893 .remove_memory = intel_i915_remove_entries,
1894 .alloc_by_type = intel_i830_alloc_by_type,
1895 .free_by_type = intel_i810_free_by_type,
1896 .agp_alloc_page = agp_generic_alloc_page,
1897 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1898 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
6c00a61e 1899 .chipset_flush = intel_i915_chipset_flush,
1da177e4
LT		 1900};
1901
e5524f35 1902static const struct agp_bridge_driver intel_i965_driver = {
65c25aad
EA		 1903 .owner = THIS_MODULE,
1904 .aperture_sizes = intel_i830_sizes,
1905 .size_type = FIXED_APER_SIZE,
1906 .num_aperture_sizes = 4,
1907 .needs_scratch_page = TRUE,
1908 .configure = intel_i915_configure,
c41e0deb 1909 .fetch_size = intel_i9xx_fetch_size,
65c25aad
EA		 1910 .cleanup = intel_i915_cleanup,
1911 .tlb_flush = intel_i810_tlbflush,
7d915a38 1912 .mask_memory = intel_i965_mask_memory,
65c25aad
EA		 1913 .masks = intel_i810_masks,
1914 .agp_enable = intel_i810_agp_enable,
1915 .cache_flush = global_cache_flush,
1916 .create_gatt_table = intel_i965_create_gatt_table,
1917 .free_gatt_table = intel_i830_free_gatt_table,
1918 .insert_memory = intel_i915_insert_entries,
1919 .remove_memory = intel_i915_remove_entries,
1920 .alloc_by_type = intel_i830_alloc_by_type,
1921 .free_by_type = intel_i810_free_by_type,
1922 .agp_alloc_page = agp_generic_alloc_page,
1923 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1924 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
6c00a61e 1925 .chipset_flush = intel_i915_chipset_flush,
65c25aad 1926};
1da177e4 1927
e5524f35 1928static const struct agp_bridge_driver intel_7505_driver = {
1da177e4
LT		 1929 .owner = THIS_MODULE,
1930 .aperture_sizes = intel_8xx_sizes,
1931 .size_type = U8_APER_SIZE,
1932 .num_aperture_sizes = 7,
1933 .configure = intel_7505_configure,
1934 .fetch_size = intel_8xx_fetch_size,
1935 .cleanup = intel_8xx_cleanup,
1936 .tlb_flush = intel_8xx_tlbflush,
1937 .mask_memory = agp_generic_mask_memory,
1938 .masks = intel_generic_masks,
1939 .agp_enable = agp_generic_enable,
1940 .cache_flush = global_cache_flush,
1941 .create_gatt_table = agp_generic_create_gatt_table,
1942 .free_gatt_table = agp_generic_free_gatt_table,
1943 .insert_memory = agp_generic_insert_memory,
1944 .remove_memory = agp_generic_remove_memory,
1945 .alloc_by_type = agp_generic_alloc_by_type,
1946 .free_by_type = agp_generic_free_by_type,
1947 .agp_alloc_page = agp_generic_alloc_page,
1948 .agp_destroy_page = agp_generic_destroy_page,
a030ce44 1949 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1da177e4
LT		 1950};
1951
874808c6
WZ		 1952static const struct agp_bridge_driver intel_g33_driver = {
1953 .owner = THIS_MODULE,
1954 .aperture_sizes = intel_i830_sizes,
1955 .size_type = FIXED_APER_SIZE,
1956 .num_aperture_sizes = 4,
1957 .needs_scratch_page = TRUE,
1958 .configure = intel_i915_configure,
1959 .fetch_size = intel_i9xx_fetch_size,
1960 .cleanup = intel_i915_cleanup,
1961 .tlb_flush = intel_i810_tlbflush,
1962 .mask_memory = intel_i965_mask_memory,
1963 .masks = intel_i810_masks,
1964 .agp_enable = intel_i810_agp_enable,
1965 .cache_flush = global_cache_flush,
1966 .create_gatt_table = intel_i915_create_gatt_table,
1967 .free_gatt_table = intel_i830_free_gatt_table,
1968 .insert_memory = intel_i915_insert_entries,
1969 .remove_memory = intel_i915_remove_entries,
1970 .alloc_by_type = intel_i830_alloc_by_type,
1971 .free_by_type = intel_i810_free_by_type,
1972 .agp_alloc_page = agp_generic_alloc_page,
1973 .agp_destroy_page = agp_generic_destroy_page,
1974 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
6c00a61e 1975 .chipset_flush = intel_i915_chipset_flush,
874808c6 1976};
1da177e4 1977
9614ece1 1978static int find_gmch(u16 device)
1da177e4 1979{
9614ece1 1980 struct pci_dev *gmch_device;
1da177e4 1981
9614ece1
WZ		 1982 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1983 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1984 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
f011ae74 1985 device, gmch_device);
1da177e4
LT		 1986 }
1987
9614ece1 1988 if (!gmch_device)
1da177e4
LT		 1989 return 0;
1990
9614ece1 1991 intel_private.pcidev = gmch_device;
1da177e4
LT		 1992 return 1;
1993}
1994
9614ece1
WZ		 1995/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
1996 * driver and gmch_driver must be non-null, and find_gmch will determine
1997 * which one should be used if a gmch_chip_id is present.
1998 */
1999static const struct intel_driver_description {
2000 unsigned int chip_id;
2001 unsigned int gmch_chip_id;
88889851 2002 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
9614ece1
WZ		 2003 char *name;
2004 const struct agp_bridge_driver *driver;
2005 const struct agp_bridge_driver *gmch_driver;
2006} intel_agp_chipsets[] = {
88889851
WZ		 2007 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2008 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2009 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2010 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
9614ece1 2011 NULL, &intel_810_driver },
88889851 2012 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
9614ece1 2013 NULL, &intel_810_driver },
88889851 2014 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
9614ece1 2015 NULL, &intel_810_driver },
88889851
WZ		 2016 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2017 &intel_815_driver, &intel_810_driver },
2018 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2019 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2020 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
9614ece1 2021 &intel_830mp_driver, &intel_830_driver },
88889851
WZ		 2022 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2023 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2024 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
9614ece1 2025 &intel_845_driver, &intel_830_driver },
88889851
WZ		 2026 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2027 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2028 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
9614ece1 2029 &intel_845_driver, &intel_830_driver },
88889851
WZ		 2030 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2031 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
9614ece1 2032 &intel_845_driver, &intel_830_driver },
88889851 2033 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
e914a36a
CM		 2034 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2035 NULL, &intel_915_driver },
88889851 2036 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
47d46379 2037 NULL, &intel_915_driver },
88889851 2038 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
47d46379 2039 NULL, &intel_915_driver },
88889851 2040 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
47d46379 2041 NULL, &intel_915_driver },
dde47876 2042 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
47d46379 2043 NULL, &intel_915_driver },
dde47876 2044 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
47d46379 2045 NULL, &intel_915_driver },
88889851 2046 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
47d46379 2047 NULL, &intel_i965_driver },
9119f85a 2048 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
47d46379 2049 NULL, &intel_i965_driver },
88889851 2050 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
47d46379 2051 NULL, &intel_i965_driver },
88889851 2052 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
47d46379 2053 NULL, &intel_i965_driver },
dde47876 2054 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
47d46379 2055 NULL, &intel_i965_driver },
dde47876 2056 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
47d46379 2057 NULL, &intel_i965_driver },
88889851
WZ		 2058 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2059 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2060 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
47d46379 2061 NULL, &intel_g33_driver },
88889851 2062 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
47d46379 2063 NULL, &intel_g33_driver },
88889851 2064 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
47d46379 2065 NULL, &intel_g33_driver },
4e8b6e25
ZW		 2066 { PCI_DEVICE_ID_INTEL_IGD_HB, PCI_DEVICE_ID_INTEL_IGD_IG, 0,
2067 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
88889851 2068 { 0, 0, 0, NULL, NULL, NULL }
9614ece1
WZ		 2069};
2070
1da177e4
LT		 2071static int __devinit agp_intel_probe(struct pci_dev *pdev,
2072 const struct pci_device_id *ent)
2073{
2074 struct agp_bridge_data *bridge;
1da177e4
LT		 2075 u8 cap_ptr = 0;
2076 struct resource *r;
9614ece1 2077 int i;
1da177e4
LT		 2078
2079 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2080
2081 bridge = agp_alloc_bridge();
2082 if (!bridge)
2083 return -ENOMEM;
2084
9614ece1
WZ		 2085 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2086 /* In case that multiple models of gfx chip may
2087 stand on same host bridge type, this can be
2088 sure we detect the right IGD. */
88889851
WZ		 2089 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2090 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2091 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2092 bridge->driver =
2093 intel_agp_chipsets[i].gmch_driver;
2094 break;
2095 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2096 continue;
2097 } else {
2098 bridge->driver = intel_agp_chipsets[i].driver;
2099 break;
2100 }
2101 }
9614ece1
WZ		 2102 }
2103
2104 if (intel_agp_chipsets[i].name == NULL) {
1da177e4 2105 if (cap_ptr)
9614ece1 2106 printk(KERN_WARNING PFX "Unsupported Intel chipset"
f011ae74 2107 "(device id: %04x)\n", pdev->device);
9614ece1
WZ		 2108 agp_put_bridge(bridge);
2109 return -ENODEV;
2110 }
2111
9614ece1 2112 if (bridge->driver == NULL) {
47d46379
WZ		 2113 /* bridge has no AGP and no IGD detected */
2114 if (cap_ptr)
2115 printk(KERN_WARNING PFX "Failed to find bridge device "
2116 "(chip_id: %04x)\n",
2117 intel_agp_chipsets[i].gmch_chip_id);
1da177e4
LT		 2118 agp_put_bridge(bridge);
2119 return -ENODEV;
f011ae74 2120 }
1da177e4
LT		 2121
2122 bridge->dev = pdev;
2123 bridge->capndx = cap_ptr;
c4ca8817 2124 bridge->dev_private_data = &intel_private;
1da177e4 2125
9614ece1
WZ		 2126 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
2127 intel_agp_chipsets[i].name);
1da177e4
LT		 2128
2129 /*
2130 * The following fixes the case where the BIOS has "forgotten" to
2131 * provide an address range for the GART.
2132 * 20030610 - hamish@zot.org
2133 */
2134 r = &pdev->resource[0];
2135 if (!r->start && r->end) {
6a92a4e0 2136 if (pci_assign_resource(pdev, 0)) {
1da177e4
LT		 2137 printk(KERN_ERR PFX "could not assign resource 0\n");
2138 agp_put_bridge(bridge);
2139 return -ENODEV;
2140 }
2141 }
2142
2143 /*
2144 * If the device has not been properly setup, the following will catch
2145 * the problem and should stop the system from crashing.
2146 * 20030610 - hamish@zot.org
2147 */
2148 if (pci_enable_device(pdev)) {
2149 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
2150 agp_put_bridge(bridge);
2151 return -ENODEV;
2152 }
2153
2154 /* Fill in the mode register */
2155 if (cap_ptr) {
2156 pci_read_config_dword(pdev,
2157 bridge->capndx+PCI_AGP_STATUS,
2158 &bridge->mode);
2159 }
2160
2161 pci_set_drvdata(pdev, bridge);
2162 return agp_add_bridge(bridge);
1da177e4
LT		 2163}
2164
2165static void __devexit agp_intel_remove(struct pci_dev *pdev)
2166{
2167 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2168
2169 agp_remove_bridge(bridge);
2170
c4ca8817
WZ		 2171 if (intel_private.pcidev)
2172 pci_dev_put(intel_private.pcidev);
1da177e4
LT		 2173
2174 agp_put_bridge(bridge);
2175}
2176
85be7d60 2177#ifdef CONFIG_PM
1da177e4
LT		 2178static int agp_intel_resume(struct pci_dev *pdev)
2179{
2180 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2181
2182 pci_restore_state(pdev);
2183
4b95320f
WZ		 2184 /* We should restore our graphics device's config space,
2185 * as host bridge (00:00) resumes before graphics device (02:00),
2186 * then our access to its pci space can work right.
2187 */
c4ca8817
WZ		 2188 if (intel_private.pcidev)
2189 pci_restore_state(intel_private.pcidev);
4b95320f 2190
1da177e4
LT		 2191 if (bridge->driver == &intel_generic_driver)
2192 intel_configure();
2193 else if (bridge->driver == &intel_850_driver)
2194 intel_850_configure();
2195 else if (bridge->driver == &intel_845_driver)
2196 intel_845_configure();
2197 else if (bridge->driver == &intel_830mp_driver)
2198 intel_830mp_configure();
2199 else if (bridge->driver == &intel_915_driver)
2200 intel_i915_configure();
2201 else if (bridge->driver == &intel_830_driver)
2202 intel_i830_configure();
2203 else if (bridge->driver == &intel_810_driver)
2204 intel_i810_configure();
08da3f41
DJ		 2205 else if (bridge->driver == &intel_i965_driver)
2206 intel_i915_configure();
1da177e4
LT		 2207
2208 return 0;
2209}
85be7d60 2210#endif
1da177e4
LT		 2211
2212static struct pci_device_id agp_intel_pci_table[] = {
2213#define ID(x) \
2214 { \
2215 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2216 .class_mask = ~0, \
2217 .vendor = PCI_VENDOR_ID_INTEL, \
2218 .device = x, \
2219 .subvendor = PCI_ANY_ID, \
2220 .subdevice = PCI_ANY_ID, \
2221 }
2222 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2223 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2224 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2225 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2226 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2227 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2228 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2229 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2230 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2231 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2232 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2233 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2234 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2235 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2236 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2237 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2238 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2239 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2240 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2241 ID(PCI_DEVICE_ID_INTEL_7505_0),
2242 ID(PCI_DEVICE_ID_INTEL_7205_0),
e914a36a 2243 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
1da177e4
LT		 2244 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2245 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
d0de98fa 2246 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
3b0e8ead 2247 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
dde47876 2248 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
65c25aad 2249 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
9119f85a 2250 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
65c25aad
EA		 2251 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2252 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
4598af33 2253 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
dde47876 2254 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
874808c6
WZ		 2255 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2256 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2257 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
4e8b6e25 2258 ID(PCI_DEVICE_ID_INTEL_IGD_HB),
1da177e4
LT		 2259 { }
2260};
2261
2262MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2263
2264static struct pci_driver agp_intel_pci_driver = {
2265 .name = "agpgart-intel",
2266 .id_table = agp_intel_pci_table,
2267 .probe = agp_intel_probe,
2268 .remove = __devexit_p(agp_intel_remove),
85be7d60 2269#ifdef CONFIG_PM
1da177e4 2270 .resume = agp_intel_resume,
85be7d60 2271#endif
1da177e4
LT		 2272};
2273
2274static int __init agp_intel_init(void)
2275{
2276 if (agp_off)
2277 return -EINVAL;
2278 return pci_register_driver(&agp_intel_pci_driver);
2279}
2280
2281static void __exit agp_intel_cleanup(void)
2282{
2283 pci_unregister_driver(&agp_intel_pci_driver);
2284}
2285
2286module_init(agp_intel_init);
2287module_exit(agp_intel_cleanup);
2288
2289MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2290MODULE_LICENSE("GPL and additional rights");
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