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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Intel AGPGART routines. | |
3 | */ | |
4 | ||
1da177e4 LT |
5 | #include <linux/module.h> |
6 | #include <linux/pci.h> | |
7 | #include <linux/init.h> | |
1eaf122c | 8 | #include <linux/kernel.h> |
1da177e4 LT |
9 | #include <linux/pagemap.h> |
10 | #include <linux/agp_backend.h> | |
11 | #include "agp.h" | |
12 | ||
17661681 ZW |
13 | /* |
14 | * If we have Intel graphics, we're not going to have anything other than | |
15 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent | |
16 | * on the Intel IOMMU support (CONFIG_DMAR). | |
17 | * Only newer chipsets need to bother with this, of course. | |
18 | */ | |
19 | #ifdef CONFIG_DMAR | |
20 | #define USE_PCI_DMA_API 1 | |
21 | #endif | |
22 | ||
e914a36a CM |
23 | #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
24 | #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a | |
65c25aad EA |
25 | #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
26 | #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 | |
9119f85a ZW |
27 | #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 |
28 | #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 | |
65c25aad EA |
29 | #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 |
30 | #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 | |
31 | #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 | |
32 | #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 | |
4598af33 WZ |
33 | #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
34 | #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 | |
dde47876 | 35 | #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
c8eebfd6 | 36 | #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
dde47876 | 37 | #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
df80b148 | 38 | #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
107f517b AJ |
39 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 |
40 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 | |
41 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 | |
42 | #define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 | |
874808c6 WZ |
43 | #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
44 | #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 | |
45 | #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 | |
46 | #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 | |
47 | #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 | |
48 | #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 | |
38d8a956 FH |
49 | #define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 |
50 | #define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 | |
99d32bd5 ZW |
51 | #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
52 | #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 | |
107f517b AJ |
53 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 |
54 | #define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 | |
25ce77ab ZW |
55 | #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 |
56 | #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 | |
57 | #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 | |
58 | #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 | |
a50ccc6c ZW |
59 | #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
60 | #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 | |
107f517b AJ |
61 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 |
62 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 | |
63 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 | |
64 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 | |
3ff99164 | 65 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a |
107f517b | 66 | #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 |
1089e300 EA |
67 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 |
68 | #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG 0x0102 | |
65c25aad | 69 | |
f011ae74 DA |
70 | /* cover 915 and 945 variants */ |
71 | #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ | |
72 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ | |
73 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \ | |
74 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \ | |
75 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \ | |
76 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB) | |
77 | ||
65c25aad | 78 | #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ |
f011ae74 DA |
79 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \ |
80 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ | |
81 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \ | |
82 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \ | |
82e14a62 | 83 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB) |
65c25aad | 84 | |
874808c6 WZ |
85 | #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \ |
86 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \ | |
2177832f | 87 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \ |
107f517b AJ |
88 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ |
89 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
2177832f | 90 | |
107f517b AJ |
91 | #define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \ |
92 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB) | |
65c25aad | 93 | |
107f517b | 94 | #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \ |
25ce77ab | 95 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \ |
82e14a62 | 96 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \ |
a50ccc6c | 97 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \ |
32cb055b | 98 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \ |
38d8a956 | 99 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \ |
107f517b AJ |
100 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \ |
101 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \ | |
3ff99164 | 102 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \ |
1089e300 EA |
103 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \ |
104 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) | |
25ce77ab | 105 | |
a030ce44 TH |
106 | extern int agp_memory_reserved; |
107 | ||
108 | ||
1da177e4 LT |
109 | /* Intel 815 register */ |
110 | #define INTEL_815_APCONT 0x51 | |
111 | #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF | |
112 | ||
113 | /* Intel i820 registers */ | |
114 | #define INTEL_I820_RDCR 0x51 | |
115 | #define INTEL_I820_ERRSTS 0xc8 | |
116 | ||
117 | /* Intel i840 registers */ | |
118 | #define INTEL_I840_MCHCFG 0x50 | |
119 | #define INTEL_I840_ERRSTS 0xc8 | |
120 | ||
121 | /* Intel i850 registers */ | |
122 | #define INTEL_I850_MCHCFG 0x50 | |
123 | #define INTEL_I850_ERRSTS 0xc8 | |
124 | ||
125 | /* intel 915G registers */ | |
126 | #define I915_GMADDR 0x18 | |
127 | #define I915_MMADDR 0x10 | |
128 | #define I915_PTEADDR 0x1C | |
129 | #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) | |
130 | #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) | |
25ce77ab ZW |
131 | #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
132 | #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) | |
133 | #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) | |
134 | #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) | |
135 | #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) | |
136 | #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) | |
137 | ||
6c00a61e | 138 | #define I915_IFPADDR 0x60 |
1da177e4 | 139 | |
65c25aad EA |
140 | /* Intel 965G registers */ |
141 | #define I965_MSAC 0x62 | |
6c00a61e | 142 | #define I965_IFPADDR 0x70 |
1da177e4 LT |
143 | |
144 | /* Intel 7505 registers */ | |
145 | #define INTEL_I7505_APSIZE 0x74 | |
146 | #define INTEL_I7505_NCAPID 0x60 | |
147 | #define INTEL_I7505_NISTAT 0x6c | |
148 | #define INTEL_I7505_ATTBASE 0x78 | |
149 | #define INTEL_I7505_ERRSTS 0x42 | |
150 | #define INTEL_I7505_AGPCTRL 0x70 | |
151 | #define INTEL_I7505_MCHCFG 0x50 | |
152 | ||
14bc490b ZW |
153 | #define SNB_GMCH_CTRL 0x50 |
154 | #define SNB_GMCH_GMS_STOLEN_MASK 0xF8 | |
155 | #define SNB_GMCH_GMS_STOLEN_32M (1 << 3) | |
156 | #define SNB_GMCH_GMS_STOLEN_64M (2 << 3) | |
157 | #define SNB_GMCH_GMS_STOLEN_96M (3 << 3) | |
158 | #define SNB_GMCH_GMS_STOLEN_128M (4 << 3) | |
159 | #define SNB_GMCH_GMS_STOLEN_160M (5 << 3) | |
160 | #define SNB_GMCH_GMS_STOLEN_192M (6 << 3) | |
161 | #define SNB_GMCH_GMS_STOLEN_224M (7 << 3) | |
162 | #define SNB_GMCH_GMS_STOLEN_256M (8 << 3) | |
163 | #define SNB_GMCH_GMS_STOLEN_288M (9 << 3) | |
164 | #define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) | |
165 | #define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) | |
166 | #define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) | |
167 | #define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) | |
168 | #define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) | |
169 | #define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) | |
170 | #define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) | |
171 | ||
e5524f35 | 172 | static const struct aper_size_info_fixed intel_i810_sizes[] = |
1da177e4 LT |
173 | { |
174 | {64, 16384, 4}, | |
175 | /* The 32M mode still requires a 64k gatt */ | |
176 | {32, 8192, 4} | |
177 | }; | |
178 | ||
179 | #define AGP_DCACHE_MEMORY 1 | |
180 | #define AGP_PHYS_MEMORY 2 | |
a030ce44 | 181 | #define INTEL_AGP_CACHED_MEMORY 3 |
1da177e4 LT |
182 | |
183 | static struct gatt_mask intel_i810_masks[] = | |
184 | { | |
185 | {.mask = I810_PTE_VALID, .type = 0}, | |
186 | {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, | |
a030ce44 TH |
187 | {.mask = I810_PTE_VALID, .type = 0}, |
188 | {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, | |
189 | .type = INTEL_AGP_CACHED_MEMORY} | |
1da177e4 LT |
190 | }; |
191 | ||
c4ca8817 WZ |
192 | static struct _intel_private { |
193 | struct pci_dev *pcidev; /* device one */ | |
194 | u8 __iomem *registers; | |
195 | u32 __iomem *gtt; /* I915G */ | |
1da177e4 | 196 | int num_dcache_entries; |
c4ca8817 WZ |
197 | /* gtt_entries is the number of gtt entries that are already mapped |
198 | * to stolen memory. Stolen memory is larger than the memory mapped | |
199 | * through gtt_entries, as it includes some reserved space for the BIOS | |
200 | * popup and for the GTT. | |
201 | */ | |
202 | int gtt_entries; /* i830+ */ | |
fc619013 | 203 | int gtt_total_size; |
2162e6a2 DA |
204 | union { |
205 | void __iomem *i9xx_flush_page; | |
206 | void *i8xx_flush_page; | |
207 | }; | |
208 | struct page *i8xx_page; | |
6c00a61e | 209 | struct resource ifp_resource; |
4d64dd9e | 210 | int resource_valid; |
c4ca8817 | 211 | } intel_private; |
1da177e4 | 212 | |
17661681 | 213 | #ifdef USE_PCI_DMA_API |
c2980d8c | 214 | static int intel_agp_map_page(struct page *page, dma_addr_t *ret) |
17661681 | 215 | { |
c2980d8c DW |
216 | *ret = pci_map_page(intel_private.pcidev, page, 0, |
217 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
218 | if (pci_dma_mapping_error(intel_private.pcidev, *ret)) |
219 | return -EINVAL; | |
220 | return 0; | |
221 | } | |
222 | ||
c2980d8c | 223 | static void intel_agp_unmap_page(struct page *page, dma_addr_t dma) |
17661681 | 224 | { |
c2980d8c DW |
225 | pci_unmap_page(intel_private.pcidev, dma, |
226 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
17661681 ZW |
227 | } |
228 | ||
91b8e305 DW |
229 | static void intel_agp_free_sglist(struct agp_memory *mem) |
230 | { | |
f692775d DW |
231 | struct sg_table st; |
232 | ||
233 | st.sgl = mem->sg_list; | |
234 | st.orig_nents = st.nents = mem->page_count; | |
235 | ||
236 | sg_free_table(&st); | |
91b8e305 | 237 | |
91b8e305 DW |
238 | mem->sg_list = NULL; |
239 | mem->num_sg = 0; | |
240 | } | |
241 | ||
17661681 ZW |
242 | static int intel_agp_map_memory(struct agp_memory *mem) |
243 | { | |
f692775d | 244 | struct sg_table st; |
17661681 ZW |
245 | struct scatterlist *sg; |
246 | int i; | |
247 | ||
248 | DBG("try mapping %lu pages\n", (unsigned long)mem->page_count); | |
249 | ||
f692775d | 250 | if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL)) |
17661681 | 251 | return -ENOMEM; |
17661681 | 252 | |
f692775d DW |
253 | mem->sg_list = sg = st.sgl; |
254 | ||
17661681 ZW |
255 | for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg)) |
256 | sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0); | |
257 | ||
258 | mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list, | |
259 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 DW |
260 | if (unlikely(!mem->num_sg)) { |
261 | intel_agp_free_sglist(mem); | |
17661681 ZW |
262 | return -ENOMEM; |
263 | } | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static void intel_agp_unmap_memory(struct agp_memory *mem) | |
268 | { | |
269 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); | |
270 | ||
271 | pci_unmap_sg(intel_private.pcidev, mem->sg_list, | |
272 | mem->page_count, PCI_DMA_BIDIRECTIONAL); | |
91b8e305 | 273 | intel_agp_free_sglist(mem); |
17661681 ZW |
274 | } |
275 | ||
276 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
277 | off_t pg_start, int mask_type) | |
278 | { | |
279 | struct scatterlist *sg; | |
280 | int i, j; | |
281 | ||
282 | j = pg_start; | |
283 | ||
284 | WARN_ON(!mem->num_sg); | |
285 | ||
286 | if (mem->num_sg == mem->page_count) { | |
287 | for_each_sg(mem->sg_list, sg, mem->page_count, i) { | |
288 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
289 | sg_dma_address(sg), mask_type), | |
290 | intel_private.gtt+j); | |
291 | j++; | |
292 | } | |
293 | } else { | |
294 | /* sg may merge pages, but we have to seperate | |
295 | * per-page addr for GTT */ | |
296 | unsigned int len, m; | |
297 | ||
298 | for_each_sg(mem->sg_list, sg, mem->num_sg, i) { | |
299 | len = sg_dma_len(sg) / PAGE_SIZE; | |
300 | for (m = 0; m < len; m++) { | |
301 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
302 | sg_dma_address(sg) + m * PAGE_SIZE, | |
303 | mask_type), | |
304 | intel_private.gtt+j); | |
305 | j++; | |
306 | } | |
307 | } | |
308 | } | |
309 | readl(intel_private.gtt+j-1); | |
310 | } | |
311 | ||
312 | #else | |
313 | ||
314 | static void intel_agp_insert_sg_entries(struct agp_memory *mem, | |
315 | off_t pg_start, int mask_type) | |
316 | { | |
317 | int i, j; | |
e3deb204 EA |
318 | u32 cache_bits = 0; |
319 | ||
320 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { | |
321 | cache_bits = I830_PTE_SYSTEM_CACHED; | |
322 | } | |
17661681 ZW |
323 | |
324 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
325 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 326 | page_to_phys(mem->pages[i]), mask_type), |
17661681 ZW |
327 | intel_private.gtt+j); |
328 | } | |
329 | ||
330 | readl(intel_private.gtt+j-1); | |
331 | } | |
332 | ||
333 | #endif | |
334 | ||
1da177e4 LT |
335 | static int intel_i810_fetch_size(void) |
336 | { | |
337 | u32 smram_miscc; | |
338 | struct aper_size_info_fixed *values; | |
339 | ||
340 | pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); | |
341 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
342 | ||
343 | if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { | |
e3cf6951 | 344 | dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n"); |
1da177e4 LT |
345 | return 0; |
346 | } | |
347 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { | |
348 | agp_bridge->previous_size = | |
349 | agp_bridge->current_size = (void *) (values + 1); | |
350 | agp_bridge->aperture_size_idx = 1; | |
351 | return values[1].size; | |
352 | } else { | |
353 | agp_bridge->previous_size = | |
354 | agp_bridge->current_size = (void *) (values); | |
355 | agp_bridge->aperture_size_idx = 0; | |
356 | return values[0].size; | |
357 | } | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int intel_i810_configure(void) | |
363 | { | |
364 | struct aper_size_info_fixed *current_size; | |
365 | u32 temp; | |
366 | int i; | |
367 | ||
368 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
369 | ||
c4ca8817 WZ |
370 | if (!intel_private.registers) { |
371 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); | |
e4ac5e4f DJ |
372 | temp &= 0xfff80000; |
373 | ||
c4ca8817 WZ |
374 | intel_private.registers = ioremap(temp, 128 * 4096); |
375 | if (!intel_private.registers) { | |
e3cf6951 BH |
376 | dev_err(&intel_private.pcidev->dev, |
377 | "can't remap memory\n"); | |
e4ac5e4f DJ |
378 | return -ENOMEM; |
379 | } | |
1da177e4 LT |
380 | } |
381 | ||
c4ca8817 | 382 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
1da177e4 LT |
383 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
384 | /* This will need to be dynamically assigned */ | |
e3cf6951 BH |
385 | dev_info(&intel_private.pcidev->dev, |
386 | "detected 4MB dedicated video ram\n"); | |
c4ca8817 | 387 | intel_private.num_dcache_entries = 1024; |
1da177e4 | 388 | } |
c4ca8817 | 389 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 | 390 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
c4ca8817 WZ |
391 | writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
392 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
393 | |
394 | if (agp_bridge->driver->needs_scratch_page) { | |
395 | for (i = 0; i < current_size->num_entries; i++) { | |
c4ca8817 | 396 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 397 | } |
44d49441 | 398 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */ |
1da177e4 LT |
399 | } |
400 | global_cache_flush(); | |
401 | return 0; | |
402 | } | |
403 | ||
404 | static void intel_i810_cleanup(void) | |
405 | { | |
c4ca8817 WZ |
406 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
407 | readl(intel_private.registers); /* PCI Posting. */ | |
408 | iounmap(intel_private.registers); | |
1da177e4 LT |
409 | } |
410 | ||
411 | static void intel_i810_tlbflush(struct agp_memory *mem) | |
412 | { | |
413 | return; | |
414 | } | |
415 | ||
416 | static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) | |
417 | { | |
418 | return; | |
419 | } | |
420 | ||
421 | /* Exists to support ARGB cursors */ | |
07613ba2 | 422 | static struct page *i8xx_alloc_pages(void) |
1da177e4 | 423 | { |
f011ae74 | 424 | struct page *page; |
1da177e4 | 425 | |
66c669ba | 426 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
1da177e4 LT |
427 | if (page == NULL) |
428 | return NULL; | |
429 | ||
6d238cc4 AV |
430 | if (set_pages_uc(page, 4) < 0) { |
431 | set_pages_wb(page, 4); | |
89cf7ccc | 432 | __free_pages(page, 2); |
1da177e4 LT |
433 | return NULL; |
434 | } | |
1da177e4 | 435 | get_page(page); |
1da177e4 | 436 | atomic_inc(&agp_bridge->current_memory_agp); |
07613ba2 | 437 | return page; |
1da177e4 LT |
438 | } |
439 | ||
07613ba2 | 440 | static void i8xx_destroy_pages(struct page *page) |
1da177e4 | 441 | { |
07613ba2 | 442 | if (page == NULL) |
1da177e4 LT |
443 | return; |
444 | ||
6d238cc4 | 445 | set_pages_wb(page, 4); |
1da177e4 | 446 | put_page(page); |
89cf7ccc | 447 | __free_pages(page, 2); |
1da177e4 LT |
448 | atomic_dec(&agp_bridge->current_memory_agp); |
449 | } | |
450 | ||
a030ce44 TH |
451 | static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, |
452 | int type) | |
453 | { | |
454 | if (type < AGP_USER_TYPES) | |
455 | return type; | |
456 | else if (type == AGP_USER_CACHED_MEMORY) | |
457 | return INTEL_AGP_CACHED_MEMORY; | |
458 | else | |
459 | return 0; | |
460 | } | |
461 | ||
1da177e4 LT |
462 | static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, |
463 | int type) | |
464 | { | |
465 | int i, j, num_entries; | |
466 | void *temp; | |
a030ce44 TH |
467 | int ret = -EINVAL; |
468 | int mask_type; | |
1da177e4 | 469 | |
5aa80c72 | 470 | if (mem->page_count == 0) |
a030ce44 | 471 | goto out; |
5aa80c72 | 472 | |
1da177e4 LT |
473 | temp = agp_bridge->current_size; |
474 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
475 | ||
6a92a4e0 | 476 | if ((pg_start + mem->page_count) > num_entries) |
a030ce44 | 477 | goto out_err; |
6a92a4e0 | 478 | |
1da177e4 | 479 | |
a030ce44 TH |
480 | for (j = pg_start; j < (pg_start + mem->page_count); j++) { |
481 | if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { | |
482 | ret = -EBUSY; | |
483 | goto out_err; | |
1da177e4 | 484 | } |
1da177e4 LT |
485 | } |
486 | ||
a030ce44 TH |
487 | if (type != mem->type) |
488 | goto out_err; | |
5aa80c72 | 489 | |
a030ce44 TH |
490 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); |
491 | ||
492 | switch (mask_type) { | |
493 | case AGP_DCACHE_MEMORY: | |
494 | if (!mem->is_flushed) | |
495 | global_cache_flush(); | |
496 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { | |
497 | writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, | |
c4ca8817 | 498 | intel_private.registers+I810_PTE_BASE+(i*4)); |
a030ce44 | 499 | } |
c4ca8817 | 500 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
a030ce44 TH |
501 | break; |
502 | case AGP_PHYS_MEMORY: | |
503 | case AGP_NORMAL_MEMORY: | |
504 | if (!mem->is_flushed) | |
505 | global_cache_flush(); | |
506 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
507 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 508 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 509 | intel_private.registers+I810_PTE_BASE+(j*4)); |
a030ce44 | 510 | } |
c4ca8817 | 511 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
a030ce44 TH |
512 | break; |
513 | default: | |
514 | goto out_err; | |
1da177e4 | 515 | } |
1da177e4 LT |
516 | |
517 | agp_bridge->driver->tlb_flush(mem); | |
a030ce44 TH |
518 | out: |
519 | ret = 0; | |
520 | out_err: | |
9516b030 | 521 | mem->is_flushed = true; |
a030ce44 | 522 | return ret; |
1da177e4 LT |
523 | } |
524 | ||
525 | static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, | |
526 | int type) | |
527 | { | |
528 | int i; | |
529 | ||
5aa80c72 TH |
530 | if (mem->page_count == 0) |
531 | return 0; | |
532 | ||
1da177e4 | 533 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { |
c4ca8817 | 534 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 535 | } |
c4ca8817 | 536 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 537 | |
1da177e4 LT |
538 | agp_bridge->driver->tlb_flush(mem); |
539 | return 0; | |
540 | } | |
541 | ||
542 | /* | |
543 | * The i810/i830 requires a physical address to program its mouse | |
544 | * pointer into hardware. | |
545 | * However the Xserver still writes to it through the agp aperture. | |
546 | */ | |
547 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) | |
548 | { | |
549 | struct agp_memory *new; | |
07613ba2 | 550 | struct page *page; |
1da177e4 | 551 | |
1da177e4 | 552 | switch (pg_count) { |
07613ba2 | 553 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
1da177e4 LT |
554 | break; |
555 | case 4: | |
556 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 | 557 | page = i8xx_alloc_pages(); |
1da177e4 LT |
558 | break; |
559 | default: | |
560 | return NULL; | |
561 | } | |
562 | ||
07613ba2 | 563 | if (page == NULL) |
1da177e4 LT |
564 | return NULL; |
565 | ||
566 | new = agp_create_memory(pg_count); | |
567 | if (new == NULL) | |
568 | return NULL; | |
569 | ||
07613ba2 | 570 | new->pages[0] = page; |
1da177e4 LT |
571 | if (pg_count == 4) { |
572 | /* kludge to get 4 physical pages for ARGB cursor */ | |
07613ba2 DA |
573 | new->pages[1] = new->pages[0] + 1; |
574 | new->pages[2] = new->pages[1] + 1; | |
575 | new->pages[3] = new->pages[2] + 1; | |
1da177e4 LT |
576 | } |
577 | new->page_count = pg_count; | |
578 | new->num_scratch_pages = pg_count; | |
579 | new->type = AGP_PHYS_MEMORY; | |
07613ba2 | 580 | new->physical = page_to_phys(new->pages[0]); |
1da177e4 LT |
581 | return new; |
582 | } | |
583 | ||
584 | static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) | |
585 | { | |
586 | struct agp_memory *new; | |
587 | ||
588 | if (type == AGP_DCACHE_MEMORY) { | |
c4ca8817 | 589 | if (pg_count != intel_private.num_dcache_entries) |
1da177e4 LT |
590 | return NULL; |
591 | ||
592 | new = agp_create_memory(1); | |
593 | if (new == NULL) | |
594 | return NULL; | |
595 | ||
596 | new->type = AGP_DCACHE_MEMORY; | |
597 | new->page_count = pg_count; | |
598 | new->num_scratch_pages = 0; | |
a030ce44 | 599 | agp_free_page_array(new); |
1da177e4 LT |
600 | return new; |
601 | } | |
602 | if (type == AGP_PHYS_MEMORY) | |
603 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
604 | return NULL; |
605 | } | |
606 | ||
607 | static void intel_i810_free_by_type(struct agp_memory *curr) | |
608 | { | |
609 | agp_free_key(curr->key); | |
6a92a4e0 | 610 | if (curr->type == AGP_PHYS_MEMORY) { |
1da177e4 | 611 | if (curr->page_count == 4) |
07613ba2 | 612 | i8xx_destroy_pages(curr->pages[0]); |
88d51967 | 613 | else { |
07613ba2 | 614 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 615 | AGP_PAGE_DESTROY_UNMAP); |
07613ba2 | 616 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
a2721e99 | 617 | AGP_PAGE_DESTROY_FREE); |
88d51967 | 618 | } |
a030ce44 | 619 | agp_free_page_array(curr); |
1da177e4 LT |
620 | } |
621 | kfree(curr); | |
622 | } | |
623 | ||
624 | static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 625 | dma_addr_t addr, int type) |
1da177e4 LT |
626 | { |
627 | /* Type checking must be done elsewhere */ | |
628 | return addr | bridge->driver->masks[type].mask; | |
629 | } | |
630 | ||
631 | static struct aper_size_info_fixed intel_i830_sizes[] = | |
632 | { | |
633 | {128, 32768, 5}, | |
634 | /* The 64M mode still requires a 128k gatt */ | |
635 | {64, 16384, 5}, | |
636 | {256, 65536, 6}, | |
65c25aad | 637 | {512, 131072, 7}, |
1da177e4 LT |
638 | }; |
639 | ||
1da177e4 LT |
640 | static void intel_i830_init_gtt_entries(void) |
641 | { | |
642 | u16 gmch_ctrl; | |
14bc490b | 643 | int gtt_entries = 0; |
1da177e4 LT |
644 | u8 rdct; |
645 | int local = 0; | |
646 | static const int ddt[4] = { 0, 16, 32, 64 }; | |
c41e0deb | 647 | int size; /* reserved space (in kb) at the top of stolen memory */ |
1da177e4 | 648 | |
f011ae74 | 649 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 650 | |
c41e0deb EA |
651 | if (IS_I965) { |
652 | u32 pgetbl_ctl; | |
c4ca8817 | 653 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
c41e0deb | 654 | |
c41e0deb EA |
655 | /* The 965 has a field telling us the size of the GTT, |
656 | * which may be larger than what is necessary to map the | |
657 | * aperture. | |
658 | */ | |
659 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { | |
660 | case I965_PGETBL_SIZE_128KB: | |
661 | size = 128; | |
662 | break; | |
663 | case I965_PGETBL_SIZE_256KB: | |
664 | size = 256; | |
665 | break; | |
666 | case I965_PGETBL_SIZE_512KB: | |
667 | size = 512; | |
668 | break; | |
4e8b6e25 ZW |
669 | case I965_PGETBL_SIZE_1MB: |
670 | size = 1024; | |
671 | break; | |
672 | case I965_PGETBL_SIZE_2MB: | |
673 | size = 2048; | |
674 | break; | |
675 | case I965_PGETBL_SIZE_1_5MB: | |
676 | size = 1024 + 512; | |
677 | break; | |
c41e0deb | 678 | default: |
e3cf6951 BH |
679 | dev_info(&intel_private.pcidev->dev, |
680 | "unknown page table size, assuming 512KB\n"); | |
c41e0deb EA |
681 | size = 512; |
682 | } | |
683 | size += 4; /* add in BIOS popup space */ | |
107f517b | 684 | } else if (IS_G33 && !IS_PINEVIEW) { |
874808c6 WZ |
685 | /* G33's GTT size defined in gmch_ctrl */ |
686 | switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) { | |
687 | case G33_PGETBL_SIZE_1M: | |
688 | size = 1024; | |
689 | break; | |
690 | case G33_PGETBL_SIZE_2M: | |
691 | size = 2048; | |
692 | break; | |
693 | default: | |
e3cf6951 BH |
694 | dev_info(&agp_bridge->dev->dev, |
695 | "unknown page table size 0x%x, assuming 512KB\n", | |
874808c6 WZ |
696 | (gmch_ctrl & G33_PGETBL_SIZE_MASK)); |
697 | size = 512; | |
698 | } | |
699 | size += 4; | |
107f517b | 700 | } else if (IS_G4X || IS_PINEVIEW) { |
25ce77ab | 701 | /* On 4 series hardware, GTT stolen is separate from graphics |
82e14a62 EA |
702 | * stolen, ignore it in stolen gtt entries counting. However, |
703 | * 4KB of the stolen memory doesn't get mapped to the GTT. | |
704 | */ | |
705 | size = 4; | |
c41e0deb EA |
706 | } else { |
707 | /* On previous hardware, the GTT size was just what was | |
708 | * required to map the aperture. | |
709 | */ | |
710 | size = agp_bridge->driver->fetch_size() + 4; | |
711 | } | |
1da177e4 LT |
712 | |
713 | if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || | |
714 | agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { | |
715 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { | |
716 | case I830_GMCH_GMS_STOLEN_512: | |
717 | gtt_entries = KB(512) - KB(size); | |
718 | break; | |
719 | case I830_GMCH_GMS_STOLEN_1024: | |
720 | gtt_entries = MB(1) - KB(size); | |
721 | break; | |
722 | case I830_GMCH_GMS_STOLEN_8192: | |
723 | gtt_entries = MB(8) - KB(size); | |
724 | break; | |
725 | case I830_GMCH_GMS_LOCAL: | |
c4ca8817 | 726 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
1da177e4 LT |
727 | gtt_entries = (I830_RDRAM_ND(rdct) + 1) * |
728 | MB(ddt[I830_RDRAM_DDT(rdct)]); | |
729 | local = 1; | |
730 | break; | |
731 | default: | |
732 | gtt_entries = 0; | |
733 | break; | |
734 | } | |
1089e300 EA |
735 | } else if (agp_bridge->dev->device == |
736 | PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB) { | |
14bc490b ZW |
737 | /* |
738 | * SandyBridge has new memory control reg at 0x50.w | |
1089e300 | 739 | */ |
14bc490b ZW |
740 | u16 snb_gmch_ctl; |
741 | pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
742 | switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { | |
743 | case SNB_GMCH_GMS_STOLEN_32M: | |
744 | gtt_entries = MB(32) - KB(size); | |
745 | break; | |
746 | case SNB_GMCH_GMS_STOLEN_64M: | |
747 | gtt_entries = MB(64) - KB(size); | |
748 | break; | |
749 | case SNB_GMCH_GMS_STOLEN_96M: | |
750 | gtt_entries = MB(96) - KB(size); | |
751 | break; | |
752 | case SNB_GMCH_GMS_STOLEN_128M: | |
753 | gtt_entries = MB(128) - KB(size); | |
754 | break; | |
755 | case SNB_GMCH_GMS_STOLEN_160M: | |
756 | gtt_entries = MB(160) - KB(size); | |
757 | break; | |
758 | case SNB_GMCH_GMS_STOLEN_192M: | |
759 | gtt_entries = MB(192) - KB(size); | |
760 | break; | |
761 | case SNB_GMCH_GMS_STOLEN_224M: | |
762 | gtt_entries = MB(224) - KB(size); | |
763 | break; | |
764 | case SNB_GMCH_GMS_STOLEN_256M: | |
765 | gtt_entries = MB(256) - KB(size); | |
766 | break; | |
767 | case SNB_GMCH_GMS_STOLEN_288M: | |
768 | gtt_entries = MB(288) - KB(size); | |
769 | break; | |
770 | case SNB_GMCH_GMS_STOLEN_320M: | |
771 | gtt_entries = MB(320) - KB(size); | |
772 | break; | |
773 | case SNB_GMCH_GMS_STOLEN_352M: | |
774 | gtt_entries = MB(352) - KB(size); | |
775 | break; | |
776 | case SNB_GMCH_GMS_STOLEN_384M: | |
777 | gtt_entries = MB(384) - KB(size); | |
778 | break; | |
779 | case SNB_GMCH_GMS_STOLEN_416M: | |
780 | gtt_entries = MB(416) - KB(size); | |
781 | break; | |
782 | case SNB_GMCH_GMS_STOLEN_448M: | |
783 | gtt_entries = MB(448) - KB(size); | |
784 | break; | |
785 | case SNB_GMCH_GMS_STOLEN_480M: | |
786 | gtt_entries = MB(480) - KB(size); | |
787 | break; | |
788 | case SNB_GMCH_GMS_STOLEN_512M: | |
789 | gtt_entries = MB(512) - KB(size); | |
790 | break; | |
791 | } | |
1da177e4 | 792 | } else { |
e67aa27a | 793 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
1da177e4 LT |
794 | case I855_GMCH_GMS_STOLEN_1M: |
795 | gtt_entries = MB(1) - KB(size); | |
796 | break; | |
797 | case I855_GMCH_GMS_STOLEN_4M: | |
798 | gtt_entries = MB(4) - KB(size); | |
799 | break; | |
800 | case I855_GMCH_GMS_STOLEN_8M: | |
801 | gtt_entries = MB(8) - KB(size); | |
802 | break; | |
803 | case I855_GMCH_GMS_STOLEN_16M: | |
804 | gtt_entries = MB(16) - KB(size); | |
805 | break; | |
806 | case I855_GMCH_GMS_STOLEN_32M: | |
807 | gtt_entries = MB(32) - KB(size); | |
808 | break; | |
809 | case I915_GMCH_GMS_STOLEN_48M: | |
810 | /* Check it's really I915G */ | |
25ce77ab | 811 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
812 | gtt_entries = MB(48) - KB(size); |
813 | else | |
814 | gtt_entries = 0; | |
815 | break; | |
816 | case I915_GMCH_GMS_STOLEN_64M: | |
817 | /* Check it's really I915G */ | |
25ce77ab | 818 | if (IS_I915 || IS_I965 || IS_G33 || IS_G4X) |
1da177e4 LT |
819 | gtt_entries = MB(64) - KB(size); |
820 | else | |
821 | gtt_entries = 0; | |
874808c6 WZ |
822 | break; |
823 | case G33_GMCH_GMS_STOLEN_128M: | |
25ce77ab | 824 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
825 | gtt_entries = MB(128) - KB(size); |
826 | else | |
827 | gtt_entries = 0; | |
828 | break; | |
829 | case G33_GMCH_GMS_STOLEN_256M: | |
25ce77ab | 830 | if (IS_G33 || IS_I965 || IS_G4X) |
874808c6 WZ |
831 | gtt_entries = MB(256) - KB(size); |
832 | else | |
833 | gtt_entries = 0; | |
834 | break; | |
25ce77ab ZW |
835 | case INTEL_GMCH_GMS_STOLEN_96M: |
836 | if (IS_I965 || IS_G4X) | |
837 | gtt_entries = MB(96) - KB(size); | |
838 | else | |
839 | gtt_entries = 0; | |
840 | break; | |
841 | case INTEL_GMCH_GMS_STOLEN_160M: | |
842 | if (IS_I965 || IS_G4X) | |
843 | gtt_entries = MB(160) - KB(size); | |
844 | else | |
845 | gtt_entries = 0; | |
846 | break; | |
847 | case INTEL_GMCH_GMS_STOLEN_224M: | |
848 | if (IS_I965 || IS_G4X) | |
849 | gtt_entries = MB(224) - KB(size); | |
850 | else | |
851 | gtt_entries = 0; | |
852 | break; | |
853 | case INTEL_GMCH_GMS_STOLEN_352M: | |
854 | if (IS_I965 || IS_G4X) | |
855 | gtt_entries = MB(352) - KB(size); | |
856 | else | |
857 | gtt_entries = 0; | |
858 | break; | |
1da177e4 LT |
859 | default: |
860 | gtt_entries = 0; | |
861 | break; | |
862 | } | |
863 | } | |
9c1e8a4e | 864 | if (gtt_entries > 0) { |
e3cf6951 | 865 | dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", |
1da177e4 | 866 | gtt_entries / KB(1), local ? "local" : "stolen"); |
9c1e8a4e LR |
867 | gtt_entries /= KB(4); |
868 | } else { | |
e3cf6951 BH |
869 | dev_info(&agp_bridge->dev->dev, |
870 | "no pre-allocated video memory detected\n"); | |
9c1e8a4e LR |
871 | gtt_entries = 0; |
872 | } | |
1da177e4 | 873 | |
c4ca8817 | 874 | intel_private.gtt_entries = gtt_entries; |
1da177e4 LT |
875 | } |
876 | ||
2162e6a2 DA |
877 | static void intel_i830_fini_flush(void) |
878 | { | |
879 | kunmap(intel_private.i8xx_page); | |
880 | intel_private.i8xx_flush_page = NULL; | |
881 | unmap_page_from_agp(intel_private.i8xx_page); | |
2162e6a2 DA |
882 | |
883 | __free_page(intel_private.i8xx_page); | |
4d64dd9e | 884 | intel_private.i8xx_page = NULL; |
2162e6a2 DA |
885 | } |
886 | ||
887 | static void intel_i830_setup_flush(void) | |
888 | { | |
4d64dd9e DA |
889 | /* return if we've already set the flush mechanism up */ |
890 | if (intel_private.i8xx_page) | |
891 | return; | |
2162e6a2 DA |
892 | |
893 | intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32); | |
f011ae74 | 894 | if (!intel_private.i8xx_page) |
2162e6a2 | 895 | return; |
2162e6a2 | 896 | |
2162e6a2 DA |
897 | intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page); |
898 | if (!intel_private.i8xx_flush_page) | |
899 | intel_i830_fini_flush(); | |
900 | } | |
901 | ||
e517a5e9 EA |
902 | static void |
903 | do_wbinvd(void *null) | |
904 | { | |
905 | wbinvd(); | |
906 | } | |
907 | ||
908 | /* The chipset_flush interface needs to get data that has already been | |
909 | * flushed out of the CPU all the way out to main memory, because the GPU | |
910 | * doesn't snoop those buffers. | |
911 | * | |
912 | * The 8xx series doesn't have the same lovely interface for flushing the | |
913 | * chipset write buffers that the later chips do. According to the 865 | |
914 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in | |
915 | * that buffer out, we just fill 1KB and clflush it out, on the assumption | |
916 | * that it'll push whatever was in there out. It appears to work. | |
917 | */ | |
2162e6a2 DA |
918 | static void intel_i830_chipset_flush(struct agp_bridge_data *bridge) |
919 | { | |
920 | unsigned int *pg = intel_private.i8xx_flush_page; | |
2162e6a2 | 921 | |
e517a5e9 | 922 | memset(pg, 0, 1024); |
f011ae74 | 923 | |
e517a5e9 EA |
924 | if (cpu_has_clflush) { |
925 | clflush_cache_range(pg, 1024); | |
926 | } else { | |
927 | if (on_each_cpu(do_wbinvd, NULL, 1) != 0) | |
928 | printk(KERN_ERR "Timed out waiting for cache flush.\n"); | |
929 | } | |
2162e6a2 DA |
930 | } |
931 | ||
1da177e4 LT |
932 | /* The intel i830 automatically initializes the agp aperture during POST. |
933 | * Use the memory already set aside for in the GTT. | |
934 | */ | |
935 | static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) | |
936 | { | |
937 | int page_order; | |
938 | struct aper_size_info_fixed *size; | |
939 | int num_entries; | |
940 | u32 temp; | |
941 | ||
942 | size = agp_bridge->current_size; | |
943 | page_order = size->page_order; | |
944 | num_entries = size->num_entries; | |
945 | agp_bridge->gatt_table_real = NULL; | |
946 | ||
f011ae74 | 947 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp); |
1da177e4 LT |
948 | temp &= 0xfff80000; |
949 | ||
f011ae74 | 950 | intel_private.registers = ioremap(temp, 128 * 4096); |
c4ca8817 | 951 | if (!intel_private.registers) |
1da177e4 LT |
952 | return -ENOMEM; |
953 | ||
c4ca8817 | 954 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
955 | global_cache_flush(); /* FIXME: ?? */ |
956 | ||
957 | /* we have to call this as early as possible after the MMIO base address is known */ | |
958 | intel_i830_init_gtt_entries(); | |
959 | ||
960 | agp_bridge->gatt_table = NULL; | |
961 | ||
962 | agp_bridge->gatt_bus_addr = temp; | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
967 | /* Return the gatt table to a sane state. Use the top of stolen | |
968 | * memory for the GTT. | |
969 | */ | |
970 | static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) | |
971 | { | |
972 | return 0; | |
973 | } | |
974 | ||
975 | static int intel_i830_fetch_size(void) | |
976 | { | |
977 | u16 gmch_ctrl; | |
978 | struct aper_size_info_fixed *values; | |
979 | ||
980 | values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); | |
981 | ||
982 | if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && | |
983 | agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { | |
984 | /* 855GM/852GM/865G has 128MB aperture size */ | |
985 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
986 | agp_bridge->aperture_size_idx = 0; | |
987 | return values[0].size; | |
988 | } | |
989 | ||
f011ae74 | 990 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 LT |
991 | |
992 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { | |
993 | agp_bridge->previous_size = agp_bridge->current_size = (void *) values; | |
994 | agp_bridge->aperture_size_idx = 0; | |
995 | return values[0].size; | |
996 | } else { | |
997 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); | |
998 | agp_bridge->aperture_size_idx = 1; | |
999 | return values[1].size; | |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static int intel_i830_configure(void) | |
1006 | { | |
1007 | struct aper_size_info_fixed *current_size; | |
1008 | u32 temp; | |
1009 | u16 gmch_ctrl; | |
1010 | int i; | |
1011 | ||
1012 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
1013 | ||
f011ae74 | 1014 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp); |
1da177e4 LT |
1015 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); |
1016 | ||
f011ae74 | 1017 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 1018 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 1019 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 1020 | |
c4ca8817 WZ |
1021 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
1022 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
1023 | |
1024 | if (agp_bridge->driver->needs_scratch_page) { | |
c4ca8817 WZ |
1025 | for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) { |
1026 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); | |
1da177e4 | 1027 | } |
44d49441 | 1028 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */ |
1da177e4 LT |
1029 | } |
1030 | ||
1031 | global_cache_flush(); | |
2162e6a2 DA |
1032 | |
1033 | intel_i830_setup_flush(); | |
1da177e4 LT |
1034 | return 0; |
1035 | } | |
1036 | ||
1037 | static void intel_i830_cleanup(void) | |
1038 | { | |
c4ca8817 | 1039 | iounmap(intel_private.registers); |
1da177e4 LT |
1040 | } |
1041 | ||
f011ae74 DA |
1042 | static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start, |
1043 | int type) | |
1da177e4 | 1044 | { |
f011ae74 | 1045 | int i, j, num_entries; |
1da177e4 | 1046 | void *temp; |
a030ce44 TH |
1047 | int ret = -EINVAL; |
1048 | int mask_type; | |
1da177e4 | 1049 | |
5aa80c72 | 1050 | if (mem->page_count == 0) |
a030ce44 | 1051 | goto out; |
5aa80c72 | 1052 | |
1da177e4 LT |
1053 | temp = agp_bridge->current_size; |
1054 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1055 | ||
c4ca8817 | 1056 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1057 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
1058 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
1059 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1060 | |
e3cf6951 BH |
1061 | dev_info(&intel_private.pcidev->dev, |
1062 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 1063 | goto out_err; |
1da177e4 LT |
1064 | } |
1065 | ||
1066 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1067 | goto out_err; |
1da177e4 LT |
1068 | |
1069 | /* The i830 can't check the GTT for entries since its read only, | |
1070 | * depend on the caller to make the correct offset decisions. | |
1071 | */ | |
1072 | ||
a030ce44 TH |
1073 | if (type != mem->type) |
1074 | goto out_err; | |
1075 | ||
1076 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1077 | |
a030ce44 TH |
1078 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1079 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1080 | goto out_err; | |
1081 | ||
1082 | if (!mem->is_flushed) | |
5aa80c72 | 1083 | global_cache_flush(); |
1da177e4 LT |
1084 | |
1085 | for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { | |
1086 | writel(agp_bridge->driver->mask_memory(agp_bridge, | |
6a12235c | 1087 | page_to_phys(mem->pages[i]), mask_type), |
c4ca8817 | 1088 | intel_private.registers+I810_PTE_BASE+(j*4)); |
1da177e4 | 1089 | } |
c4ca8817 | 1090 | readl(intel_private.registers+I810_PTE_BASE+((j-1)*4)); |
1da177e4 | 1091 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1092 | |
1093 | out: | |
1094 | ret = 0; | |
1095 | out_err: | |
9516b030 | 1096 | mem->is_flushed = true; |
a030ce44 | 1097 | return ret; |
1da177e4 LT |
1098 | } |
1099 | ||
f011ae74 DA |
1100 | static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start, |
1101 | int type) | |
1da177e4 LT |
1102 | { |
1103 | int i; | |
1104 | ||
5aa80c72 TH |
1105 | if (mem->page_count == 0) |
1106 | return 0; | |
1da177e4 | 1107 | |
c4ca8817 | 1108 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1109 | dev_info(&intel_private.pcidev->dev, |
1110 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1111 | return -EINVAL; |
1112 | } | |
1113 | ||
1114 | for (i = pg_start; i < (mem->page_count + pg_start); i++) { | |
c4ca8817 | 1115 | writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4)); |
1da177e4 | 1116 | } |
c4ca8817 | 1117 | readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); |
1da177e4 | 1118 | |
1da177e4 LT |
1119 | agp_bridge->driver->tlb_flush(mem); |
1120 | return 0; | |
1121 | } | |
1122 | ||
f011ae74 | 1123 | static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type) |
1da177e4 LT |
1124 | { |
1125 | if (type == AGP_PHYS_MEMORY) | |
1126 | return alloc_agpphysmem_i8xx(pg_count, type); | |
1da177e4 LT |
1127 | /* always return NULL for other allocation types for now */ |
1128 | return NULL; | |
1129 | } | |
1130 | ||
6c00a61e DA |
1131 | static int intel_alloc_chipset_flush_resource(void) |
1132 | { | |
1133 | int ret; | |
1134 | ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE, | |
1135 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, | |
1136 | pcibios_align_resource, agp_bridge->dev); | |
6c00a61e | 1137 | |
2162e6a2 | 1138 | return ret; |
6c00a61e DA |
1139 | } |
1140 | ||
1141 | static void intel_i915_setup_chipset_flush(void) | |
1142 | { | |
1143 | int ret; | |
1144 | u32 temp; | |
1145 | ||
1146 | pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp); | |
1147 | if (!(temp & 0x1)) { | |
1148 | intel_alloc_chipset_flush_resource(); | |
4d64dd9e | 1149 | intel_private.resource_valid = 1; |
6c00a61e DA |
1150 | pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
1151 | } else { | |
1152 | temp &= ~1; | |
1153 | ||
4d64dd9e | 1154 | intel_private.resource_valid = 1; |
6c00a61e DA |
1155 | intel_private.ifp_resource.start = temp; |
1156 | intel_private.ifp_resource.end = temp + PAGE_SIZE; | |
1157 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1158 | /* some BIOSes reserve this area in a pnp some don't */ |
1159 | if (ret) | |
1160 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1161 | } |
1162 | } | |
1163 | ||
1164 | static void intel_i965_g33_setup_chipset_flush(void) | |
1165 | { | |
1166 | u32 temp_hi, temp_lo; | |
1167 | int ret; | |
1168 | ||
1169 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi); | |
1170 | pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo); | |
1171 | ||
1172 | if (!(temp_lo & 0x1)) { | |
1173 | ||
1174 | intel_alloc_chipset_flush_resource(); | |
1175 | ||
4d64dd9e | 1176 | intel_private.resource_valid = 1; |
1fa4db7d AM |
1177 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4, |
1178 | upper_32_bits(intel_private.ifp_resource.start)); | |
6c00a61e | 1179 | pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
6c00a61e DA |
1180 | } else { |
1181 | u64 l64; | |
f011ae74 | 1182 | |
6c00a61e DA |
1183 | temp_lo &= ~0x1; |
1184 | l64 = ((u64)temp_hi << 32) | temp_lo; | |
1185 | ||
4d64dd9e | 1186 | intel_private.resource_valid = 1; |
6c00a61e DA |
1187 | intel_private.ifp_resource.start = l64; |
1188 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; | |
1189 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); | |
4d64dd9e DA |
1190 | /* some BIOSes reserve this area in a pnp some don't */ |
1191 | if (ret) | |
1192 | intel_private.resource_valid = 0; | |
6c00a61e DA |
1193 | } |
1194 | } | |
1195 | ||
2162e6a2 DA |
1196 | static void intel_i9xx_setup_flush(void) |
1197 | { | |
4d64dd9e DA |
1198 | /* return if already configured */ |
1199 | if (intel_private.ifp_resource.start) | |
1200 | return; | |
2162e6a2 | 1201 | |
4d64dd9e | 1202 | /* setup a resource for this object */ |
2162e6a2 DA |
1203 | intel_private.ifp_resource.name = "Intel Flush Page"; |
1204 | intel_private.ifp_resource.flags = IORESOURCE_MEM; | |
1205 | ||
1206 | /* Setup chipset flush for 915 */ | |
7d15ddf7 | 1207 | if (IS_I965 || IS_G33 || IS_G4X) { |
2162e6a2 DA |
1208 | intel_i965_g33_setup_chipset_flush(); |
1209 | } else { | |
1210 | intel_i915_setup_chipset_flush(); | |
1211 | } | |
1212 | ||
1213 | if (intel_private.ifp_resource.start) { | |
1214 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); | |
1215 | if (!intel_private.i9xx_flush_page) | |
e3cf6951 | 1216 | dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing"); |
2162e6a2 DA |
1217 | } |
1218 | } | |
1219 | ||
1da177e4 LT |
1220 | static int intel_i915_configure(void) |
1221 | { | |
1222 | struct aper_size_info_fixed *current_size; | |
1223 | u32 temp; | |
1224 | u16 gmch_ctrl; | |
1225 | int i; | |
1226 | ||
1227 | current_size = A_SIZE_FIX(agp_bridge->current_size); | |
1228 | ||
c4ca8817 | 1229 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp); |
1da177e4 LT |
1230 | |
1231 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1232 | ||
f011ae74 | 1233 | pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl); |
1da177e4 | 1234 | gmch_ctrl |= I830_GMCH_ENABLED; |
f011ae74 | 1235 | pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl); |
1da177e4 | 1236 | |
c4ca8817 WZ |
1237 | writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL); |
1238 | readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ | |
1da177e4 LT |
1239 | |
1240 | if (agp_bridge->driver->needs_scratch_page) { | |
fc619013 | 1241 | for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) { |
c4ca8817 | 1242 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
1da177e4 | 1243 | } |
44d49441 | 1244 | readl(intel_private.gtt+i-1); /* PCI Posting. */ |
1da177e4 LT |
1245 | } |
1246 | ||
1247 | global_cache_flush(); | |
6c00a61e | 1248 | |
2162e6a2 | 1249 | intel_i9xx_setup_flush(); |
f011ae74 | 1250 | |
1da177e4 LT |
1251 | return 0; |
1252 | } | |
1253 | ||
1254 | static void intel_i915_cleanup(void) | |
1255 | { | |
2162e6a2 DA |
1256 | if (intel_private.i9xx_flush_page) |
1257 | iounmap(intel_private.i9xx_flush_page); | |
4d64dd9e DA |
1258 | if (intel_private.resource_valid) |
1259 | release_resource(&intel_private.ifp_resource); | |
1260 | intel_private.ifp_resource.start = 0; | |
1261 | intel_private.resource_valid = 0; | |
c4ca8817 WZ |
1262 | iounmap(intel_private.gtt); |
1263 | iounmap(intel_private.registers); | |
1da177e4 LT |
1264 | } |
1265 | ||
6c00a61e DA |
1266 | static void intel_i915_chipset_flush(struct agp_bridge_data *bridge) |
1267 | { | |
2162e6a2 DA |
1268 | if (intel_private.i9xx_flush_page) |
1269 | writel(1, intel_private.i9xx_flush_page); | |
6c00a61e DA |
1270 | } |
1271 | ||
f011ae74 DA |
1272 | static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start, |
1273 | int type) | |
1da177e4 | 1274 | { |
17661681 | 1275 | int num_entries; |
1da177e4 | 1276 | void *temp; |
a030ce44 TH |
1277 | int ret = -EINVAL; |
1278 | int mask_type; | |
1da177e4 | 1279 | |
5aa80c72 | 1280 | if (mem->page_count == 0) |
a030ce44 | 1281 | goto out; |
5aa80c72 | 1282 | |
1da177e4 LT |
1283 | temp = agp_bridge->current_size; |
1284 | num_entries = A_SIZE_FIX(temp)->num_entries; | |
1285 | ||
c4ca8817 | 1286 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1287 | dev_printk(KERN_DEBUG, &intel_private.pcidev->dev, |
1288 | "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n", | |
1289 | pg_start, intel_private.gtt_entries); | |
1da177e4 | 1290 | |
e3cf6951 BH |
1291 | dev_info(&intel_private.pcidev->dev, |
1292 | "trying to insert into local/stolen memory\n"); | |
a030ce44 | 1293 | goto out_err; |
1da177e4 LT |
1294 | } |
1295 | ||
1296 | if ((pg_start + mem->page_count) > num_entries) | |
a030ce44 | 1297 | goto out_err; |
1da177e4 | 1298 | |
17661681 | 1299 | /* The i915 can't check the GTT for entries since it's read only; |
1da177e4 LT |
1300 | * depend on the caller to make the correct offset decisions. |
1301 | */ | |
1302 | ||
a030ce44 TH |
1303 | if (type != mem->type) |
1304 | goto out_err; | |
1305 | ||
1306 | mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); | |
1da177e4 | 1307 | |
a030ce44 TH |
1308 | if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && |
1309 | mask_type != INTEL_AGP_CACHED_MEMORY) | |
1310 | goto out_err; | |
1311 | ||
1312 | if (!mem->is_flushed) | |
5aa80c72 | 1313 | global_cache_flush(); |
1da177e4 | 1314 | |
17661681 | 1315 | intel_agp_insert_sg_entries(mem, pg_start, mask_type); |
1da177e4 | 1316 | agp_bridge->driver->tlb_flush(mem); |
a030ce44 TH |
1317 | |
1318 | out: | |
1319 | ret = 0; | |
1320 | out_err: | |
9516b030 | 1321 | mem->is_flushed = true; |
a030ce44 | 1322 | return ret; |
1da177e4 LT |
1323 | } |
1324 | ||
f011ae74 DA |
1325 | static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start, |
1326 | int type) | |
1da177e4 LT |
1327 | { |
1328 | int i; | |
1329 | ||
5aa80c72 TH |
1330 | if (mem->page_count == 0) |
1331 | return 0; | |
1da177e4 | 1332 | |
c4ca8817 | 1333 | if (pg_start < intel_private.gtt_entries) { |
e3cf6951 BH |
1334 | dev_info(&intel_private.pcidev->dev, |
1335 | "trying to disable local/stolen memory\n"); | |
1da177e4 LT |
1336 | return -EINVAL; |
1337 | } | |
1338 | ||
f011ae74 | 1339 | for (i = pg_start; i < (mem->page_count + pg_start); i++) |
c4ca8817 | 1340 | writel(agp_bridge->scratch_page, intel_private.gtt+i); |
f011ae74 | 1341 | |
c4ca8817 | 1342 | readl(intel_private.gtt+i-1); |
1da177e4 | 1343 | |
1da177e4 LT |
1344 | agp_bridge->driver->tlb_flush(mem); |
1345 | return 0; | |
1346 | } | |
1347 | ||
c41e0deb EA |
1348 | /* Return the aperture size by just checking the resource length. The effect |
1349 | * described in the spec of the MSAC registers is just changing of the | |
1350 | * resource size. | |
1351 | */ | |
1352 | static int intel_i9xx_fetch_size(void) | |
1da177e4 | 1353 | { |
1eaf122c | 1354 | int num_sizes = ARRAY_SIZE(intel_i830_sizes); |
c41e0deb EA |
1355 | int aper_size; /* size in megabytes */ |
1356 | int i; | |
1da177e4 | 1357 | |
c4ca8817 | 1358 | aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1); |
1da177e4 | 1359 | |
c41e0deb EA |
1360 | for (i = 0; i < num_sizes; i++) { |
1361 | if (aper_size == intel_i830_sizes[i].size) { | |
1362 | agp_bridge->current_size = intel_i830_sizes + i; | |
1363 | agp_bridge->previous_size = agp_bridge->current_size; | |
1364 | return aper_size; | |
1365 | } | |
1366 | } | |
1da177e4 | 1367 | |
c41e0deb | 1368 | return 0; |
1da177e4 LT |
1369 | } |
1370 | ||
1371 | /* The intel i915 automatically initializes the agp aperture during POST. | |
1372 | * Use the memory already set aside for in the GTT. | |
1373 | */ | |
1374 | static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) | |
1375 | { | |
1376 | int page_order; | |
1377 | struct aper_size_info_fixed *size; | |
1378 | int num_entries; | |
1379 | u32 temp, temp2; | |
4740622c | 1380 | int gtt_map_size = 256 * 1024; |
1da177e4 LT |
1381 | |
1382 | size = agp_bridge->current_size; | |
1383 | page_order = size->page_order; | |
1384 | num_entries = size->num_entries; | |
1385 | agp_bridge->gatt_table_real = NULL; | |
1386 | ||
c4ca8817 | 1387 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
f011ae74 | 1388 | pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2); |
1da177e4 | 1389 | |
4740622c ZW |
1390 | if (IS_G33) |
1391 | gtt_map_size = 1024 * 1024; /* 1M on G33 */ | |
1392 | intel_private.gtt = ioremap(temp2, gtt_map_size); | |
c4ca8817 | 1393 | if (!intel_private.gtt) |
1da177e4 LT |
1394 | return -ENOMEM; |
1395 | ||
fc619013 DW |
1396 | intel_private.gtt_total_size = gtt_map_size / 4; |
1397 | ||
1da177e4 LT |
1398 | temp &= 0xfff80000; |
1399 | ||
f011ae74 | 1400 | intel_private.registers = ioremap(temp, 128 * 4096); |
5bdbc7dc ST |
1401 | if (!intel_private.registers) { |
1402 | iounmap(intel_private.gtt); | |
1da177e4 | 1403 | return -ENOMEM; |
5bdbc7dc | 1404 | } |
1da177e4 | 1405 | |
c4ca8817 | 1406 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1da177e4 LT |
1407 | global_cache_flush(); /* FIXME: ? */ |
1408 | ||
1409 | /* we have to call this as early as possible after the MMIO base address is known */ | |
1410 | intel_i830_init_gtt_entries(); | |
1411 | ||
1412 | agp_bridge->gatt_table = NULL; | |
1413 | ||
1414 | agp_bridge->gatt_bus_addr = temp; | |
1415 | ||
1416 | return 0; | |
1417 | } | |
7d915a38 LT |
1418 | |
1419 | /* | |
1420 | * The i965 supports 36-bit physical addresses, but to keep | |
1421 | * the format of the GTT the same, the bits that don't fit | |
1422 | * in a 32-bit word are shifted down to bits 4..7. | |
1423 | * | |
1424 | * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" | |
1425 | * is always zero on 32-bit architectures, so no need to make | |
1426 | * this conditional. | |
1427 | */ | |
1428 | static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, | |
2a4ceb6d | 1429 | dma_addr_t addr, int type) |
7d915a38 LT |
1430 | { |
1431 | /* Shift high bits down */ | |
1432 | addr |= (addr >> 28) & 0xf0; | |
1433 | ||
1434 | /* Type checking must be done elsewhere */ | |
1435 | return addr | bridge->driver->masks[type].mask; | |
1436 | } | |
1437 | ||
25ce77ab ZW |
1438 | static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size) |
1439 | { | |
1440 | switch (agp_bridge->dev->device) { | |
99d32bd5 | 1441 | case PCI_DEVICE_ID_INTEL_GM45_HB: |
107f517b | 1442 | case PCI_DEVICE_ID_INTEL_EAGLELAKE_HB: |
25ce77ab ZW |
1443 | case PCI_DEVICE_ID_INTEL_Q45_HB: |
1444 | case PCI_DEVICE_ID_INTEL_G45_HB: | |
a50ccc6c | 1445 | case PCI_DEVICE_ID_INTEL_G41_HB: |
38d8a956 | 1446 | case PCI_DEVICE_ID_INTEL_B43_HB: |
107f517b AJ |
1447 | case PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB: |
1448 | case PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB: | |
1449 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB: | |
3ff99164 | 1450 | case PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB: |
1089e300 | 1451 | case PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB: |
25ce77ab ZW |
1452 | *gtt_offset = *gtt_size = MB(2); |
1453 | break; | |
1454 | default: | |
1455 | *gtt_offset = *gtt_size = KB(512); | |
1456 | } | |
1457 | } | |
1458 | ||
65c25aad | 1459 | /* The intel i965 automatically initializes the agp aperture during POST. |
c41e0deb EA |
1460 | * Use the memory already set aside for in the GTT. |
1461 | */ | |
65c25aad EA |
1462 | static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) |
1463 | { | |
62c96b9d DA |
1464 | int page_order; |
1465 | struct aper_size_info_fixed *size; | |
1466 | int num_entries; | |
1467 | u32 temp; | |
1468 | int gtt_offset, gtt_size; | |
65c25aad | 1469 | |
62c96b9d DA |
1470 | size = agp_bridge->current_size; |
1471 | page_order = size->page_order; | |
1472 | num_entries = size->num_entries; | |
1473 | agp_bridge->gatt_table_real = NULL; | |
65c25aad | 1474 | |
62c96b9d | 1475 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp); |
65c25aad | 1476 | |
62c96b9d | 1477 | temp &= 0xfff00000; |
65c25aad | 1478 | |
25ce77ab | 1479 | intel_i965_get_gtt_range(>t_offset, >t_size); |
4e8b6e25 | 1480 | |
62c96b9d | 1481 | intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size); |
65c25aad | 1482 | |
62c96b9d DA |
1483 | if (!intel_private.gtt) |
1484 | return -ENOMEM; | |
65c25aad | 1485 | |
fc619013 DW |
1486 | intel_private.gtt_total_size = gtt_size / 4; |
1487 | ||
62c96b9d DA |
1488 | intel_private.registers = ioremap(temp, 128 * 4096); |
1489 | if (!intel_private.registers) { | |
5bdbc7dc ST |
1490 | iounmap(intel_private.gtt); |
1491 | return -ENOMEM; | |
1492 | } | |
65c25aad | 1493 | |
62c96b9d DA |
1494 | temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000; |
1495 | global_cache_flush(); /* FIXME: ? */ | |
65c25aad | 1496 | |
62c96b9d DA |
1497 | /* we have to call this as early as possible after the MMIO base address is known */ |
1498 | intel_i830_init_gtt_entries(); | |
65c25aad | 1499 | |
62c96b9d | 1500 | agp_bridge->gatt_table = NULL; |
65c25aad | 1501 | |
62c96b9d | 1502 | agp_bridge->gatt_bus_addr = temp; |
65c25aad | 1503 | |
62c96b9d | 1504 | return 0; |
65c25aad EA |
1505 | } |
1506 | ||
1da177e4 LT |
1507 | |
1508 | static int intel_fetch_size(void) | |
1509 | { | |
1510 | int i; | |
1511 | u16 temp; | |
1512 | struct aper_size_info_16 *values; | |
1513 | ||
1514 | pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1515 | values = A_SIZE_16(agp_bridge->driver->aperture_sizes); | |
1516 | ||
1517 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1518 | if (temp == values[i].size_value) { | |
1519 | agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); | |
1520 | agp_bridge->aperture_size_idx = i; | |
1521 | return values[i].size; | |
1522 | } | |
1523 | } | |
1524 | ||
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | static int __intel_8xx_fetch_size(u8 temp) | |
1529 | { | |
1530 | int i; | |
1531 | struct aper_size_info_8 *values; | |
1532 | ||
1533 | values = A_SIZE_8(agp_bridge->driver->aperture_sizes); | |
1534 | ||
1535 | for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { | |
1536 | if (temp == values[i].size_value) { | |
1537 | agp_bridge->previous_size = | |
1538 | agp_bridge->current_size = (void *) (values + i); | |
1539 | agp_bridge->aperture_size_idx = i; | |
1540 | return values[i].size; | |
1541 | } | |
1542 | } | |
1543 | return 0; | |
1544 | } | |
1545 | ||
1546 | static int intel_8xx_fetch_size(void) | |
1547 | { | |
1548 | u8 temp; | |
1549 | ||
1550 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1551 | return __intel_8xx_fetch_size(temp); | |
1552 | } | |
1553 | ||
1554 | static int intel_815_fetch_size(void) | |
1555 | { | |
1556 | u8 temp; | |
1557 | ||
1558 | /* Intel 815 chipsets have a _weird_ APSIZE register with only | |
1559 | * one non-reserved bit, so mask the others out ... */ | |
1560 | pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); | |
1561 | temp &= (1 << 3); | |
1562 | ||
1563 | return __intel_8xx_fetch_size(temp); | |
1564 | } | |
1565 | ||
1566 | static void intel_tlbflush(struct agp_memory *mem) | |
1567 | { | |
1568 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); | |
1569 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1570 | } | |
1571 | ||
1572 | ||
1573 | static void intel_8xx_tlbflush(struct agp_memory *mem) | |
1574 | { | |
1575 | u32 temp; | |
1576 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1577 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); | |
1578 | pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); | |
1579 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); | |
1580 | } | |
1581 | ||
1582 | ||
1583 | static void intel_cleanup(void) | |
1584 | { | |
1585 | u16 temp; | |
1586 | struct aper_size_info_16 *previous_size; | |
1587 | ||
1588 | previous_size = A_SIZE_16(agp_bridge->previous_size); | |
1589 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1590 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1591 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1592 | } | |
1593 | ||
1594 | ||
1595 | static void intel_8xx_cleanup(void) | |
1596 | { | |
1597 | u16 temp; | |
1598 | struct aper_size_info_8 *previous_size; | |
1599 | ||
1600 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1601 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); | |
1602 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); | |
1603 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); | |
1604 | } | |
1605 | ||
1606 | ||
1607 | static int intel_configure(void) | |
1608 | { | |
1609 | u32 temp; | |
1610 | u16 temp2; | |
1611 | struct aper_size_info_16 *current_size; | |
1612 | ||
1613 | current_size = A_SIZE_16(agp_bridge->current_size); | |
1614 | ||
1615 | /* aperture size */ | |
1616 | pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1617 | ||
1618 | /* address to map to */ | |
1619 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1620 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1621 | ||
1622 | /* attbase - aperture base */ | |
1623 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1624 | ||
1625 | /* agpctrl */ | |
1626 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); | |
1627 | ||
1628 | /* paccfg/nbxcfg */ | |
1629 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1630 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, | |
1631 | (temp2 & ~(1 << 10)) | (1 << 9)); | |
1632 | /* clear any possible error conditions */ | |
1633 | pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); | |
1634 | return 0; | |
1635 | } | |
1636 | ||
1637 | static int intel_815_configure(void) | |
1638 | { | |
1639 | u32 temp, addr; | |
1640 | u8 temp2; | |
1641 | struct aper_size_info_8 *current_size; | |
1642 | ||
1643 | /* attbase - aperture base */ | |
1644 | /* the Intel 815 chipset spec. says that bits 29-31 in the | |
1645 | * ATTBASE register are reserved -> try not to write them */ | |
1646 | if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { | |
e3cf6951 | 1647 | dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high"); |
1da177e4 LT |
1648 | return -EINVAL; |
1649 | } | |
1650 | ||
1651 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1652 | ||
1653 | /* aperture size */ | |
1654 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1655 | current_size->size_value); | |
1656 | ||
1657 | /* address to map to */ | |
1658 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1659 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1660 | ||
1661 | pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); | |
1662 | addr &= INTEL_815_ATTBASE_MASK; | |
1663 | addr |= agp_bridge->gatt_bus_addr; | |
1664 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); | |
1665 | ||
1666 | /* agpctrl */ | |
1667 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1668 | ||
1669 | /* apcont */ | |
1670 | pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); | |
1671 | pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); | |
1672 | ||
1673 | /* clear any possible error conditions */ | |
1674 | /* Oddness : this chipset seems to have no ERRSTS register ! */ | |
1675 | return 0; | |
1676 | } | |
1677 | ||
1678 | static void intel_820_tlbflush(struct agp_memory *mem) | |
1679 | { | |
1680 | return; | |
1681 | } | |
1682 | ||
1683 | static void intel_820_cleanup(void) | |
1684 | { | |
1685 | u8 temp; | |
1686 | struct aper_size_info_8 *previous_size; | |
1687 | ||
1688 | previous_size = A_SIZE_8(agp_bridge->previous_size); | |
1689 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); | |
1690 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, | |
1691 | temp & ~(1 << 1)); | |
1692 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, | |
1693 | previous_size->size_value); | |
1694 | } | |
1695 | ||
1696 | ||
1697 | static int intel_820_configure(void) | |
1698 | { | |
1699 | u32 temp; | |
1700 | u8 temp2; | |
1701 | struct aper_size_info_8 *current_size; | |
1702 | ||
1703 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1704 | ||
1705 | /* aperture size */ | |
1706 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1707 | ||
1708 | /* address to map to */ | |
1709 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1710 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1711 | ||
1712 | /* attbase - aperture base */ | |
1713 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1714 | ||
1715 | /* agpctrl */ | |
1716 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1717 | ||
1718 | /* global enable aperture access */ | |
1719 | /* This flag is not accessed through MCHCFG register as in */ | |
1720 | /* i850 chipset. */ | |
1721 | pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); | |
1722 | pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); | |
1723 | /* clear any possible AGP-related error conditions */ | |
1724 | pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); | |
1725 | return 0; | |
1726 | } | |
1727 | ||
1728 | static int intel_840_configure(void) | |
1729 | { | |
1730 | u32 temp; | |
1731 | u16 temp2; | |
1732 | struct aper_size_info_8 *current_size; | |
1733 | ||
1734 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1735 | ||
1736 | /* aperture size */ | |
1737 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1738 | ||
1739 | /* address to map to */ | |
1740 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1741 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1742 | ||
1743 | /* attbase - aperture base */ | |
1744 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1745 | ||
1746 | /* agpctrl */ | |
1747 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1748 | ||
1749 | /* mcgcfg */ | |
1750 | pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); | |
1751 | pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); | |
1752 | /* clear any possible error conditions */ | |
1753 | pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); | |
1754 | return 0; | |
1755 | } | |
1756 | ||
1757 | static int intel_845_configure(void) | |
1758 | { | |
1759 | u32 temp; | |
1760 | u8 temp2; | |
1761 | struct aper_size_info_8 *current_size; | |
1762 | ||
1763 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1764 | ||
1765 | /* aperture size */ | |
1766 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1767 | ||
b0825488 MG |
1768 | if (agp_bridge->apbase_config != 0) { |
1769 | pci_write_config_dword(agp_bridge->dev, AGP_APBASE, | |
1770 | agp_bridge->apbase_config); | |
1771 | } else { | |
1772 | /* address to map to */ | |
1773 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1774 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1775 | agp_bridge->apbase_config = temp; | |
1776 | } | |
1da177e4 LT |
1777 | |
1778 | /* attbase - aperture base */ | |
1779 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1780 | ||
1781 | /* agpctrl */ | |
1782 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1783 | ||
1784 | /* agpm */ | |
1785 | pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); | |
1786 | pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); | |
1787 | /* clear any possible error conditions */ | |
1788 | pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); | |
2162e6a2 DA |
1789 | |
1790 | intel_i830_setup_flush(); | |
1da177e4 LT |
1791 | return 0; |
1792 | } | |
1793 | ||
1794 | static int intel_850_configure(void) | |
1795 | { | |
1796 | u32 temp; | |
1797 | u16 temp2; | |
1798 | struct aper_size_info_8 *current_size; | |
1799 | ||
1800 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1801 | ||
1802 | /* aperture size */ | |
1803 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1804 | ||
1805 | /* address to map to */ | |
1806 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1807 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1808 | ||
1809 | /* attbase - aperture base */ | |
1810 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1811 | ||
1812 | /* agpctrl */ | |
1813 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1814 | ||
1815 | /* mcgcfg */ | |
1816 | pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); | |
1817 | pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); | |
1818 | /* clear any possible AGP-related error conditions */ | |
1819 | pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); | |
1820 | return 0; | |
1821 | } | |
1822 | ||
1823 | static int intel_860_configure(void) | |
1824 | { | |
1825 | u32 temp; | |
1826 | u16 temp2; | |
1827 | struct aper_size_info_8 *current_size; | |
1828 | ||
1829 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1830 | ||
1831 | /* aperture size */ | |
1832 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1833 | ||
1834 | /* address to map to */ | |
1835 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1836 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1837 | ||
1838 | /* attbase - aperture base */ | |
1839 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1840 | ||
1841 | /* agpctrl */ | |
1842 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1843 | ||
1844 | /* mcgcfg */ | |
1845 | pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); | |
1846 | pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); | |
1847 | /* clear any possible AGP-related error conditions */ | |
1848 | pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); | |
1849 | return 0; | |
1850 | } | |
1851 | ||
1852 | static int intel_830mp_configure(void) | |
1853 | { | |
1854 | u32 temp; | |
1855 | u16 temp2; | |
1856 | struct aper_size_info_8 *current_size; | |
1857 | ||
1858 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1859 | ||
1860 | /* aperture size */ | |
1861 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1862 | ||
1863 | /* address to map to */ | |
1864 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1865 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1866 | ||
1867 | /* attbase - aperture base */ | |
1868 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1869 | ||
1870 | /* agpctrl */ | |
1871 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1872 | ||
1873 | /* gmch */ | |
1874 | pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); | |
1875 | pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); | |
1876 | /* clear any possible AGP-related error conditions */ | |
1877 | pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); | |
1878 | return 0; | |
1879 | } | |
1880 | ||
1881 | static int intel_7505_configure(void) | |
1882 | { | |
1883 | u32 temp; | |
1884 | u16 temp2; | |
1885 | struct aper_size_info_8 *current_size; | |
1886 | ||
1887 | current_size = A_SIZE_8(agp_bridge->current_size); | |
1888 | ||
1889 | /* aperture size */ | |
1890 | pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); | |
1891 | ||
1892 | /* address to map to */ | |
1893 | pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); | |
1894 | agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); | |
1895 | ||
1896 | /* attbase - aperture base */ | |
1897 | pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); | |
1898 | ||
1899 | /* agpctrl */ | |
1900 | pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); | |
1901 | ||
1902 | /* mchcfg */ | |
1903 | pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); | |
1904 | pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); | |
1905 | ||
1906 | return 0; | |
1907 | } | |
1908 | ||
1909 | /* Setup function */ | |
e5524f35 | 1910 | static const struct gatt_mask intel_generic_masks[] = |
1da177e4 LT |
1911 | { |
1912 | {.mask = 0x00000017, .type = 0} | |
1913 | }; | |
1914 | ||
e5524f35 | 1915 | static const struct aper_size_info_8 intel_815_sizes[2] = |
1da177e4 LT |
1916 | { |
1917 | {64, 16384, 4, 0}, | |
1918 | {32, 8192, 3, 8}, | |
1919 | }; | |
1920 | ||
e5524f35 | 1921 | static const struct aper_size_info_8 intel_8xx_sizes[7] = |
1da177e4 LT |
1922 | { |
1923 | {256, 65536, 6, 0}, | |
1924 | {128, 32768, 5, 32}, | |
1925 | {64, 16384, 4, 48}, | |
1926 | {32, 8192, 3, 56}, | |
1927 | {16, 4096, 2, 60}, | |
1928 | {8, 2048, 1, 62}, | |
1929 | {4, 1024, 0, 63} | |
1930 | }; | |
1931 | ||
e5524f35 | 1932 | static const struct aper_size_info_16 intel_generic_sizes[7] = |
1da177e4 LT |
1933 | { |
1934 | {256, 65536, 6, 0}, | |
1935 | {128, 32768, 5, 32}, | |
1936 | {64, 16384, 4, 48}, | |
1937 | {32, 8192, 3, 56}, | |
1938 | {16, 4096, 2, 60}, | |
1939 | {8, 2048, 1, 62}, | |
1940 | {4, 1024, 0, 63} | |
1941 | }; | |
1942 | ||
e5524f35 | 1943 | static const struct aper_size_info_8 intel_830mp_sizes[4] = |
1da177e4 LT |
1944 | { |
1945 | {256, 65536, 6, 0}, | |
1946 | {128, 32768, 5, 32}, | |
1947 | {64, 16384, 4, 48}, | |
1948 | {32, 8192, 3, 56} | |
1949 | }; | |
1950 | ||
e5524f35 | 1951 | static const struct agp_bridge_driver intel_generic_driver = { |
1da177e4 LT |
1952 | .owner = THIS_MODULE, |
1953 | .aperture_sizes = intel_generic_sizes, | |
1954 | .size_type = U16_APER_SIZE, | |
1955 | .num_aperture_sizes = 7, | |
1956 | .configure = intel_configure, | |
1957 | .fetch_size = intel_fetch_size, | |
1958 | .cleanup = intel_cleanup, | |
1959 | .tlb_flush = intel_tlbflush, | |
1960 | .mask_memory = agp_generic_mask_memory, | |
1961 | .masks = intel_generic_masks, | |
1962 | .agp_enable = agp_generic_enable, | |
1963 | .cache_flush = global_cache_flush, | |
1964 | .create_gatt_table = agp_generic_create_gatt_table, | |
1965 | .free_gatt_table = agp_generic_free_gatt_table, | |
1966 | .insert_memory = agp_generic_insert_memory, | |
1967 | .remove_memory = agp_generic_remove_memory, | |
1968 | .alloc_by_type = agp_generic_alloc_by_type, | |
1969 | .free_by_type = agp_generic_free_by_type, | |
1970 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1971 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1972 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 1973 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 1974 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
1975 | }; |
1976 | ||
e5524f35 | 1977 | static const struct agp_bridge_driver intel_810_driver = { |
1da177e4 LT |
1978 | .owner = THIS_MODULE, |
1979 | .aperture_sizes = intel_i810_sizes, | |
1980 | .size_type = FIXED_APER_SIZE, | |
1981 | .num_aperture_sizes = 2, | |
c7258012 | 1982 | .needs_scratch_page = true, |
1da177e4 LT |
1983 | .configure = intel_i810_configure, |
1984 | .fetch_size = intel_i810_fetch_size, | |
1985 | .cleanup = intel_i810_cleanup, | |
1986 | .tlb_flush = intel_i810_tlbflush, | |
1987 | .mask_memory = intel_i810_mask_memory, | |
1988 | .masks = intel_i810_masks, | |
1989 | .agp_enable = intel_i810_agp_enable, | |
1990 | .cache_flush = global_cache_flush, | |
1991 | .create_gatt_table = agp_generic_create_gatt_table, | |
1992 | .free_gatt_table = agp_generic_free_gatt_table, | |
1993 | .insert_memory = intel_i810_insert_entries, | |
1994 | .remove_memory = intel_i810_remove_entries, | |
1995 | .alloc_by_type = intel_i810_alloc_by_type, | |
1996 | .free_by_type = intel_i810_free_by_type, | |
1997 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 1998 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 1999 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2000 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2001 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2002 | }; |
2003 | ||
e5524f35 | 2004 | static const struct agp_bridge_driver intel_815_driver = { |
1da177e4 LT |
2005 | .owner = THIS_MODULE, |
2006 | .aperture_sizes = intel_815_sizes, | |
2007 | .size_type = U8_APER_SIZE, | |
2008 | .num_aperture_sizes = 2, | |
2009 | .configure = intel_815_configure, | |
2010 | .fetch_size = intel_815_fetch_size, | |
2011 | .cleanup = intel_8xx_cleanup, | |
2012 | .tlb_flush = intel_8xx_tlbflush, | |
2013 | .mask_memory = agp_generic_mask_memory, | |
2014 | .masks = intel_generic_masks, | |
2015 | .agp_enable = agp_generic_enable, | |
2016 | .cache_flush = global_cache_flush, | |
2017 | .create_gatt_table = agp_generic_create_gatt_table, | |
2018 | .free_gatt_table = agp_generic_free_gatt_table, | |
2019 | .insert_memory = agp_generic_insert_memory, | |
2020 | .remove_memory = agp_generic_remove_memory, | |
2021 | .alloc_by_type = agp_generic_alloc_by_type, | |
2022 | .free_by_type = agp_generic_free_by_type, | |
2023 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2024 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2025 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2026 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2027 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2028 | }; |
2029 | ||
e5524f35 | 2030 | static const struct agp_bridge_driver intel_830_driver = { |
1da177e4 LT |
2031 | .owner = THIS_MODULE, |
2032 | .aperture_sizes = intel_i830_sizes, | |
2033 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 2034 | .num_aperture_sizes = 4, |
c7258012 | 2035 | .needs_scratch_page = true, |
1da177e4 LT |
2036 | .configure = intel_i830_configure, |
2037 | .fetch_size = intel_i830_fetch_size, | |
2038 | .cleanup = intel_i830_cleanup, | |
2039 | .tlb_flush = intel_i810_tlbflush, | |
2040 | .mask_memory = intel_i810_mask_memory, | |
2041 | .masks = intel_i810_masks, | |
2042 | .agp_enable = intel_i810_agp_enable, | |
2043 | .cache_flush = global_cache_flush, | |
2044 | .create_gatt_table = intel_i830_create_gatt_table, | |
2045 | .free_gatt_table = intel_i830_free_gatt_table, | |
2046 | .insert_memory = intel_i830_insert_entries, | |
2047 | .remove_memory = intel_i830_remove_entries, | |
2048 | .alloc_by_type = intel_i830_alloc_by_type, | |
2049 | .free_by_type = intel_i810_free_by_type, | |
2050 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2051 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2052 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2053 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2054 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
2162e6a2 | 2055 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
2056 | }; |
2057 | ||
e5524f35 | 2058 | static const struct agp_bridge_driver intel_820_driver = { |
1da177e4 LT |
2059 | .owner = THIS_MODULE, |
2060 | .aperture_sizes = intel_8xx_sizes, | |
2061 | .size_type = U8_APER_SIZE, | |
2062 | .num_aperture_sizes = 7, | |
2063 | .configure = intel_820_configure, | |
2064 | .fetch_size = intel_8xx_fetch_size, | |
2065 | .cleanup = intel_820_cleanup, | |
2066 | .tlb_flush = intel_820_tlbflush, | |
2067 | .mask_memory = agp_generic_mask_memory, | |
2068 | .masks = intel_generic_masks, | |
2069 | .agp_enable = agp_generic_enable, | |
2070 | .cache_flush = global_cache_flush, | |
2071 | .create_gatt_table = agp_generic_create_gatt_table, | |
2072 | .free_gatt_table = agp_generic_free_gatt_table, | |
2073 | .insert_memory = agp_generic_insert_memory, | |
2074 | .remove_memory = agp_generic_remove_memory, | |
2075 | .alloc_by_type = agp_generic_alloc_by_type, | |
2076 | .free_by_type = agp_generic_free_by_type, | |
2077 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2078 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2079 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2080 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2081 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2082 | }; |
2083 | ||
e5524f35 | 2084 | static const struct agp_bridge_driver intel_830mp_driver = { |
1da177e4 LT |
2085 | .owner = THIS_MODULE, |
2086 | .aperture_sizes = intel_830mp_sizes, | |
2087 | .size_type = U8_APER_SIZE, | |
2088 | .num_aperture_sizes = 4, | |
2089 | .configure = intel_830mp_configure, | |
2090 | .fetch_size = intel_8xx_fetch_size, | |
2091 | .cleanup = intel_8xx_cleanup, | |
2092 | .tlb_flush = intel_8xx_tlbflush, | |
2093 | .mask_memory = agp_generic_mask_memory, | |
2094 | .masks = intel_generic_masks, | |
2095 | .agp_enable = agp_generic_enable, | |
2096 | .cache_flush = global_cache_flush, | |
2097 | .create_gatt_table = agp_generic_create_gatt_table, | |
2098 | .free_gatt_table = agp_generic_free_gatt_table, | |
2099 | .insert_memory = agp_generic_insert_memory, | |
2100 | .remove_memory = agp_generic_remove_memory, | |
2101 | .alloc_by_type = agp_generic_alloc_by_type, | |
2102 | .free_by_type = agp_generic_free_by_type, | |
2103 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2104 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2105 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2106 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2107 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2108 | }; |
2109 | ||
e5524f35 | 2110 | static const struct agp_bridge_driver intel_840_driver = { |
1da177e4 LT |
2111 | .owner = THIS_MODULE, |
2112 | .aperture_sizes = intel_8xx_sizes, | |
2113 | .size_type = U8_APER_SIZE, | |
2114 | .num_aperture_sizes = 7, | |
2115 | .configure = intel_840_configure, | |
2116 | .fetch_size = intel_8xx_fetch_size, | |
2117 | .cleanup = intel_8xx_cleanup, | |
2118 | .tlb_flush = intel_8xx_tlbflush, | |
2119 | .mask_memory = agp_generic_mask_memory, | |
2120 | .masks = intel_generic_masks, | |
2121 | .agp_enable = agp_generic_enable, | |
2122 | .cache_flush = global_cache_flush, | |
2123 | .create_gatt_table = agp_generic_create_gatt_table, | |
2124 | .free_gatt_table = agp_generic_free_gatt_table, | |
2125 | .insert_memory = agp_generic_insert_memory, | |
2126 | .remove_memory = agp_generic_remove_memory, | |
2127 | .alloc_by_type = agp_generic_alloc_by_type, | |
2128 | .free_by_type = agp_generic_free_by_type, | |
2129 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2130 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2131 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2132 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2133 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2134 | }; |
2135 | ||
e5524f35 | 2136 | static const struct agp_bridge_driver intel_845_driver = { |
1da177e4 LT |
2137 | .owner = THIS_MODULE, |
2138 | .aperture_sizes = intel_8xx_sizes, | |
2139 | .size_type = U8_APER_SIZE, | |
2140 | .num_aperture_sizes = 7, | |
2141 | .configure = intel_845_configure, | |
2142 | .fetch_size = intel_8xx_fetch_size, | |
2143 | .cleanup = intel_8xx_cleanup, | |
2144 | .tlb_flush = intel_8xx_tlbflush, | |
2145 | .mask_memory = agp_generic_mask_memory, | |
2146 | .masks = intel_generic_masks, | |
2147 | .agp_enable = agp_generic_enable, | |
2148 | .cache_flush = global_cache_flush, | |
2149 | .create_gatt_table = agp_generic_create_gatt_table, | |
2150 | .free_gatt_table = agp_generic_free_gatt_table, | |
2151 | .insert_memory = agp_generic_insert_memory, | |
2152 | .remove_memory = agp_generic_remove_memory, | |
2153 | .alloc_by_type = agp_generic_alloc_by_type, | |
2154 | .free_by_type = agp_generic_free_by_type, | |
2155 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2156 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2157 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2158 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2159 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
2162e6a2 | 2160 | .chipset_flush = intel_i830_chipset_flush, |
1da177e4 LT |
2161 | }; |
2162 | ||
e5524f35 | 2163 | static const struct agp_bridge_driver intel_850_driver = { |
1da177e4 LT |
2164 | .owner = THIS_MODULE, |
2165 | .aperture_sizes = intel_8xx_sizes, | |
2166 | .size_type = U8_APER_SIZE, | |
2167 | .num_aperture_sizes = 7, | |
2168 | .configure = intel_850_configure, | |
2169 | .fetch_size = intel_8xx_fetch_size, | |
2170 | .cleanup = intel_8xx_cleanup, | |
2171 | .tlb_flush = intel_8xx_tlbflush, | |
2172 | .mask_memory = agp_generic_mask_memory, | |
2173 | .masks = intel_generic_masks, | |
2174 | .agp_enable = agp_generic_enable, | |
2175 | .cache_flush = global_cache_flush, | |
2176 | .create_gatt_table = agp_generic_create_gatt_table, | |
2177 | .free_gatt_table = agp_generic_free_gatt_table, | |
2178 | .insert_memory = agp_generic_insert_memory, | |
2179 | .remove_memory = agp_generic_remove_memory, | |
2180 | .alloc_by_type = agp_generic_alloc_by_type, | |
2181 | .free_by_type = agp_generic_free_by_type, | |
2182 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2183 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2184 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2185 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2186 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2187 | }; |
2188 | ||
e5524f35 | 2189 | static const struct agp_bridge_driver intel_860_driver = { |
1da177e4 LT |
2190 | .owner = THIS_MODULE, |
2191 | .aperture_sizes = intel_8xx_sizes, | |
2192 | .size_type = U8_APER_SIZE, | |
2193 | .num_aperture_sizes = 7, | |
2194 | .configure = intel_860_configure, | |
2195 | .fetch_size = intel_8xx_fetch_size, | |
2196 | .cleanup = intel_8xx_cleanup, | |
2197 | .tlb_flush = intel_8xx_tlbflush, | |
2198 | .mask_memory = agp_generic_mask_memory, | |
2199 | .masks = intel_generic_masks, | |
2200 | .agp_enable = agp_generic_enable, | |
2201 | .cache_flush = global_cache_flush, | |
2202 | .create_gatt_table = agp_generic_create_gatt_table, | |
2203 | .free_gatt_table = agp_generic_free_gatt_table, | |
2204 | .insert_memory = agp_generic_insert_memory, | |
2205 | .remove_memory = agp_generic_remove_memory, | |
2206 | .alloc_by_type = agp_generic_alloc_by_type, | |
2207 | .free_by_type = agp_generic_free_by_type, | |
2208 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2209 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2210 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2211 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2212 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2213 | }; |
2214 | ||
e5524f35 | 2215 | static const struct agp_bridge_driver intel_915_driver = { |
1da177e4 LT |
2216 | .owner = THIS_MODULE, |
2217 | .aperture_sizes = intel_i830_sizes, | |
2218 | .size_type = FIXED_APER_SIZE, | |
c14635eb | 2219 | .num_aperture_sizes = 4, |
c7258012 | 2220 | .needs_scratch_page = true, |
1da177e4 | 2221 | .configure = intel_i915_configure, |
c41e0deb | 2222 | .fetch_size = intel_i9xx_fetch_size, |
1da177e4 LT |
2223 | .cleanup = intel_i915_cleanup, |
2224 | .tlb_flush = intel_i810_tlbflush, | |
2225 | .mask_memory = intel_i810_mask_memory, | |
2226 | .masks = intel_i810_masks, | |
2227 | .agp_enable = intel_i810_agp_enable, | |
2228 | .cache_flush = global_cache_flush, | |
2229 | .create_gatt_table = intel_i915_create_gatt_table, | |
2230 | .free_gatt_table = intel_i830_free_gatt_table, | |
2231 | .insert_memory = intel_i915_insert_entries, | |
2232 | .remove_memory = intel_i915_remove_entries, | |
2233 | .alloc_by_type = intel_i830_alloc_by_type, | |
2234 | .free_by_type = intel_i810_free_by_type, | |
2235 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2236 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2237 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2238 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2239 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2240 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2241 | #ifdef USE_PCI_DMA_API |
2242 | .agp_map_page = intel_agp_map_page, | |
2243 | .agp_unmap_page = intel_agp_unmap_page, | |
2244 | .agp_map_memory = intel_agp_map_memory, | |
2245 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2246 | #endif | |
1da177e4 LT |
2247 | }; |
2248 | ||
e5524f35 | 2249 | static const struct agp_bridge_driver intel_i965_driver = { |
62c96b9d DA |
2250 | .owner = THIS_MODULE, |
2251 | .aperture_sizes = intel_i830_sizes, | |
2252 | .size_type = FIXED_APER_SIZE, | |
2253 | .num_aperture_sizes = 4, | |
2254 | .needs_scratch_page = true, | |
0e480e5f DA |
2255 | .configure = intel_i915_configure, |
2256 | .fetch_size = intel_i9xx_fetch_size, | |
62c96b9d DA |
2257 | .cleanup = intel_i915_cleanup, |
2258 | .tlb_flush = intel_i810_tlbflush, | |
2259 | .mask_memory = intel_i965_mask_memory, | |
2260 | .masks = intel_i810_masks, | |
2261 | .agp_enable = intel_i810_agp_enable, | |
2262 | .cache_flush = global_cache_flush, | |
2263 | .create_gatt_table = intel_i965_create_gatt_table, | |
2264 | .free_gatt_table = intel_i830_free_gatt_table, | |
2265 | .insert_memory = intel_i915_insert_entries, | |
2266 | .remove_memory = intel_i915_remove_entries, | |
2267 | .alloc_by_type = intel_i830_alloc_by_type, | |
2268 | .free_by_type = intel_i810_free_by_type, | |
2269 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2270 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2271 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2272 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2273 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2274 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2275 | #ifdef USE_PCI_DMA_API |
2276 | .agp_map_page = intel_agp_map_page, | |
2277 | .agp_unmap_page = intel_agp_unmap_page, | |
2278 | .agp_map_memory = intel_agp_map_memory, | |
2279 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2280 | #endif | |
65c25aad | 2281 | }; |
1da177e4 | 2282 | |
e5524f35 | 2283 | static const struct agp_bridge_driver intel_7505_driver = { |
1da177e4 LT |
2284 | .owner = THIS_MODULE, |
2285 | .aperture_sizes = intel_8xx_sizes, | |
2286 | .size_type = U8_APER_SIZE, | |
2287 | .num_aperture_sizes = 7, | |
2288 | .configure = intel_7505_configure, | |
2289 | .fetch_size = intel_8xx_fetch_size, | |
2290 | .cleanup = intel_8xx_cleanup, | |
2291 | .tlb_flush = intel_8xx_tlbflush, | |
2292 | .mask_memory = agp_generic_mask_memory, | |
2293 | .masks = intel_generic_masks, | |
2294 | .agp_enable = agp_generic_enable, | |
2295 | .cache_flush = global_cache_flush, | |
2296 | .create_gatt_table = agp_generic_create_gatt_table, | |
2297 | .free_gatt_table = agp_generic_free_gatt_table, | |
2298 | .insert_memory = agp_generic_insert_memory, | |
2299 | .remove_memory = agp_generic_remove_memory, | |
2300 | .alloc_by_type = agp_generic_alloc_by_type, | |
2301 | .free_by_type = agp_generic_free_by_type, | |
2302 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2303 | .agp_alloc_pages = agp_generic_alloc_pages, |
1da177e4 | 2304 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2305 | .agp_destroy_pages = agp_generic_destroy_pages, |
a030ce44 | 2306 | .agp_type_to_mask_type = agp_generic_type_to_mask_type, |
1da177e4 LT |
2307 | }; |
2308 | ||
874808c6 | 2309 | static const struct agp_bridge_driver intel_g33_driver = { |
62c96b9d DA |
2310 | .owner = THIS_MODULE, |
2311 | .aperture_sizes = intel_i830_sizes, | |
2312 | .size_type = FIXED_APER_SIZE, | |
2313 | .num_aperture_sizes = 4, | |
2314 | .needs_scratch_page = true, | |
2315 | .configure = intel_i915_configure, | |
2316 | .fetch_size = intel_i9xx_fetch_size, | |
2317 | .cleanup = intel_i915_cleanup, | |
2318 | .tlb_flush = intel_i810_tlbflush, | |
2319 | .mask_memory = intel_i965_mask_memory, | |
2320 | .masks = intel_i810_masks, | |
2321 | .agp_enable = intel_i810_agp_enable, | |
2322 | .cache_flush = global_cache_flush, | |
2323 | .create_gatt_table = intel_i915_create_gatt_table, | |
2324 | .free_gatt_table = intel_i830_free_gatt_table, | |
2325 | .insert_memory = intel_i915_insert_entries, | |
2326 | .remove_memory = intel_i915_remove_entries, | |
2327 | .alloc_by_type = intel_i830_alloc_by_type, | |
2328 | .free_by_type = intel_i810_free_by_type, | |
2329 | .agp_alloc_page = agp_generic_alloc_page, | |
37acee10 | 2330 | .agp_alloc_pages = agp_generic_alloc_pages, |
62c96b9d | 2331 | .agp_destroy_page = agp_generic_destroy_page, |
bd07928c | 2332 | .agp_destroy_pages = agp_generic_destroy_pages, |
62c96b9d | 2333 | .agp_type_to_mask_type = intel_i830_type_to_mask_type, |
6c00a61e | 2334 | .chipset_flush = intel_i915_chipset_flush, |
17661681 ZW |
2335 | #ifdef USE_PCI_DMA_API |
2336 | .agp_map_page = intel_agp_map_page, | |
2337 | .agp_unmap_page = intel_agp_unmap_page, | |
2338 | .agp_map_memory = intel_agp_map_memory, | |
2339 | .agp_unmap_memory = intel_agp_unmap_memory, | |
2340 | #endif | |
874808c6 | 2341 | }; |
1da177e4 | 2342 | |
9614ece1 | 2343 | static int find_gmch(u16 device) |
1da177e4 | 2344 | { |
9614ece1 | 2345 | struct pci_dev *gmch_device; |
1da177e4 | 2346 | |
9614ece1 WZ |
2347 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
2348 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { | |
2349 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, | |
f011ae74 | 2350 | device, gmch_device); |
1da177e4 LT |
2351 | } |
2352 | ||
9614ece1 | 2353 | if (!gmch_device) |
1da177e4 LT |
2354 | return 0; |
2355 | ||
9614ece1 | 2356 | intel_private.pcidev = gmch_device; |
1da177e4 LT |
2357 | return 1; |
2358 | } | |
2359 | ||
9614ece1 WZ |
2360 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
2361 | * driver and gmch_driver must be non-null, and find_gmch will determine | |
2362 | * which one should be used if a gmch_chip_id is present. | |
2363 | */ | |
2364 | static const struct intel_driver_description { | |
2365 | unsigned int chip_id; | |
2366 | unsigned int gmch_chip_id; | |
88889851 | 2367 | unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */ |
9614ece1 WZ |
2368 | char *name; |
2369 | const struct agp_bridge_driver *driver; | |
2370 | const struct agp_bridge_driver *gmch_driver; | |
2371 | } intel_agp_chipsets[] = { | |
88889851 WZ |
2372 | { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL }, |
2373 | { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL }, | |
2374 | { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL }, | |
2375 | { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810", | |
9614ece1 | 2376 | NULL, &intel_810_driver }, |
88889851 | 2377 | { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810", |
9614ece1 | 2378 | NULL, &intel_810_driver }, |
88889851 | 2379 | { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810", |
9614ece1 | 2380 | NULL, &intel_810_driver }, |
88889851 WZ |
2381 | { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815", |
2382 | &intel_815_driver, &intel_810_driver }, | |
2383 | { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2384 | { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL }, | |
2385 | { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M", | |
9614ece1 | 2386 | &intel_830mp_driver, &intel_830_driver }, |
88889851 WZ |
2387 | { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL }, |
2388 | { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL }, | |
2389 | { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M", | |
9614ece1 | 2390 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2391 | { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL }, |
347486bb SH |
2392 | { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854", |
2393 | &intel_845_driver, &intel_830_driver }, | |
88889851 WZ |
2394 | { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL }, |
2395 | { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM", | |
9614ece1 | 2396 | &intel_845_driver, &intel_830_driver }, |
88889851 WZ |
2397 | { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL }, |
2398 | { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865", | |
9614ece1 | 2399 | &intel_845_driver, &intel_830_driver }, |
88889851 | 2400 | { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL }, |
e914a36a CM |
2401 | { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)", |
2402 | NULL, &intel_915_driver }, | |
88889851 | 2403 | { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G", |
47d46379 | 2404 | NULL, &intel_915_driver }, |
88889851 | 2405 | { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM", |
47d46379 | 2406 | NULL, &intel_915_driver }, |
88889851 | 2407 | { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G", |
47d46379 | 2408 | NULL, &intel_915_driver }, |
dde47876 | 2409 | { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM", |
47d46379 | 2410 | NULL, &intel_915_driver }, |
dde47876 | 2411 | { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME", |
47d46379 | 2412 | NULL, &intel_915_driver }, |
88889851 | 2413 | { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ", |
47d46379 | 2414 | NULL, &intel_i965_driver }, |
9119f85a | 2415 | { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35", |
47d46379 | 2416 | NULL, &intel_i965_driver }, |
88889851 | 2417 | { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q", |
47d46379 | 2418 | NULL, &intel_i965_driver }, |
88889851 | 2419 | { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G", |
47d46379 | 2420 | NULL, &intel_i965_driver }, |
dde47876 | 2421 | { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM", |
47d46379 | 2422 | NULL, &intel_i965_driver }, |
dde47876 | 2423 | { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE", |
47d46379 | 2424 | NULL, &intel_i965_driver }, |
88889851 WZ |
2425 | { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL }, |
2426 | { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL }, | |
2427 | { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33", | |
47d46379 | 2428 | NULL, &intel_g33_driver }, |
88889851 | 2429 | { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35", |
47d46379 | 2430 | NULL, &intel_g33_driver }, |
88889851 | 2431 | { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33", |
47d46379 | 2432 | NULL, &intel_g33_driver }, |
af86d4b0 | 2433 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, 0, "GMA3150", |
2177832f | 2434 | NULL, &intel_g33_driver }, |
af86d4b0 | 2435 | { PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, 0, "GMA3150", |
2177832f | 2436 | NULL, &intel_g33_driver }, |
99d32bd5 | 2437 | { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0, |
107f517b AJ |
2438 | "GM45", NULL, &intel_i965_driver }, |
2439 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, 0, | |
2440 | "Eaglelake", NULL, &intel_i965_driver }, | |
25ce77ab ZW |
2441 | { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0, |
2442 | "Q45/Q43", NULL, &intel_i965_driver }, | |
2443 | { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0, | |
2444 | "G45/G43", NULL, &intel_i965_driver }, | |
38d8a956 FH |
2445 | { PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG, 0, |
2446 | "B43", NULL, &intel_i965_driver }, | |
a50ccc6c ZW |
2447 | { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0, |
2448 | "G41", NULL, &intel_i965_driver }, | |
107f517b | 2449 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 0, |
af86d4b0 | 2450 | "HD Graphics", NULL, &intel_i965_driver }, |
107f517b | 2451 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, |
af86d4b0 | 2452 | "HD Graphics", NULL, &intel_i965_driver }, |
107f517b | 2453 | { PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, |
af86d4b0 | 2454 | "HD Graphics", NULL, &intel_i965_driver }, |
3ff99164 | 2455 | { PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 0, |
af86d4b0 | 2456 | "HD Graphics", NULL, &intel_i965_driver }, |
1089e300 EA |
2457 | { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_IG, 0, |
2458 | "Sandybridge", NULL, &intel_i965_driver }, | |
88889851 | 2459 | { 0, 0, 0, NULL, NULL, NULL } |
9614ece1 WZ |
2460 | }; |
2461 | ||
1da177e4 LT |
2462 | static int __devinit agp_intel_probe(struct pci_dev *pdev, |
2463 | const struct pci_device_id *ent) | |
2464 | { | |
2465 | struct agp_bridge_data *bridge; | |
1da177e4 LT |
2466 | u8 cap_ptr = 0; |
2467 | struct resource *r; | |
9614ece1 | 2468 | int i; |
1da177e4 LT |
2469 | |
2470 | cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); | |
2471 | ||
2472 | bridge = agp_alloc_bridge(); | |
2473 | if (!bridge) | |
2474 | return -ENOMEM; | |
2475 | ||
9614ece1 WZ |
2476 | for (i = 0; intel_agp_chipsets[i].name != NULL; i++) { |
2477 | /* In case that multiple models of gfx chip may | |
2478 | stand on same host bridge type, this can be | |
2479 | sure we detect the right IGD. */ | |
88889851 WZ |
2480 | if (pdev->device == intel_agp_chipsets[i].chip_id) { |
2481 | if ((intel_agp_chipsets[i].gmch_chip_id != 0) && | |
2482 | find_gmch(intel_agp_chipsets[i].gmch_chip_id)) { | |
2483 | bridge->driver = | |
2484 | intel_agp_chipsets[i].gmch_driver; | |
2485 | break; | |
2486 | } else if (intel_agp_chipsets[i].multi_gmch_chip) { | |
2487 | continue; | |
2488 | } else { | |
2489 | bridge->driver = intel_agp_chipsets[i].driver; | |
2490 | break; | |
2491 | } | |
2492 | } | |
9614ece1 WZ |
2493 | } |
2494 | ||
2495 | if (intel_agp_chipsets[i].name == NULL) { | |
1da177e4 | 2496 | if (cap_ptr) |
e3cf6951 BH |
2497 | dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", |
2498 | pdev->vendor, pdev->device); | |
9614ece1 WZ |
2499 | agp_put_bridge(bridge); |
2500 | return -ENODEV; | |
2501 | } | |
2502 | ||
9614ece1 | 2503 | if (bridge->driver == NULL) { |
47d46379 WZ |
2504 | /* bridge has no AGP and no IGD detected */ |
2505 | if (cap_ptr) | |
e3cf6951 BH |
2506 | dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n", |
2507 | intel_agp_chipsets[i].gmch_chip_id); | |
1da177e4 LT |
2508 | agp_put_bridge(bridge); |
2509 | return -ENODEV; | |
f011ae74 | 2510 | } |
1da177e4 LT |
2511 | |
2512 | bridge->dev = pdev; | |
2513 | bridge->capndx = cap_ptr; | |
c4ca8817 | 2514 | bridge->dev_private_data = &intel_private; |
1da177e4 | 2515 | |
e3cf6951 | 2516 | dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name); |
1da177e4 LT |
2517 | |
2518 | /* | |
2519 | * The following fixes the case where the BIOS has "forgotten" to | |
2520 | * provide an address range for the GART. | |
2521 | * 20030610 - hamish@zot.org | |
2522 | */ | |
2523 | r = &pdev->resource[0]; | |
2524 | if (!r->start && r->end) { | |
6a92a4e0 | 2525 | if (pci_assign_resource(pdev, 0)) { |
e3cf6951 | 2526 | dev_err(&pdev->dev, "can't assign resource 0\n"); |
1da177e4 LT |
2527 | agp_put_bridge(bridge); |
2528 | return -ENODEV; | |
2529 | } | |
2530 | } | |
2531 | ||
2532 | /* | |
2533 | * If the device has not been properly setup, the following will catch | |
2534 | * the problem and should stop the system from crashing. | |
2535 | * 20030610 - hamish@zot.org | |
2536 | */ | |
2537 | if (pci_enable_device(pdev)) { | |
e3cf6951 | 2538 | dev_err(&pdev->dev, "can't enable PCI device\n"); |
1da177e4 LT |
2539 | agp_put_bridge(bridge); |
2540 | return -ENODEV; | |
2541 | } | |
2542 | ||
2543 | /* Fill in the mode register */ | |
2544 | if (cap_ptr) { | |
2545 | pci_read_config_dword(pdev, | |
2546 | bridge->capndx+PCI_AGP_STATUS, | |
2547 | &bridge->mode); | |
2548 | } | |
2549 | ||
9b974cc1 | 2550 | if (bridge->driver->mask_memory == intel_i965_mask_memory) { |
ec402ba9 DW |
2551 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(36))) |
2552 | dev_err(&intel_private.pcidev->dev, | |
2553 | "set gfx device dma mask 36bit failed!\n"); | |
9b974cc1 ZW |
2554 | else |
2555 | pci_set_consistent_dma_mask(intel_private.pcidev, | |
2556 | DMA_BIT_MASK(36)); | |
2557 | } | |
ec402ba9 | 2558 | |
1da177e4 LT |
2559 | pci_set_drvdata(pdev, bridge); |
2560 | return agp_add_bridge(bridge); | |
1da177e4 LT |
2561 | } |
2562 | ||
2563 | static void __devexit agp_intel_remove(struct pci_dev *pdev) | |
2564 | { | |
2565 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
2566 | ||
2567 | agp_remove_bridge(bridge); | |
2568 | ||
c4ca8817 WZ |
2569 | if (intel_private.pcidev) |
2570 | pci_dev_put(intel_private.pcidev); | |
1da177e4 LT |
2571 | |
2572 | agp_put_bridge(bridge); | |
2573 | } | |
2574 | ||
85be7d60 | 2575 | #ifdef CONFIG_PM |
1da177e4 LT |
2576 | static int agp_intel_resume(struct pci_dev *pdev) |
2577 | { | |
2578 | struct agp_bridge_data *bridge = pci_get_drvdata(pdev); | |
a8c84df9 | 2579 | int ret_val; |
1da177e4 | 2580 | |
1da177e4 LT |
2581 | if (bridge->driver == &intel_generic_driver) |
2582 | intel_configure(); | |
2583 | else if (bridge->driver == &intel_850_driver) | |
2584 | intel_850_configure(); | |
2585 | else if (bridge->driver == &intel_845_driver) | |
2586 | intel_845_configure(); | |
2587 | else if (bridge->driver == &intel_830mp_driver) | |
2588 | intel_830mp_configure(); | |
2589 | else if (bridge->driver == &intel_915_driver) | |
2590 | intel_i915_configure(); | |
2591 | else if (bridge->driver == &intel_830_driver) | |
2592 | intel_i830_configure(); | |
2593 | else if (bridge->driver == &intel_810_driver) | |
2594 | intel_i810_configure(); | |
08da3f41 DJ |
2595 | else if (bridge->driver == &intel_i965_driver) |
2596 | intel_i915_configure(); | |
1da177e4 | 2597 | |
a8c84df9 KP |
2598 | ret_val = agp_rebind_memory(); |
2599 | if (ret_val != 0) | |
2600 | return ret_val; | |
2601 | ||
1da177e4 LT |
2602 | return 0; |
2603 | } | |
85be7d60 | 2604 | #endif |
1da177e4 LT |
2605 | |
2606 | static struct pci_device_id agp_intel_pci_table[] = { | |
2607 | #define ID(x) \ | |
2608 | { \ | |
2609 | .class = (PCI_CLASS_BRIDGE_HOST << 8), \ | |
2610 | .class_mask = ~0, \ | |
2611 | .vendor = PCI_VENDOR_ID_INTEL, \ | |
2612 | .device = x, \ | |
2613 | .subvendor = PCI_ANY_ID, \ | |
2614 | .subdevice = PCI_ANY_ID, \ | |
2615 | } | |
2616 | ID(PCI_DEVICE_ID_INTEL_82443LX_0), | |
2617 | ID(PCI_DEVICE_ID_INTEL_82443BX_0), | |
2618 | ID(PCI_DEVICE_ID_INTEL_82443GX_0), | |
2619 | ID(PCI_DEVICE_ID_INTEL_82810_MC1), | |
2620 | ID(PCI_DEVICE_ID_INTEL_82810_MC3), | |
2621 | ID(PCI_DEVICE_ID_INTEL_82810E_MC), | |
2622 | ID(PCI_DEVICE_ID_INTEL_82815_MC), | |
2623 | ID(PCI_DEVICE_ID_INTEL_82820_HB), | |
2624 | ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), | |
2625 | ID(PCI_DEVICE_ID_INTEL_82830_HB), | |
2626 | ID(PCI_DEVICE_ID_INTEL_82840_HB), | |
2627 | ID(PCI_DEVICE_ID_INTEL_82845_HB), | |
2628 | ID(PCI_DEVICE_ID_INTEL_82845G_HB), | |
2629 | ID(PCI_DEVICE_ID_INTEL_82850_HB), | |
347486bb | 2630 | ID(PCI_DEVICE_ID_INTEL_82854_HB), |
1da177e4 LT |
2631 | ID(PCI_DEVICE_ID_INTEL_82855PM_HB), |
2632 | ID(PCI_DEVICE_ID_INTEL_82855GM_HB), | |
2633 | ID(PCI_DEVICE_ID_INTEL_82860_HB), | |
2634 | ID(PCI_DEVICE_ID_INTEL_82865_HB), | |
2635 | ID(PCI_DEVICE_ID_INTEL_82875_HB), | |
2636 | ID(PCI_DEVICE_ID_INTEL_7505_0), | |
2637 | ID(PCI_DEVICE_ID_INTEL_7205_0), | |
e914a36a | 2638 | ID(PCI_DEVICE_ID_INTEL_E7221_HB), |
1da177e4 LT |
2639 | ID(PCI_DEVICE_ID_INTEL_82915G_HB), |
2640 | ID(PCI_DEVICE_ID_INTEL_82915GM_HB), | |
d0de98fa | 2641 | ID(PCI_DEVICE_ID_INTEL_82945G_HB), |
3b0e8ead | 2642 | ID(PCI_DEVICE_ID_INTEL_82945GM_HB), |
dde47876 | 2643 | ID(PCI_DEVICE_ID_INTEL_82945GME_HB), |
107f517b AJ |
2644 | ID(PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB), |
2645 | ID(PCI_DEVICE_ID_INTEL_PINEVIEW_HB), | |
65c25aad | 2646 | ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), |
9119f85a | 2647 | ID(PCI_DEVICE_ID_INTEL_82G35_HB), |
65c25aad EA |
2648 | ID(PCI_DEVICE_ID_INTEL_82965Q_HB), |
2649 | ID(PCI_DEVICE_ID_INTEL_82965G_HB), | |
4598af33 | 2650 | ID(PCI_DEVICE_ID_INTEL_82965GM_HB), |
dde47876 | 2651 | ID(PCI_DEVICE_ID_INTEL_82965GME_HB), |
874808c6 WZ |
2652 | ID(PCI_DEVICE_ID_INTEL_G33_HB), |
2653 | ID(PCI_DEVICE_ID_INTEL_Q35_HB), | |
2654 | ID(PCI_DEVICE_ID_INTEL_Q33_HB), | |
99d32bd5 | 2655 | ID(PCI_DEVICE_ID_INTEL_GM45_HB), |
107f517b | 2656 | ID(PCI_DEVICE_ID_INTEL_EAGLELAKE_HB), |
25ce77ab ZW |
2657 | ID(PCI_DEVICE_ID_INTEL_Q45_HB), |
2658 | ID(PCI_DEVICE_ID_INTEL_G45_HB), | |
a50ccc6c | 2659 | ID(PCI_DEVICE_ID_INTEL_G41_HB), |
38d8a956 | 2660 | ID(PCI_DEVICE_ID_INTEL_B43_HB), |
107f517b AJ |
2661 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB), |
2662 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB), | |
2663 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB), | |
3ff99164 | 2664 | ID(PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB), |
1089e300 | 2665 | ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), |
1da177e4 LT |
2666 | { } |
2667 | }; | |
2668 | ||
2669 | MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); | |
2670 | ||
2671 | static struct pci_driver agp_intel_pci_driver = { | |
2672 | .name = "agpgart-intel", | |
2673 | .id_table = agp_intel_pci_table, | |
2674 | .probe = agp_intel_probe, | |
2675 | .remove = __devexit_p(agp_intel_remove), | |
85be7d60 | 2676 | #ifdef CONFIG_PM |
1da177e4 | 2677 | .resume = agp_intel_resume, |
85be7d60 | 2678 | #endif |
1da177e4 LT |
2679 | }; |
2680 | ||
2681 | static int __init agp_intel_init(void) | |
2682 | { | |
2683 | if (agp_off) | |
2684 | return -EINVAL; | |
2685 | return pci_register_driver(&agp_intel_pci_driver); | |
2686 | } | |
2687 | ||
2688 | static void __exit agp_intel_cleanup(void) | |
2689 | { | |
2690 | pci_unregister_driver(&agp_intel_pci_driver); | |
2691 | } | |
2692 | ||
2693 | module_init(agp_intel_init); | |
2694 | module_exit(agp_intel_cleanup); | |
2695 | ||
f4432c5c | 2696 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
1da177e4 | 2697 | MODULE_LICENSE("GPL and additional rights"); |