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sata_sil24: separate out sil24_do_softreset()
[net-next-2.6.git] / drivers / ata / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667 30#include <linux/libata.h>
edb33667
TH		 31
32#define DRV_NAME "sata_sil24"
8bc3fc47 33#define DRV_VERSION "0.9"
edb33667 34
edb33667
TH		 35/*
36 * Port request block (PRB) 32 bytes
37 */
38struct sil24_prb {
b4772574
AD		 39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
edb33667
TH		 42 u8 fis[6 * 4];
43};
44
45/*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48struct sil24_sge {
b4772574
AD		 49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
edb33667
TH		 52};
53
54/*
55 * Port multiplier
56 */
57struct sil24_port_multiplier {
b4772574
AD		 58 __le32 diag;
59 __le32 sactive;
edb33667
TH		 60};
61
62enum {
0d5ff566
TH		 63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
edb33667
TH		 66 /*
67 * Global controller registers (128 bytes @ BAR0)
68 */
69 /* 32 bit regs */
70 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
71 HOST_CTRL = 0x40,
72 HOST_IRQ_STAT = 0x44,
73 HOST_PHY_CFG = 0x48,
74 HOST_BIST_CTRL = 0x50,
75 HOST_BIST_PTRN = 0x54,
76 HOST_BIST_STAT = 0x58,
77 HOST_MEM_BIST_STAT = 0x5c,
78 HOST_FLASH_CMD = 0x70,
79 /* 8 bit regs */
80 HOST_FLASH_DATA = 0x74,
81 HOST_TRANSITION_DETECT = 0x75,
82 HOST_GPIO_CTRL = 0x76,
83 HOST_I2C_ADDR = 0x78, /* 32 bit */
84 HOST_I2C_DATA = 0x7c,
85 HOST_I2C_XFER_CNT = 0x7e,
86 HOST_I2C_CTRL = 0x7f,
87
88 /* HOST_SLOT_STAT bits */
89 HOST_SSTAT_ATTN = (1 << 31),
90
7dafc3fd
TH		 91 /* HOST_CTRL bits */
92 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
93 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
94 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
95 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
96 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
d2298dca 97 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
7dafc3fd 98
edb33667
TH		 99 /*
100 * Port registers
101 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
102 */
103 PORT_REGS_SIZE = 0x2000,
135da345 104
28c8f3b4 105 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
135da345 106 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
edb33667 107
28c8f3b4 108 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
c0c55908
TH		 109 PORT_PMP_STATUS = 0x0000, /* port device status offset */
110 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
111 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112
edb33667 113 /* 32 bit regs */
83bbecc9
TH		 114 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
115 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
116 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
117 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
118 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 119 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 120 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
121 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 122 PORT_FIS_CFG = 0x1028,
123 PORT_FIFO_THRES = 0x102c,
124 /* 16 bit regs */
125 PORT_DECODE_ERR_CNT = 0x1040,
126 PORT_DECODE_ERR_THRESH = 0x1042,
127 PORT_CRC_ERR_CNT = 0x1044,
128 PORT_CRC_ERR_THRESH = 0x1046,
129 PORT_HSHK_ERR_CNT = 0x1048,
130 PORT_HSHK_ERR_THRESH = 0x104a,
131 /* 32 bit regs */
132 PORT_PHY_CFG = 0x1050,
133 PORT_SLOT_STAT = 0x1800,
134 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
c0c55908 135 PORT_CONTEXT = 0x1e04,
edb33667
TH		 136 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
137 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
138 PORT_SCONTROL = 0x1f00,
139 PORT_SSTATUS = 0x1f04,
140 PORT_SERROR = 0x1f08,
141 PORT_SACTIVE = 0x1f0c,
142
143 /* PORT_CTRL_STAT bits */
144 PORT_CS_PORT_RST = (1 << 0), /* port reset */
145 PORT_CS_DEV_RST = (1 << 1), /* device reset */
146 PORT_CS_INIT = (1 << 2), /* port initialize */
147 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 148 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
28c8f3b4 149 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
e382eb1d 150 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
28c8f3b4 151 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
e382eb1d 152 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 153
154 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
155 /* bits[11:0] are masked */
156 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
157 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
158 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
159 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
160 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
161 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
7dafc3fd
TH		 162 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
163 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
164 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
165 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
166 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
3b9f1d0f 167 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
edb33667 168
88ce7550 169 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
0542925b
TH		 170 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 PORT_IRQ_UNK_FIS,
88ce7550 172
edb33667
TH		 173 /* bits[27:16] are unmasked (raw) */
174 PORT_IRQ_RAW_SHIFT = 16,
175 PORT_IRQ_MASKED_MASK = 0x7ff,
176 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
177
178 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
179 PORT_IRQ_STEER_SHIFT = 30,
180 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
181
182 /* PORT_CMD_ERR constants */
183 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
184 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
185 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
186 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
187 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
188 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
189 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
190 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
191 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
192 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
193 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
194 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
195 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
196 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
197 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
198 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
199 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
200 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
201 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
64008802 202 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
edb33667 203 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 204 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 205
d10cb35a
TH		 206 /* bits of PRB control field */
207 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
208 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
209 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
210 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
211 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
212
213 /* PRB protocol field */
214 PRB_PROT_PACKET = (1 << 0),
215 PRB_PROT_TCQ = (1 << 1),
216 PRB_PROT_NCQ = (1 << 2),
217 PRB_PROT_READ = (1 << 3),
218 PRB_PROT_WRITE = (1 << 4),
219 PRB_PROT_TRANSPARENT = (1 << 5),
220
edb33667
TH		 221 /*
222 * Other constants
223 */
224 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 225 SGE_LNK = (1 << 30), /* linked list
226 Points to SGT, not SGE */
227 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
228 data address ignored */
edb33667 229
aee10a03
TH		 230 SIL24_MAX_CMDS = 31,
231
edb33667
TH		 232 /* board id */
233 BID_SIL3124 = 0,
234 BID_SIL3132 = 1,
042c21fd 235 BID_SIL3131 = 2,
edb33667 236
9466d85b
TH		 237 /* host flags */
238 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
aee10a03 239 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
3cadbcc0
TH		 240 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY |
241 ATA_FLAG_ACPI_SATA,
37024e8e 242 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
9466d85b 243
edb33667
TH		 244 IRQ_STAT_4PORTS = 0xf,
245};
246
69ad185f 247struct sil24_ata_block {
edb33667
TH		 248 struct sil24_prb prb;
249 struct sil24_sge sge[LIBATA_MAX_PRD];
250};
251
69ad185f
TH		 252struct sil24_atapi_block {
253 struct sil24_prb prb;
254 u8 cdb[16];
255 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
256};
257
258union sil24_cmd_block {
259 struct sil24_ata_block ata;
260 struct sil24_atapi_block atapi;
261};
262
88ce7550
TH		 263static struct sil24_cerr_info {
264 unsigned int err_mask, action;
265 const char *desc;
266} sil24_cerr_db[] = {
267 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
268 "device error" },
269 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
270 "device error via D2H FIS" },
271 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
272 "device error via SDB FIS" },
273 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
274 "error in data FIS" },
275 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
276 "failed to transmit command FIS" },
277 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
278 "protocol mismatch" },
279 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
280 "data directon mismatch" },
281 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
282 "ran out of SGEs while writing" },
283 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
284 "ran out of SGEs while reading" },
285 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
286 "invalid data directon for ATAPI CDB" },
287 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
288 "SGT no on qword boundary" },
289 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI target abort while fetching SGT" },
291 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
292 "PCI master abort while fetching SGT" },
293 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "PCI parity error while fetching SGT" },
295 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
296 "PRB not on qword boundary" },
297 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI target abort while fetching PRB" },
299 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
300 "PCI master abort while fetching PRB" },
301 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
302 "PCI parity error while fetching PRB" },
303 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
304 "undefined error while transferring data" },
305 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
306 "PCI target abort while transferring data" },
307 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
308 "PCI master abort while transferring data" },
309 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
310 "PCI parity error while transferring data" },
311 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
312 "FIS received while sending service FIS" },
313};
314
edb33667
TH		 315/*
316 * ap->private_data
317 *
318 * The preview driver always returned 0 for status. We emulate it
319 * here from the previous interrupt.
320 */
321struct sil24_port_priv {
69ad185f 322 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 323 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 324 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 325};
326
cd0d3bbc 327static void sil24_dev_config(struct ata_device *dev);
edb33667 328static u8 sil24_check_status(struct ata_port *ap);
edb33667
TH		 329static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
330static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 331static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
edb33667 332static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 333static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
edb33667 334static void sil24_irq_clear(struct ata_port *ap);
88ce7550
TH		 335static void sil24_freeze(struct ata_port *ap);
336static void sil24_thaw(struct ata_port *ap);
337static void sil24_error_handler(struct ata_port *ap);
338static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
edb33667 339static int sil24_port_start(struct ata_port *ap);
edb33667 340static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
281d426c 341#ifdef CONFIG_PM
d2298dca 342static int sil24_pci_device_resume(struct pci_dev *pdev);
281d426c 343#endif
edb33667 344
3b7d697d 345static const struct pci_device_id sil24_pci_tbl[] = {
54bb3a94
JG		 346 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
347 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
348 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
722d67b6 349 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
54bb3a94
JG		 350 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
351 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
352
1fcce839 353 { } /* terminate list */
edb33667
TH		 354};
355
356static struct pci_driver sil24_pci_driver = {
357 .name = DRV_NAME,
358 .id_table = sil24_pci_tbl,
359 .probe = sil24_init_one,
24dc5f33 360 .remove = ata_pci_remove_one,
281d426c 361#ifdef CONFIG_PM
d2298dca
TH		 362 .suspend = ata_pci_device_suspend,
363 .resume = sil24_pci_device_resume,
281d426c 364#endif
edb33667
TH		 365};
366
193515d5 367static struct scsi_host_template sil24_sht = {
edb33667
TH		 368 .module = THIS_MODULE,
369 .name = DRV_NAME,
370 .ioctl = ata_scsi_ioctl,
371 .queuecommand = ata_scsi_queuecmd,
aee10a03
TH		 372 .change_queue_depth = ata_scsi_change_queue_depth,
373 .can_queue = SIL24_MAX_CMDS,
edb33667
TH		 374 .this_id = ATA_SHT_THIS_ID,
375 .sg_tablesize = LIBATA_MAX_PRD,
edb33667
TH		 376 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
377 .emulated = ATA_SHT_EMULATED,
378 .use_clustering = ATA_SHT_USE_CLUSTERING,
379 .proc_name = DRV_NAME,
380 .dma_boundary = ATA_DMA_BOUNDARY,
381 .slave_configure = ata_scsi_slave_config,
ccf68c34 382 .slave_destroy = ata_scsi_slave_destroy,
edb33667 383 .bios_param = ata_std_bios_param,
edb33667
TH		 384};
385
057ace5e 386static const struct ata_port_operations sil24_ops = {
edb33667
TH		 387 .port_disable = ata_port_disable,
388
69ad185f
TH		 389 .dev_config = sil24_dev_config,
390
edb33667
TH		 391 .check_status = sil24_check_status,
392 .check_altstatus = sil24_check_status,
edb33667
TH		 393 .dev_select = ata_noop_dev_select,
394
7f726d12
TH		 395 .tf_read = sil24_tf_read,
396
edb33667
TH		 397 .qc_prep = sil24_qc_prep,
398 .qc_issue = sil24_qc_issue,
399
edb33667 400 .irq_clear = sil24_irq_clear,
246ce3b6
AI		 401 .irq_on = ata_dummy_irq_on,
402 .irq_ack = ata_dummy_irq_ack,
edb33667
TH		 403
404 .scr_read = sil24_scr_read,
405 .scr_write = sil24_scr_write,
406
88ce7550
TH		 407 .freeze = sil24_freeze,
408 .thaw = sil24_thaw,
409 .error_handler = sil24_error_handler,
410 .post_internal_cmd = sil24_post_internal_cmd,
411
edb33667 412 .port_start = sil24_port_start,
edb33667
TH		 413};
414
042c21fd 415/*
cca3974e 416 * Use bits 30-31 of port_flags to encode available port numbers.
042c21fd
TH		 417 * Current maxium is 4.
418 */
419#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
420#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
421
4447d351 422static const struct ata_port_info sil24_port_info[] = {
edb33667
TH		 423 /* sil_3124 */
424 {
cca3974e 425 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
37024e8e 426 SIL24_FLAG_PCIX_IRQ_WOC,
edb33667
TH		 427 .pio_mask = 0x1f, /* pio0-4 */
428 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 429 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 430 .port_ops = &sil24_ops,
431 },
2e9edbf8 432 /* sil_3132 */
edb33667 433 {
cca3974e 434 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
042c21fd
TH		 435 .pio_mask = 0x1f, /* pio0-4 */
436 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 437 .udma_mask = ATA_UDMA5, /* udma0-5 */
042c21fd
TH		 438 .port_ops = &sil24_ops,
439 },
440 /* sil_3131/sil_3531 */
441 {
cca3974e 442 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
edb33667
TH		 443 .pio_mask = 0x1f, /* pio0-4 */
444 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 445 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 446 .port_ops = &sil24_ops,
447 },
448};
449
aee10a03
TH		 450static int sil24_tag(int tag)
451{
452 if (unlikely(ata_tag_internal(tag)))
453 return 0;
454 return tag;
455}
456
cd0d3bbc 457static void sil24_dev_config(struct ata_device *dev)
69ad185f 458{
cd0d3bbc 459 void __iomem *port = dev->ap->ioaddr.cmd_addr;
69ad185f 460
6e7846e9 461 if (dev->cdb_len == 16)
69ad185f
TH		 462 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
463 else
464 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
465}
466
e59f0dad 467static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
6a575fa9 468{
0d5ff566 469 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 470 struct sil24_prb __iomem *prb;
4b4a5eae 471 u8 fis[6 * 4];
6a575fa9 472
e59f0dad
TH		 473 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
474 memcpy_fromio(fis, prb->fis, sizeof(fis));
475 ata_tf_from_fis(fis, tf);
6a575fa9
TH		 476}
477
edb33667
TH		 478static u8 sil24_check_status(struct ata_port *ap)
479{
6a575fa9
TH		 480 struct sil24_port_priv *pp = ap->private_data;
481 return pp->tf.command;
edb33667
TH		 482}
483
edb33667
TH		 484static int sil24_scr_map[] = {
485 [SCR_CONTROL] = 0,
486 [SCR_STATUS] = 1,
487 [SCR_ERROR] = 2,
488 [SCR_ACTIVE] = 3,
489};
490
491static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
492{
0d5ff566 493 void __iomem *scr_addr = ap->ioaddr.scr_addr;
edb33667 494 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 495 void __iomem *addr;
edb33667
TH		 496 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
497 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
498 }
499 return 0xffffffffU;
500}
501
502static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
503{
0d5ff566 504 void __iomem *scr_addr = ap->ioaddr.scr_addr;
edb33667 505 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 506 void __iomem *addr;
edb33667
TH		 507 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
508 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
509 }
510}
511
7f726d12
TH		 512static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
513{
514 struct sil24_port_priv *pp = ap->private_data;
515 *tf = pp->tf;
516}
517
b5bc421c
TH		 518static int sil24_init_port(struct ata_port *ap)
519{
0d5ff566 520 void __iomem *port = ap->ioaddr.cmd_addr;
b5bc421c
TH		 521 u32 tmp;
522
523 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
524 ata_wait_register(port + PORT_CTRL_STAT,
525 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
526 tmp = ata_wait_register(port + PORT_CTRL_STAT,
527 PORT_CS_RDY, 0, 10, 100);
528
529 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
530 return -EIO;
531 return 0;
532}
533
37b99cba
TH		 534static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
535 const struct ata_taskfile *tf,
536 int is_cmd, u32 ctrl,
537 unsigned long timeout_msec)
edb33667 538{
0d5ff566 539 void __iomem *port = ap->ioaddr.cmd_addr;
ca45160d 540 struct sil24_port_priv *pp = ap->private_data;
69ad185f 541 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 542 dma_addr_t paddr = pp->cmd_block_dma;
37b99cba
TH		 543 u32 irq_enabled, irq_mask, irq_stat;
544 int rc;
545
546 prb->ctrl = cpu_to_le16(ctrl);
547 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
548
549 /* temporarily plug completion and error interrupts */
550 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
551 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
552
553 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
554 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
555
556 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
557 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
558 10, timeout_msec);
559
560 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
561 irq_stat >>= PORT_IRQ_RAW_SHIFT;
562
563 if (irq_stat & PORT_IRQ_COMPLETE)
564 rc = 0;
565 else {
566 /* force port into known state */
567 sil24_init_port(ap);
568
569 if (irq_stat & PORT_IRQ_ERROR)
570 rc = -EIO;
571 else
572 rc = -EBUSY;
573 }
574
575 /* restore IRQ enabled */
576 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
577
578 return rc;
579}
580
975530e8
TH		 581static int sil24_do_softreset(struct ata_port *ap, unsigned int *class,
582 int pmp, unsigned long deadline)
37b99cba
TH		 583{
584 unsigned long timeout_msec = 0;
e59f0dad 585 struct ata_taskfile tf;
643be977 586 const char *reason;
37b99cba 587 int rc;
ca45160d 588
07b73470
TH		 589 DPRINTK("ENTER\n");
590
81952c54 591 if (ata_port_offline(ap)) {
10d996ad
TH		 592 DPRINTK("PHY reports no device\n");
593 *class = ATA_DEV_NONE;
594 goto out;
595 }
596
2555d6c2
TH		 597 /* put the port into known state */
598 if (sil24_init_port(ap)) {
599 reason ="port not ready";
600 goto err;
601 }
602
0eaa6058 603 /* do SRST */
37b99cba
TH		 604 if (time_after(deadline, jiffies))
605 timeout_msec = jiffies_to_msecs(deadline - jiffies);
ca45160d 606
37b99cba 607 ata_tf_init(ap->device, &tf); /* doesn't really matter */
975530e8
TH		 608 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
609 timeout_msec);
37b99cba
TH		 610 if (rc == -EBUSY) {
611 reason = "timeout";
612 goto err;
613 } else if (rc) {
614 reason = "SRST command error";
643be977 615 goto err;
07b73470 616 }
10d996ad 617
e59f0dad
TH		 618 sil24_read_tf(ap, 0, &tf);
619 *class = ata_dev_classify(&tf);
10d996ad 620
07b73470
TH		 621 if (*class == ATA_DEV_UNKNOWN)
622 *class = ATA_DEV_NONE;
ca45160d 623
10d996ad 624 out:
07b73470 625 DPRINTK("EXIT, class=%u\n", *class);
ca45160d 626 return 0;
643be977
TH		 627
628 err:
f15a1daf 629 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
643be977 630 return -EIO;
ca45160d
TH		 631}
632
975530e8
TH		 633static int sil24_softreset(struct ata_port *ap, unsigned int *class,
634 unsigned long deadline)
635{
636 return sil24_do_softreset(ap, class, 0, deadline);
637}
638
d4b2bab4
TH		 639static int sil24_hardreset(struct ata_port *ap, unsigned int *class,
640 unsigned long deadline)
489ff4c7 641{
0d5ff566 642 void __iomem *port = ap->ioaddr.cmd_addr;
ecc2e2b9 643 const char *reason;
e8e008e7 644 int tout_msec, rc;
ecc2e2b9
TH		 645 u32 tmp;
646
647 /* sil24 does the right thing(tm) without any protection */
3c567b7d 648 sata_set_spd(ap);
ecc2e2b9
TH		 649
650 tout_msec = 100;
81952c54 651 if (ata_port_online(ap))
ecc2e2b9
TH		 652 tout_msec = 5000;
653
654 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
655 tmp = ata_wait_register(port + PORT_CTRL_STAT,
656 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
657
e8e008e7
TH		 658 /* SStatus oscillates between zero and valid status after
659 * DEV_RST, debounce it.
ecc2e2b9 660 */
d4b2bab4 661 rc = sata_phy_debounce(ap, sata_deb_timing_long, deadline);
e8e008e7
TH		 662 if (rc) {
663 reason = "PHY debouncing failed";
664 goto err;
665 }
ecc2e2b9
TH		 666
667 if (tmp & PORT_CS_DEV_RST) {
81952c54 668 if (ata_port_offline(ap))
ecc2e2b9
TH		 669 return 0;
670 reason = "link not ready";
671 goto err;
672 }
673
e8e008e7
TH		 674 /* Sil24 doesn't store signature FIS after hardreset, so we
675 * can't wait for BSY to clear. Some devices take a long time
676 * to get ready and those devices will choke if we don't wait
677 * for BSY clearance here. Tell libata to perform follow-up
678 * softreset.
ecc2e2b9 679 */
e8e008e7 680 return -EAGAIN;
ecc2e2b9
TH		 681
682 err:
f15a1daf 683 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
ecc2e2b9 684 return -EIO;
489ff4c7
TH		 685}
686
edb33667 687static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 688 struct sil24_sge *sge)
edb33667 689{
972c26bd 690 struct scatterlist *sg;
edb33667 691
972c26bd 692 ata_for_each_sg(sg, qc) {
edb33667
TH		 693 sge->addr = cpu_to_le64(sg_dma_address(sg));
694 sge->cnt = cpu_to_le32(sg_dma_len(sg));
972c26bd
JG		 695 if (ata_sg_is_last(sg, qc))
696 sge->flags = cpu_to_le32(SGE_TRM);
697 else
698 sge->flags = 0;
972c26bd 699 sge++;
edb33667
TH		 700 }
701}
702
703static void sil24_qc_prep(struct ata_queued_cmd *qc)
704{
705 struct ata_port *ap = qc->ap;
706 struct sil24_port_priv *pp = ap->private_data;
aee10a03 707 union sil24_cmd_block *cb;
69ad185f
TH		 708 struct sil24_prb *prb;
709 struct sil24_sge *sge;
bad28a37 710 u16 ctrl = 0;
edb33667 711
aee10a03
TH		 712 cb = &pp->cmd_block[sil24_tag(qc->tag)];
713
edb33667
TH		 714 switch (qc->tf.protocol) {
715 case ATA_PROT_PIO:
716 case ATA_PROT_DMA:
aee10a03 717 case ATA_PROT_NCQ:
edb33667 718 case ATA_PROT_NODATA:
69ad185f
TH		 719 prb = &cb->ata.prb;
720 sge = cb->ata.sge;
edb33667 721 break;
69ad185f
TH		 722
723 case ATA_PROT_ATAPI:
724 case ATA_PROT_ATAPI_DMA:
725 case ATA_PROT_ATAPI_NODATA:
726 prb = &cb->atapi.prb;
727 sge = cb->atapi.sge;
728 memset(cb->atapi.cdb, 0, 32);
6e7846e9 729 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f
TH		 730
731 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
732 if (qc->tf.flags & ATA_TFLAG_WRITE)
bad28a37 733 ctrl = PRB_CTRL_PACKET_WRITE;
69ad185f 734 else
bad28a37
TH		 735 ctrl = PRB_CTRL_PACKET_READ;
736 }
69ad185f
TH		 737 break;
738
edb33667 739 default:
69ad185f
TH		 740 prb = NULL; /* shut up, gcc */
741 sge = NULL;
edb33667
TH		 742 BUG();
743 }
744
bad28a37 745 prb->ctrl = cpu_to_le16(ctrl);
9977126c 746 ata_tf_to_fis(&qc->tf, 0, 1, prb->fis);
edb33667
TH		 747
748 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 749 sil24_fill_sg(qc, sge);
edb33667
TH		 750}
751
9a3d9eb0 752static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 753{
754 struct ata_port *ap = qc->ap;
755 struct sil24_port_priv *pp = ap->private_data;
0d5ff566 756 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 757 unsigned int tag = sil24_tag(qc->tag);
758 dma_addr_t paddr;
759 void __iomem *activate;
edb33667 760
aee10a03
TH		 761 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
762 activate = port + PORT_CMD_ACTIVATE + tag * 8;
763
764 writel((u32)paddr, activate);
765 writel((u64)paddr >> 32, activate + 4);
26ec634c 766
edb33667
TH		 767 return 0;
768}
769
770static void sil24_irq_clear(struct ata_port *ap)
771{
772 /* unused */
773}
774
88ce7550 775static void sil24_freeze(struct ata_port *ap)
7d1ce682 776{
0d5ff566 777 void __iomem *port = ap->ioaddr.cmd_addr;
7d1ce682 778
88ce7550
TH		 779 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
780 * PORT_IRQ_ENABLE instead.
781 */
782 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
7d1ce682
TH		 783}
784
88ce7550 785static void sil24_thaw(struct ata_port *ap)
edb33667 786{
0d5ff566 787 void __iomem *port = ap->ioaddr.cmd_addr;
edb33667
TH		 788 u32 tmp;
789
88ce7550
TH		 790 /* clear IRQ */
791 tmp = readl(port + PORT_IRQ_STAT);
792 writel(tmp, port + PORT_IRQ_STAT);
edb33667 793
88ce7550
TH		 794 /* turn IRQ back on */
795 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
edb33667
TH		 796}
797
88ce7550 798static void sil24_error_intr(struct ata_port *ap)
8746618d 799{
0d5ff566 800 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 801 struct sil24_port_priv *pp = ap->private_data;
88ce7550
TH		 802 struct ata_eh_info *ehi = &ap->eh_info;
803 int freeze = 0;
804 u32 irq_stat;
8746618d 805
88ce7550 806 /* on error, we need to clear IRQ explicitly */
8746618d 807 irq_stat = readl(port + PORT_IRQ_STAT);
88ce7550 808 writel(irq_stat, port + PORT_IRQ_STAT);
ad6e90f6 809
88ce7550
TH		 810 /* first, analyze and record host port events */
811 ata_ehi_clear_desc(ehi);
ad6e90f6 812
88ce7550 813 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
8746618d 814
0542925b
TH		 815 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
816 ata_ehi_hotplugged(ehi);
817 ata_ehi_push_desc(ehi, ", %s",
818 irq_stat & PORT_IRQ_PHYRDY_CHG ?
819 "PHY RDY changed" : "device exchanged");
88ce7550 820 freeze = 1;
6a575fa9
TH		 821 }
822
88ce7550
TH		 823 if (irq_stat & PORT_IRQ_UNK_FIS) {
824 ehi->err_mask |= AC_ERR_HSM;
825 ehi->action |= ATA_EH_SOFTRESET;
826 ata_ehi_push_desc(ehi , ", unknown FIS");
827 freeze = 1;
828 }
829
830 /* deal with command error */
831 if (irq_stat & PORT_IRQ_ERROR) {
832 struct sil24_cerr_info *ci = NULL;
833 unsigned int err_mask = 0, action = 0;
834 struct ata_queued_cmd *qc;
835 u32 cerr;
836
837 /* analyze CMD_ERR */
838 cerr = readl(port + PORT_CMD_ERR);
839 if (cerr < ARRAY_SIZE(sil24_cerr_db))
840 ci = &sil24_cerr_db[cerr];
841
842 if (ci && ci->desc) {
843 err_mask |= ci->err_mask;
844 action |= ci->action;
845 ata_ehi_push_desc(ehi, ", %s", ci->desc);
846 } else {
847 err_mask |= AC_ERR_OTHER;
848 action |= ATA_EH_SOFTRESET;
849 ata_ehi_push_desc(ehi, ", unknown command error %d",
850 cerr);
851 }
852
853 /* record error info */
854 qc = ata_qc_from_tag(ap, ap->active_tag);
855 if (qc) {
e59f0dad 856 sil24_read_tf(ap, qc->tag, &pp->tf);
88ce7550
TH		 857 qc->err_mask |= err_mask;
858 } else
859 ehi->err_mask |= err_mask;
860
861 ehi->action |= action;
a22e2eb0 862 }
88ce7550
TH		 863
864 /* freeze or abort */
865 if (freeze)
866 ata_port_freeze(ap);
867 else
868 ata_port_abort(ap);
8746618d
TH		 869}
870
aee10a03
TH		 871static void sil24_finish_qc(struct ata_queued_cmd *qc)
872{
e59f0dad
TH		 873 struct ata_port *ap = qc->ap;
874 struct sil24_port_priv *pp = ap->private_data;
875
aee10a03 876 if (qc->flags & ATA_QCFLAG_RESULT_TF)
e59f0dad 877 sil24_read_tf(ap, qc->tag, &pp->tf);
aee10a03
TH		 878}
879
edb33667
TH		 880static inline void sil24_host_intr(struct ata_port *ap)
881{
0d5ff566 882 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 883 u32 slot_stat, qc_active;
884 int rc;
edb33667
TH		 885
886 slot_stat = readl(port + PORT_SLOT_STAT);
37024e8e 887
88ce7550
TH		 888 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
889 sil24_error_intr(ap);
890 return;
891 }
892
893 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
894 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
37024e8e 895
aee10a03
TH		 896 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
897 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
898 if (rc > 0)
899 return;
900 if (rc < 0) {
901 struct ata_eh_info *ehi = &ap->eh_info;
902 ehi->err_mask |= AC_ERR_HSM;
903 ehi->action |= ATA_EH_SOFTRESET;
904 ata_port_freeze(ap);
88ce7550
TH		 905 return;
906 }
907
908 if (ata_ratelimit())
909 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
aee10a03
TH		 910 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
911 slot_stat, ap->active_tag, ap->sactive);
edb33667
TH		 912}
913
7d12e780 914static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
edb33667 915{
cca3974e 916 struct ata_host *host = dev_instance;
0d5ff566 917 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
edb33667
TH		 918 unsigned handled = 0;
919 u32 status;
920 int i;
921
0d5ff566 922 status = readl(host_base + HOST_IRQ_STAT);
edb33667 923
06460aea
TH		 924 if (status == 0xffffffff) {
925 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
926 "PCI fault or device removal?\n");
927 goto out;
928 }
929
edb33667
TH		 930 if (!(status & IRQ_STAT_4PORTS))
931 goto out;
932
cca3974e 933 spin_lock(&host->lock);
edb33667 934
cca3974e 935 for (i = 0; i < host->n_ports; i++)
edb33667 936 if (status & (1 << i)) {
cca3974e 937 struct ata_port *ap = host->ports[i];
198e0fed 938 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
825cd6dd 939 sil24_host_intr(ap);
3cc4571c
TH		 940 handled++;
941 } else
942 printk(KERN_ERR DRV_NAME
943 ": interrupt from disabled port %d\n", i);
edb33667
TH		 944 }
945
cca3974e 946 spin_unlock(&host->lock);
edb33667
TH		 947 out:
948 return IRQ_RETVAL(handled);
949}
950
88ce7550
TH		 951static void sil24_error_handler(struct ata_port *ap)
952{
953 struct ata_eh_context *ehc = &ap->eh_context;
954
955 if (sil24_init_port(ap)) {
956 ata_eh_freeze_port(ap);
957 ehc->i.action |= ATA_EH_HARDRESET;
958 }
959
960 /* perform recovery */
f5914a46
TH		 961 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
962 ata_std_postreset);
88ce7550
TH		 963}
964
965static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
966{
967 struct ata_port *ap = qc->ap;
968
88ce7550 969 /* make DMA engine forget about the failed command */
a51d644a 970 if (qc->flags & ATA_QCFLAG_FAILED)
88ce7550
TH		 971 sil24_init_port(ap);
972}
973
edb33667
TH		 974static int sil24_port_start(struct ata_port *ap)
975{
cca3974e 976 struct device *dev = ap->host->dev;
edb33667 977 struct sil24_port_priv *pp;
69ad185f 978 union sil24_cmd_block *cb;
aee10a03 979 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
edb33667 980 dma_addr_t cb_dma;
24dc5f33 981 int rc;
edb33667 982
24dc5f33 983 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edb33667 984 if (!pp)
24dc5f33 985 return -ENOMEM;
edb33667 986
6a575fa9
TH		 987 pp->tf.command = ATA_DRDY;
988
24dc5f33 989 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb 990 if (!cb)
24dc5f33 991 return -ENOMEM;
edb33667
TH		 992 memset(cb, 0, cb_size);
993
6037d6bb
JG		 994 rc = ata_pad_alloc(ap, dev);
995 if (rc)
24dc5f33 996 return rc;
6037d6bb 997
edb33667
TH		 998 pp->cmd_block = cb;
999 pp->cmd_block_dma = cb_dma;
1000
1001 ap->private_data = pp;
1002
1003 return 0;
edb33667
TH		 1004}
1005
4447d351 1006static void sil24_init_controller(struct ata_host *host)
2a41a610 1007{
4447d351
TH		 1008 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1009 void __iomem *port_base = host->iomap[SIL24_PORT_BAR];
2a41a610
TH		 1010 u32 tmp;
1011 int i;
1012
1013 /* GPIO off */
1014 writel(0, host_base + HOST_FLASH_CMD);
1015
1016 /* clear global reset & mask interrupts during initialization */
1017 writel(0, host_base + HOST_CTRL);
1018
1019 /* init ports */
4447d351 1020 for (i = 0; i < host->n_ports; i++) {
2a41a610
TH		 1021 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1022
1023 /* Initial PHY setting */
1024 writel(0x20c, port + PORT_PHY_CFG);
1025
1026 /* Clear port RST */
1027 tmp = readl(port + PORT_CTRL_STAT);
1028 if (tmp & PORT_CS_PORT_RST) {
1029 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1030 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1031 PORT_CS_PORT_RST,
1032 PORT_CS_PORT_RST, 10, 100);
1033 if (tmp & PORT_CS_PORT_RST)
4447d351 1034 dev_printk(KERN_ERR, host->dev,
2a41a610
TH		 1035 "failed to clear port RST\n");
1036 }
1037
1038 /* Configure IRQ WoC */
4447d351 1039 if (host->ports[0]->flags & SIL24_FLAG_PCIX_IRQ_WOC)
2a41a610
TH		 1040 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1041 else
1042 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1043
1044 /* Zero error counters. */
1045 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1046 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1047 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1048 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1049 writel(0x0000, port + PORT_CRC_ERR_CNT);
1050 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1051
1052 /* Always use 64bit activation */
1053 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1054
1055 /* Clear port multiplier enable and resume bits */
28c8f3b4
TH		 1056 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1057 port + PORT_CTRL_CLR);
2a41a610
TH		 1058 }
1059
1060 /* Turn on interrupts */
1061 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1062}
1063
edb33667
TH		 1064static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1065{
1066 static int printed_version = 0;
4447d351
TH		 1067 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1068 const struct ata_port_info *ppi[] = { &pi, NULL };
1069 void __iomem * const *iomap;
1070 struct ata_host *host;
edb33667 1071 int i, rc;
37024e8e 1072 u32 tmp;
edb33667
TH		 1073
1074 if (!printed_version++)
a9524a76 1075 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667 1076
4447d351 1077 /* acquire resources */
24dc5f33 1078 rc = pcim_enable_device(pdev);
edb33667
TH		 1079 if (rc)
1080 return rc;
1081
0d5ff566
TH		 1082 rc = pcim_iomap_regions(pdev,
1083 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1084 DRV_NAME);
edb33667 1085 if (rc)
24dc5f33 1086 return rc;
4447d351 1087 iomap = pcim_iomap_table(pdev);
edb33667 1088
4447d351
TH		 1089 /* apply workaround for completion IRQ loss on PCI-X errata */
1090 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1091 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1092 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1093 dev_printk(KERN_INFO, &pdev->dev,
1094 "Applying completion IRQ loss on PCI-X "
1095 "errata fix\n");
1096 else
1097 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1098 }
edb33667 1099
4447d351
TH		 1100 /* allocate and fill host */
1101 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1102 SIL24_FLAG2NPORTS(ppi[0]->flags));
1103 if (!host)
1104 return -ENOMEM;
1105 host->iomap = iomap;
edb33667 1106
4447d351
TH		 1107 for (i = 0; i < host->n_ports; i++) {
1108 void __iomem *port = iomap[SIL24_PORT_BAR] + i * PORT_REGS_SIZE;
edb33667 1109
4447d351
TH		 1110 host->ports[i]->ioaddr.cmd_addr = port;
1111 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
edb33667 1112
4447d351
TH		 1113 ata_std_ports(&host->ports[i]->ioaddr);
1114 }
edb33667 1115
4447d351 1116 /* configure and activate the device */
26ec634c
TH		 1117 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1118 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1119 if (rc) {
1120 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1121 if (rc) {
1122 dev_printk(KERN_ERR, &pdev->dev,
1123 "64-bit DMA enable failed\n");
24dc5f33 1124 return rc;
26ec634c
TH		 1125 }
1126 }
1127 } else {
1128 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1129 if (rc) {
1130 dev_printk(KERN_ERR, &pdev->dev,
1131 "32-bit DMA enable failed\n");
24dc5f33 1132 return rc;
26ec634c
TH		 1133 }
1134 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1135 if (rc) {
1136 dev_printk(KERN_ERR, &pdev->dev,
1137 "32-bit consistent DMA enable failed\n");
24dc5f33 1138 return rc;
26ec634c 1139 }
edb33667
TH		 1140 }
1141
4447d351 1142 sil24_init_controller(host);
edb33667
TH		 1143
1144 pci_set_master(pdev);
4447d351
TH		 1145 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1146 &sil24_sht);
edb33667
TH		 1147}
1148
281d426c 1149#ifdef CONFIG_PM
d2298dca
TH		 1150static int sil24_pci_device_resume(struct pci_dev *pdev)
1151{
cca3974e 1152 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1153 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
553c4aa6 1154 int rc;
d2298dca 1155
553c4aa6
TH		 1156 rc = ata_pci_device_do_resume(pdev);
1157 if (rc)
1158 return rc;
d2298dca
TH		 1159
1160 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
0d5ff566 1161 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
d2298dca 1162
4447d351 1163 sil24_init_controller(host);
d2298dca 1164
cca3974e 1165 ata_host_resume(host);
d2298dca
TH		 1166
1167 return 0;
1168}
281d426c 1169#endif
d2298dca 1170
edb33667
TH		 1171static int __init sil24_init(void)
1172{
b7887196 1173 return pci_register_driver(&sil24_pci_driver);
edb33667
TH		 1174}
1175
1176static void __exit sil24_exit(void)
1177{
1178 pci_unregister_driver(&sil24_pci_driver);
1179}
1180
1181MODULE_AUTHOR("Tejun Heo");
1182MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1183MODULE_LICENSE("GPL");
1184MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1185
1186module_init(sil24_init);
1187module_exit(sil24_exit);
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