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libata: clean up dummy port_ops
[net-next-2.6.git] / drivers / ata / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667 30#include <linux/libata.h>
edb33667
TH		 31
32#define DRV_NAME "sata_sil24"
3454dc69 33#define DRV_VERSION "1.1"
edb33667 34
edb33667
TH		 35/*
36 * Port request block (PRB) 32 bytes
37 */
38struct sil24_prb {
b4772574
AD		 39 __le16 ctrl;
40 __le16 prot;
41 __le32 rx_cnt;
edb33667
TH		 42 u8 fis[6 * 4];
43};
44
45/*
46 * Scatter gather entry (SGE) 16 bytes
47 */
48struct sil24_sge {
b4772574
AD		 49 __le64 addr;
50 __le32 cnt;
51 __le32 flags;
edb33667
TH		 52};
53
54/*
55 * Port multiplier
56 */
57struct sil24_port_multiplier {
b4772574
AD		 58 __le32 diag;
59 __le32 sactive;
edb33667
TH		 60};
61
62enum {
0d5ff566
TH		 63 SIL24_HOST_BAR = 0,
64 SIL24_PORT_BAR = 2,
65
93e2618e
TH		 66 /* sil24 fetches in chunks of 64bytes. The first block
67 * contains the PRB and two SGEs. From the second block, it's
68 * consisted of four SGEs and called SGT. Calculate the
69 * number of SGTs that fit into one page.
70 */
71 SIL24_PRB_SZ = sizeof(struct sil24_prb)
72 + 2 * sizeof(struct sil24_sge),
73 SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ)
74 / (4 * sizeof(struct sil24_sge)),
75
76 /* This will give us one unused SGEs for ATA. This extra SGE
77 * will be used to store CDB for ATAPI devices.
78 */
79 SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1,
80
edb33667
TH		 81 /*
82 * Global controller registers (128 bytes @ BAR0)
83 */
84 /* 32 bit regs */
85 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
86 HOST_CTRL = 0x40,
87 HOST_IRQ_STAT = 0x44,
88 HOST_PHY_CFG = 0x48,
89 HOST_BIST_CTRL = 0x50,
90 HOST_BIST_PTRN = 0x54,
91 HOST_BIST_STAT = 0x58,
92 HOST_MEM_BIST_STAT = 0x5c,
93 HOST_FLASH_CMD = 0x70,
94 /* 8 bit regs */
95 HOST_FLASH_DATA = 0x74,
96 HOST_TRANSITION_DETECT = 0x75,
97 HOST_GPIO_CTRL = 0x76,
98 HOST_I2C_ADDR = 0x78, /* 32 bit */
99 HOST_I2C_DATA = 0x7c,
100 HOST_I2C_XFER_CNT = 0x7e,
101 HOST_I2C_CTRL = 0x7f,
102
103 /* HOST_SLOT_STAT bits */
104 HOST_SSTAT_ATTN = (1 << 31),
105
7dafc3fd
TH		 106 /* HOST_CTRL bits */
107 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
108 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
109 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
110 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
111 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
d2298dca 112 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
7dafc3fd 113
edb33667
TH		 114 /*
115 * Port registers
116 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
117 */
118 PORT_REGS_SIZE = 0x2000,
135da345 119
28c8f3b4 120 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
135da345 121 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
edb33667 122
28c8f3b4 123 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
c0c55908
TH		 124 PORT_PMP_STATUS = 0x0000, /* port device status offset */
125 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
126 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
127
edb33667 128 /* 32 bit regs */
83bbecc9
TH		 129 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
130 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
131 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
132 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
133 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 134 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 135 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
136 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 137 PORT_FIS_CFG = 0x1028,
138 PORT_FIFO_THRES = 0x102c,
139 /* 16 bit regs */
140 PORT_DECODE_ERR_CNT = 0x1040,
141 PORT_DECODE_ERR_THRESH = 0x1042,
142 PORT_CRC_ERR_CNT = 0x1044,
143 PORT_CRC_ERR_THRESH = 0x1046,
144 PORT_HSHK_ERR_CNT = 0x1048,
145 PORT_HSHK_ERR_THRESH = 0x104a,
146 /* 32 bit regs */
147 PORT_PHY_CFG = 0x1050,
148 PORT_SLOT_STAT = 0x1800,
149 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
c0c55908 150 PORT_CONTEXT = 0x1e04,
edb33667
TH		 151 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
152 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
153 PORT_SCONTROL = 0x1f00,
154 PORT_SSTATUS = 0x1f04,
155 PORT_SERROR = 0x1f08,
156 PORT_SACTIVE = 0x1f0c,
157
158 /* PORT_CTRL_STAT bits */
159 PORT_CS_PORT_RST = (1 << 0), /* port reset */
160 PORT_CS_DEV_RST = (1 << 1), /* device reset */
161 PORT_CS_INIT = (1 << 2), /* port initialize */
162 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 163 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
28c8f3b4 164 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
e382eb1d 165 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
28c8f3b4 166 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
e382eb1d 167 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 168
169 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
170 /* bits[11:0] are masked */
171 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
172 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
173 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
174 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
175 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
176 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
7dafc3fd
TH		 177 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
178 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
179 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
180 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
181 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
3b9f1d0f 182 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
edb33667 183
88ce7550 184 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
0542925b 185 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
854c73a2 186 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
88ce7550 187
edb33667
TH		 188 /* bits[27:16] are unmasked (raw) */
189 PORT_IRQ_RAW_SHIFT = 16,
190 PORT_IRQ_MASKED_MASK = 0x7ff,
191 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
192
193 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
194 PORT_IRQ_STEER_SHIFT = 30,
195 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
196
197 /* PORT_CMD_ERR constants */
198 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
199 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
200 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
201 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
202 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
203 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
204 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
205 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
206 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
207 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
208 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
209 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
210 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
211 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
212 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
213 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
214 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
215 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
216 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
64008802 217 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
edb33667 218 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 219 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 220
d10cb35a
TH		 221 /* bits of PRB control field */
222 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
223 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
224 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
225 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
226 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
227
228 /* PRB protocol field */
229 PRB_PROT_PACKET = (1 << 0),
230 PRB_PROT_TCQ = (1 << 1),
231 PRB_PROT_NCQ = (1 << 2),
232 PRB_PROT_READ = (1 << 3),
233 PRB_PROT_WRITE = (1 << 4),
234 PRB_PROT_TRANSPARENT = (1 << 5),
235
edb33667
TH		 236 /*
237 * Other constants
238 */
239 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 240 SGE_LNK = (1 << 30), /* linked list
241 Points to SGT, not SGE */
242 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
243 data address ignored */
edb33667 244
aee10a03
TH		 245 SIL24_MAX_CMDS = 31,
246
edb33667
TH		 247 /* board id */
248 BID_SIL3124 = 0,
249 BID_SIL3132 = 1,
042c21fd 250 BID_SIL3131 = 2,
edb33667 251
9466d85b
TH		 252 /* host flags */
253 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
aee10a03 254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
854c73a2 255 ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
3454dc69 256 ATA_FLAG_AN | ATA_FLAG_PMP,
37024e8e 257 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
9466d85b 258
edb33667
TH		 259 IRQ_STAT_4PORTS = 0xf,
260};
261
69ad185f 262struct sil24_ata_block {
edb33667 263 struct sil24_prb prb;
93e2618e 264 struct sil24_sge sge[SIL24_MAX_SGE];
edb33667
TH		 265};
266
69ad185f
TH		 267struct sil24_atapi_block {
268 struct sil24_prb prb;
269 u8 cdb[16];
93e2618e 270 struct sil24_sge sge[SIL24_MAX_SGE];
69ad185f
TH		 271};
272
273union sil24_cmd_block {
274 struct sil24_ata_block ata;
275 struct sil24_atapi_block atapi;
276};
277
88ce7550
TH		 278static struct sil24_cerr_info {
279 unsigned int err_mask, action;
280 const char *desc;
281} sil24_cerr_db[] = {
f90f0828 282 [0] = { AC_ERR_DEV, 0,
88ce7550 283 "device error" },
f90f0828 284 [PORT_CERR_DEV] = { AC_ERR_DEV, 0,
88ce7550 285 "device error via D2H FIS" },
f90f0828 286 [PORT_CERR_SDB] = { AC_ERR_DEV, 0,
88ce7550 287 "device error via SDB FIS" },
cf480626 288 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
88ce7550 289 "error in data FIS" },
cf480626 290 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET,
88ce7550 291 "failed to transmit command FIS" },
cf480626 292 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 293 "protocol mismatch" },
cf480626 294 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 295 "data directon mismatch" },
cf480626 296 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 297 "ran out of SGEs while writing" },
cf480626 298 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 299 "ran out of SGEs while reading" },
cf480626 300 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550 301 "invalid data directon for ATAPI CDB" },
cf480626 302 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
7293fa8f 303 "SGT not on qword boundary" },
cf480626 304 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 305 "PCI target abort while fetching SGT" },
cf480626 306 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 307 "PCI master abort while fetching SGT" },
cf480626 308 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 309 "PCI parity error while fetching SGT" },
cf480626 310 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
88ce7550 311 "PRB not on qword boundary" },
cf480626 312 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 313 "PCI target abort while fetching PRB" },
cf480626 314 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 315 "PCI master abort while fetching PRB" },
cf480626 316 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 317 "PCI parity error while fetching PRB" },
cf480626 318 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 319 "undefined error while transferring data" },
cf480626 320 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 321 "PCI target abort while transferring data" },
cf480626 322 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 323 "PCI master abort while transferring data" },
cf480626 324 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
88ce7550 325 "PCI parity error while transferring data" },
cf480626 326 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
88ce7550
TH		 327 "FIS received while sending service FIS" },
328};
329
edb33667
TH		 330/*
331 * ap->private_data
332 *
333 * The preview driver always returned 0 for status. We emulate it
334 * here from the previous interrupt.
335 */
336struct sil24_port_priv {
69ad185f 337 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 338 dma_addr_t cmd_block_dma; /* DMA base addr for them */
23818034 339 int do_port_rst;
edb33667
TH		 340};
341
cd0d3bbc 342static void sil24_dev_config(struct ata_device *dev);
da3dbb17
TH		 343static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val);
344static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
3454dc69 345static int sil24_qc_defer(struct ata_queued_cmd *qc);
edb33667 346static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 347static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
79f97dad 348static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
3454dc69
TH		 349static void sil24_pmp_attach(struct ata_port *ap);
350static void sil24_pmp_detach(struct ata_port *ap);
88ce7550
TH		 351static void sil24_freeze(struct ata_port *ap);
352static void sil24_thaw(struct ata_port *ap);
a1efdaba
TH		 353static int sil24_softreset(struct ata_link *link, unsigned int *class,
354 unsigned long deadline);
355static int sil24_hardreset(struct ata_link *link, unsigned int *class,
356 unsigned long deadline);
357static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
358 unsigned long deadline);
359static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
360 unsigned long deadline);
88ce7550
TH		 361static void sil24_error_handler(struct ata_port *ap);
362static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
edb33667 363static int sil24_port_start(struct ata_port *ap);
edb33667 364static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
281d426c 365#ifdef CONFIG_PM
d2298dca 366static int sil24_pci_device_resume(struct pci_dev *pdev);
3454dc69 367static int sil24_port_resume(struct ata_port *ap);
281d426c 368#endif
edb33667 369
3b7d697d 370static const struct pci_device_id sil24_pci_tbl[] = {
54bb3a94
JG		 371 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
372 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
373 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
722d67b6 374 { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
54bb3a94
JG		 375 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
376 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
377
1fcce839 378 { } /* terminate list */
edb33667
TH		 379};
380
381static struct pci_driver sil24_pci_driver = {
382 .name = DRV_NAME,
383 .id_table = sil24_pci_tbl,
384 .probe = sil24_init_one,
24dc5f33 385 .remove = ata_pci_remove_one,
281d426c 386#ifdef CONFIG_PM
d2298dca
TH		 387 .suspend = ata_pci_device_suspend,
388 .resume = sil24_pci_device_resume,
281d426c 389#endif
edb33667
TH		 390};
391
193515d5 392static struct scsi_host_template sil24_sht = {
68d1d07b 393 ATA_NCQ_SHT(DRV_NAME),
aee10a03 394 .can_queue = SIL24_MAX_CMDS,
93e2618e 395 .sg_tablesize = SIL24_MAX_SGE,
edb33667 396 .dma_boundary = ATA_DMA_BOUNDARY,
edb33667
TH		 397};
398
029cfd6b
TH		 399static struct ata_port_operations sil24_ops = {
400 .inherits = &sata_pmp_port_ops,
69ad185f 401
3454dc69 402 .qc_defer = sil24_qc_defer,
edb33667
TH		 403 .qc_prep = sil24_qc_prep,
404 .qc_issue = sil24_qc_issue,
79f97dad 405 .qc_fill_rtf = sil24_qc_fill_rtf,
edb33667 406
029cfd6b
TH		 407 .freeze = sil24_freeze,
408 .thaw = sil24_thaw,
a1efdaba
TH		 409 .softreset = sil24_softreset,
410 .hardreset = sil24_hardreset,
411 .pmp_softreset = sil24_pmp_softreset,
412 .pmp_hardreset = sil24_pmp_hardreset,
029cfd6b
TH		 413 .error_handler = sil24_error_handler,
414 .post_internal_cmd = sil24_post_internal_cmd,
415 .dev_config = sil24_dev_config,
edb33667
TH		 416
417 .scr_read = sil24_scr_read,
418 .scr_write = sil24_scr_write,
3454dc69
TH		 419 .pmp_attach = sil24_pmp_attach,
420 .pmp_detach = sil24_pmp_detach,
3454dc69 421
edb33667 422 .port_start = sil24_port_start,
3454dc69
TH		 423#ifdef CONFIG_PM
424 .port_resume = sil24_port_resume,
425#endif
edb33667
TH		 426};
427
042c21fd 428/*
cca3974e 429 * Use bits 30-31 of port_flags to encode available port numbers.
042c21fd
TH		 430 * Current maxium is 4.
431 */
432#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
433#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
434
4447d351 435static const struct ata_port_info sil24_port_info[] = {
edb33667
TH		 436 /* sil_3124 */
437 {
cca3974e 438 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
37024e8e 439 SIL24_FLAG_PCIX_IRQ_WOC,
edb33667
TH		 440 .pio_mask = 0x1f, /* pio0-4 */
441 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 442 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 443 .port_ops = &sil24_ops,
444 },
2e9edbf8 445 /* sil_3132 */
edb33667 446 {
cca3974e 447 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
042c21fd
TH		 448 .pio_mask = 0x1f, /* pio0-4 */
449 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 450 .udma_mask = ATA_UDMA5, /* udma0-5 */
042c21fd
TH		 451 .port_ops = &sil24_ops,
452 },
453 /* sil_3131/sil_3531 */
454 {
cca3974e 455 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
edb33667
TH		 456 .pio_mask = 0x1f, /* pio0-4 */
457 .mwdma_mask = 0x07, /* mwdma0-2 */
bf6263a8 458 .udma_mask = ATA_UDMA5, /* udma0-5 */
edb33667
TH		 459 .port_ops = &sil24_ops,
460 },
461};
462
aee10a03
TH		 463static int sil24_tag(int tag)
464{
465 if (unlikely(ata_tag_internal(tag)))
466 return 0;
467 return tag;
468}
469
cd0d3bbc 470static void sil24_dev_config(struct ata_device *dev)
69ad185f 471{
9af5c9c9 472 void __iomem *port = dev->link->ap->ioaddr.cmd_addr;
69ad185f 473
6e7846e9 474 if (dev->cdb_len == 16)
69ad185f
TH		 475 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
476 else
477 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
478}
479
e59f0dad 480static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
6a575fa9 481{
0d5ff566 482 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 483 struct sil24_prb __iomem *prb;
4b4a5eae 484 u8 fis[6 * 4];
6a575fa9 485
e59f0dad
TH		 486 prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
487 memcpy_fromio(fis, prb->fis, sizeof(fis));
488 ata_tf_from_fis(fis, tf);
6a575fa9
TH		 489}
490
edb33667
TH		 491static int sil24_scr_map[] = {
492 [SCR_CONTROL] = 0,
493 [SCR_STATUS] = 1,
494 [SCR_ERROR] = 2,
495 [SCR_ACTIVE] = 3,
496};
497
da3dbb17 498static int sil24_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
edb33667 499{
0d5ff566 500 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 501
edb33667 502 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 503 void __iomem *addr;
edb33667 504 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
da3dbb17
TH		 505 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
506 return 0;
edb33667 507 }
da3dbb17 508 return -EINVAL;
edb33667
TH		 509}
510
da3dbb17 511static int sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
edb33667 512{
0d5ff566 513 void __iomem *scr_addr = ap->ioaddr.scr_addr;
da3dbb17 514
edb33667 515 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 516 void __iomem *addr;
edb33667
TH		 517 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
518 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
da3dbb17 519 return 0;
edb33667 520 }
da3dbb17 521 return -EINVAL;
edb33667
TH		 522}
523
23818034
TH		 524static void sil24_config_port(struct ata_port *ap)
525{
526 void __iomem *port = ap->ioaddr.cmd_addr;
527
528 /* configure IRQ WoC */
529 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
530 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
531 else
532 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
533
534 /* zero error counters. */
535 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
536 writel(0x8000, port + PORT_CRC_ERR_THRESH);
537 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
538 writel(0x0000, port + PORT_DECODE_ERR_CNT);
539 writel(0x0000, port + PORT_CRC_ERR_CNT);
540 writel(0x0000, port + PORT_HSHK_ERR_CNT);
541
542 /* always use 64bit activation */
543 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
544
545 /* clear port multiplier enable and resume bits */
546 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
547}
548
3454dc69
TH		 549static void sil24_config_pmp(struct ata_port *ap, int attached)
550{
551 void __iomem *port = ap->ioaddr.cmd_addr;
552
553 if (attached)
554 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
555 else
556 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
557}
558
559static void sil24_clear_pmp(struct ata_port *ap)
560{
561 void __iomem *port = ap->ioaddr.cmd_addr;
562 int i;
563
564 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
565
566 for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
567 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
568
569 writel(0, pmp_base + PORT_PMP_STATUS);
570 writel(0, pmp_base + PORT_PMP_QACTIVE);
571 }
572}
573
b5bc421c
TH		 574static int sil24_init_port(struct ata_port *ap)
575{
0d5ff566 576 void __iomem *port = ap->ioaddr.cmd_addr;
23818034 577 struct sil24_port_priv *pp = ap->private_data;
b5bc421c
TH		 578 u32 tmp;
579
3454dc69
TH		 580 /* clear PMP error status */
581 if (ap->nr_pmp_links)
582 sil24_clear_pmp(ap);
583
b5bc421c
TH		 584 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
585 ata_wait_register(port + PORT_CTRL_STAT,
586 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
587 tmp = ata_wait_register(port + PORT_CTRL_STAT,
588 PORT_CS_RDY, 0, 10, 100);
589
23818034
TH		 590 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
591 pp->do_port_rst = 1;
cf480626 592 ap->link.eh_context.i.action |= ATA_EH_RESET;
b5bc421c 593 return -EIO;
23818034
TH		 594 }
595
b5bc421c
TH		 596 return 0;
597}
598
37b99cba
TH		 599static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
600 const struct ata_taskfile *tf,
601 int is_cmd, u32 ctrl,
602 unsigned long timeout_msec)
edb33667 603{
0d5ff566 604 void __iomem *port = ap->ioaddr.cmd_addr;
ca45160d 605 struct sil24_port_priv *pp = ap->private_data;
69ad185f 606 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 607 dma_addr_t paddr = pp->cmd_block_dma;
37b99cba
TH		 608 u32 irq_enabled, irq_mask, irq_stat;
609 int rc;
610
611 prb->ctrl = cpu_to_le16(ctrl);
612 ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
613
614 /* temporarily plug completion and error interrupts */
615 irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
616 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
617
618 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
619 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
620
621 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
622 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
623 10, timeout_msec);
624
625 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
626 irq_stat >>= PORT_IRQ_RAW_SHIFT;
627
628 if (irq_stat & PORT_IRQ_COMPLETE)
629 rc = 0;
630 else {
631 /* force port into known state */
632 sil24_init_port(ap);
633
634 if (irq_stat & PORT_IRQ_ERROR)
635 rc = -EIO;
636 else
637 rc = -EBUSY;
638 }
639
640 /* restore IRQ enabled */
641 writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
642
643 return rc;
644}
645
cc0680a5 646static int sil24_do_softreset(struct ata_link *link, unsigned int *class,
975530e8 647 int pmp, unsigned long deadline)
37b99cba 648{
cc0680a5 649 struct ata_port *ap = link->ap;
37b99cba 650 unsigned long timeout_msec = 0;
e59f0dad 651 struct ata_taskfile tf;
643be977 652 const char *reason;
37b99cba 653 int rc;
ca45160d 654
07b73470
TH		 655 DPRINTK("ENTER\n");
656
cc0680a5 657 if (ata_link_offline(link)) {
10d996ad
TH		 658 DPRINTK("PHY reports no device\n");
659 *class = ATA_DEV_NONE;
660 goto out;
661 }
662
2555d6c2
TH		 663 /* put the port into known state */
664 if (sil24_init_port(ap)) {
5796d1c4 665 reason = "port not ready";
2555d6c2
TH		 666 goto err;
667 }
668
0eaa6058 669 /* do SRST */
37b99cba
TH		 670 if (time_after(deadline, jiffies))
671 timeout_msec = jiffies_to_msecs(deadline - jiffies);
ca45160d 672
cc0680a5 673 ata_tf_init(link->device, &tf); /* doesn't really matter */
975530e8
TH		 674 rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
675 timeout_msec);
37b99cba
TH		 676 if (rc == -EBUSY) {
677 reason = "timeout";
678 goto err;
679 } else if (rc) {
680 reason = "SRST command error";
643be977 681 goto err;
07b73470 682 }
10d996ad 683
e59f0dad
TH		 684 sil24_read_tf(ap, 0, &tf);
685 *class = ata_dev_classify(&tf);
10d996ad 686
07b73470
TH		 687 if (*class == ATA_DEV_UNKNOWN)
688 *class = ATA_DEV_NONE;
ca45160d 689
10d996ad 690 out:
07b73470 691 DPRINTK("EXIT, class=%u\n", *class);
ca45160d 692 return 0;
643be977
TH		 693
694 err:
cc0680a5 695 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
643be977 696 return -EIO;
ca45160d
TH		 697}
698
cc0680a5 699static int sil24_softreset(struct ata_link *link, unsigned int *class,
975530e8
TH		 700 unsigned long deadline)
701{
3454dc69 702 return sil24_do_softreset(link, class, SATA_PMP_CTRL_PORT, deadline);
975530e8
TH		 703}
704
cc0680a5 705static int sil24_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 706 unsigned long deadline)
489ff4c7 707{
cc0680a5 708 struct ata_port *ap = link->ap;
0d5ff566 709 void __iomem *port = ap->ioaddr.cmd_addr;
23818034
TH		 710 struct sil24_port_priv *pp = ap->private_data;
711 int did_port_rst = 0;
ecc2e2b9 712 const char *reason;
e8e008e7 713 int tout_msec, rc;
ecc2e2b9
TH		 714 u32 tmp;
715
23818034
TH		 716 retry:
717 /* Sometimes, DEV_RST is not enough to recover the controller.
718 * This happens often after PM DMA CS errata.
719 */
720 if (pp->do_port_rst) {
721 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
722 "state, performing PORT_RST\n");
723
724 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
725 msleep(10);
726 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
727 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
728 10, 5000);
729
730 /* restore port configuration */
731 sil24_config_port(ap);
732 sil24_config_pmp(ap, ap->nr_pmp_links);
733
734 pp->do_port_rst = 0;
735 did_port_rst = 1;
736 }
737
ecc2e2b9 738 /* sil24 does the right thing(tm) without any protection */
cc0680a5 739 sata_set_spd(link);
ecc2e2b9
TH		 740
741 tout_msec = 100;
cc0680a5 742 if (ata_link_online(link))
ecc2e2b9
TH		 743 tout_msec = 5000;
744
745 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
746 tmp = ata_wait_register(port + PORT_CTRL_STAT,
5796d1c4
JG		 747 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
748 tout_msec);
ecc2e2b9 749
e8e008e7
TH		 750 /* SStatus oscillates between zero and valid status after
751 * DEV_RST, debounce it.
ecc2e2b9 752 */
cc0680a5 753 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
e8e008e7
TH		 754 if (rc) {
755 reason = "PHY debouncing failed";
756 goto err;
757 }
ecc2e2b9
TH		 758
759 if (tmp & PORT_CS_DEV_RST) {
cc0680a5 760 if (ata_link_offline(link))
ecc2e2b9
TH		 761 return 0;
762 reason = "link not ready";
763 goto err;
764 }
765
e8e008e7
TH		 766 /* Sil24 doesn't store signature FIS after hardreset, so we
767 * can't wait for BSY to clear. Some devices take a long time
768 * to get ready and those devices will choke if we don't wait
769 * for BSY clearance here. Tell libata to perform follow-up
770 * softreset.
ecc2e2b9 771 */
e8e008e7 772 return -EAGAIN;
ecc2e2b9
TH		 773
774 err:
23818034
TH		 775 if (!did_port_rst) {
776 pp->do_port_rst = 1;
777 goto retry;
778 }
779
cc0680a5 780 ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason);
ecc2e2b9 781 return -EIO;
489ff4c7
TH		 782}
783
edb33667 784static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 785 struct sil24_sge *sge)
edb33667 786{
972c26bd 787 struct scatterlist *sg;
3be6cbd7 788 struct sil24_sge *last_sge = NULL;
ff2aeb1e 789 unsigned int si;
edb33667 790
ff2aeb1e 791 for_each_sg(qc->sg, sg, qc->n_elem, si) {
edb33667
TH		 792 sge->addr = cpu_to_le64(sg_dma_address(sg));
793 sge->cnt = cpu_to_le32(sg_dma_len(sg));
3be6cbd7
JG		 794 sge->flags = 0;
795
796 last_sge = sge;
972c26bd 797 sge++;
edb33667 798 }
3be6cbd7 799
ff2aeb1e 800 last_sge->flags = cpu_to_le32(SGE_TRM);
edb33667
TH		 801}
802
3454dc69
TH		 803static int sil24_qc_defer(struct ata_queued_cmd *qc)
804{
805 struct ata_link *link = qc->dev->link;
806 struct ata_port *ap = link->ap;
807 u8 prot = qc->tf.protocol;
13cc546b
GG		 808
809 /*
810 * There is a bug in the chip:
811 * Port LRAM Causes the PRB/SGT Data to be Corrupted
812 * If the host issues a read request for LRAM and SActive registers
813 * while active commands are available in the port, PRB/SGT data in
814 * the LRAM can become corrupted. This issue applies only when
815 * reading from, but not writing to, the LRAM.
816 *
817 * Therefore, reading LRAM when there is no particular error [and
818 * other commands may be outstanding] is prohibited.
819 *
820 * To avoid this bug there are two situations where a command must run
821 * exclusive of any other commands on the port:
822 *
823 * - ATAPI commands which check the sense data
824 * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
825 * set.
826 *
827 */
405e66b3 828 int is_excl = (ata_is_atapi(prot) ||
13cc546b
GG		 829 (qc->flags & ATA_QCFLAG_RESULT_TF));
830
3454dc69
TH		 831 if (unlikely(ap->excl_link)) {
832 if (link == ap->excl_link) {
833 if (ap->nr_active_links)
834 return ATA_DEFER_PORT;
835 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
836 } else
837 return ATA_DEFER_PORT;
13cc546b 838 } else if (unlikely(is_excl)) {
3454dc69
TH		 839 ap->excl_link = link;
840 if (ap->nr_active_links)
841 return ATA_DEFER_PORT;
842 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
843 }
844
845 return ata_std_qc_defer(qc);
846}
847
edb33667
TH		 848static void sil24_qc_prep(struct ata_queued_cmd *qc)
849{
850 struct ata_port *ap = qc->ap;
851 struct sil24_port_priv *pp = ap->private_data;
aee10a03 852 union sil24_cmd_block *cb;
69ad185f
TH		 853 struct sil24_prb *prb;
854 struct sil24_sge *sge;
bad28a37 855 u16 ctrl = 0;
edb33667 856
aee10a03
TH		 857 cb = &pp->cmd_block[sil24_tag(qc->tag)];
858
405e66b3 859 if (!ata_is_atapi(qc->tf.protocol)) {
69ad185f
TH		 860 prb = &cb->ata.prb;
861 sge = cb->ata.sge;
405e66b3 862 } else {
69ad185f
TH		 863 prb = &cb->atapi.prb;
864 sge = cb->atapi.sge;
865 memset(cb->atapi.cdb, 0, 32);
6e7846e9 866 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f 867
405e66b3 868 if (ata_is_data(qc->tf.protocol)) {
69ad185f 869 if (qc->tf.flags & ATA_TFLAG_WRITE)
bad28a37 870 ctrl = PRB_CTRL_PACKET_WRITE;
69ad185f 871 else
bad28a37
TH		 872 ctrl = PRB_CTRL_PACKET_READ;
873 }
edb33667
TH		 874 }
875
bad28a37 876 prb->ctrl = cpu_to_le16(ctrl);
3454dc69 877 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
edb33667
TH		 878
879 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 880 sil24_fill_sg(qc, sge);
edb33667
TH		 881}
882
9a3d9eb0 883static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 884{
885 struct ata_port *ap = qc->ap;
886 struct sil24_port_priv *pp = ap->private_data;
0d5ff566 887 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 888 unsigned int tag = sil24_tag(qc->tag);
889 dma_addr_t paddr;
890 void __iomem *activate;
edb33667 891
aee10a03
TH		 892 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
893 activate = port + PORT_CMD_ACTIVATE + tag * 8;
894
895 writel((u32)paddr, activate);
896 writel((u64)paddr >> 32, activate + 4);
26ec634c 897
edb33667
TH		 898 return 0;
899}
900
79f97dad
TH		 901static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
902{
903 sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
904 return true;
905}
906
3454dc69
TH		 907static void sil24_pmp_attach(struct ata_port *ap)
908{
909 sil24_config_pmp(ap, 1);
910 sil24_init_port(ap);
911}
912
913static void sil24_pmp_detach(struct ata_port *ap)
914{
915 sil24_init_port(ap);
916 sil24_config_pmp(ap, 0);
917}
918
3454dc69
TH		 919static int sil24_pmp_softreset(struct ata_link *link, unsigned int *class,
920 unsigned long deadline)
921{
922 return sil24_do_softreset(link, class, link->pmp, deadline);
923}
924
925static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
926 unsigned long deadline)
927{
928 int rc;
929
930 rc = sil24_init_port(link->ap);
931 if (rc) {
932 ata_link_printk(link, KERN_ERR,
933 "hardreset failed (port not ready)\n");
934 return rc;
935 }
936
5958e302 937 return sata_std_hardreset(link, class, deadline);
3454dc69
TH		 938}
939
88ce7550 940static void sil24_freeze(struct ata_port *ap)
7d1ce682 941{
0d5ff566 942 void __iomem *port = ap->ioaddr.cmd_addr;
7d1ce682 943
88ce7550
TH		 944 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
945 * PORT_IRQ_ENABLE instead.
946 */
947 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
7d1ce682
TH		 948}
949
88ce7550 950static void sil24_thaw(struct ata_port *ap)
edb33667 951{
0d5ff566 952 void __iomem *port = ap->ioaddr.cmd_addr;
edb33667
TH		 953 u32 tmp;
954
88ce7550
TH		 955 /* clear IRQ */
956 tmp = readl(port + PORT_IRQ_STAT);
957 writel(tmp, port + PORT_IRQ_STAT);
edb33667 958
88ce7550
TH		 959 /* turn IRQ back on */
960 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
edb33667
TH		 961}
962
88ce7550 963static void sil24_error_intr(struct ata_port *ap)
8746618d 964{
0d5ff566 965 void __iomem *port = ap->ioaddr.cmd_addr;
e59f0dad 966 struct sil24_port_priv *pp = ap->private_data;
3454dc69
TH		 967 struct ata_queued_cmd *qc = NULL;
968 struct ata_link *link;
969 struct ata_eh_info *ehi;
970 int abort = 0, freeze = 0;
88ce7550 971 u32 irq_stat;
8746618d 972
88ce7550 973 /* on error, we need to clear IRQ explicitly */
8746618d 974 irq_stat = readl(port + PORT_IRQ_STAT);
88ce7550 975 writel(irq_stat, port + PORT_IRQ_STAT);
ad6e90f6 976
88ce7550 977 /* first, analyze and record host port events */
3454dc69
TH		 978 link = &ap->link;
979 ehi = &link->eh_info;
88ce7550 980 ata_ehi_clear_desc(ehi);
ad6e90f6 981
88ce7550 982 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
8746618d 983
854c73a2 984 if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
854c73a2 985 ata_ehi_push_desc(ehi, "SDB notify");
7d77b247 986 sata_async_notification(ap);
854c73a2
TH		 987 }
988
0542925b
TH		 989 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
990 ata_ehi_hotplugged(ehi);
b64bbc39
TH		 991 ata_ehi_push_desc(ehi, "%s",
992 irq_stat & PORT_IRQ_PHYRDY_CHG ?
993 "PHY RDY changed" : "device exchanged");
88ce7550 994 freeze = 1;
6a575fa9
TH		 995 }
996
88ce7550
TH		 997 if (irq_stat & PORT_IRQ_UNK_FIS) {
998 ehi->err_mask |= AC_ERR_HSM;
cf480626 999 ehi->action |= ATA_EH_RESET;
b64bbc39 1000 ata_ehi_push_desc(ehi, "unknown FIS");
88ce7550
TH		 1001 freeze = 1;
1002 }
1003
1004 /* deal with command error */
1005 if (irq_stat & PORT_IRQ_ERROR) {
1006 struct sil24_cerr_info *ci = NULL;
1007 unsigned int err_mask = 0, action = 0;
3454dc69
TH		 1008 u32 context, cerr;
1009 int pmp;
1010
1011 abort = 1;
1012
1013 /* DMA Context Switch Failure in Port Multiplier Mode
1014 * errata. If we have active commands to 3 or more
1015 * devices, any error condition on active devices can
1016 * corrupt DMA context switching.
1017 */
1018 if (ap->nr_active_links >= 3) {
1019 ehi->err_mask |= AC_ERR_OTHER;
cf480626 1020 ehi->action |= ATA_EH_RESET;
3454dc69 1021 ata_ehi_push_desc(ehi, "PMP DMA CS errata");
23818034 1022 pp->do_port_rst = 1;
3454dc69
TH		 1023 freeze = 1;
1024 }
1025
1026 /* find out the offending link and qc */
1027 if (ap->nr_pmp_links) {
1028 context = readl(port + PORT_CONTEXT);
1029 pmp = (context >> 5) & 0xf;
1030
1031 if (pmp < ap->nr_pmp_links) {
1032 link = &ap->pmp_link[pmp];
1033 ehi = &link->eh_info;
1034 qc = ata_qc_from_tag(ap, link->active_tag);
1035
1036 ata_ehi_clear_desc(ehi);
1037 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1038 irq_stat);
1039 } else {
1040 err_mask |= AC_ERR_HSM;
cf480626 1041 action |= ATA_EH_RESET;
3454dc69
TH		 1042 freeze = 1;
1043 }
1044 } else
1045 qc = ata_qc_from_tag(ap, link->active_tag);
88ce7550
TH		 1046
1047 /* analyze CMD_ERR */
1048 cerr = readl(port + PORT_CMD_ERR);
1049 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1050 ci = &sil24_cerr_db[cerr];
1051
1052 if (ci && ci->desc) {
1053 err_mask |= ci->err_mask;
1054 action |= ci->action;
cf480626 1055 if (action & ATA_EH_RESET)
c2e14f11 1056 freeze = 1;
b64bbc39 1057 ata_ehi_push_desc(ehi, "%s", ci->desc);
88ce7550
TH		 1058 } else {
1059 err_mask |= AC_ERR_OTHER;
cf480626 1060 action |= ATA_EH_RESET;
c2e14f11 1061 freeze = 1;
b64bbc39 1062 ata_ehi_push_desc(ehi, "unknown command error %d",
88ce7550
TH		 1063 cerr);
1064 }
1065
1066 /* record error info */
520d06f9 1067 if (qc)
88ce7550 1068 qc->err_mask |= err_mask;
520d06f9 1069 else
88ce7550
TH		 1070 ehi->err_mask |= err_mask;
1071
1072 ehi->action |= action;
3454dc69
TH		 1073
1074 /* if PMP, resume */
1075 if (ap->nr_pmp_links)
1076 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
a22e2eb0 1077 }
88ce7550
TH		 1078
1079 /* freeze or abort */
1080 if (freeze)
1081 ata_port_freeze(ap);
3454dc69
TH		 1082 else if (abort) {
1083 if (qc)
1084 ata_link_abort(qc->dev->link);
1085 else
1086 ata_port_abort(ap);
1087 }
8746618d
TH		 1088}
1089
edb33667
TH		 1090static inline void sil24_host_intr(struct ata_port *ap)
1091{
0d5ff566 1092 void __iomem *port = ap->ioaddr.cmd_addr;
aee10a03
TH		 1093 u32 slot_stat, qc_active;
1094 int rc;
edb33667 1095
228f47b9
TH		 1096 /* If PCIX_IRQ_WOC, there's an inherent race window between
1097 * clearing IRQ pending status and reading PORT_SLOT_STAT
1098 * which may cause spurious interrupts afterwards. This is
1099 * unavoidable and much better than losing interrupts which
1100 * happens if IRQ pending is cleared after reading
1101 * PORT_SLOT_STAT.
1102 */
1103 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1104 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1105
edb33667 1106 slot_stat = readl(port + PORT_SLOT_STAT);
37024e8e 1107
88ce7550
TH		 1108 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1109 sil24_error_intr(ap);
1110 return;
1111 }
1112
aee10a03 1113 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
79f97dad 1114 rc = ata_qc_complete_multiple(ap, qc_active);
aee10a03
TH		 1115 if (rc > 0)
1116 return;
1117 if (rc < 0) {
9af5c9c9 1118 struct ata_eh_info *ehi = &ap->link.eh_info;
aee10a03 1119 ehi->err_mask |= AC_ERR_HSM;
cf480626 1120 ehi->action |= ATA_EH_RESET;
aee10a03 1121 ata_port_freeze(ap);
88ce7550
TH		 1122 return;
1123 }
1124
228f47b9
TH		 1125 /* spurious interrupts are expected if PCIX_IRQ_WOC */
1126 if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
88ce7550 1127 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
aee10a03 1128 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
9af5c9c9 1129 slot_stat, ap->link.active_tag, ap->link.sactive);
edb33667
TH		 1130}
1131
7d12e780 1132static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
edb33667 1133{
cca3974e 1134 struct ata_host *host = dev_instance;
0d5ff566 1135 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
edb33667
TH		 1136 unsigned handled = 0;
1137 u32 status;
1138 int i;
1139
0d5ff566 1140 status = readl(host_base + HOST_IRQ_STAT);
edb33667 1141
06460aea
TH		 1142 if (status == 0xffffffff) {
1143 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
1144 "PCI fault or device removal?\n");
1145 goto out;
1146 }
1147
edb33667
TH		 1148 if (!(status & IRQ_STAT_4PORTS))
1149 goto out;
1150
cca3974e 1151 spin_lock(&host->lock);
edb33667 1152
cca3974e 1153 for (i = 0; i < host->n_ports; i++)
edb33667 1154 if (status & (1 << i)) {
cca3974e 1155 struct ata_port *ap = host->ports[i];
198e0fed 1156 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
825cd6dd 1157 sil24_host_intr(ap);
3cc4571c
TH		 1158 handled++;
1159 } else
1160 printk(KERN_ERR DRV_NAME
1161 ": interrupt from disabled port %d\n", i);
edb33667
TH		 1162 }
1163
cca3974e 1164 spin_unlock(&host->lock);
edb33667
TH		 1165 out:
1166 return IRQ_RETVAL(handled);
1167}
1168
88ce7550
TH		 1169static void sil24_error_handler(struct ata_port *ap)
1170{
23818034
TH		 1171 struct sil24_port_priv *pp = ap->private_data;
1172
3454dc69 1173 if (sil24_init_port(ap))
88ce7550 1174 ata_eh_freeze_port(ap);
88ce7550 1175
a1efdaba 1176 sata_pmp_error_handler(ap);
23818034
TH		 1177
1178 pp->do_port_rst = 0;
88ce7550
TH		 1179}
1180
1181static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1182{
1183 struct ata_port *ap = qc->ap;
1184
88ce7550 1185 /* make DMA engine forget about the failed command */
3454dc69
TH		 1186 if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1187 ata_eh_freeze_port(ap);
88ce7550
TH		 1188}
1189
edb33667
TH		 1190static int sil24_port_start(struct ata_port *ap)
1191{
cca3974e 1192 struct device *dev = ap->host->dev;
edb33667 1193 struct sil24_port_priv *pp;
69ad185f 1194 union sil24_cmd_block *cb;
aee10a03 1195 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
edb33667
TH		 1196 dma_addr_t cb_dma;
1197
24dc5f33 1198 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
edb33667 1199 if (!pp)
24dc5f33 1200 return -ENOMEM;
edb33667 1201
24dc5f33 1202 cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb 1203 if (!cb)
24dc5f33 1204 return -ENOMEM;
edb33667
TH		 1205 memset(cb, 0, cb_size);
1206
edb33667
TH		 1207 pp->cmd_block = cb;
1208 pp->cmd_block_dma = cb_dma;
1209
1210 ap->private_data = pp;
1211
1212 return 0;
edb33667
TH		 1213}
1214
4447d351 1215static void sil24_init_controller(struct ata_host *host)
2a41a610 1216{
4447d351 1217 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
2a41a610
TH		 1218 u32 tmp;
1219 int i;
1220
1221 /* GPIO off */
1222 writel(0, host_base + HOST_FLASH_CMD);
1223
1224 /* clear global reset & mask interrupts during initialization */
1225 writel(0, host_base + HOST_CTRL);
1226
1227 /* init ports */
4447d351 1228 for (i = 0; i < host->n_ports; i++) {
23818034
TH		 1229 struct ata_port *ap = host->ports[i];
1230 void __iomem *port = ap->ioaddr.cmd_addr;
2a41a610
TH		 1231
1232 /* Initial PHY setting */
1233 writel(0x20c, port + PORT_PHY_CFG);
1234
1235 /* Clear port RST */
1236 tmp = readl(port + PORT_CTRL_STAT);
1237 if (tmp & PORT_CS_PORT_RST) {
1238 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1239 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1240 PORT_CS_PORT_RST,
1241 PORT_CS_PORT_RST, 10, 100);
1242 if (tmp & PORT_CS_PORT_RST)
4447d351 1243 dev_printk(KERN_ERR, host->dev,
5796d1c4 1244 "failed to clear port RST\n");
2a41a610
TH		 1245 }
1246
23818034
TH		 1247 /* configure port */
1248 sil24_config_port(ap);
2a41a610
TH		 1249 }
1250
1251 /* Turn on interrupts */
1252 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1253}
1254
edb33667
TH		 1255static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1256{
93e2618e 1257 extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
5796d1c4 1258 static int printed_version;
4447d351
TH		 1259 struct ata_port_info pi = sil24_port_info[ent->driver_data];
1260 const struct ata_port_info *ppi[] = { &pi, NULL };
1261 void __iomem * const *iomap;
1262 struct ata_host *host;
edb33667 1263 int i, rc;
37024e8e 1264 u32 tmp;
edb33667 1265
93e2618e
TH		 1266 /* cause link error if sil24_cmd_block is sized wrongly */
1267 if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1268 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1269
edb33667 1270 if (!printed_version++)
a9524a76 1271 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667 1272
4447d351 1273 /* acquire resources */
24dc5f33 1274 rc = pcim_enable_device(pdev);
edb33667
TH		 1275 if (rc)
1276 return rc;
1277
0d5ff566
TH		 1278 rc = pcim_iomap_regions(pdev,
1279 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1280 DRV_NAME);
edb33667 1281 if (rc)
24dc5f33 1282 return rc;
4447d351 1283 iomap = pcim_iomap_table(pdev);
edb33667 1284
4447d351
TH		 1285 /* apply workaround for completion IRQ loss on PCI-X errata */
1286 if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1287 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1288 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1289 dev_printk(KERN_INFO, &pdev->dev,
1290 "Applying completion IRQ loss on PCI-X "
1291 "errata fix\n");
1292 else
1293 pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1294 }
edb33667 1295
4447d351
TH		 1296 /* allocate and fill host */
1297 host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1298 SIL24_FLAG2NPORTS(ppi[0]->flags));
1299 if (!host)
1300 return -ENOMEM;
1301 host->iomap = iomap;
edb33667 1302
4447d351 1303 for (i = 0; i < host->n_ports; i++) {
cbcdd875
TH		 1304 struct ata_port *ap = host->ports[i];
1305 size_t offset = ap->port_no * PORT_REGS_SIZE;
1306 void __iomem *port = iomap[SIL24_PORT_BAR] + offset;
edb33667 1307
4447d351
TH		 1308 host->ports[i]->ioaddr.cmd_addr = port;
1309 host->ports[i]->ioaddr.scr_addr = port + PORT_SCONTROL;
edb33667 1310
cbcdd875
TH		 1311 ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1312 ata_port_pbar_desc(ap, SIL24_PORT_BAR, offset, "port");
4447d351 1313 }
edb33667 1314
4447d351 1315 /* configure and activate the device */
26ec634c
TH		 1316 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1317 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1318 if (rc) {
1319 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1320 if (rc) {
1321 dev_printk(KERN_ERR, &pdev->dev,
1322 "64-bit DMA enable failed\n");
24dc5f33 1323 return rc;
26ec634c
TH		 1324 }
1325 }
1326 } else {
1327 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1328 if (rc) {
1329 dev_printk(KERN_ERR, &pdev->dev,
1330 "32-bit DMA enable failed\n");
24dc5f33 1331 return rc;
26ec634c
TH		 1332 }
1333 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1334 if (rc) {
1335 dev_printk(KERN_ERR, &pdev->dev,
1336 "32-bit consistent DMA enable failed\n");
24dc5f33 1337 return rc;
26ec634c 1338 }
edb33667
TH		 1339 }
1340
4447d351 1341 sil24_init_controller(host);
edb33667
TH		 1342
1343 pci_set_master(pdev);
4447d351
TH		 1344 return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1345 &sil24_sht);
edb33667
TH		 1346}
1347
281d426c 1348#ifdef CONFIG_PM
d2298dca
TH		 1349static int sil24_pci_device_resume(struct pci_dev *pdev)
1350{
cca3974e 1351 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1352 void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
553c4aa6 1353 int rc;
d2298dca 1354
553c4aa6
TH		 1355 rc = ata_pci_device_do_resume(pdev);
1356 if (rc)
1357 return rc;
d2298dca
TH		 1358
1359 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
0d5ff566 1360 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
d2298dca 1361
4447d351 1362 sil24_init_controller(host);
d2298dca 1363
cca3974e 1364 ata_host_resume(host);
d2298dca
TH		 1365
1366 return 0;
1367}
3454dc69
TH		 1368
1369static int sil24_port_resume(struct ata_port *ap)
1370{
1371 sil24_config_pmp(ap, ap->nr_pmp_links);
1372 return 0;
1373}
281d426c 1374#endif
d2298dca 1375
edb33667
TH		 1376static int __init sil24_init(void)
1377{
b7887196 1378 return pci_register_driver(&sil24_pci_driver);
edb33667
TH		 1379}
1380
1381static void __exit sil24_exit(void)
1382{
1383 pci_unregister_driver(&sil24_pci_driver);
1384}
1385
1386MODULE_AUTHOR("Tejun Heo");
1387MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1388MODULE_LICENSE("GPL");
1389MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1390
1391module_init(sil24_init);
1392module_exit(sil24_exit);
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