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sata_mv: introduce support for ATAPI devices
[net-next-2.6.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
85afb934
ML		 34 * --> Develop a low-power-consumption strategy, and implement it.
35 *
36 * --> [Experiment, low priority] Investigate interrupt coalescing.
37 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
38 * the overhead reduced by interrupt mitigation is quite often not
39 * worth the latency cost.
40 *
41 * --> [Experiment, Marvell value added] Is it possible to use target
42 * mode to cross-connect two Linux boxes with Marvell cards? If so,
43 * creating LibATA target mode support would be very interesting.
44 *
45 * Target mode, for those without docs, is the ability to directly
46 * connect two SATA ports.
47 */
4a05e209 48
20f733e7
BR		 49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/pci.h>
52#include <linux/init.h>
53#include <linux/blkdev.h>
54#include <linux/delay.h>
55#include <linux/interrupt.h>
8d8b6004 56#include <linux/dmapool.h>
20f733e7 57#include <linux/dma-mapping.h>
a9524a76 58#include <linux/device.h>
f351b2d6
SB		 59#include <linux/platform_device.h>
60#include <linux/ata_platform.h>
15a32632 61#include <linux/mbus.h>
c46938cc 62#include <linux/bitops.h>
20f733e7 63#include <scsi/scsi_host.h>
193515d5 64#include <scsi/scsi_cmnd.h>
6c08772e 65#include <scsi/scsi_device.h>
20f733e7 66#include <linux/libata.h>
20f733e7
BR		 67
68#define DRV_NAME "sata_mv"
da14265e 69#define DRV_VERSION "1.26"
20f733e7
BR		 70
71enum {
72 /* BAR's are enumerated in terms of pci_resource_start() terms */
73 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
74 MV_IO_BAR = 2, /* offset 0x18: IO space */
75 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
76
77 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
78 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
79
80 MV_PCI_REG_BASE = 0,
81 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 82 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
83 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
84 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
85 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
86 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
87
20f733e7 88 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 89 MV_FLASH_CTL_OFS = 0x1046c,
90 MV_GPIO_PORT_CTL_OFS = 0x104f0,
91 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 92
93 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
94 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
95 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
96 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
97
31961943
BR		 98 MV_MAX_Q_DEPTH = 32,
99 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
100
101 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
102 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 103 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
104 */
105 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
106 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 107 MV_MAX_SG_CT = 256,
31961943 108 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 109
352fab70 110 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 111 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 112 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
113 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
114 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 115
116 /* Host Flags */
117 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
118 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 119
c5d3e45a 120 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91b1a84c 121 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
ad3aef51 122
91b1a84c 123 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 124
91b1a84c 125 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE |
ad3aef51 126 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
da14265e 127 ATA_FLAG_NCQ,
91b1a84c
ML		 128
129 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 130
31961943
BR		 131 CRQB_FLAG_READ = (1 << 0),
132 CRQB_TAG_SHIFT = 1,
c5d3e45a 133 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 134 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 135 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 136 CRQB_CMD_ADDR_SHIFT = 8,
137 CRQB_CMD_CS = (0x2 << 11),
138 CRQB_CMD_LAST = (1 << 15),
139
140 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 141 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
142 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 143
144 EPRD_FLAG_END_OF_TBL = (1 << 31),
145
20f733e7
BR		 146 /* PCI interface registers */
147
31961943 148 PCI_COMMAND_OFS = 0xc00,
8e7decdb 149 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 150
20f733e7
BR		 151 PCI_MAIN_CMD_STS_OFS = 0xd30,
152 STOP_PCI_MASTER = (1 << 2),
153 PCI_MASTER_EMPTY = (1 << 3),
154 GLOB_SFT_RST = (1 << 4),
155
8e7decdb
ML		 156 MV_PCI_MODE_OFS = 0xd00,
157 MV_PCI_MODE_MASK = 0x30,
158
522479fb
JG		 159 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
160 MV_PCI_DISC_TIMER = 0xd04,
161 MV_PCI_MSI_TRIGGER = 0xc38,
162 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 163 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 164 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
165 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
166 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
167 MV_PCI_ERR_COMMAND = 0x1d50,
168
02a121da
ML		 169 PCI_IRQ_CAUSE_OFS = 0x1d58,
170 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 171 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
172
02a121da
ML		 173 PCIE_IRQ_CAUSE_OFS = 0x1900,
174 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 175 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 176
7368f919
ML		 177 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
178 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
179 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
180 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
181 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 182 ERR_IRQ = (1 << 0), /* shift by port # */
183 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 184 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
185 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
186 PCI_ERR = (1 << 18),
187 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
188 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 189 PORTS_0_3_COAL_DONE = (1 << 8),
190 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 191 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
192 GPIO_INT = (1 << 22),
193 SELF_INT = (1 << 23),
194 TWSI_INT = (1 << 24),
195 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 196 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 197 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 198
199 /* SATAHC registers */
200 HC_CFG_OFS = 0,
201
202 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 203 DMA_IRQ = (1 << 0), /* shift by port # */
204 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 205 DEV_IRQ = (1 << 8), /* shift by port # */
206
207 /* Shadow block registers */
31961943
BR		 208 SHD_BLK_OFS = 0x100,
209 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 210
211 /* SATA registers */
212 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
213 SATA_ACTIVE_OFS = 0x350,
0c58912e 214 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 215 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 216
e12bef50 217 LTMODE_OFS = 0x30c,
17c5aab5
ML		 218 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
219
47c2b677 220 PHY_MODE3 = 0x310,
bca1c4eb 221 PHY_MODE4 = 0x314,
ba069e37
ML		 222 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
223 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
224 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
225 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
226
bca1c4eb 227 PHY_MODE2 = 0x330,
e12bef50 228 SATA_IFCTL_OFS = 0x344,
8e7decdb 229 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 230 SATA_IFSTAT_OFS = 0x34c,
231 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 232
8e7decdb
ML		 233 FISCFG_OFS = 0x360,
234 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
235 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 236
c9d39130 237 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 238 MV5_LTMODE_OFS = 0x30,
239 MV5_PHY_CTL_OFS = 0x0C,
240 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 241
242 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 243
244 /* Port registers */
245 EDMA_CFG_OFS = 0,
0c58912e
ML		 246 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
247 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
248 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
249 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
250 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 251 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
252 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 253
254 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
255 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 256 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
257 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
258 EDMA_ERR_DEV = (1 << 2), /* device error */
259 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
260 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
261 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 262 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
263 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 264 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 265 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 266 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
267 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
268 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
269 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 270
6c1153e0 271 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 272 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
273 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
274 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
275 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
276
6c1153e0 277 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 278
6c1153e0 279 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 280 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
283 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
284 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
285
6c1153e0 286 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 287
6c1153e0 288 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 289 EDMA_ERR_OVERRUN_5 = (1 << 5),
290 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 291
292 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
293 EDMA_ERR_LNK_CTRL_RX_1 |
294 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 295 EDMA_ERR_LNK_CTRL_TX,
646a4da5 296
bdd4ddde
JG		 297 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
298 EDMA_ERR_PRD_PAR |
299 EDMA_ERR_DEV_DCON |
300 EDMA_ERR_DEV_CON |
301 EDMA_ERR_SERR |
302 EDMA_ERR_SELF_DIS |
6c1153e0 303 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 304 EDMA_ERR_CRPB_PAR |
305 EDMA_ERR_INTRL_PAR |
306 EDMA_ERR_IORDY |
307 EDMA_ERR_LNK_CTRL_RX_2 |
308 EDMA_ERR_LNK_DATA_RX |
309 EDMA_ERR_LNK_DATA_TX |
310 EDMA_ERR_TRANS_PROTO,
e12bef50 311
bdd4ddde
JG		 312 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
313 EDMA_ERR_PRD_PAR |
314 EDMA_ERR_DEV_DCON |
315 EDMA_ERR_DEV_CON |
316 EDMA_ERR_OVERRUN_5 |
317 EDMA_ERR_UNDERRUN_5 |
318 EDMA_ERR_SELF_DIS_5 |
6c1153e0 319 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 320 EDMA_ERR_CRPB_PAR |
321 EDMA_ERR_INTRL_PAR |
322 EDMA_ERR_IORDY,
20f733e7 323
31961943
BR		 324 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
325 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 326
327 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
328 EDMA_REQ_Q_PTR_SHIFT = 5,
329
330 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
331 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
332 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 333 EDMA_RSP_Q_PTR_SHIFT = 3,
334
0ea9e179
JG		 335 EDMA_CMD_OFS = 0x28, /* EDMA command register */
336 EDMA_EN = (1 << 0), /* enable EDMA */
337 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 338 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
339
340 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
341 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
342 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 343
8e7decdb
ML		 344 EDMA_IORDY_TMOUT_OFS = 0x34,
345 EDMA_ARB_CFG_OFS = 0x38,
346
347 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 348
da14265e
ML		 349
350 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
351 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
352 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
353 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
354
31961943
BR		 355 /* Host private flags (hp_flags) */
356 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 357 MV_HP_ERRATA_50XXB0 = (1 << 1),
358 MV_HP_ERRATA_50XXB2 = (1 << 2),
359 MV_HP_ERRATA_60X1B2 = (1 << 3),
360 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 361 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
362 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
363 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 364 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 365 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 366 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
20f733e7 367
31961943 368 /* Port private flags (pp_flags) */
0ea9e179 369 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 370 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 371 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 372 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 373};
374
ee9ccdf7
JG		 375#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
376#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 377#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 378#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 379#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 380
15a32632
LB		 381#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
382#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
383
095fec88 384enum {
baf14aa1
JG		 385 /* DMA boundary 0xffff is required by the s/g splitting
386 * we need on /length/ in mv_fill-sg().
387 */
388 MV_DMA_BOUNDARY = 0xffffU,
095fec88 389
0ea9e179
JG		 390 /* mask of register bits containing lower 32 bits
391 * of EDMA request queue DMA address
392 */
095fec88
JG		 393 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
394
0ea9e179 395 /* ditto, for response queue */
095fec88
JG		 396 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
397};
398
522479fb
JG		 399enum chip_type {
400 chip_504x,
401 chip_508x,
402 chip_5080,
403 chip_604x,
404 chip_608x,
e4e7b892
JG		 405 chip_6042,
406 chip_7042,
f351b2d6 407 chip_soc,
522479fb
JG		 408};
409
31961943
BR		 410/* Command ReQuest Block: 32B */
411struct mv_crqb {
e1469874
ML		 412 __le32 sg_addr;
413 __le32 sg_addr_hi;
414 __le16 ctrl_flags;
415 __le16 ata_cmd[11];
31961943 416};
20f733e7 417
e4e7b892 418struct mv_crqb_iie {
e1469874
ML		 419 __le32 addr;
420 __le32 addr_hi;
421 __le32 flags;
422 __le32 len;
423 __le32 ata_cmd[4];
e4e7b892
JG		 424};
425
31961943
BR		 426/* Command ResPonse Block: 8B */
427struct mv_crpb {
e1469874
ML		 428 __le16 id;
429 __le16 flags;
430 __le32 tmstmp;
20f733e7
BR		 431};
432
31961943
BR		 433/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
434struct mv_sg {
e1469874
ML		 435 __le32 addr;
436 __le32 flags_size;
437 __le32 addr_hi;
438 __le32 reserved;
31961943 439};
20f733e7 440
31961943
BR		 441struct mv_port_priv {
442 struct mv_crqb *crqb;
443 dma_addr_t crqb_dma;
444 struct mv_crpb *crpb;
445 dma_addr_t crpb_dma;
eb73d558
ML		 446 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
447 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 448
449 unsigned int req_idx;
450 unsigned int resp_idx;
451
31961943 452 u32 pp_flags;
29d187bb 453 unsigned int delayed_eh_pmp_map;
31961943
BR		 454};
455
bca1c4eb
JG		 456struct mv_port_signal {
457 u32 amps;
458 u32 pre;
459};
460
02a121da
ML		 461struct mv_host_priv {
462 u32 hp_flags;
96e2c487 463 u32 main_irq_mask;
02a121da
ML		 464 struct mv_port_signal signal[8];
465 const struct mv_hw_ops *ops;
f351b2d6
SB		 466 int n_ports;
467 void __iomem *base;
7368f919
ML		 468 void __iomem *main_irq_cause_addr;
469 void __iomem *main_irq_mask_addr;
02a121da
ML		 470 u32 irq_cause_ofs;
471 u32 irq_mask_ofs;
472 u32 unmask_all_irqs;
da2fa9ba
ML		 473 /*
474 * These consistent DMA memory pools give us guaranteed
475 * alignment for hardware-accessed data structures,
476 * and less memory waste in accomplishing the alignment.
477 */
478 struct dma_pool *crqb_pool;
479 struct dma_pool *crpb_pool;
480 struct dma_pool *sg_tbl_pool;
02a121da
ML		 481};
482
47c2b677 483struct mv_hw_ops {
2a47ce06
JG		 484 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
485 unsigned int port);
47c2b677
JG		 486 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
487 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
488 void __iomem *mmio);
c9d39130
JG		 489 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
490 unsigned int n_hc);
522479fb 491 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 492 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 493};
494
82ef04fb
TH		 495static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
496static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
497static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
498static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 499static int mv_port_start(struct ata_port *ap);
500static void mv_port_stop(struct ata_port *ap);
3e4a1391 501static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 502static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 503static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 504static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 505static int mv_hardreset(struct ata_link *link, unsigned int *class,
506 unsigned long deadline);
bdd4ddde
JG		 507static void mv_eh_freeze(struct ata_port *ap);
508static void mv_eh_thaw(struct ata_port *ap);
f273827e 509static void mv6_dev_config(struct ata_device *dev);
20f733e7 510
2a47ce06
JG		 511static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
512 unsigned int port);
47c2b677
JG		 513static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
514static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
515 void __iomem *mmio);
c9d39130
JG		 516static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
517 unsigned int n_hc);
522479fb 518static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 519static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 520
2a47ce06
JG		 521static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
522 unsigned int port);
47c2b677
JG		 523static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
524static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
525 void __iomem *mmio);
c9d39130
JG		 526static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
527 unsigned int n_hc);
522479fb 528static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 529static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
530 void __iomem *mmio);
531static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
532 void __iomem *mmio);
533static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
534 void __iomem *mmio, unsigned int n_hc);
535static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
536 void __iomem *mmio);
537static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 538static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 539static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 540 unsigned int port_no);
e12bef50 541static int mv_stop_edma(struct ata_port *ap);
b562468c 542static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 543static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 544
e49856d8
ML		 545static void mv_pmp_select(struct ata_port *ap, int pmp);
546static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline);
548static int mv_softreset(struct ata_link *link, unsigned int *class,
549 unsigned long deadline);
29d187bb 550static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 551static void mv_process_crpb_entries(struct ata_port *ap,
552 struct mv_port_priv *pp);
47c2b677 553
da14265e
ML		 554static unsigned long mv_mode_filter(struct ata_device *dev,
555 unsigned long xfer_mask);
556static void mv_sff_irq_clear(struct ata_port *ap);
557static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
558static void mv_bmdma_setup(struct ata_queued_cmd *qc);
559static void mv_bmdma_start(struct ata_queued_cmd *qc);
560static void mv_bmdma_stop(struct ata_queued_cmd *qc);
561static u8 mv_bmdma_status(struct ata_port *ap);
562
eb73d558
ML		 563/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
564 * because we have to allow room for worst case splitting of
565 * PRDs for 64K boundaries in mv_fill_sg().
566 */
c5d3e45a 567static struct scsi_host_template mv5_sht = {
68d1d07b 568 ATA_BASE_SHT(DRV_NAME),
baf14aa1 569 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 570 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 571};
572
573static struct scsi_host_template mv6_sht = {
68d1d07b 574 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 575 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 576 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 577 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 578};
579
029cfd6b
TH		 580static struct ata_port_operations mv5_ops = {
581 .inherits = &ata_sff_port_ops,
c9d39130 582
3e4a1391 583 .qc_defer = mv_qc_defer,
c9d39130
JG		 584 .qc_prep = mv_qc_prep,
585 .qc_issue = mv_qc_issue,
c9d39130 586
bdd4ddde
JG		 587 .freeze = mv_eh_freeze,
588 .thaw = mv_eh_thaw,
a1efdaba 589 .hardreset = mv_hardreset,
a1efdaba 590 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 591 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 592
c9d39130
JG		 593 .scr_read = mv5_scr_read,
594 .scr_write = mv5_scr_write,
595
596 .port_start = mv_port_start,
597 .port_stop = mv_port_stop,
c9d39130
JG		 598};
599
029cfd6b
TH		 600static struct ata_port_operations mv6_ops = {
601 .inherits = &mv5_ops,
f273827e 602 .dev_config = mv6_dev_config,
20f733e7
BR		 603 .scr_read = mv_scr_read,
604 .scr_write = mv_scr_write,
605
e49856d8
ML		 606 .pmp_hardreset = mv_pmp_hardreset,
607 .pmp_softreset = mv_softreset,
608 .softreset = mv_softreset,
29d187bb 609 .error_handler = mv_pmp_error_handler,
da14265e
ML		 610
611 .sff_irq_clear = mv_sff_irq_clear,
612 .check_atapi_dma = mv_check_atapi_dma,
613 .bmdma_setup = mv_bmdma_setup,
614 .bmdma_start = mv_bmdma_start,
615 .bmdma_stop = mv_bmdma_stop,
616 .bmdma_status = mv_bmdma_status,
617 .mode_filter = mv_mode_filter,
20f733e7
BR		 618};
619
029cfd6b
TH		 620static struct ata_port_operations mv_iie_ops = {
621 .inherits = &mv6_ops,
622 .dev_config = ATA_OP_NULL,
e4e7b892 623 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 624};
625
98ac62de 626static const struct ata_port_info mv_port_info[] = {
20f733e7 627 { /* chip_504x */
91b1a84c 628 .flags = MV_GEN_I_FLAGS,
31961943 629 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 630 .udma_mask = ATA_UDMA6,
c9d39130 631 .port_ops = &mv5_ops,
20f733e7
BR		 632 },
633 { /* chip_508x */
91b1a84c 634 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
31961943 635 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 636 .udma_mask = ATA_UDMA6,
c9d39130 637 .port_ops = &mv5_ops,
20f733e7 638 },
47c2b677 639 { /* chip_5080 */
91b1a84c 640 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 641 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 642 .udma_mask = ATA_UDMA6,
c9d39130 643 .port_ops = &mv5_ops,
47c2b677 644 },
20f733e7 645 { /* chip_604x */
91b1a84c 646 .flags = MV_GEN_II_FLAGS,
31961943 647 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 648 .udma_mask = ATA_UDMA6,
c9d39130 649 .port_ops = &mv6_ops,
20f733e7
BR		 650 },
651 { /* chip_608x */
91b1a84c 652 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
31961943 653 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 654 .udma_mask = ATA_UDMA6,
c9d39130 655 .port_ops = &mv6_ops,
20f733e7 656 },
e4e7b892 657 { /* chip_6042 */
91b1a84c 658 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 659 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 660 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 661 .port_ops = &mv_iie_ops,
662 },
663 { /* chip_7042 */
91b1a84c 664 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 665 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 666 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 667 .port_ops = &mv_iie_ops,
668 },
f351b2d6 669 { /* chip_soc */
91b1a84c 670 .flags = MV_GEN_IIE_FLAGS,
17c5aab5
ML		 671 .pio_mask = 0x1f, /* pio0-4 */
672 .udma_mask = ATA_UDMA6,
673 .port_ops = &mv_iie_ops,
f351b2d6 674 },
20f733e7
BR		 675};
676
3b7d697d 677static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 678 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
679 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
680 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
681 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 682 /* RocketRAID 1720/174x have different identifiers */
683 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 684 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
685 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 686
687 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
688 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
689 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
690 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
691 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
692
693 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
694
d9f9c6bc
FA		 695 /* Adaptec 1430SA */
696 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
697
02a121da 698 /* Marvell 7042 support */
6a3d586d
MT		 699 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
700
02a121da
ML		 701 /* Highpoint RocketRAID PCIe series */
702 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
703 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
704
2d2744fc 705 { } /* terminate list */
20f733e7
BR		 706};
707
47c2b677
JG		 708static const struct mv_hw_ops mv5xxx_ops = {
709 .phy_errata = mv5_phy_errata,
710 .enable_leds = mv5_enable_leds,
711 .read_preamp = mv5_read_preamp,
712 .reset_hc = mv5_reset_hc,
522479fb
JG		 713 .reset_flash = mv5_reset_flash,
714 .reset_bus = mv5_reset_bus,
47c2b677
JG		 715};
716
717static const struct mv_hw_ops mv6xxx_ops = {
718 .phy_errata = mv6_phy_errata,
719 .enable_leds = mv6_enable_leds,
720 .read_preamp = mv6_read_preamp,
721 .reset_hc = mv6_reset_hc,
522479fb
JG		 722 .reset_flash = mv6_reset_flash,
723 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 724};
725
f351b2d6
SB		 726static const struct mv_hw_ops mv_soc_ops = {
727 .phy_errata = mv6_phy_errata,
728 .enable_leds = mv_soc_enable_leds,
729 .read_preamp = mv_soc_read_preamp,
730 .reset_hc = mv_soc_reset_hc,
731 .reset_flash = mv_soc_reset_flash,
732 .reset_bus = mv_soc_reset_bus,
733};
734
20f733e7
BR		 735/*
736 * Functions
737 */
738
739static inline void writelfl(unsigned long data, void __iomem *addr)
740{
741 writel(data, addr);
742 (void) readl(addr); /* flush to avoid PCI posted write */
743}
744
c9d39130
JG		 745static inline unsigned int mv_hc_from_port(unsigned int port)
746{
747 return port >> MV_PORT_HC_SHIFT;
748}
749
750static inline unsigned int mv_hardport_from_port(unsigned int port)
751{
752 return port & MV_PORT_MASK;
753}
754
1cfd19ae
ML		 755/*
756 * Consolidate some rather tricky bit shift calculations.
757 * This is hot-path stuff, so not a function.
758 * Simple code, with two return values, so macro rather than inline.
759 *
760 * port is the sole input, in range 0..7.
7368f919
ML		 761 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
762 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 763 *
764 * Note that port and hardport may be the same variable in some cases.
765 */
766#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
767{ \
768 shift = mv_hc_from_port(port) * HC_SHIFT; \
769 hardport = mv_hardport_from_port(port); \
770 shift += hardport * 2; \
771}
772
352fab70
ML		 773static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
774{
775 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
776}
777
c9d39130
JG		 778static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
779 unsigned int port)
780{
781 return mv_hc_base(base, mv_hc_from_port(port));
782}
783
20f733e7
BR		 784static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
785{
c9d39130 786 return mv_hc_base_from_port(base, port) +
8b260248 787 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 788 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 789}
790
e12bef50
ML		 791static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
792{
793 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
794 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
795
796 return hc_mmio + ofs;
797}
798
f351b2d6
SB		 799static inline void __iomem *mv_host_base(struct ata_host *host)
800{
801 struct mv_host_priv *hpriv = host->private_data;
802 return hpriv->base;
803}
804
20f733e7
BR		 805static inline void __iomem *mv_ap_base(struct ata_port *ap)
806{
f351b2d6 807 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 808}
809
cca3974e 810static inline int mv_get_hc_count(unsigned long port_flags)
31961943 811{
cca3974e 812 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 813}
814
c5d3e45a
JG		 815static void mv_set_edma_ptrs(void __iomem *port_mmio,
816 struct mv_host_priv *hpriv,
817 struct mv_port_priv *pp)
818{
bdd4ddde
JG		 819 u32 index;
820
c5d3e45a
JG		 821 /*
822 * initialize request queue
823 */
fcfb1f77
ML		 824 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 826
c5d3e45a
JG		 827 WARN_ON(pp->crqb_dma & 0x3ff);
828 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 829 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a 830 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
5cf73bfb 831 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 832
833 /*
834 * initialize response queue
835 */
fcfb1f77
ML		 836 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
837 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 838
c5d3e45a
JG		 839 WARN_ON(pp->crpb_dma & 0xff);
840 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
5cf73bfb 841 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
bdd4ddde 842 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 843 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 844}
845
c4de573b
ML		 846static void mv_set_main_irq_mask(struct ata_host *host,
847 u32 disable_bits, u32 enable_bits)
848{
849 struct mv_host_priv *hpriv = host->private_data;
850 u32 old_mask, new_mask;
851
96e2c487 852 old_mask = hpriv->main_irq_mask;
c4de573b 853 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 854 if (new_mask != old_mask) {
855 hpriv->main_irq_mask = new_mask;
c4de573b 856 writelfl(new_mask, hpriv->main_irq_mask_addr);
96e2c487 857 }
c4de573b
ML		 858}
859
860static void mv_enable_port_irqs(struct ata_port *ap,
861 unsigned int port_bits)
862{
863 unsigned int shift, hardport, port = ap->port_no;
864 u32 disable_bits, enable_bits;
865
866 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
867
868 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
869 enable_bits = port_bits << shift;
870 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
871}
872
00b81235
ML		 873static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
874 void __iomem *port_mmio,
875 unsigned int port_irqs)
876{
877 struct mv_host_priv *hpriv = ap->host->private_data;
878 int hardport = mv_hardport_from_port(ap->port_no);
879 void __iomem *hc_mmio = mv_hc_base_from_port(
880 mv_host_base(ap->host), ap->port_no);
881 u32 hc_irq_cause;
882
883 /* clear EDMA event indicators, if any */
884 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
885
886 /* clear pending irq events */
887 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
888 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
889
890 /* clear FIS IRQ Cause */
891 if (IS_GEN_IIE(hpriv))
892 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
893
894 mv_enable_port_irqs(ap, port_irqs);
895}
896
05b308e1 897/**
00b81235 898 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 899 * @base: port base address
900 * @pp: port private data
901 *
beec7dbc
TH		 902 * Verify the local cache of the eDMA state is accurate with a
903 * WARN_ON.
05b308e1
BR		 904 *
905 * LOCKING:
906 * Inherited from caller.
907 */
00b81235 908static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 909 struct mv_port_priv *pp, u8 protocol)
20f733e7 910{
72109168
ML		 911 int want_ncq = (protocol == ATA_PROT_NCQ);
912
913 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
914 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
915 if (want_ncq != using_ncq)
b562468c 916 mv_stop_edma(ap);
72109168 917 }
c5d3e45a 918 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 919 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 920
00b81235 921 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 922
f630d562 923 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 924 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 925
f630d562 926 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 927 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
928 }
20f733e7
BR		 929}
930
9b2c4e0b
ML		 931static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
932{
933 void __iomem *port_mmio = mv_ap_base(ap);
934 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
935 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
936 int i;
937
938 /*
939 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 940 * No idea what a good "timeout" value might be, but measurements
941 * indicate that it often requires hundreds of microseconds
942 * with two drives in-use. So we use the 15msec value above
943 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 944 */
945 for (i = 0; i < timeout; ++i) {
946 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
947 if ((edma_stat & empty_idle) == empty_idle)
948 break;
949 udelay(per_loop);
950 }
951 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
952}
953
05b308e1 954/**
e12bef50 955 * mv_stop_edma_engine - Disable eDMA engine
b562468c 956 * @port_mmio: io base address
05b308e1
BR		 957 *
958 * LOCKING:
959 * Inherited from caller.
960 */
b562468c 961static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 962{
b562468c 963 int i;
31961943 964
b562468c
ML		 965 /* Disable eDMA. The disable bit auto clears. */
966 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 967
b562468c
ML		 968 /* Wait for the chip to confirm eDMA is off. */
969 for (i = 10000; i > 0; i--) {
970 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 971 if (!(reg & EDMA_EN))
b562468c
ML		 972 return 0;
973 udelay(10);
31961943 974 }
b562468c 975 return -EIO;
20f733e7
BR		 976}
977
e12bef50 978static int mv_stop_edma(struct ata_port *ap)
0ea9e179 979{
b562468c
ML		 980 void __iomem *port_mmio = mv_ap_base(ap);
981 struct mv_port_priv *pp = ap->private_data;
0ea9e179 982
b562468c
ML		 983 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
984 return 0;
985 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 986 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 987 if (mv_stop_edma_engine(port_mmio)) {
988 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
989 return -EIO;
990 }
991 return 0;
0ea9e179
JG		 992}
993
8a70f8dc 994#ifdef ATA_DEBUG
31961943 995static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 996{
31961943
BR		 997 int b, w;
998 for (b = 0; b < bytes; ) {
999 DPRINTK("%p: ", start + b);
1000 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1001 printk("%08x ", readl(start + b));
31961943
BR		 1002 b += sizeof(u32);
1003 }
1004 printk("\n");
1005 }
31961943 1006}
8a70f8dc
JG		 1007#endif
1008
31961943
BR		 1009static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1010{
1011#ifdef ATA_DEBUG
1012 int b, w;
1013 u32 dw;
1014 for (b = 0; b < bytes; ) {
1015 DPRINTK("%02x: ", b);
1016 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1017 (void) pci_read_config_dword(pdev, b, &dw);
1018 printk("%08x ", dw);
31961943
BR		 1019 b += sizeof(u32);
1020 }
1021 printk("\n");
1022 }
1023#endif
1024}
1025static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1026 struct pci_dev *pdev)
1027{
1028#ifdef ATA_DEBUG
8b260248 1029 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1030 port >> MV_PORT_HC_SHIFT);
1031 void __iomem *port_base;
1032 int start_port, num_ports, p, start_hc, num_hcs, hc;
1033
1034 if (0 > port) {
1035 start_hc = start_port = 0;
1036 num_ports = 8; /* shld be benign for 4 port devs */
1037 num_hcs = 2;
1038 } else {
1039 start_hc = port >> MV_PORT_HC_SHIFT;
1040 start_port = port;
1041 num_ports = num_hcs = 1;
1042 }
8b260248 1043 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1044 num_ports > 1 ? num_ports - 1 : start_port);
1045
1046 if (NULL != pdev) {
1047 DPRINTK("PCI config space regs:\n");
1048 mv_dump_pci_cfg(pdev, 0x68);
1049 }
1050 DPRINTK("PCI regs:\n");
1051 mv_dump_mem(mmio_base+0xc00, 0x3c);
1052 mv_dump_mem(mmio_base+0xd00, 0x34);
1053 mv_dump_mem(mmio_base+0xf00, 0x4);
1054 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1055 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1056 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1057 DPRINTK("HC regs (HC %i):\n", hc);
1058 mv_dump_mem(hc_base, 0x1c);
1059 }
1060 for (p = start_port; p < start_port + num_ports; p++) {
1061 port_base = mv_port_base(mmio_base, p);
2dcb407e 1062 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1063 mv_dump_mem(port_base, 0x54);
2dcb407e 1064 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1065 mv_dump_mem(port_base+0x300, 0x60);
1066 }
1067#endif
20f733e7
BR		 1068}
1069
1070static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1071{
1072 unsigned int ofs;
1073
1074 switch (sc_reg_in) {
1075 case SCR_STATUS:
1076 case SCR_CONTROL:
1077 case SCR_ERROR:
1078 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1079 break;
1080 case SCR_ACTIVE:
1081 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1082 break;
1083 default:
1084 ofs = 0xffffffffU;
1085 break;
1086 }
1087 return ofs;
1088}
1089
82ef04fb 1090static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1091{
1092 unsigned int ofs = mv_scr_offset(sc_reg_in);
1093
da3dbb17 1094 if (ofs != 0xffffffffU) {
82ef04fb 1095 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1096 return 0;
1097 } else
1098 return -EINVAL;
20f733e7
BR		 1099}
1100
82ef04fb 1101static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1102{
1103 unsigned int ofs = mv_scr_offset(sc_reg_in);
1104
da3dbb17 1105 if (ofs != 0xffffffffU) {
82ef04fb 1106 writelfl(val, mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1107 return 0;
1108 } else
1109 return -EINVAL;
20f733e7
BR		 1110}
1111
f273827e
ML		 1112static void mv6_dev_config(struct ata_device *adev)
1113{
1114 /*
e49856d8
ML		 1115 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1116 *
1117 * Gen-II does not support NCQ over a port multiplier
1118 * (no FIS-based switching).
f273827e 1119 */
e49856d8 1120 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1121 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1122 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1123 ata_dev_printk(adev, KERN_INFO,
1124 "NCQ disabled for command-based switching\n");
352fab70 1125 }
e49856d8 1126 }
f273827e
ML		 1127}
1128
3e4a1391
ML		 1129static int mv_qc_defer(struct ata_queued_cmd *qc)
1130{
1131 struct ata_link *link = qc->dev->link;
1132 struct ata_port *ap = link->ap;
1133 struct mv_port_priv *pp = ap->private_data;
1134
29d187bb
ML		 1135 /*
1136 * Don't allow new commands if we're in a delayed EH state
1137 * for NCQ and/or FIS-based switching.
1138 */
1139 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1140 return ATA_DEFER_PORT;
3e4a1391
ML		 1141 /*
1142 * If the port is completely idle, then allow the new qc.
1143 */
1144 if (ap->nr_active_links == 0)
1145 return 0;
1146
4bdee6c5
TH		 1147 /*
1148 * The port is operating in host queuing mode (EDMA) with NCQ
1149 * enabled, allow multiple NCQ commands. EDMA also allows
1150 * queueing multiple DMA commands but libata core currently
1151 * doesn't allow it.
1152 */
1153 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1154 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1155 return 0;
1156
3e4a1391
ML		 1157 return ATA_DEFER_PORT;
1158}
1159
00f42eab 1160static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1161{
00f42eab
ML		 1162 u32 new_fiscfg, old_fiscfg;
1163 u32 new_ltmode, old_ltmode;
1164 u32 new_haltcond, old_haltcond;
1165
1166 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1167 old_ltmode = readl(port_mmio + LTMODE_OFS);
1168 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1169
1170 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1171 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1172 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1173
1174 if (want_fbs) {
1175 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1176 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1177 if (want_ncq)
1178 new_haltcond &= ~EDMA_ERR_DEV;
1179 else
1180 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1181 }
00f42eab 1182
8e7decdb
ML		 1183 if (new_fiscfg != old_fiscfg)
1184 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1185 if (new_ltmode != old_ltmode)
1186 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1187 if (new_haltcond != old_haltcond)
1188 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1189}
1190
dd2890f6
ML		 1191static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1192{
1193 struct mv_host_priv *hpriv = ap->host->private_data;
1194 u32 old, new;
1195
1196 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1197 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1198 if (want_ncq)
1199 new = old | (1 << 22);
1200 else
1201 new = old & ~(1 << 22);
1202 if (new != old)
1203 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1204}
1205
00b81235 1206static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1207{
0c58912e 1208 u32 cfg;
e12bef50
ML		 1209 struct mv_port_priv *pp = ap->private_data;
1210 struct mv_host_priv *hpriv = ap->host->private_data;
1211 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1212
1213 /* set up non-NCQ EDMA configuration */
0c58912e 1214 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00b81235 1215 pp->pp_flags &= ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN);
e4e7b892 1216
0c58912e 1217 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1218 cfg |= (1 << 8); /* enab config burst size mask */
1219
dd2890f6 1220 else if (IS_GEN_II(hpriv)) {
e4e7b892 1221 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1222 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1223
dd2890f6 1224 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1225 int want_fbs = sata_pmp_attached(ap);
1226 /*
1227 * Possible future enhancement:
1228 *
1229 * The chip can use FBS with non-NCQ, if we allow it,
1230 * But first we need to have the error handling in place
1231 * for this mode (datasheet section 7.3.15.4.2.3).
1232 * So disallow non-NCQ FBS for now.
1233 */
1234 want_fbs &= want_ncq;
1235
1236 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1237
1238 if (want_fbs) {
1239 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1240 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1241 }
1242
e728eabe 1243 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1244 if (want_edma) {
1245 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1246 if (!IS_SOC(hpriv))
1247 cfg |= (1 << 18); /* enab early completion */
1248 }
616d4a98
ML		 1249 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1250 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1251 }
1252
72109168
ML		 1253 if (want_ncq) {
1254 cfg |= EDMA_CFG_NCQ;
1255 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1256 }
72109168 1257
e4e7b892
JG		 1258 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1259}
1260
da2fa9ba
ML		 1261static void mv_port_free_dma_mem(struct ata_port *ap)
1262{
1263 struct mv_host_priv *hpriv = ap->host->private_data;
1264 struct mv_port_priv *pp = ap->private_data;
eb73d558 1265 int tag;
da2fa9ba
ML		 1266
1267 if (pp->crqb) {
1268 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1269 pp->crqb = NULL;
1270 }
1271 if (pp->crpb) {
1272 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1273 pp->crpb = NULL;
1274 }
eb73d558
ML		 1275 /*
1276 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1277 * For later hardware, we have one unique sg_tbl per NCQ tag.
1278 */
1279 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1280 if (pp->sg_tbl[tag]) {
1281 if (tag == 0 || !IS_GEN_I(hpriv))
1282 dma_pool_free(hpriv->sg_tbl_pool,
1283 pp->sg_tbl[tag],
1284 pp->sg_tbl_dma[tag]);
1285 pp->sg_tbl[tag] = NULL;
1286 }
da2fa9ba
ML		 1287 }
1288}
1289
05b308e1
BR		 1290/**
1291 * mv_port_start - Port specific init/start routine.
1292 * @ap: ATA channel to manipulate
1293 *
1294 * Allocate and point to DMA memory, init port private memory,
1295 * zero indices.
1296 *
1297 * LOCKING:
1298 * Inherited from caller.
1299 */
31961943
BR		 1300static int mv_port_start(struct ata_port *ap)
1301{
cca3974e
JG		 1302 struct device *dev = ap->host->dev;
1303 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1304 struct mv_port_priv *pp;
dde20207 1305 int tag;
31961943 1306
24dc5f33 1307 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1308 if (!pp)
24dc5f33 1309 return -ENOMEM;
da2fa9ba 1310 ap->private_data = pp;
31961943 1311
da2fa9ba
ML		 1312 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1313 if (!pp->crqb)
1314 return -ENOMEM;
1315 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1316
da2fa9ba
ML		 1317 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1318 if (!pp->crpb)
1319 goto out_port_free_dma_mem;
1320 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1321
3bd0a70e
ML		 1322 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1323 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1324 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1325 /*
1326 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1327 * For later hardware, we need one unique sg_tbl per NCQ tag.
1328 */
1329 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1330 if (tag == 0 || !IS_GEN_I(hpriv)) {
1331 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1332 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1333 if (!pp->sg_tbl[tag])
1334 goto out_port_free_dma_mem;
1335 } else {
1336 pp->sg_tbl[tag] = pp->sg_tbl[0];
1337 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1338 }
1339 }
31961943 1340 return 0;
da2fa9ba
ML		 1341
1342out_port_free_dma_mem:
1343 mv_port_free_dma_mem(ap);
1344 return -ENOMEM;
31961943
BR		 1345}
1346
05b308e1
BR		 1347/**
1348 * mv_port_stop - Port specific cleanup/stop routine.
1349 * @ap: ATA channel to manipulate
1350 *
1351 * Stop DMA, cleanup port memory.
1352 *
1353 * LOCKING:
cca3974e 1354 * This routine uses the host lock to protect the DMA stop.
05b308e1 1355 */
31961943
BR		 1356static void mv_port_stop(struct ata_port *ap)
1357{
e12bef50 1358 mv_stop_edma(ap);
88e675e1 1359 mv_enable_port_irqs(ap, 0);
da2fa9ba 1360 mv_port_free_dma_mem(ap);
31961943
BR		 1361}
1362
05b308e1
BR		 1363/**
1364 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1365 * @qc: queued command whose SG list to source from
1366 *
1367 * Populate the SG list and mark the last entry.
1368 *
1369 * LOCKING:
1370 * Inherited from caller.
1371 */
6c08772e 1372static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1373{
1374 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1375 struct scatterlist *sg;
3be6cbd7 1376 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1377 unsigned int si;
31961943 1378
eb73d558 1379 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1380 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1381 dma_addr_t addr = sg_dma_address(sg);
1382 u32 sg_len = sg_dma_len(sg);
22374677 1383
4007b493
OJ		 1384 while (sg_len) {
1385 u32 offset = addr & 0xffff;
1386 u32 len = sg_len;
22374677 1387
32cd11a6 1388 if (offset + len > 0x10000)
4007b493
OJ		 1389 len = 0x10000 - offset;
1390
1391 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1392 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1393 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1394 mv_sg->reserved = 0;
4007b493
OJ		 1395
1396 sg_len -= len;
1397 addr += len;
1398
3be6cbd7 1399 last_sg = mv_sg;
4007b493 1400 mv_sg++;
4007b493 1401 }
31961943 1402 }
3be6cbd7
JG		 1403
1404 if (likely(last_sg))
1405 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1406 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1407}
1408
5796d1c4 1409static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1410{
559eedad 1411 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1412 (last ? CRQB_CMD_LAST : 0);
559eedad 1413 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1414}
1415
da14265e
ML		 1416/**
1417 * mv_mode_filter - Allow ATAPI DMA only on GenII chips.
1418 * @dev: device whose xfer modes are being configured.
1419 *
1420 * Only the GenII hardware can use DMA with ATAPI drives.
1421 */
1422static unsigned long mv_mode_filter(struct ata_device *adev,
1423 unsigned long xfer_mask)
1424{
1425 if (adev->class == ATA_DEV_ATAPI) {
1426 struct mv_host_priv *hpriv = adev->link->ap->host->private_data;
1427 if (!IS_GEN_II(hpriv)) {
1428 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
1429 ata_dev_printk(adev, KERN_INFO,
1430 "ATAPI DMA not supported on this chipset\n");
1431 }
1432 }
1433 return xfer_mask;
1434}
1435
1436/**
1437 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1438 * @ap: Port associated with this ATA transaction.
1439 *
1440 * We need this only for ATAPI bmdma transactions,
1441 * as otherwise we experience spurious interrupts
1442 * after libata-sff handles the bmdma interrupts.
1443 */
1444static void mv_sff_irq_clear(struct ata_port *ap)
1445{
1446 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1447}
1448
1449/**
1450 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1451 * @qc: queued command to check for chipset/DMA compatibility.
1452 *
1453 * The bmdma engines cannot handle speculative data sizes
1454 * (bytecount under/over flow). So only allow DMA for
1455 * data transfer commands with known data sizes.
1456 *
1457 * LOCKING:
1458 * Inherited from caller.
1459 */
1460static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1461{
1462 struct scsi_cmnd *scmd = qc->scsicmd;
1463
1464 if (scmd) {
1465 switch (scmd->cmnd[0]) {
1466 case READ_6:
1467 case READ_10:
1468 case READ_12:
1469 case WRITE_6:
1470 case WRITE_10:
1471 case WRITE_12:
1472 case GPCMD_READ_CD:
1473 case GPCMD_SEND_DVD_STRUCTURE:
1474 case GPCMD_SEND_CUE_SHEET:
1475 return 0; /* DMA is safe */
1476 }
1477 }
1478 return -EOPNOTSUPP; /* use PIO instead */
1479}
1480
1481/**
1482 * mv_bmdma_setup - Set up BMDMA transaction
1483 * @qc: queued command to prepare DMA for.
1484 *
1485 * LOCKING:
1486 * Inherited from caller.
1487 */
1488static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1489{
1490 struct ata_port *ap = qc->ap;
1491 void __iomem *port_mmio = mv_ap_base(ap);
1492 struct mv_port_priv *pp = ap->private_data;
1493
1494 mv_fill_sg(qc);
1495
1496 /* clear all DMA cmd bits */
1497 writel(0, port_mmio + BMDMA_CMD_OFS);
1498
1499 /* load PRD table addr. */
1500 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1501 port_mmio + BMDMA_PRD_HIGH_OFS);
1502 writelfl(pp->sg_tbl_dma[qc->tag],
1503 port_mmio + BMDMA_PRD_LOW_OFS);
1504
1505 /* issue r/w command */
1506 ap->ops->sff_exec_command(ap, &qc->tf);
1507}
1508
1509/**
1510 * mv_bmdma_start - Start a BMDMA transaction
1511 * @qc: queued command to start DMA on.
1512 *
1513 * LOCKING:
1514 * Inherited from caller.
1515 */
1516static void mv_bmdma_start(struct ata_queued_cmd *qc)
1517{
1518 struct ata_port *ap = qc->ap;
1519 void __iomem *port_mmio = mv_ap_base(ap);
1520 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1521 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1522
1523 /* start host DMA transaction */
1524 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1525}
1526
1527/**
1528 * mv_bmdma_stop - Stop BMDMA transfer
1529 * @qc: queued command to stop DMA on.
1530 *
1531 * Clears the ATA_DMA_START flag in the bmdma control register
1532 *
1533 * LOCKING:
1534 * Inherited from caller.
1535 */
1536static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1537{
1538 struct ata_port *ap = qc->ap;
1539 void __iomem *port_mmio = mv_ap_base(ap);
1540 u32 cmd;
1541
1542 /* clear start/stop bit */
1543 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1544 cmd &= ~ATA_DMA_START;
1545 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1546
1547 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1548 ata_sff_dma_pause(ap);
1549}
1550
1551/**
1552 * mv_bmdma_status - Read BMDMA status
1553 * @ap: port for which to retrieve DMA status.
1554 *
1555 * Read and return equivalent of the sff BMDMA status register.
1556 *
1557 * LOCKING:
1558 * Inherited from caller.
1559 */
1560static u8 mv_bmdma_status(struct ata_port *ap)
1561{
1562 void __iomem *port_mmio = mv_ap_base(ap);
1563 u32 reg, status;
1564
1565 /*
1566 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1567 * and the ATA_DMA_INTR bit doesn't exist.
1568 */
1569 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1570 if (reg & ATA_DMA_ACTIVE)
1571 status = ATA_DMA_ACTIVE;
1572 else
1573 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1574 return status;
1575}
1576
05b308e1
BR		 1577/**
1578 * mv_qc_prep - Host specific command preparation.
1579 * @qc: queued command to prepare
1580 *
1581 * This routine simply redirects to the general purpose routine
1582 * if command is not DMA. Else, it handles prep of the CRQB
1583 * (command request block), does some sanity checking, and calls
1584 * the SG load routine.
1585 *
1586 * LOCKING:
1587 * Inherited from caller.
1588 */
31961943
BR		 1589static void mv_qc_prep(struct ata_queued_cmd *qc)
1590{
1591 struct ata_port *ap = qc->ap;
1592 struct mv_port_priv *pp = ap->private_data;
e1469874 1593 __le16 *cw;
31961943
BR		 1594 struct ata_taskfile *tf;
1595 u16 flags = 0;
a6432436 1596 unsigned in_index;
31961943 1597
138bfdd0
ML		 1598 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1599 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1600 return;
20f733e7 1601
31961943
BR		 1602 /* Fill in command request block
1603 */
e4e7b892 1604 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1605 flags |= CRQB_FLAG_READ;
beec7dbc 1606 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1607 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1608 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1609
bdd4ddde 1610 /* get current queue index from software */
fcfb1f77 1611 in_index = pp->req_idx;
a6432436
ML		 1612
1613 pp->crqb[in_index].sg_addr =
eb73d558 1614 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1615 pp->crqb[in_index].sg_addr_hi =
eb73d558 1616 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1617 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1618
a6432436 1619 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1620 tf = &qc->tf;
1621
1622 /* Sadly, the CRQB cannot accomodate all registers--there are
1623 * only 11 bytes...so we must pick and choose required
1624 * registers based on the command. So, we drop feature and
1625 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 1626 * NCQ. NCQ will drop hob_nsect, which is not needed there
1627 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 1628 */
31961943
BR		 1629 switch (tf->command) {
1630 case ATA_CMD_READ:
1631 case ATA_CMD_READ_EXT:
1632 case ATA_CMD_WRITE:
1633 case ATA_CMD_WRITE_EXT:
c15d85c8 1634 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1635 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1636 break;
31961943
BR		 1637 case ATA_CMD_FPDMA_READ:
1638 case ATA_CMD_FPDMA_WRITE:
8b260248 1639 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1640 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1641 break;
31961943
BR		 1642 default:
1643 /* The only other commands EDMA supports in non-queued and
1644 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1645 * of which are defined/used by Linux. If we get here, this
1646 * driver needs work.
1647 *
1648 * FIXME: modify libata to give qc_prep a return value and
1649 * return error here.
1650 */
1651 BUG_ON(tf->command);
1652 break;
1653 }
1654 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1655 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1656 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1657 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1658 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1659 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1660 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1661 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1662 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1663
e4e7b892
JG		 1664 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1665 return;
1666 mv_fill_sg(qc);
1667}
1668
1669/**
1670 * mv_qc_prep_iie - Host specific command preparation.
1671 * @qc: queued command to prepare
1672 *
1673 * This routine simply redirects to the general purpose routine
1674 * if command is not DMA. Else, it handles prep of the CRQB
1675 * (command request block), does some sanity checking, and calls
1676 * the SG load routine.
1677 *
1678 * LOCKING:
1679 * Inherited from caller.
1680 */
1681static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1682{
1683 struct ata_port *ap = qc->ap;
1684 struct mv_port_priv *pp = ap->private_data;
1685 struct mv_crqb_iie *crqb;
1686 struct ata_taskfile *tf;
a6432436 1687 unsigned in_index;
e4e7b892
JG		 1688 u32 flags = 0;
1689
138bfdd0
ML		 1690 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1691 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1692 return;
1693
e12bef50 1694 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1695 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1696 flags |= CRQB_FLAG_READ;
1697
beec7dbc 1698 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1699 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1700 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1701 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1702
bdd4ddde 1703 /* get current queue index from software */
fcfb1f77 1704 in_index = pp->req_idx;
a6432436
ML		 1705
1706 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1707 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1708 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1709 crqb->flags = cpu_to_le32(flags);
1710
1711 tf = &qc->tf;
1712 crqb->ata_cmd[0] = cpu_to_le32(
1713 (tf->command << 16) |
1714 (tf->feature << 24)
1715 );
1716 crqb->ata_cmd[1] = cpu_to_le32(
1717 (tf->lbal << 0) |
1718 (tf->lbam << 8) |
1719 (tf->lbah << 16) |
1720 (tf->device << 24)
1721 );
1722 crqb->ata_cmd[2] = cpu_to_le32(
1723 (tf->hob_lbal << 0) |
1724 (tf->hob_lbam << 8) |
1725 (tf->hob_lbah << 16) |
1726 (tf->hob_feature << 24)
1727 );
1728 crqb->ata_cmd[3] = cpu_to_le32(
1729 (tf->nsect << 0) |
1730 (tf->hob_nsect << 8)
1731 );
1732
1733 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1734 return;
31961943
BR		 1735 mv_fill_sg(qc);
1736}
1737
05b308e1
BR		 1738/**
1739 * mv_qc_issue - Initiate a command to the host
1740 * @qc: queued command to start
1741 *
1742 * This routine simply redirects to the general purpose routine
1743 * if command is not DMA. Else, it sanity checks our local
1744 * caches of the request producer/consumer indices then enables
1745 * DMA and bumps the request producer index.
1746 *
1747 * LOCKING:
1748 * Inherited from caller.
1749 */
9a3d9eb0 1750static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1751{
f48765cc 1752 static int limit_warnings = 10;
c5d3e45a
JG		 1753 struct ata_port *ap = qc->ap;
1754 void __iomem *port_mmio = mv_ap_base(ap);
1755 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1756 u32 in_index;
f48765cc
ML		 1757 unsigned int port_irqs = DONE_IRQ | ERR_IRQ;
1758
1759 switch (qc->tf.protocol) {
1760 case ATA_PROT_DMA:
1761 case ATA_PROT_NCQ:
1762 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
1763 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1764 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1765
1766 /* Write the request in pointer to kick the EDMA to life */
1767 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1768 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1769 return 0;
31961943 1770
f48765cc 1771 case ATA_PROT_PIO:
c6112bd8
ML		 1772 /*
1773 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1774 *
1775 * Someday, we might implement special polling workarounds
1776 * for these, but it all seems rather unnecessary since we
1777 * normally use only DMA for commands which transfer more
1778 * than a single block of data.
1779 *
1780 * Much of the time, this could just work regardless.
1781 * So for now, just log the incident, and allow the attempt.
1782 */
c7843e8f 1783 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 1784 --limit_warnings;
1785 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1786 ": attempting PIO w/multiple DRQ: "
1787 "this may fail due to h/w errata\n");
1788 }
f48765cc
ML		 1789 /* drop through */
1790 case ATAPI_PROT_PIO:
1791 port_irqs = ERR_IRQ; /* leave DONE_IRQ masked for PIO */
1792 /* drop through */
1793 default:
17c5aab5
ML		 1794 /*
1795 * We're about to send a non-EDMA capable command to the
31961943
BR		 1796 * port. Turn off EDMA so there won't be problems accessing
1797 * shadow block, etc registers.
1798 */
b562468c 1799 mv_stop_edma(ap);
f48765cc
ML		 1800 mv_edma_cfg(ap, 0, 0);
1801 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
e49856d8 1802 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1803 return ata_sff_qc_issue(qc);
31961943 1804 }
31961943
BR		 1805}
1806
8f767f8a
ML		 1807static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1808{
1809 struct mv_port_priv *pp = ap->private_data;
1810 struct ata_queued_cmd *qc;
1811
1812 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1813 return NULL;
1814 qc = ata_qc_from_tag(ap, ap->link.active_tag);
95db5051
ML		 1815 if (qc) {
1816 if (qc->tf.flags & ATA_TFLAG_POLLING)
1817 qc = NULL;
1818 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
1819 qc = NULL;
1820 }
8f767f8a
ML		 1821 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1822 qc = NULL;
1823 return qc;
1824}
1825
29d187bb
ML		 1826static void mv_pmp_error_handler(struct ata_port *ap)
1827{
1828 unsigned int pmp, pmp_map;
1829 struct mv_port_priv *pp = ap->private_data;
1830
1831 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1832 /*
1833 * Perform NCQ error analysis on failed PMPs
1834 * before we freeze the port entirely.
1835 *
1836 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1837 */
1838 pmp_map = pp->delayed_eh_pmp_map;
1839 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1840 for (pmp = 0; pmp_map != 0; pmp++) {
1841 unsigned int this_pmp = (1 << pmp);
1842 if (pmp_map & this_pmp) {
1843 struct ata_link *link = &ap->pmp_link[pmp];
1844 pmp_map &= ~this_pmp;
1845 ata_eh_analyze_ncq_error(link);
1846 }
1847 }
1848 ata_port_freeze(ap);
1849 }
1850 sata_pmp_error_handler(ap);
1851}
1852
4c299ca3
ML		 1853static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1854{
1855 void __iomem *port_mmio = mv_ap_base(ap);
1856
1857 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1858}
1859
4c299ca3
ML		 1860static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1861{
1862 struct ata_eh_info *ehi;
1863 unsigned int pmp;
1864
1865 /*
1866 * Initialize EH info for PMPs which saw device errors
1867 */
1868 ehi = &ap->link.eh_info;
1869 for (pmp = 0; pmp_map != 0; pmp++) {
1870 unsigned int this_pmp = (1 << pmp);
1871 if (pmp_map & this_pmp) {
1872 struct ata_link *link = &ap->pmp_link[pmp];
1873
1874 pmp_map &= ~this_pmp;
1875 ehi = &link->eh_info;
1876 ata_ehi_clear_desc(ehi);
1877 ata_ehi_push_desc(ehi, "dev err");
1878 ehi->err_mask |= AC_ERR_DEV;
1879 ehi->action |= ATA_EH_RESET;
1880 ata_link_abort(link);
1881 }
1882 }
1883}
1884
06aaca3f
ML		 1885static int mv_req_q_empty(struct ata_port *ap)
1886{
1887 void __iomem *port_mmio = mv_ap_base(ap);
1888 u32 in_ptr, out_ptr;
1889
1890 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1891 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1892 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1893 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1894 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1895}
1896
4c299ca3
ML		 1897static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1898{
1899 struct mv_port_priv *pp = ap->private_data;
1900 int failed_links;
1901 unsigned int old_map, new_map;
1902
1903 /*
1904 * Device error during FBS+NCQ operation:
1905 *
1906 * Set a port flag to prevent further I/O being enqueued.
1907 * Leave the EDMA running to drain outstanding commands from this port.
1908 * Perform the post-mortem/EH only when all responses are complete.
1909 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1910 */
1911 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1912 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1913 pp->delayed_eh_pmp_map = 0;
1914 }
1915 old_map = pp->delayed_eh_pmp_map;
1916 new_map = old_map | mv_get_err_pmp_map(ap);
1917
1918 if (old_map != new_map) {
1919 pp->delayed_eh_pmp_map = new_map;
1920 mv_pmp_eh_prep(ap, new_map & ~old_map);
1921 }
c46938cc 1922 failed_links = hweight16(new_map);
4c299ca3
ML		 1923
1924 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1925 "failed_links=%d nr_active_links=%d\n",
1926 __func__, pp->delayed_eh_pmp_map,
1927 ap->qc_active, failed_links,
1928 ap->nr_active_links);
1929
06aaca3f 1930 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 1931 mv_process_crpb_entries(ap, pp);
1932 mv_stop_edma(ap);
1933 mv_eh_freeze(ap);
1934 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1935 return 1; /* handled */
1936 }
1937 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1938 return 1; /* handled */
1939}
1940
1941static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1942{
1943 /*
1944 * Possible future enhancement:
1945 *
1946 * FBS+non-NCQ operation is not yet implemented.
1947 * See related notes in mv_edma_cfg().
1948 *
1949 * Device error during FBS+non-NCQ operation:
1950 *
1951 * We need to snapshot the shadow registers for each failed command.
1952 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1953 */
1954 return 0; /* not handled */
1955}
1956
1957static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1958{
1959 struct mv_port_priv *pp = ap->private_data;
1960
1961 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1962 return 0; /* EDMA was not active: not handled */
1963 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1964 return 0; /* FBS was not active: not handled */
1965
1966 if (!(edma_err_cause & EDMA_ERR_DEV))
1967 return 0; /* non DEV error: not handled */
1968 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1969 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1970 return 0; /* other problems: not handled */
1971
1972 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1973 /*
1974 * EDMA should NOT have self-disabled for this case.
1975 * If it did, then something is wrong elsewhere,
1976 * and we cannot handle it here.
1977 */
1978 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1979 ata_port_printk(ap, KERN_WARNING,
1980 "%s: err_cause=0x%x pp_flags=0x%x\n",
1981 __func__, edma_err_cause, pp->pp_flags);
1982 return 0; /* not handled */
1983 }
1984 return mv_handle_fbs_ncq_dev_err(ap);
1985 } else {
1986 /*
1987 * EDMA should have self-disabled for this case.
1988 * If it did not, then something is wrong elsewhere,
1989 * and we cannot handle it here.
1990 */
1991 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1992 ata_port_printk(ap, KERN_WARNING,
1993 "%s: err_cause=0x%x pp_flags=0x%x\n",
1994 __func__, edma_err_cause, pp->pp_flags);
1995 return 0; /* not handled */
1996 }
1997 return mv_handle_fbs_non_ncq_dev_err(ap);
1998 }
1999 return 0; /* not handled */
2000}
2001
a9010329 2002static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2003{
8f767f8a 2004 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2005 char *when = "idle";
8f767f8a 2006
8f767f8a 2007 ata_ehi_clear_desc(ehi);
a9010329
ML		 2008 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2009 when = "disabled";
2010 } else if (edma_was_enabled) {
2011 when = "EDMA enabled";
8f767f8a
ML		 2012 } else {
2013 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2014 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2015 when = "polling";
8f767f8a 2016 }
a9010329 2017 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2018 ehi->err_mask |= AC_ERR_OTHER;
2019 ehi->action |= ATA_EH_RESET;
2020 ata_port_freeze(ap);
2021}
2022
05b308e1
BR		 2023/**
2024 * mv_err_intr - Handle error interrupts on the port
2025 * @ap: ATA channel to manipulate
2026 *
8d07379d
ML		 2027 * Most cases require a full reset of the chip's state machine,
2028 * which also performs a COMRESET.
2029 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2030 *
2031 * LOCKING:
2032 * Inherited from caller.
2033 */
37b9046a 2034static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2035{
2036 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2037 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2038 u32 fis_cause = 0;
bdd4ddde
JG		 2039 struct mv_port_priv *pp = ap->private_data;
2040 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2041 unsigned int action = 0, err_mask = 0;
9af5c9c9 2042 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2043 struct ata_queued_cmd *qc;
2044 int abort = 0;
20f733e7 2045
8d07379d 2046 /*
37b9046a 2047 * Read and clear the SError and err_cause bits.
e4006077
ML		 2048 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2049 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2050 */
37b9046a
ML		 2051 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2052 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2053
bdd4ddde 2054 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 2055 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2056 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2057 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2058 }
8d07379d 2059 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 2060
4c299ca3
ML		 2061 if (edma_err_cause & EDMA_ERR_DEV) {
2062 /*
2063 * Device errors during FIS-based switching operation
2064 * require special handling.
2065 */
2066 if (mv_handle_dev_err(ap, edma_err_cause))
2067 return;
2068 }
2069
37b9046a
ML		 2070 qc = mv_get_active_qc(ap);
2071 ata_ehi_clear_desc(ehi);
2072 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2073 edma_err_cause, pp->pp_flags);
e4006077 2074
c443c500 2075 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2076 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 2077 if (fis_cause & SATA_FIS_IRQ_AN) {
2078 u32 ec = edma_err_cause &
2079 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2080 sata_async_notification(ap);
2081 if (!ec)
2082 return; /* Just an AN; no need for the nukes */
2083 ata_ehi_push_desc(ehi, "SDB notify");
2084 }
2085 }
bdd4ddde 2086 /*
352fab70 2087 * All generations share these EDMA error cause bits:
bdd4ddde 2088 */
37b9046a 2089 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2090 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2091 action |= ATA_EH_RESET;
2092 ata_ehi_push_desc(ehi, "dev error");
2093 }
bdd4ddde 2094 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2095 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2096 EDMA_ERR_INTRL_PAR)) {
2097 err_mask |= AC_ERR_ATA_BUS;
cf480626 2098 action |= ATA_EH_RESET;
b64bbc39 2099 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2100 }
2101 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2102 ata_ehi_hotplugged(ehi);
2103 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2104 "dev disconnect" : "dev connect");
cf480626 2105 action |= ATA_EH_RESET;
bdd4ddde
JG		 2106 }
2107
352fab70
ML		 2108 /*
2109 * Gen-I has a different SELF_DIS bit,
2110 * different FREEZE bits, and no SERR bit:
2111 */
ee9ccdf7 2112 if (IS_GEN_I(hpriv)) {
bdd4ddde 2113 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2114 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2115 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2116 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2117 }
2118 } else {
2119 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2120 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2121 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2122 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2123 }
bdd4ddde 2124 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2125 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2126 err_mask |= AC_ERR_ATA_BUS;
cf480626 2127 action |= ATA_EH_RESET;
bdd4ddde 2128 }
afb0edd9 2129 }
20f733e7 2130
bdd4ddde
JG		 2131 if (!err_mask) {
2132 err_mask = AC_ERR_OTHER;
cf480626 2133 action |= ATA_EH_RESET;
bdd4ddde
JG		 2134 }
2135
2136 ehi->serror |= serr;
2137 ehi->action |= action;
2138
2139 if (qc)
2140 qc->err_mask |= err_mask;
2141 else
2142 ehi->err_mask |= err_mask;
2143
37b9046a
ML		 2144 if (err_mask == AC_ERR_DEV) {
2145 /*
2146 * Cannot do ata_port_freeze() here,
2147 * because it would kill PIO access,
2148 * which is needed for further diagnosis.
2149 */
2150 mv_eh_freeze(ap);
2151 abort = 1;
2152 } else if (edma_err_cause & eh_freeze_mask) {
2153 /*
2154 * Note to self: ata_port_freeze() calls ata_port_abort()
2155 */
bdd4ddde 2156 ata_port_freeze(ap);
37b9046a
ML		 2157 } else {
2158 abort = 1;
2159 }
2160
2161 if (abort) {
2162 if (qc)
2163 ata_link_abort(qc->dev->link);
2164 else
2165 ata_port_abort(ap);
2166 }
bdd4ddde
JG		 2167}
2168
fcfb1f77
ML		 2169static void mv_process_crpb_response(struct ata_port *ap,
2170 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2171{
2172 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2173
2174 if (qc) {
2175 u8 ata_status;
2176 u16 edma_status = le16_to_cpu(response->flags);
2177 /*
2178 * edma_status from a response queue entry:
2179 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2180 * MSB is saved ATA status from command completion.
2181 */
2182 if (!ncq_enabled) {
2183 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2184 if (err_cause) {
2185 /*
2186 * Error will be seen/handled by mv_err_intr().
2187 * So do nothing at all here.
2188 */
2189 return;
2190 }
2191 }
2192 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2193 if (!ac_err_mask(ata_status))
2194 ata_qc_complete(qc);
2195 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2196 } else {
2197 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2198 __func__, tag);
2199 }
2200}
2201
2202static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2203{
2204 void __iomem *port_mmio = mv_ap_base(ap);
2205 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2206 u32 in_index;
bdd4ddde 2207 bool work_done = false;
fcfb1f77 2208 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2209
fcfb1f77 2210 /* Get the hardware queue position index */
bdd4ddde
JG		 2211 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2212 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2213
fcfb1f77
ML		 2214 /* Process new responses from since the last time we looked */
2215 while (in_index != pp->resp_idx) {
6c1153e0 2216 unsigned int tag;
fcfb1f77 2217 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2218
fcfb1f77 2219 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2220
fcfb1f77
ML		 2221 if (IS_GEN_I(hpriv)) {
2222 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2223 tag = ap->link.active_tag;
fcfb1f77
ML		 2224 } else {
2225 /* Gen II/IIE: get command tag from CRPB entry */
2226 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2227 }
fcfb1f77 2228 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2229 work_done = true;
bdd4ddde
JG		 2230 }
2231
352fab70 2232 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2233 if (work_done)
2234 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2235 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2236 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2237}
2238
a9010329
ML		 2239static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2240{
2241 struct mv_port_priv *pp;
2242 int edma_was_enabled;
2243
2244 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2245 mv_unexpected_intr(ap, 0);
2246 return;
2247 }
2248 /*
2249 * Grab a snapshot of the EDMA_EN flag setting,
2250 * so that we have a consistent view for this port,
2251 * even if something we call of our routines changes it.
2252 */
2253 pp = ap->private_data;
2254 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2255 /*
2256 * Process completed CRPB response(s) before other events.
2257 */
2258 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2259 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2260 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2261 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2262 }
2263 /*
2264 * Handle chip-reported errors, or continue on to handle PIO.
2265 */
2266 if (unlikely(port_cause & ERR_IRQ)) {
2267 mv_err_intr(ap);
2268 } else if (!edma_was_enabled) {
2269 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2270 if (qc)
2271 ata_sff_host_intr(ap, qc);
2272 else
2273 mv_unexpected_intr(ap, edma_was_enabled);
2274 }
2275}
2276
05b308e1
BR		 2277/**
2278 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2279 * @host: host specific structure
7368f919 2280 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2281 *
2282 * LOCKING:
2283 * Inherited from caller.
2284 */
7368f919 2285static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2286{
f351b2d6 2287 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2288 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2289 unsigned int handled = 0, port;
20f733e7 2290
a3718c1f 2291 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2292 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2293 unsigned int p, shift, hardport, port_cause;
2294
a3718c1f 2295 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2296 /*
eabd5eb1
ML		 2297 * Each hc within the host has its own hc_irq_cause register,
2298 * where the interrupting ports bits get ack'd.
a3718c1f 2299 */
eabd5eb1
ML		 2300 if (hardport == 0) { /* first port on this hc ? */
2301 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2302 u32 port_mask, ack_irqs;
2303 /*
2304 * Skip this entire hc if nothing pending for any ports
2305 */
2306 if (!hc_cause) {
2307 port += MV_PORTS_PER_HC - 1;
2308 continue;
2309 }
2310 /*
2311 * We don't need/want to read the hc_irq_cause register,
2312 * because doing so hurts performance, and
2313 * main_irq_cause already gives us everything we need.
2314 *
2315 * But we do have to *write* to the hc_irq_cause to ack
2316 * the ports that we are handling this time through.
2317 *
2318 * This requires that we create a bitmap for those
2319 * ports which interrupted us, and use that bitmap
2320 * to ack (only) those ports via hc_irq_cause.
2321 */
2322 ack_irqs = 0;
2323 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2324 if ((port + p) >= hpriv->n_ports)
2325 break;
2326 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2327 if (hc_cause & port_mask)
2328 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2329 }
a3718c1f 2330 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2331 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2332 handled = 1;
2333 }
8f767f8a 2334 /*
a9010329 2335 * Handle interrupts signalled for this port:
8f767f8a 2336 */
a9010329
ML		 2337 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2338 if (port_cause)
2339 mv_port_intr(ap, port_cause);
20f733e7 2340 }
a3718c1f 2341 return handled;
20f733e7
BR		 2342}
2343
a3718c1f 2344static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2345{
02a121da 2346 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2347 struct ata_port *ap;
2348 struct ata_queued_cmd *qc;
2349 struct ata_eh_info *ehi;
2350 unsigned int i, err_mask, printed = 0;
2351 u32 err_cause;
2352
02a121da 2353 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2354
2355 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2356 err_cause);
2357
2358 DPRINTK("All regs @ PCI error\n");
2359 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2360
02a121da 2361 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2362
2363 for (i = 0; i < host->n_ports; i++) {
2364 ap = host->ports[i];
936fd732 2365 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2366 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2367 ata_ehi_clear_desc(ehi);
2368 if (!printed++)
2369 ata_ehi_push_desc(ehi,
2370 "PCI err cause 0x%08x", err_cause);
2371 err_mask = AC_ERR_HOST_BUS;
cf480626 2372 ehi->action = ATA_EH_RESET;
9af5c9c9 2373 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2374 if (qc)
2375 qc->err_mask |= err_mask;
2376 else
2377 ehi->err_mask |= err_mask;
2378
2379 ata_port_freeze(ap);
2380 }
2381 }
a3718c1f 2382 return 1; /* handled */
bdd4ddde
JG		 2383}
2384
05b308e1 2385/**
c5d3e45a 2386 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2387 * @irq: unused
2388 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2389 *
2390 * Read the read only register to determine if any host
2391 * controllers have pending interrupts. If so, call lower level
2392 * routine to handle. Also check for PCI errors which are only
2393 * reported here.
2394 *
8b260248 2395 * LOCKING:
cca3974e 2396 * This routine holds the host lock while processing pending
05b308e1
BR		 2397 * interrupts.
2398 */
7d12e780 2399static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2400{
cca3974e 2401 struct ata_host *host = dev_instance;
f351b2d6 2402 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2403 unsigned int handled = 0;
6d3c30ef 2404 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2405 u32 main_irq_cause, pending_irqs;
20f733e7 2406
646a4da5 2407 spin_lock(&host->lock);
6d3c30ef
ML		 2408
2409 /* for MSI: block new interrupts while in here */
2410 if (using_msi)
2411 writel(0, hpriv->main_irq_mask_addr);
2412
7368f919 2413 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2414 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2415 /*
2416 * Deal with cases where we either have nothing pending, or have read
2417 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2418 */
a44253d2 2419 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2420 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2421 handled = mv_pci_error(host, hpriv->base);
2422 else
a44253d2 2423 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2424 }
6d3c30ef
ML		 2425
2426 /* for MSI: unmask; interrupt cause bits will retrigger now */
2427 if (using_msi)
2428 writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
2429
9d51af7b
ML		 2430 spin_unlock(&host->lock);
2431
20f733e7
BR		 2432 return IRQ_RETVAL(handled);
2433}
2434
c9d39130
JG		 2435static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2436{
2437 unsigned int ofs;
2438
2439 switch (sc_reg_in) {
2440 case SCR_STATUS:
2441 case SCR_ERROR:
2442 case SCR_CONTROL:
2443 ofs = sc_reg_in * sizeof(u32);
2444 break;
2445 default:
2446 ofs = 0xffffffffU;
2447 break;
2448 }
2449 return ofs;
2450}
2451
82ef04fb 2452static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 2453{
82ef04fb 2454 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2455 void __iomem *mmio = hpriv->base;
82ef04fb 2456 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2457 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2458
da3dbb17
TH		 2459 if (ofs != 0xffffffffU) {
2460 *val = readl(addr + ofs);
2461 return 0;
2462 } else
2463 return -EINVAL;
c9d39130
JG		 2464}
2465
82ef04fb 2466static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 2467{
82ef04fb 2468 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2469 void __iomem *mmio = hpriv->base;
82ef04fb 2470 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2471 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2472
da3dbb17 2473 if (ofs != 0xffffffffU) {
0d5ff566 2474 writelfl(val, addr + ofs);
da3dbb17
TH		 2475 return 0;
2476 } else
2477 return -EINVAL;
c9d39130
JG		 2478}
2479
7bb3c529 2480static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2481{
7bb3c529 2482 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2483 int early_5080;
2484
44c10138 2485 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2486
2487 if (!early_5080) {
2488 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2489 tmp |= (1 << 0);
2490 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2491 }
2492
7bb3c529 2493 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2494}
2495
2496static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2497{
8e7decdb 2498 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2499}
2500
47c2b677 2501static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2502 void __iomem *mmio)
2503{
c9d39130
JG		 2504 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2505 u32 tmp;
2506
2507 tmp = readl(phy_mmio + MV5_PHY_MODE);
2508
2509 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2510 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2511}
2512
47c2b677 2513static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2514{
522479fb
JG		 2515 u32 tmp;
2516
8e7decdb 2517 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2518
2519 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2520
2521 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2522 tmp |= ~(1 << 0);
2523 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2524}
2525
2a47ce06
JG		 2526static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2527 unsigned int port)
bca1c4eb 2528{
c9d39130
JG		 2529 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2530 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2531 u32 tmp;
2532 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2533
2534 if (fix_apm_sq) {
8e7decdb 2535 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2536 tmp |= (1 << 19);
8e7decdb 2537 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2538
8e7decdb 2539 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2540 tmp &= ~0x3;
2541 tmp |= 0x1;
8e7decdb 2542 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2543 }
2544
2545 tmp = readl(phy_mmio + MV5_PHY_MODE);
2546 tmp &= ~mask;
2547 tmp |= hpriv->signal[port].pre;
2548 tmp |= hpriv->signal[port].amps;
2549 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2550}
2551
c9d39130
JG		 2552
2553#undef ZERO
2554#define ZERO(reg) writel(0, port_mmio + (reg))
2555static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2556 unsigned int port)
2557{
2558 void __iomem *port_mmio = mv_port_base(mmio, port);
2559
e12bef50 2560 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2561
2562 ZERO(0x028); /* command */
2563 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2564 ZERO(0x004); /* timer */
2565 ZERO(0x008); /* irq err cause */
2566 ZERO(0x00c); /* irq err mask */
2567 ZERO(0x010); /* rq bah */
2568 ZERO(0x014); /* rq inp */
2569 ZERO(0x018); /* rq outp */
2570 ZERO(0x01c); /* respq bah */
2571 ZERO(0x024); /* respq outp */
2572 ZERO(0x020); /* respq inp */
2573 ZERO(0x02c); /* test control */
8e7decdb 2574 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2575}
2576#undef ZERO
2577
2578#define ZERO(reg) writel(0, hc_mmio + (reg))
2579static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2580 unsigned int hc)
47c2b677 2581{
c9d39130
JG		 2582 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2583 u32 tmp;
2584
2585 ZERO(0x00c);
2586 ZERO(0x010);
2587 ZERO(0x014);
2588 ZERO(0x018);
2589
2590 tmp = readl(hc_mmio + 0x20);
2591 tmp &= 0x1c1c1c1c;
2592 tmp |= 0x03030303;
2593 writel(tmp, hc_mmio + 0x20);
2594}
2595#undef ZERO
2596
2597static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2598 unsigned int n_hc)
2599{
2600 unsigned int hc, port;
2601
2602 for (hc = 0; hc < n_hc; hc++) {
2603 for (port = 0; port < MV_PORTS_PER_HC; port++)
2604 mv5_reset_hc_port(hpriv, mmio,
2605 (hc * MV_PORTS_PER_HC) + port);
2606
2607 mv5_reset_one_hc(hpriv, mmio, hc);
2608 }
2609
2610 return 0;
47c2b677
JG		 2611}
2612
101ffae2
JG		 2613#undef ZERO
2614#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2615static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2616{
02a121da 2617 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2618 u32 tmp;
2619
8e7decdb 2620 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2621 tmp &= 0xff00ffff;
8e7decdb 2622 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2623
2624 ZERO(MV_PCI_DISC_TIMER);
2625 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2626 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 2627 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2628 ZERO(hpriv->irq_cause_ofs);
2629 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2630 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2631 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2632 ZERO(MV_PCI_ERR_ATTRIBUTE);
2633 ZERO(MV_PCI_ERR_COMMAND);
2634}
2635#undef ZERO
2636
2637static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2638{
2639 u32 tmp;
2640
2641 mv5_reset_flash(hpriv, mmio);
2642
8e7decdb 2643 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2644 tmp &= 0x3;
2645 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2646 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2647}
2648
2649/**
2650 * mv6_reset_hc - Perform the 6xxx global soft reset
2651 * @mmio: base address of the HBA
2652 *
2653 * This routine only applies to 6xxx parts.
2654 *
2655 * LOCKING:
2656 * Inherited from caller.
2657 */
c9d39130
JG		 2658static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2659 unsigned int n_hc)
101ffae2
JG		 2660{
2661 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2662 int i, rc = 0;
2663 u32 t;
2664
2665 /* Following procedure defined in PCI "main command and status
2666 * register" table.
2667 */
2668 t = readl(reg);
2669 writel(t | STOP_PCI_MASTER, reg);
2670
2671 for (i = 0; i < 1000; i++) {
2672 udelay(1);
2673 t = readl(reg);
2dcb407e 2674 if (PCI_MASTER_EMPTY & t)
101ffae2 2675 break;
101ffae2
JG		 2676 }
2677 if (!(PCI_MASTER_EMPTY & t)) {
2678 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2679 rc = 1;
2680 goto done;
2681 }
2682
2683 /* set reset */
2684 i = 5;
2685 do {
2686 writel(t | GLOB_SFT_RST, reg);
2687 t = readl(reg);
2688 udelay(1);
2689 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2690
2691 if (!(GLOB_SFT_RST & t)) {
2692 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2693 rc = 1;
2694 goto done;
2695 }
2696
2697 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2698 i = 5;
2699 do {
2700 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2701 t = readl(reg);
2702 udelay(1);
2703 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2704
2705 if (GLOB_SFT_RST & t) {
2706 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2707 rc = 1;
2708 }
2709done:
2710 return rc;
2711}
2712
47c2b677 2713static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2714 void __iomem *mmio)
2715{
2716 void __iomem *port_mmio;
2717 u32 tmp;
2718
8e7decdb 2719 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2720 if ((tmp & (1 << 0)) == 0) {
47c2b677 2721 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2722 hpriv->signal[idx].pre = 0x1 << 5;
2723 return;
2724 }
2725
2726 port_mmio = mv_port_base(mmio, idx);
2727 tmp = readl(port_mmio + PHY_MODE2);
2728
2729 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2730 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2731}
2732
47c2b677 2733static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2734{
8e7decdb 2735 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2736}
2737
c9d39130 2738static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2739 unsigned int port)
bca1c4eb 2740{
c9d39130
JG		 2741 void __iomem *port_mmio = mv_port_base(mmio, port);
2742
bca1c4eb 2743 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2744 int fix_phy_mode2 =
2745 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2746 int fix_phy_mode4 =
47c2b677 2747 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 2748 u32 m2, m3;
47c2b677
JG		 2749
2750 if (fix_phy_mode2) {
2751 m2 = readl(port_mmio + PHY_MODE2);
2752 m2 &= ~(1 << 16);
2753 m2 |= (1 << 31);
2754 writel(m2, port_mmio + PHY_MODE2);
2755
2756 udelay(200);
2757
2758 m2 = readl(port_mmio + PHY_MODE2);
2759 m2 &= ~((1 << 16) | (1 << 31));
2760 writel(m2, port_mmio + PHY_MODE2);
2761
2762 udelay(200);
2763 }
2764
8c30a8b9
ML		 2765 /*
2766 * Gen-II/IIe PHY_MODE3 errata RM#2:
2767 * Achieves better receiver noise performance than the h/w default:
2768 */
2769 m3 = readl(port_mmio + PHY_MODE3);
2770 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 2771
0388a8c0
ML		 2772 /* Guideline 88F5182 (GL# SATA-S11) */
2773 if (IS_SOC(hpriv))
2774 m3 &= ~0x1c;
2775
bca1c4eb 2776 if (fix_phy_mode4) {
ba069e37
ML		 2777 u32 m4 = readl(port_mmio + PHY_MODE4);
2778 /*
2779 * Enforce reserved-bit restrictions on GenIIe devices only.
2780 * For earlier chipsets, force only the internal config field
2781 * (workaround for errata FEr SATA#10 part 1).
2782 */
8c30a8b9 2783 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 2784 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2785 else
2786 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 2787 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 2788 }
b406c7a6
ML		 2789 /*
2790 * Workaround for 60x1-B2 errata SATA#13:
2791 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2792 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2793 */
2794 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2795
2796 /* Revert values of pre-emphasis and signal amps to the saved ones */
2797 m2 = readl(port_mmio + PHY_MODE2);
2798
2799 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2800 m2 |= hpriv->signal[port].amps;
2801 m2 |= hpriv->signal[port].pre;
47c2b677 2802 m2 &= ~(1 << 16);
bca1c4eb 2803
e4e7b892
JG		 2804 /* according to mvSata 3.6.1, some IIE values are fixed */
2805 if (IS_GEN_IIE(hpriv)) {
2806 m2 &= ~0xC30FF01F;
2807 m2 |= 0x0000900F;
2808 }
2809
bca1c4eb
JG		 2810 writel(m2, port_mmio + PHY_MODE2);
2811}
2812
f351b2d6
SB		 2813/* TODO: use the generic LED interface to configure the SATA Presence */
2814/* & Acitivy LEDs on the board */
2815static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2816 void __iomem *mmio)
2817{
2818 return;
2819}
2820
2821static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2822 void __iomem *mmio)
2823{
2824 void __iomem *port_mmio;
2825 u32 tmp;
2826
2827 port_mmio = mv_port_base(mmio, idx);
2828 tmp = readl(port_mmio + PHY_MODE2);
2829
2830 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2831 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2832}
2833
2834#undef ZERO
2835#define ZERO(reg) writel(0, port_mmio + (reg))
2836static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2837 void __iomem *mmio, unsigned int port)
2838{
2839 void __iomem *port_mmio = mv_port_base(mmio, port);
2840
e12bef50 2841 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2842
2843 ZERO(0x028); /* command */
2844 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2845 ZERO(0x004); /* timer */
2846 ZERO(0x008); /* irq err cause */
2847 ZERO(0x00c); /* irq err mask */
2848 ZERO(0x010); /* rq bah */
2849 ZERO(0x014); /* rq inp */
2850 ZERO(0x018); /* rq outp */
2851 ZERO(0x01c); /* respq bah */
2852 ZERO(0x024); /* respq outp */
2853 ZERO(0x020); /* respq inp */
2854 ZERO(0x02c); /* test control */
8e7decdb 2855 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2856}
2857
2858#undef ZERO
2859
2860#define ZERO(reg) writel(0, hc_mmio + (reg))
2861static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2862 void __iomem *mmio)
2863{
2864 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2865
2866 ZERO(0x00c);
2867 ZERO(0x010);
2868 ZERO(0x014);
2869
2870}
2871
2872#undef ZERO
2873
2874static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2875 void __iomem *mmio, unsigned int n_hc)
2876{
2877 unsigned int port;
2878
2879 for (port = 0; port < hpriv->n_ports; port++)
2880 mv_soc_reset_hc_port(hpriv, mmio, port);
2881
2882 mv_soc_reset_one_hc(hpriv, mmio);
2883
2884 return 0;
2885}
2886
2887static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2888 void __iomem *mmio)
2889{
2890 return;
2891}
2892
2893static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2894{
2895 return;
2896}
2897
8e7decdb 2898static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2899{
8e7decdb 2900 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2901
8e7decdb 2902 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2903 if (want_gen2i)
8e7decdb
ML		 2904 ifcfg |= (1 << 7); /* enable gen2i speed */
2905 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2906}
2907
e12bef50 2908static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2909 unsigned int port_no)
2910{
2911 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2912
8e7decdb
ML		 2913 /*
2914 * The datasheet warns against setting EDMA_RESET when EDMA is active
2915 * (but doesn't say what the problem might be). So we first try
2916 * to disable the EDMA engine before doing the EDMA_RESET operation.
2917 */
0d8be5cb 2918 mv_stop_edma_engine(port_mmio);
8e7decdb 2919 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2920
b67a1064 2921 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2922 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2923 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2924 }
b67a1064 2925 /*
8e7decdb 2926 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2927 * link, and physical layers. It resets all SATA interface registers
2928 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2929 */
8e7decdb 2930 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2931 udelay(25); /* allow reset propagation */
c9d39130
JG		 2932 writelfl(0, port_mmio + EDMA_CMD_OFS);
2933
2934 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2935
ee9ccdf7 2936 if (IS_GEN_I(hpriv))
c9d39130
JG		 2937 mdelay(1);
2938}
2939
e49856d8 2940static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2941{
e49856d8
ML		 2942 if (sata_pmp_supported(ap)) {
2943 void __iomem *port_mmio = mv_ap_base(ap);
2944 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2945 int old = reg & 0xf;
22374677 2946
e49856d8
ML		 2947 if (old != pmp) {
2948 reg = (reg & ~0xf) | pmp;
2949 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2950 }
22374677 2951 }
20f733e7
BR		 2952}
2953
e49856d8
ML		 2954static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2955 unsigned long deadline)
22374677 2956{
e49856d8
ML		 2957 mv_pmp_select(link->ap, sata_srst_pmp(link));
2958 return sata_std_hardreset(link, class, deadline);
2959}
bdd4ddde 2960
e49856d8
ML		 2961static int mv_softreset(struct ata_link *link, unsigned int *class,
2962 unsigned long deadline)
2963{
2964 mv_pmp_select(link->ap, sata_srst_pmp(link));
2965 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2966}
2967
cc0680a5 2968static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2969 unsigned long deadline)
31961943 2970{
cc0680a5 2971 struct ata_port *ap = link->ap;
bdd4ddde 2972 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2973 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2974 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2975 int rc, attempts = 0, extra = 0;
2976 u32 sstatus;
2977 bool online;
31961943 2978
e12bef50 2979 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2980 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2981
0d8be5cb
ML		 2982 /* Workaround for errata FEr SATA#10 (part 2) */
2983 do {
17c5aab5
ML		 2984 const unsigned long *timing =
2985 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2986
17c5aab5
ML		 2987 rc = sata_link_hardreset(link, timing, deadline + extra,
2988 &online, NULL);
9dcffd99 2989 rc = online ? -EAGAIN : rc;
17c5aab5 2990 if (rc)
0d8be5cb 2991 return rc;
0d8be5cb
ML		 2992 sata_scr_read(link, SCR_STATUS, &sstatus);
2993 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2994 /* Force 1.5gb/s link speed and try again */
8e7decdb 2995 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2996 if (time_after(jiffies + HZ, deadline))
2997 extra = HZ; /* only extend it once, max */
2998 }
2999 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 3000
17c5aab5 3001 return rc;
bdd4ddde
JG		 3002}
3003
bdd4ddde
JG		 3004static void mv_eh_freeze(struct ata_port *ap)
3005{
1cfd19ae 3006 mv_stop_edma(ap);
c4de573b 3007 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3008}
3009
3010static void mv_eh_thaw(struct ata_port *ap)
3011{
f351b2d6 3012 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3013 unsigned int port = ap->port_no;
3014 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3015 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3016 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3017 u32 hc_irq_cause;
bdd4ddde 3018
bdd4ddde
JG		 3019 /* clear EDMA errors on this port */
3020 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3021
3022 /* clear pending irq events */
cae6edc3 3023 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1cfd19ae 3024 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 3025
88e675e1 3026 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3027}
3028
05b308e1
BR		 3029/**
3030 * mv_port_init - Perform some early initialization on a single port.
3031 * @port: libata data structure storing shadow register addresses
3032 * @port_mmio: base address of the port
3033 *
3034 * Initialize shadow register mmio addresses, clear outstanding
3035 * interrupts on the port, and unmask interrupts for the future
3036 * start of the port.
3037 *
3038 * LOCKING:
3039 * Inherited from caller.
3040 */
31961943 3041static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3042{
0d5ff566 3043 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 3044 unsigned serr_ofs;
3045
8b260248 3046 /* PIO related setup
31961943
BR		 3047 */
3048 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3049 port->error_addr =
31961943
BR		 3050 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3051 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3052 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3053 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3054 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3055 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3056 port->status_addr =
31961943
BR		 3057 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3058 /* special case: control/altstatus doesn't have ATA_REG_ address */
3059 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3060
3061 /* unused: */
8d9db2d2 3062 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 3063
31961943
BR		 3064 /* Clear any currently outstanding port interrupt conditions */
3065 serr_ofs = mv_scr_offset(SCR_ERROR);
3066 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3067 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3068
646a4da5
ML		 3069 /* unmask all non-transient EDMA error interrupts */
3070 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 3071
8b260248 3072 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 3073 readl(port_mmio + EDMA_CFG_OFS),
3074 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3075 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 3076}
3077
616d4a98
ML		 3078static unsigned int mv_in_pcix_mode(struct ata_host *host)
3079{
3080 struct mv_host_priv *hpriv = host->private_data;
3081 void __iomem *mmio = hpriv->base;
3082 u32 reg;
3083
1f398472 3084 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98
ML		 3085 return 0; /* not PCI-X capable */
3086 reg = readl(mmio + MV_PCI_MODE_OFS);
3087 if ((reg & MV_PCI_MODE_MASK) == 0)
3088 return 0; /* conventional PCI mode */
3089 return 1; /* chip is in PCI-X mode */
3090}
3091
3092static int mv_pci_cut_through_okay(struct ata_host *host)
3093{
3094 struct mv_host_priv *hpriv = host->private_data;
3095 void __iomem *mmio = hpriv->base;
3096 u32 reg;
3097
3098 if (!mv_in_pcix_mode(host)) {
3099 reg = readl(mmio + PCI_COMMAND_OFS);
3100 if (reg & PCI_COMMAND_MRDTRIG)
3101 return 0; /* not okay */
3102 }
3103 return 1; /* okay */
3104}
3105
4447d351 3106static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3107{
4447d351
TH		 3108 struct pci_dev *pdev = to_pci_dev(host->dev);
3109 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3110 u32 hp_flags = hpriv->hp_flags;
3111
5796d1c4 3112 switch (board_idx) {
47c2b677
JG		 3113 case chip_5080:
3114 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3115 hp_flags |= MV_HP_GEN_I;
47c2b677 3116
44c10138 3117 switch (pdev->revision) {
47c2b677
JG		 3118 case 0x1:
3119 hp_flags |= MV_HP_ERRATA_50XXB0;
3120 break;
3121 case 0x3:
3122 hp_flags |= MV_HP_ERRATA_50XXB2;
3123 break;
3124 default:
3125 dev_printk(KERN_WARNING, &pdev->dev,
3126 "Applying 50XXB2 workarounds to unknown rev\n");
3127 hp_flags |= MV_HP_ERRATA_50XXB2;
3128 break;
3129 }
3130 break;
3131
bca1c4eb
JG		 3132 case chip_504x:
3133 case chip_508x:
47c2b677 3134 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3135 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3136
44c10138 3137 switch (pdev->revision) {
47c2b677
JG		 3138 case 0x0:
3139 hp_flags |= MV_HP_ERRATA_50XXB0;
3140 break;
3141 case 0x3:
3142 hp_flags |= MV_HP_ERRATA_50XXB2;
3143 break;
3144 default:
3145 dev_printk(KERN_WARNING, &pdev->dev,
3146 "Applying B2 workarounds to unknown rev\n");
3147 hp_flags |= MV_HP_ERRATA_50XXB2;
3148 break;
bca1c4eb
JG		 3149 }
3150 break;
3151
3152 case chip_604x:
3153 case chip_608x:
47c2b677 3154 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3155 hp_flags |= MV_HP_GEN_II;
47c2b677 3156
44c10138 3157 switch (pdev->revision) {
47c2b677
JG		 3158 case 0x7:
3159 hp_flags |= MV_HP_ERRATA_60X1B2;
3160 break;
3161 case 0x9:
3162 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3163 break;
3164 default:
3165 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 3166 "Applying B2 workarounds to unknown rev\n");
3167 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3168 break;
3169 }
3170 break;
3171
e4e7b892 3172 case chip_7042:
616d4a98 3173 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3174 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3175 (pdev->device == 0x2300 || pdev->device == 0x2310))
3176 {
4e520033
ML		 3177 /*
3178 * Highpoint RocketRAID PCIe 23xx series cards:
3179 *
3180 * Unconfigured drives are treated as "Legacy"
3181 * by the BIOS, and it overwrites sector 8 with
3182 * a "Lgcy" metadata block prior to Linux boot.
3183 *
3184 * Configured drives (RAID or JBOD) leave sector 8
3185 * alone, but instead overwrite a high numbered
3186 * sector for the RAID metadata. This sector can
3187 * be determined exactly, by truncating the physical
3188 * drive capacity to a nice even GB value.
3189 *
3190 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3191 *
3192 * Warn the user, lest they think we're just buggy.
3193 */
3194 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3195 " BIOS CORRUPTS DATA on all attached drives,"
3196 " regardless of if/how they are configured."
3197 " BEWARE!\n");
3198 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3199 " use sectors 8-9 on \"Legacy\" drives,"
3200 " and avoid the final two gigabytes on"
3201 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3202 }
8e7decdb 3203 /* drop through */
e4e7b892
JG		 3204 case chip_6042:
3205 hpriv->ops = &mv6xxx_ops;
e4e7b892 3206 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3207 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3208 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3209
44c10138 3210 switch (pdev->revision) {
5cf73bfb 3211 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3212 hp_flags |= MV_HP_ERRATA_60X1C0;
3213 break;
3214 default:
3215 dev_printk(KERN_WARNING, &pdev->dev,
3216 "Applying 60X1C0 workarounds to unknown rev\n");
3217 hp_flags |= MV_HP_ERRATA_60X1C0;
3218 break;
3219 }
3220 break;
f351b2d6
SB		 3221 case chip_soc:
3222 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3223 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3224 MV_HP_ERRATA_60X1C0;
f351b2d6 3225 break;
e4e7b892 3226
bca1c4eb 3227 default:
f351b2d6 3228 dev_printk(KERN_ERR, host->dev,
5796d1c4 3229 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3230 return 1;
3231 }
3232
3233 hpriv->hp_flags = hp_flags;
02a121da
ML		 3234 if (hp_flags & MV_HP_PCIE) {
3235 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3236 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3237 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3238 } else {
3239 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3240 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3241 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3242 }
bca1c4eb
JG		 3243
3244 return 0;
3245}
3246
05b308e1 3247/**
47c2b677 3248 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3249 * @host: ATA host to initialize
3250 * @board_idx: controller index
05b308e1
BR		 3251 *
3252 * If possible, do an early global reset of the host. Then do
3253 * our port init and clear/unmask all/relevant host interrupts.
3254 *
3255 * LOCKING:
3256 * Inherited from caller.
3257 */
4447d351 3258static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3259{
3260 int rc = 0, n_hc, port, hc;
4447d351 3261 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3262 void __iomem *mmio = hpriv->base;
47c2b677 3263
4447d351 3264 rc = mv_chip_id(host, board_idx);
bca1c4eb 3265 if (rc)
352fab70 3266 goto done;
f351b2d6 3267
1f398472 3268 if (IS_SOC(hpriv)) {
7368f919
ML		 3269 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3270 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
1f398472
ML		 3271 } else {
3272 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3273 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3274 }
352fab70 3275
5d0fb2e7
TR		 3276 /* initialize shadow irq mask with register's value */
3277 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3278
352fab70 3279 /* global interrupt mask: 0 == mask everything */
c4de573b 3280 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3281
4447d351 3282 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3283
4447d351 3284 for (port = 0; port < host->n_ports; port++)
47c2b677 3285 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3286
c9d39130 3287 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3288 if (rc)
20f733e7 3289 goto done;
20f733e7 3290
522479fb 3291 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3292 hpriv->ops->reset_bus(host, mmio);
47c2b677 3293 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3294
4447d351 3295 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3296 struct ata_port *ap = host->ports[port];
2a47ce06 3297 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3298
3299 mv_port_init(&ap->ioaddr, port_mmio);
3300
7bb3c529 3301#ifdef CONFIG_PCI
1f398472 3302 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3303 unsigned int offset = port_mmio - mmio;
3304 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3305 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3306 }
7bb3c529 3307#endif
20f733e7
BR		 3308 }
3309
3310 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3311 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3312
3313 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3314 "(before clear)=0x%08x\n", hc,
3315 readl(hc_mmio + HC_CFG_OFS),
3316 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3317
3318 /* Clear any currently outstanding hc interrupt conditions */
3319 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3320 }
3321
6be96ac1
ML		 3322 /* Clear any currently outstanding host interrupt conditions */
3323 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3324
6be96ac1
ML		 3325 /* and unmask interrupt generation for host regs */
3326 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2 3327
6be96ac1
ML		 3328 /*
3329 * enable only global host interrupts for now.
3330 * The per-port interrupts get done later as ports are set up.
3331 */
3332 mv_set_main_irq_mask(host, 0, PCI_ERR);
f351b2d6
SB		 3333done:
3334 return rc;
3335}
fb621e2f 3336
fbf14e2f
BB		 3337static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3338{
3339 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3340 MV_CRQB_Q_SZ, 0);
3341 if (!hpriv->crqb_pool)
3342 return -ENOMEM;
3343
3344 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3345 MV_CRPB_Q_SZ, 0);
3346 if (!hpriv->crpb_pool)
3347 return -ENOMEM;
3348
3349 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3350 MV_SG_TBL_SZ, 0);
3351 if (!hpriv->sg_tbl_pool)
3352 return -ENOMEM;
3353
3354 return 0;
3355}
3356
15a32632
LB		 3357static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3358 struct mbus_dram_target_info *dram)
3359{
3360 int i;
3361
3362 for (i = 0; i < 4; i++) {
3363 writel(0, hpriv->base + WINDOW_CTRL(i));
3364 writel(0, hpriv->base + WINDOW_BASE(i));
3365 }
3366
3367 for (i = 0; i < dram->num_cs; i++) {
3368 struct mbus_dram_window *cs = dram->cs + i;
3369
3370 writel(((cs->size - 1) & 0xffff0000) |
3371 (cs->mbus_attr << 8) |
3372 (dram->mbus_dram_target_id << 4) | 1,
3373 hpriv->base + WINDOW_CTRL(i));
3374 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3375 }
3376}
3377
f351b2d6
SB		 3378/**
3379 * mv_platform_probe - handle a positive probe of an soc Marvell
3380 * host
3381 * @pdev: platform device found
3382 *
3383 * LOCKING:
3384 * Inherited from caller.
3385 */
3386static int mv_platform_probe(struct platform_device *pdev)
3387{
3388 static int printed_version;
3389 const struct mv_sata_platform_data *mv_platform_data;
3390 const struct ata_port_info *ppi[] =
3391 { &mv_port_info[chip_soc], NULL };
3392 struct ata_host *host;
3393 struct mv_host_priv *hpriv;
3394 struct resource *res;
3395 int n_ports, rc;
20f733e7 3396
f351b2d6
SB		 3397 if (!printed_version++)
3398 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3399
f351b2d6
SB		 3400 /*
3401 * Simple resource validation ..
3402 */
3403 if (unlikely(pdev->num_resources != 2)) {
3404 dev_err(&pdev->dev, "invalid number of resources\n");
3405 return -EINVAL;
3406 }
3407
3408 /*
3409 * Get the register base first
3410 */
3411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3412 if (res == NULL)
3413 return -EINVAL;
3414
3415 /* allocate host */
3416 mv_platform_data = pdev->dev.platform_data;
3417 n_ports = mv_platform_data->n_ports;
3418
3419 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3420 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3421
3422 if (!host || !hpriv)
3423 return -ENOMEM;
3424 host->private_data = hpriv;
3425 hpriv->n_ports = n_ports;
3426
3427 host->iomap = NULL;
f1cb0ea1
SB		 3428 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3429 res->end - res->start + 1);
f351b2d6
SB		 3430 hpriv->base -= MV_SATAHC0_REG_BASE;
3431
15a32632
LB		 3432 /*
3433 * (Re-)program MBUS remapping windows if we are asked to.
3434 */
3435 if (mv_platform_data->dram != NULL)
3436 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3437
fbf14e2f
BB		 3438 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3439 if (rc)
3440 return rc;
3441
f351b2d6
SB		 3442 /* initialize adapter */
3443 rc = mv_init_host(host, chip_soc);
3444 if (rc)
3445 return rc;
3446
3447 dev_printk(KERN_INFO, &pdev->dev,
3448 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3449 host->n_ports);
3450
3451 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3452 IRQF_SHARED, &mv6_sht);
3453}
3454
3455/*
3456 *
3457 * mv_platform_remove - unplug a platform interface
3458 * @pdev: platform device
3459 *
3460 * A platform bus SATA device has been unplugged. Perform the needed
3461 * cleanup. Also called on module unload for any active devices.
3462 */
3463static int __devexit mv_platform_remove(struct platform_device *pdev)
3464{
3465 struct device *dev = &pdev->dev;
3466 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3467
3468 ata_host_detach(host);
f351b2d6 3469 return 0;
20f733e7
BR		 3470}
3471
f351b2d6
SB		 3472static struct platform_driver mv_platform_driver = {
3473 .probe = mv_platform_probe,
3474 .remove = __devexit_p(mv_platform_remove),
3475 .driver = {
3476 .name = DRV_NAME,
3477 .owner = THIS_MODULE,
3478 },
3479};
3480
3481
7bb3c529 3482#ifdef CONFIG_PCI
f351b2d6
SB		 3483static int mv_pci_init_one(struct pci_dev *pdev,
3484 const struct pci_device_id *ent);
3485
7bb3c529
SB		 3486
3487static struct pci_driver mv_pci_driver = {
3488 .name = DRV_NAME,
3489 .id_table = mv_pci_tbl,
f351b2d6 3490 .probe = mv_pci_init_one,
7bb3c529
SB		 3491 .remove = ata_pci_remove_one,
3492};
3493
3494/*
3495 * module options
3496 */
3497static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3498
3499
3500/* move to PCI layer or libata core? */
3501static int pci_go_64(struct pci_dev *pdev)
3502{
3503 int rc;
3504
3505 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3506 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3507 if (rc) {
3508 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3509 if (rc) {
3510 dev_printk(KERN_ERR, &pdev->dev,
3511 "64-bit DMA enable failed\n");
3512 return rc;
3513 }
3514 }
3515 } else {
3516 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3517 if (rc) {
3518 dev_printk(KERN_ERR, &pdev->dev,
3519 "32-bit DMA enable failed\n");
3520 return rc;
3521 }
3522 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3523 if (rc) {
3524 dev_printk(KERN_ERR, &pdev->dev,
3525 "32-bit consistent DMA enable failed\n");
3526 return rc;
3527 }
3528 }
3529
3530 return rc;
3531}
3532
05b308e1
BR		 3533/**
3534 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3535 * @host: ATA host to print info about
05b308e1
BR		 3536 *
3537 * FIXME: complete this.
3538 *
3539 * LOCKING:
3540 * Inherited from caller.
3541 */
4447d351 3542static void mv_print_info(struct ata_host *host)
31961943 3543{
4447d351
TH		 3544 struct pci_dev *pdev = to_pci_dev(host->dev);
3545 struct mv_host_priv *hpriv = host->private_data;
44c10138 3546 u8 scc;
c1e4fe71 3547 const char *scc_s, *gen;
31961943
BR		 3548
3549 /* Use this to determine the HW stepping of the chip so we know
3550 * what errata to workaround
3551 */
31961943
BR		 3552 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3553 if (scc == 0)
3554 scc_s = "SCSI";
3555 else if (scc == 0x01)
3556 scc_s = "RAID";
3557 else
c1e4fe71
JG		 3558 scc_s = "?";
3559
3560 if (IS_GEN_I(hpriv))
3561 gen = "I";
3562 else if (IS_GEN_II(hpriv))
3563 gen = "II";
3564 else if (IS_GEN_IIE(hpriv))
3565 gen = "IIE";
3566 else
3567 gen = "?";
31961943 3568
a9524a76 3569 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3570 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3571 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3572 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3573}
3574
05b308e1 3575/**
f351b2d6 3576 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3577 * @pdev: PCI device found
3578 * @ent: PCI device ID entry for the matched host
3579 *
3580 * LOCKING:
3581 * Inherited from caller.
3582 */
f351b2d6
SB		 3583static int mv_pci_init_one(struct pci_dev *pdev,
3584 const struct pci_device_id *ent)
20f733e7 3585{
2dcb407e 3586 static int printed_version;
20f733e7 3587 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3588 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3589 struct ata_host *host;
3590 struct mv_host_priv *hpriv;
3591 int n_ports, rc;
20f733e7 3592
a9524a76
JG		 3593 if (!printed_version++)
3594 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3595
4447d351
TH		 3596 /* allocate host */
3597 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3598
3599 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3600 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3601 if (!host || !hpriv)
3602 return -ENOMEM;
3603 host->private_data = hpriv;
f351b2d6 3604 hpriv->n_ports = n_ports;
4447d351
TH		 3605
3606 /* acquire resources */
24dc5f33
TH		 3607 rc = pcim_enable_device(pdev);
3608 if (rc)
20f733e7 3609 return rc;
20f733e7 3610
0d5ff566
TH		 3611 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3612 if (rc == -EBUSY)
24dc5f33 3613 pcim_pin_device(pdev);
0d5ff566 3614 if (rc)
24dc5f33 3615 return rc;
4447d351 3616 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3617 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3618
d88184fb
JG		 3619 rc = pci_go_64(pdev);
3620 if (rc)
3621 return rc;
3622
da2fa9ba
ML		 3623 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3624 if (rc)
3625 return rc;
3626
20f733e7 3627 /* initialize adapter */
4447d351 3628 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3629 if (rc)
3630 return rc;
20f733e7 3631
6d3c30ef
ML		 3632 /* Enable message-switched interrupts, if requested */
3633 if (msi && pci_enable_msi(pdev) == 0)
3634 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 3635
31961943 3636 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3637 mv_print_info(host);
20f733e7 3638
4447d351 3639 pci_set_master(pdev);
ea8b4db9 3640 pci_try_set_mwi(pdev);
4447d351 3641 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3642 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3643}
7bb3c529 3644#endif
20f733e7 3645
f351b2d6
SB		 3646static int mv_platform_probe(struct platform_device *pdev);
3647static int __devexit mv_platform_remove(struct platform_device *pdev);
3648
20f733e7
BR		 3649static int __init mv_init(void)
3650{
7bb3c529
SB		 3651 int rc = -ENODEV;
3652#ifdef CONFIG_PCI
3653 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3654 if (rc < 0)
3655 return rc;
3656#endif
3657 rc = platform_driver_register(&mv_platform_driver);
3658
3659#ifdef CONFIG_PCI
3660 if (rc < 0)
3661 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3662#endif
3663 return rc;
20f733e7
BR		 3664}
3665
3666static void __exit mv_exit(void)
3667{
7bb3c529 3668#ifdef CONFIG_PCI
20f733e7 3669 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3670#endif
f351b2d6 3671 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3672}
3673
3674MODULE_AUTHOR("Brett Russ");
3675MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3676MODULE_LICENSE("GPL");
3677MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3678MODULE_VERSION(DRV_VERSION);
17c5aab5 3679MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3680
7bb3c529 3681#ifdef CONFIG_PCI
ddef9bb3
JG		 3682module_param(msi, int, 0444);
3683MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3684#endif
ddef9bb3 3685
20f733e7
BR		 3686module_init(mv_init);
3687module_exit(mv_exit);
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