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sata_mv: remove bogus nsect restriction
[net-next-2.6.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
85afb934
ML		 38 * --> Develop a low-power-consumption strategy, and implement it.
39 *
40 * --> [Experiment, low priority] Investigate interrupt coalescing.
41 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
42 * the overhead reduced by interrupt mitigation is quite often not
43 * worth the latency cost.
44 *
45 * --> [Experiment, Marvell value added] Is it possible to use target
46 * mode to cross-connect two Linux boxes with Marvell cards? If so,
47 * creating LibATA target mode support would be very interesting.
48 *
49 * Target mode, for those without docs, is the ability to directly
50 * connect two SATA ports.
51 */
4a05e209 52
20f733e7
BR		 53#include <linux/kernel.h>
54#include <linux/module.h>
55#include <linux/pci.h>
56#include <linux/init.h>
57#include <linux/blkdev.h>
58#include <linux/delay.h>
59#include <linux/interrupt.h>
8d8b6004 60#include <linux/dmapool.h>
20f733e7 61#include <linux/dma-mapping.h>
a9524a76 62#include <linux/device.h>
f351b2d6
SB		 63#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
15a32632 65#include <linux/mbus.h>
c46938cc 66#include <linux/bitops.h>
20f733e7 67#include <scsi/scsi_host.h>
193515d5 68#include <scsi/scsi_cmnd.h>
6c08772e 69#include <scsi/scsi_device.h>
20f733e7 70#include <linux/libata.h>
20f733e7
BR		 71
72#define DRV_NAME "sata_mv"
0388a8c0 73#define DRV_VERSION "1.24"
20f733e7
BR		 74
75enum {
76 /* BAR's are enumerated in terms of pci_resource_start() terms */
77 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
78 MV_IO_BAR = 2, /* offset 0x18: IO space */
79 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
80
81 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
82 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
83
84 MV_PCI_REG_BASE = 0,
85 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 86 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
87 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
88 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
89 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
90 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
91
20f733e7 92 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 93 MV_FLASH_CTL_OFS = 0x1046c,
94 MV_GPIO_PORT_CTL_OFS = 0x104f0,
95 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 96
97 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
98 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
100 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
101
31961943
BR		 102 MV_MAX_Q_DEPTH = 32,
103 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
104
105 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
106 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 107 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
108 */
109 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
110 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 111 MV_MAX_SG_CT = 256,
31961943 112 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 113
352fab70 114 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 115 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 116 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
117 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
118 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 119
120 /* Host Flags */
121 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
122 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 123
c5d3e45a 124 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 125 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
126 ATA_FLAG_PIO_POLLING,
ad3aef51 127
47c2b677 128 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 129
ad3aef51
ML		 130 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
131 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
c443c500 132 ATA_FLAG_NCQ | ATA_FLAG_AN,
ad3aef51 133
31961943
BR		 134 CRQB_FLAG_READ = (1 << 0),
135 CRQB_TAG_SHIFT = 1,
c5d3e45a 136 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 137 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 138 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 139 CRQB_CMD_ADDR_SHIFT = 8,
140 CRQB_CMD_CS = (0x2 << 11),
141 CRQB_CMD_LAST = (1 << 15),
142
143 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 144 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
145 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 146
147 EPRD_FLAG_END_OF_TBL = (1 << 31),
148
20f733e7
BR		 149 /* PCI interface registers */
150
31961943 151 PCI_COMMAND_OFS = 0xc00,
8e7decdb 152 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 153
20f733e7
BR		 154 PCI_MAIN_CMD_STS_OFS = 0xd30,
155 STOP_PCI_MASTER = (1 << 2),
156 PCI_MASTER_EMPTY = (1 << 3),
157 GLOB_SFT_RST = (1 << 4),
158
8e7decdb
ML		 159 MV_PCI_MODE_OFS = 0xd00,
160 MV_PCI_MODE_MASK = 0x30,
161
522479fb
JG		 162 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
163 MV_PCI_DISC_TIMER = 0xd04,
164 MV_PCI_MSI_TRIGGER = 0xc38,
165 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 166 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 167 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
168 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
169 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
170 MV_PCI_ERR_COMMAND = 0x1d50,
171
02a121da
ML		 172 PCI_IRQ_CAUSE_OFS = 0x1d58,
173 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 174 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
175
02a121da
ML		 176 PCIE_IRQ_CAUSE_OFS = 0x1900,
177 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 178 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 179
7368f919
ML		 180 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
181 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
182 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
183 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
184 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 185 ERR_IRQ = (1 << 0), /* shift by port # */
186 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 187 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
188 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
189 PCI_ERR = (1 << 18),
190 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
191 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 192 PORTS_0_3_COAL_DONE = (1 << 8),
193 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 194 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
195 GPIO_INT = (1 << 22),
196 SELF_INT = (1 << 23),
197 TWSI_INT = (1 << 24),
198 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 199 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 200 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 201
202 /* SATAHC registers */
203 HC_CFG_OFS = 0,
204
205 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 206 DMA_IRQ = (1 << 0), /* shift by port # */
207 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 208 DEV_IRQ = (1 << 8), /* shift by port # */
209
210 /* Shadow block registers */
31961943
BR		 211 SHD_BLK_OFS = 0x100,
212 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 213
214 /* SATA registers */
215 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
216 SATA_ACTIVE_OFS = 0x350,
0c58912e 217 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 218 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 219
e12bef50 220 LTMODE_OFS = 0x30c,
17c5aab5
ML		 221 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
222
47c2b677 223 PHY_MODE3 = 0x310,
bca1c4eb 224 PHY_MODE4 = 0x314,
ba069e37
ML		 225 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
226 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
227 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
228 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
229
bca1c4eb 230 PHY_MODE2 = 0x330,
e12bef50 231 SATA_IFCTL_OFS = 0x344,
8e7decdb 232 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 233 SATA_IFSTAT_OFS = 0x34c,
234 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 235
8e7decdb
ML		 236 FISCFG_OFS = 0x360,
237 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
238 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 239
c9d39130 240 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 241 MV5_LTMODE_OFS = 0x30,
242 MV5_PHY_CTL_OFS = 0x0C,
243 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 244
245 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 246
247 /* Port registers */
248 EDMA_CFG_OFS = 0,
0c58912e
ML		 249 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
250 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
251 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
252 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
253 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 254 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
255 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 256
257 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
258 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 259 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
260 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
261 EDMA_ERR_DEV = (1 << 2), /* device error */
262 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
263 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
264 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 265 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
266 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 267 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 268 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 269 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
270 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
271 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
272 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 273
6c1153e0 274 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 275 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
276 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
277 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
278 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279
6c1153e0 280 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 281
6c1153e0 282 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 283 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
284 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
285 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
286 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
287 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288
6c1153e0 289 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 290
6c1153e0 291 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 292 EDMA_ERR_OVERRUN_5 = (1 << 5),
293 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 294
295 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
296 EDMA_ERR_LNK_CTRL_RX_1 |
297 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 298 EDMA_ERR_LNK_CTRL_TX,
646a4da5 299
bdd4ddde
JG		 300 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
301 EDMA_ERR_PRD_PAR |
302 EDMA_ERR_DEV_DCON |
303 EDMA_ERR_DEV_CON |
304 EDMA_ERR_SERR |
305 EDMA_ERR_SELF_DIS |
6c1153e0 306 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 307 EDMA_ERR_CRPB_PAR |
308 EDMA_ERR_INTRL_PAR |
309 EDMA_ERR_IORDY |
310 EDMA_ERR_LNK_CTRL_RX_2 |
311 EDMA_ERR_LNK_DATA_RX |
312 EDMA_ERR_LNK_DATA_TX |
313 EDMA_ERR_TRANS_PROTO,
e12bef50 314
bdd4ddde
JG		 315 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
316 EDMA_ERR_PRD_PAR |
317 EDMA_ERR_DEV_DCON |
318 EDMA_ERR_DEV_CON |
319 EDMA_ERR_OVERRUN_5 |
320 EDMA_ERR_UNDERRUN_5 |
321 EDMA_ERR_SELF_DIS_5 |
6c1153e0 322 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 323 EDMA_ERR_CRPB_PAR |
324 EDMA_ERR_INTRL_PAR |
325 EDMA_ERR_IORDY,
20f733e7 326
31961943
BR		 327 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
328 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 329
330 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
331 EDMA_REQ_Q_PTR_SHIFT = 5,
332
333 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
334 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
335 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 336 EDMA_RSP_Q_PTR_SHIFT = 3,
337
0ea9e179
JG		 338 EDMA_CMD_OFS = 0x28, /* EDMA command register */
339 EDMA_EN = (1 << 0), /* enable EDMA */
340 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 341 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
342
343 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
344 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
345 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 346
8e7decdb
ML		 347 EDMA_IORDY_TMOUT_OFS = 0x34,
348 EDMA_ARB_CFG_OFS = 0x38,
349
350 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 351
31961943
BR		 352 /* Host private flags (hp_flags) */
353 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 354 MV_HP_ERRATA_50XXB0 = (1 << 1),
355 MV_HP_ERRATA_50XXB2 = (1 << 2),
356 MV_HP_ERRATA_60X1B2 = (1 << 3),
357 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 358 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
359 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
360 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 361 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 362 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 363 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
20f733e7 364
31961943 365 /* Port private flags (pp_flags) */
0ea9e179 366 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 367 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 368 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 369 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 370};
371
ee9ccdf7
JG		 372#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
373#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 374#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 375#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 376#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 377
15a32632
LB		 378#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
379#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
380
095fec88 381enum {
baf14aa1
JG		 382 /* DMA boundary 0xffff is required by the s/g splitting
383 * we need on /length/ in mv_fill-sg().
384 */
385 MV_DMA_BOUNDARY = 0xffffU,
095fec88 386
0ea9e179
JG		 387 /* mask of register bits containing lower 32 bits
388 * of EDMA request queue DMA address
389 */
095fec88
JG		 390 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
391
0ea9e179 392 /* ditto, for response queue */
095fec88
JG		 393 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
394};
395
522479fb
JG		 396enum chip_type {
397 chip_504x,
398 chip_508x,
399 chip_5080,
400 chip_604x,
401 chip_608x,
e4e7b892
JG		 402 chip_6042,
403 chip_7042,
f351b2d6 404 chip_soc,
522479fb
JG		 405};
406
31961943
BR		 407/* Command ReQuest Block: 32B */
408struct mv_crqb {
e1469874
ML		 409 __le32 sg_addr;
410 __le32 sg_addr_hi;
411 __le16 ctrl_flags;
412 __le16 ata_cmd[11];
31961943 413};
20f733e7 414
e4e7b892 415struct mv_crqb_iie {
e1469874
ML		 416 __le32 addr;
417 __le32 addr_hi;
418 __le32 flags;
419 __le32 len;
420 __le32 ata_cmd[4];
e4e7b892
JG		 421};
422
31961943
BR		 423/* Command ResPonse Block: 8B */
424struct mv_crpb {
e1469874
ML		 425 __le16 id;
426 __le16 flags;
427 __le32 tmstmp;
20f733e7
BR		 428};
429
31961943
BR		 430/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
431struct mv_sg {
e1469874
ML		 432 __le32 addr;
433 __le32 flags_size;
434 __le32 addr_hi;
435 __le32 reserved;
31961943 436};
20f733e7 437
31961943
BR		 438struct mv_port_priv {
439 struct mv_crqb *crqb;
440 dma_addr_t crqb_dma;
441 struct mv_crpb *crpb;
442 dma_addr_t crpb_dma;
eb73d558
ML		 443 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
444 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 445
446 unsigned int req_idx;
447 unsigned int resp_idx;
448
31961943 449 u32 pp_flags;
29d187bb 450 unsigned int delayed_eh_pmp_map;
31961943
BR		 451};
452
bca1c4eb
JG		 453struct mv_port_signal {
454 u32 amps;
455 u32 pre;
456};
457
02a121da
ML		 458struct mv_host_priv {
459 u32 hp_flags;
96e2c487 460 u32 main_irq_mask;
02a121da
ML		 461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
f351b2d6
SB		 463 int n_ports;
464 void __iomem *base;
7368f919
ML		 465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
02a121da
ML		 467 u32 irq_cause_ofs;
468 u32 irq_mask_ofs;
469 u32 unmask_all_irqs;
da2fa9ba
ML		 470 /*
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
474 */
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
02a121da
ML		 478};
479
47c2b677 480struct mv_hw_ops {
2a47ce06
JG		 481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
482 unsigned int port);
47c2b677
JG		 483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
485 void __iomem *mmio);
c9d39130
JG		 486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
487 unsigned int n_hc);
522479fb 488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 490};
491
82ef04fb
TH		 492static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
493static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
494static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
495static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 496static int mv_port_start(struct ata_port *ap);
497static void mv_port_stop(struct ata_port *ap);
3e4a1391 498static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 499static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 500static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 501static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 502static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
bdd4ddde
JG		 504static void mv_eh_freeze(struct ata_port *ap);
505static void mv_eh_thaw(struct ata_port *ap);
f273827e 506static void mv6_dev_config(struct ata_device *dev);
20f733e7 507
2a47ce06
JG		 508static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
509 unsigned int port);
47c2b677
JG		 510static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
512 void __iomem *mmio);
c9d39130
JG		 513static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
514 unsigned int n_hc);
522479fb 515static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 516static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 517
2a47ce06
JG		 518static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
519 unsigned int port);
47c2b677
JG		 520static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
522 void __iomem *mmio);
c9d39130
JG		 523static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
524 unsigned int n_hc);
522479fb 525static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 526static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
527 void __iomem *mmio);
528static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
529 void __iomem *mmio);
530static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
533 void __iomem *mmio);
534static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 535static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 536static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 537 unsigned int port_no);
e12bef50 538static int mv_stop_edma(struct ata_port *ap);
b562468c 539static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 540static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 541
e49856d8
ML		 542static void mv_pmp_select(struct ata_port *ap, int pmp);
543static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
29d187bb 547static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 548static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
47c2b677 550
eb73d558
ML		 551/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
554 */
c5d3e45a 555static struct scsi_host_template mv5_sht = {
68d1d07b 556 ATA_BASE_SHT(DRV_NAME),
baf14aa1 557 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 558 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 559};
560
561static struct scsi_host_template mv6_sht = {
68d1d07b 562 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 563 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 564 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 565 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 566};
567
029cfd6b
TH		 568static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
c9d39130 570
3e4a1391 571 .qc_defer = mv_qc_defer,
c9d39130
JG		 572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
c9d39130 574
bdd4ddde
JG		 575 .freeze = mv_eh_freeze,
576 .thaw = mv_eh_thaw,
a1efdaba 577 .hardreset = mv_hardreset,
a1efdaba 578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 579 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 580
c9d39130
JG		 581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
583
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
c9d39130
JG		 586};
587
029cfd6b
TH		 588static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
f273827e 590 .dev_config = mv6_dev_config,
20f733e7
BR		 591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
593
e49856d8
ML		 594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
29d187bb 597 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 598};
599
029cfd6b
TH		 600static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
e4e7b892 603 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 604};
605
98ac62de 606static const struct ata_port_info mv_port_info[] = {
20f733e7 607 { /* chip_504x */
cca3974e 608 .flags = MV_COMMON_FLAGS,
31961943 609 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 610 .udma_mask = ATA_UDMA6,
c9d39130 611 .port_ops = &mv5_ops,
20f733e7
BR		 612 },
613 { /* chip_508x */
c5d3e45a 614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 615 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
c9d39130 617 .port_ops = &mv5_ops,
20f733e7 618 },
47c2b677 619 { /* chip_5080 */
c5d3e45a 620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 621 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 622 .udma_mask = ATA_UDMA6,
c9d39130 623 .port_ops = &mv5_ops,
47c2b677 624 },
20f733e7 625 { /* chip_604x */
138bfdd0 626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 628 ATA_FLAG_NCQ,
31961943 629 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 630 .udma_mask = ATA_UDMA6,
c9d39130 631 .port_ops = &mv6_ops,
20f733e7
BR		 632 },
633 { /* chip_608x */
c5d3e45a 634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 637 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 638 .udma_mask = ATA_UDMA6,
c9d39130 639 .port_ops = &mv6_ops,
20f733e7 640 },
e4e7b892 641 { /* chip_6042 */
ad3aef51 642 .flags = MV_GENIIE_FLAGS,
e4e7b892 643 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 644 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 645 .port_ops = &mv_iie_ops,
646 },
647 { /* chip_7042 */
ad3aef51 648 .flags = MV_GENIIE_FLAGS,
e4e7b892 649 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 650 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 651 .port_ops = &mv_iie_ops,
652 },
f351b2d6 653 { /* chip_soc */
1f398472 654 .flags = MV_GENIIE_FLAGS,
17c5aab5
ML		 655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
f351b2d6 658 },
20f733e7
BR		 659};
660
3b7d697d 661static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 666 /* RocketRAID 1720/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
cfbf723e
AC		 668 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
669 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 670
671 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
673 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
674 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
675 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
676
677 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
678
d9f9c6bc
FA		 679 /* Adaptec 1430SA */
680 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
681
02a121da 682 /* Marvell 7042 support */
6a3d586d
MT		 683 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
684
02a121da
ML		 685 /* Highpoint RocketRAID PCIe series */
686 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
687 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
688
2d2744fc 689 { } /* terminate list */
20f733e7
BR		 690};
691
47c2b677
JG		 692static const struct mv_hw_ops mv5xxx_ops = {
693 .phy_errata = mv5_phy_errata,
694 .enable_leds = mv5_enable_leds,
695 .read_preamp = mv5_read_preamp,
696 .reset_hc = mv5_reset_hc,
522479fb
JG		 697 .reset_flash = mv5_reset_flash,
698 .reset_bus = mv5_reset_bus,
47c2b677
JG		 699};
700
701static const struct mv_hw_ops mv6xxx_ops = {
702 .phy_errata = mv6_phy_errata,
703 .enable_leds = mv6_enable_leds,
704 .read_preamp = mv6_read_preamp,
705 .reset_hc = mv6_reset_hc,
522479fb
JG		 706 .reset_flash = mv6_reset_flash,
707 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 708};
709
f351b2d6
SB		 710static const struct mv_hw_ops mv_soc_ops = {
711 .phy_errata = mv6_phy_errata,
712 .enable_leds = mv_soc_enable_leds,
713 .read_preamp = mv_soc_read_preamp,
714 .reset_hc = mv_soc_reset_hc,
715 .reset_flash = mv_soc_reset_flash,
716 .reset_bus = mv_soc_reset_bus,
717};
718
20f733e7
BR		 719/*
720 * Functions
721 */
722
723static inline void writelfl(unsigned long data, void __iomem *addr)
724{
725 writel(data, addr);
726 (void) readl(addr); /* flush to avoid PCI posted write */
727}
728
c9d39130
JG		 729static inline unsigned int mv_hc_from_port(unsigned int port)
730{
731 return port >> MV_PORT_HC_SHIFT;
732}
733
734static inline unsigned int mv_hardport_from_port(unsigned int port)
735{
736 return port & MV_PORT_MASK;
737}
738
1cfd19ae
ML		 739/*
740 * Consolidate some rather tricky bit shift calculations.
741 * This is hot-path stuff, so not a function.
742 * Simple code, with two return values, so macro rather than inline.
743 *
744 * port is the sole input, in range 0..7.
7368f919
ML		 745 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
746 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 747 *
748 * Note that port and hardport may be the same variable in some cases.
749 */
750#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
751{ \
752 shift = mv_hc_from_port(port) * HC_SHIFT; \
753 hardport = mv_hardport_from_port(port); \
754 shift += hardport * 2; \
755}
756
352fab70
ML		 757static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
758{
759 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
760}
761
c9d39130
JG		 762static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
763 unsigned int port)
764{
765 return mv_hc_base(base, mv_hc_from_port(port));
766}
767
20f733e7
BR		 768static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
769{
c9d39130 770 return mv_hc_base_from_port(base, port) +
8b260248 771 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 772 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 773}
774
e12bef50
ML		 775static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
776{
777 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
778 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
779
780 return hc_mmio + ofs;
781}
782
f351b2d6
SB		 783static inline void __iomem *mv_host_base(struct ata_host *host)
784{
785 struct mv_host_priv *hpriv = host->private_data;
786 return hpriv->base;
787}
788
20f733e7
BR		 789static inline void __iomem *mv_ap_base(struct ata_port *ap)
790{
f351b2d6 791 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 792}
793
cca3974e 794static inline int mv_get_hc_count(unsigned long port_flags)
31961943 795{
cca3974e 796 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 797}
798
c5d3e45a
JG		 799static void mv_set_edma_ptrs(void __iomem *port_mmio,
800 struct mv_host_priv *hpriv,
801 struct mv_port_priv *pp)
802{
bdd4ddde
JG		 803 u32 index;
804
c5d3e45a
JG		 805 /*
806 * initialize request queue
807 */
fcfb1f77
ML		 808 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
809 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 810
c5d3e45a
JG		 811 WARN_ON(pp->crqb_dma & 0x3ff);
812 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 813 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a 814 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
5cf73bfb 815 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 816
817 /*
818 * initialize response queue
819 */
fcfb1f77
ML		 820 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
821 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 822
c5d3e45a
JG		 823 WARN_ON(pp->crpb_dma & 0xff);
824 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
5cf73bfb 825 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
bdd4ddde 826 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 827 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 828}
829
c4de573b
ML		 830static void mv_set_main_irq_mask(struct ata_host *host,
831 u32 disable_bits, u32 enable_bits)
832{
833 struct mv_host_priv *hpriv = host->private_data;
834 u32 old_mask, new_mask;
835
96e2c487 836 old_mask = hpriv->main_irq_mask;
c4de573b 837 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 838 if (new_mask != old_mask) {
839 hpriv->main_irq_mask = new_mask;
c4de573b 840 writelfl(new_mask, hpriv->main_irq_mask_addr);
96e2c487 841 }
c4de573b
ML		 842}
843
844static void mv_enable_port_irqs(struct ata_port *ap,
845 unsigned int port_bits)
846{
847 unsigned int shift, hardport, port = ap->port_no;
848 u32 disable_bits, enable_bits;
849
850 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
851
852 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
853 enable_bits = port_bits << shift;
854 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
855}
856
05b308e1
BR		 857/**
858 * mv_start_dma - Enable eDMA engine
859 * @base: port base address
860 * @pp: port private data
861 *
beec7dbc
TH		 862 * Verify the local cache of the eDMA state is accurate with a
863 * WARN_ON.
05b308e1
BR		 864 *
865 * LOCKING:
866 * Inherited from caller.
867 */
0c58912e 868static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 869 struct mv_port_priv *pp, u8 protocol)
20f733e7 870{
72109168
ML		 871 int want_ncq = (protocol == ATA_PROT_NCQ);
872
873 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
874 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
875 if (want_ncq != using_ncq)
b562468c 876 mv_stop_edma(ap);
72109168 877 }
c5d3e45a 878 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 879 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 880 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 881 void __iomem *hc_mmio = mv_hc_base_from_port(
b0bccb18 882 mv_host_base(ap->host), ap->port_no);
cae6edc3 883 u32 hc_irq_cause;
0c58912e 884
bdd4ddde 885 /* clear EDMA event indicators, if any */
f630d562 886 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 887
cae6edc3
ML		 888 /* clear pending irq events */
889 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
890 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
0c58912e 891
e12bef50 892 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 893
894 /* clear FIS IRQ Cause */
e4006077
ML		 895 if (IS_GEN_IIE(hpriv))
896 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
0c58912e 897
f630d562 898 mv_set_edma_ptrs(port_mmio, hpriv, pp);
88e675e1 899 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ);
bdd4ddde 900
f630d562 901 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 902 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
903 }
20f733e7
BR		 904}
905
9b2c4e0b
ML		 906static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
907{
908 void __iomem *port_mmio = mv_ap_base(ap);
909 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
910 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
911 int i;
912
913 /*
914 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 915 * No idea what a good "timeout" value might be, but measurements
916 * indicate that it often requires hundreds of microseconds
917 * with two drives in-use. So we use the 15msec value above
918 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 919 */
920 for (i = 0; i < timeout; ++i) {
921 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
922 if ((edma_stat & empty_idle) == empty_idle)
923 break;
924 udelay(per_loop);
925 }
926 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
927}
928
05b308e1 929/**
e12bef50 930 * mv_stop_edma_engine - Disable eDMA engine
b562468c 931 * @port_mmio: io base address
05b308e1
BR		 932 *
933 * LOCKING:
934 * Inherited from caller.
935 */
b562468c 936static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 937{
b562468c 938 int i;
31961943 939
b562468c
ML		 940 /* Disable eDMA. The disable bit auto clears. */
941 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 942
b562468c
ML		 943 /* Wait for the chip to confirm eDMA is off. */
944 for (i = 10000; i > 0; i--) {
945 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 946 if (!(reg & EDMA_EN))
b562468c
ML		 947 return 0;
948 udelay(10);
31961943 949 }
b562468c 950 return -EIO;
20f733e7
BR		 951}
952
e12bef50 953static int mv_stop_edma(struct ata_port *ap)
0ea9e179 954{
b562468c
ML		 955 void __iomem *port_mmio = mv_ap_base(ap);
956 struct mv_port_priv *pp = ap->private_data;
0ea9e179 957
b562468c
ML		 958 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
959 return 0;
960 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 961 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 962 if (mv_stop_edma_engine(port_mmio)) {
963 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
964 return -EIO;
965 }
966 return 0;
0ea9e179
JG		 967}
968
8a70f8dc 969#ifdef ATA_DEBUG
31961943 970static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 971{
31961943
BR		 972 int b, w;
973 for (b = 0; b < bytes; ) {
974 DPRINTK("%p: ", start + b);
975 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 976 printk("%08x ", readl(start + b));
31961943
BR		 977 b += sizeof(u32);
978 }
979 printk("\n");
980 }
31961943 981}
8a70f8dc
JG		 982#endif
983
31961943
BR		 984static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
985{
986#ifdef ATA_DEBUG
987 int b, w;
988 u32 dw;
989 for (b = 0; b < bytes; ) {
990 DPRINTK("%02x: ", b);
991 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 992 (void) pci_read_config_dword(pdev, b, &dw);
993 printk("%08x ", dw);
31961943
BR		 994 b += sizeof(u32);
995 }
996 printk("\n");
997 }
998#endif
999}
1000static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1001 struct pci_dev *pdev)
1002{
1003#ifdef ATA_DEBUG
8b260248 1004 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1005 port >> MV_PORT_HC_SHIFT);
1006 void __iomem *port_base;
1007 int start_port, num_ports, p, start_hc, num_hcs, hc;
1008
1009 if (0 > port) {
1010 start_hc = start_port = 0;
1011 num_ports = 8; /* shld be benign for 4 port devs */
1012 num_hcs = 2;
1013 } else {
1014 start_hc = port >> MV_PORT_HC_SHIFT;
1015 start_port = port;
1016 num_ports = num_hcs = 1;
1017 }
8b260248 1018 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1019 num_ports > 1 ? num_ports - 1 : start_port);
1020
1021 if (NULL != pdev) {
1022 DPRINTK("PCI config space regs:\n");
1023 mv_dump_pci_cfg(pdev, 0x68);
1024 }
1025 DPRINTK("PCI regs:\n");
1026 mv_dump_mem(mmio_base+0xc00, 0x3c);
1027 mv_dump_mem(mmio_base+0xd00, 0x34);
1028 mv_dump_mem(mmio_base+0xf00, 0x4);
1029 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1030 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1031 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1032 DPRINTK("HC regs (HC %i):\n", hc);
1033 mv_dump_mem(hc_base, 0x1c);
1034 }
1035 for (p = start_port; p < start_port + num_ports; p++) {
1036 port_base = mv_port_base(mmio_base, p);
2dcb407e 1037 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1038 mv_dump_mem(port_base, 0x54);
2dcb407e 1039 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1040 mv_dump_mem(port_base+0x300, 0x60);
1041 }
1042#endif
20f733e7
BR		 1043}
1044
1045static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1046{
1047 unsigned int ofs;
1048
1049 switch (sc_reg_in) {
1050 case SCR_STATUS:
1051 case SCR_CONTROL:
1052 case SCR_ERROR:
1053 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1054 break;
1055 case SCR_ACTIVE:
1056 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1057 break;
1058 default:
1059 ofs = 0xffffffffU;
1060 break;
1061 }
1062 return ofs;
1063}
1064
82ef04fb 1065static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1066{
1067 unsigned int ofs = mv_scr_offset(sc_reg_in);
1068
da3dbb17 1069 if (ofs != 0xffffffffU) {
82ef04fb 1070 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1071 return 0;
1072 } else
1073 return -EINVAL;
20f733e7
BR		 1074}
1075
82ef04fb 1076static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1077{
1078 unsigned int ofs = mv_scr_offset(sc_reg_in);
1079
da3dbb17 1080 if (ofs != 0xffffffffU) {
82ef04fb 1081 writelfl(val, mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1082 return 0;
1083 } else
1084 return -EINVAL;
20f733e7
BR		 1085}
1086
f273827e
ML		 1087static void mv6_dev_config(struct ata_device *adev)
1088{
1089 /*
e49856d8
ML		 1090 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1091 *
1092 * Gen-II does not support NCQ over a port multiplier
1093 * (no FIS-based switching).
f273827e 1094 */
e49856d8 1095 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1096 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1097 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1098 ata_dev_printk(adev, KERN_INFO,
1099 "NCQ disabled for command-based switching\n");
352fab70 1100 }
e49856d8 1101 }
f273827e
ML		 1102}
1103
3e4a1391
ML		 1104static int mv_qc_defer(struct ata_queued_cmd *qc)
1105{
1106 struct ata_link *link = qc->dev->link;
1107 struct ata_port *ap = link->ap;
1108 struct mv_port_priv *pp = ap->private_data;
1109
29d187bb
ML		 1110 /*
1111 * Don't allow new commands if we're in a delayed EH state
1112 * for NCQ and/or FIS-based switching.
1113 */
1114 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1115 return ATA_DEFER_PORT;
3e4a1391
ML		 1116 /*
1117 * If the port is completely idle, then allow the new qc.
1118 */
1119 if (ap->nr_active_links == 0)
1120 return 0;
1121
4bdee6c5
TH		 1122 /*
1123 * The port is operating in host queuing mode (EDMA) with NCQ
1124 * enabled, allow multiple NCQ commands. EDMA also allows
1125 * queueing multiple DMA commands but libata core currently
1126 * doesn't allow it.
1127 */
1128 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1129 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1130 return 0;
1131
3e4a1391
ML		 1132 return ATA_DEFER_PORT;
1133}
1134
00f42eab 1135static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1136{
00f42eab
ML		 1137 u32 new_fiscfg, old_fiscfg;
1138 u32 new_ltmode, old_ltmode;
1139 u32 new_haltcond, old_haltcond;
1140
1141 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1142 old_ltmode = readl(port_mmio + LTMODE_OFS);
1143 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1144
1145 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1146 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1147 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1148
1149 if (want_fbs) {
1150 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1151 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1152 if (want_ncq)
1153 new_haltcond &= ~EDMA_ERR_DEV;
1154 else
1155 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1156 }
00f42eab 1157
8e7decdb
ML		 1158 if (new_fiscfg != old_fiscfg)
1159 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1160 if (new_ltmode != old_ltmode)
1161 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1162 if (new_haltcond != old_haltcond)
1163 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1164}
1165
dd2890f6
ML		 1166static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1167{
1168 struct mv_host_priv *hpriv = ap->host->private_data;
1169 u32 old, new;
1170
1171 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1172 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1173 if (want_ncq)
1174 new = old | (1 << 22);
1175 else
1176 new = old & ~(1 << 22);
1177 if (new != old)
1178 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1179}
1180
e12bef50 1181static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1182{
0c58912e 1183 u32 cfg;
e12bef50
ML		 1184 struct mv_port_priv *pp = ap->private_data;
1185 struct mv_host_priv *hpriv = ap->host->private_data;
1186 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1187
1188 /* set up non-NCQ EDMA configuration */
0c58912e 1189 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00f42eab 1190 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
e4e7b892 1191
0c58912e 1192 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1193 cfg |= (1 << 8); /* enab config burst size mask */
1194
dd2890f6 1195 else if (IS_GEN_II(hpriv)) {
e4e7b892 1196 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1197 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1198
dd2890f6 1199 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1200 int want_fbs = sata_pmp_attached(ap);
1201 /*
1202 * Possible future enhancement:
1203 *
1204 * The chip can use FBS with non-NCQ, if we allow it,
1205 * But first we need to have the error handling in place
1206 * for this mode (datasheet section 7.3.15.4.2.3).
1207 * So disallow non-NCQ FBS for now.
1208 */
1209 want_fbs &= want_ncq;
1210
1211 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1212
1213 if (want_fbs) {
1214 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1215 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1216 }
1217
e728eabe
JG		 1218 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1219 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1f398472 1220 if (!IS_SOC(hpriv))
616d4a98
ML		 1221 cfg |= (1 << 18); /* enab early completion */
1222 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1223 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1224 }
1225
72109168
ML		 1226 if (want_ncq) {
1227 cfg |= EDMA_CFG_NCQ;
1228 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1229 } else
1230 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1231
e4e7b892
JG		 1232 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1233}
1234
da2fa9ba
ML		 1235static void mv_port_free_dma_mem(struct ata_port *ap)
1236{
1237 struct mv_host_priv *hpriv = ap->host->private_data;
1238 struct mv_port_priv *pp = ap->private_data;
eb73d558 1239 int tag;
da2fa9ba
ML		 1240
1241 if (pp->crqb) {
1242 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1243 pp->crqb = NULL;
1244 }
1245 if (pp->crpb) {
1246 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1247 pp->crpb = NULL;
1248 }
eb73d558
ML		 1249 /*
1250 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1251 * For later hardware, we have one unique sg_tbl per NCQ tag.
1252 */
1253 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1254 if (pp->sg_tbl[tag]) {
1255 if (tag == 0 || !IS_GEN_I(hpriv))
1256 dma_pool_free(hpriv->sg_tbl_pool,
1257 pp->sg_tbl[tag],
1258 pp->sg_tbl_dma[tag]);
1259 pp->sg_tbl[tag] = NULL;
1260 }
da2fa9ba
ML		 1261 }
1262}
1263
05b308e1
BR		 1264/**
1265 * mv_port_start - Port specific init/start routine.
1266 * @ap: ATA channel to manipulate
1267 *
1268 * Allocate and point to DMA memory, init port private memory,
1269 * zero indices.
1270 *
1271 * LOCKING:
1272 * Inherited from caller.
1273 */
31961943
BR		 1274static int mv_port_start(struct ata_port *ap)
1275{
cca3974e
JG		 1276 struct device *dev = ap->host->dev;
1277 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1278 struct mv_port_priv *pp;
dde20207 1279 int tag;
31961943 1280
24dc5f33 1281 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1282 if (!pp)
24dc5f33 1283 return -ENOMEM;
da2fa9ba 1284 ap->private_data = pp;
31961943 1285
da2fa9ba
ML		 1286 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1287 if (!pp->crqb)
1288 return -ENOMEM;
1289 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1290
da2fa9ba
ML		 1291 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1292 if (!pp->crpb)
1293 goto out_port_free_dma_mem;
1294 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1295
3bd0a70e
ML		 1296 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1297 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1298 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1299 /*
1300 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1301 * For later hardware, we need one unique sg_tbl per NCQ tag.
1302 */
1303 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1304 if (tag == 0 || !IS_GEN_I(hpriv)) {
1305 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1306 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1307 if (!pp->sg_tbl[tag])
1308 goto out_port_free_dma_mem;
1309 } else {
1310 pp->sg_tbl[tag] = pp->sg_tbl[0];
1311 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1312 }
1313 }
31961943 1314 return 0;
da2fa9ba
ML		 1315
1316out_port_free_dma_mem:
1317 mv_port_free_dma_mem(ap);
1318 return -ENOMEM;
31961943
BR		 1319}
1320
05b308e1
BR		 1321/**
1322 * mv_port_stop - Port specific cleanup/stop routine.
1323 * @ap: ATA channel to manipulate
1324 *
1325 * Stop DMA, cleanup port memory.
1326 *
1327 * LOCKING:
cca3974e 1328 * This routine uses the host lock to protect the DMA stop.
05b308e1 1329 */
31961943
BR		 1330static void mv_port_stop(struct ata_port *ap)
1331{
e12bef50 1332 mv_stop_edma(ap);
88e675e1 1333 mv_enable_port_irqs(ap, 0);
da2fa9ba 1334 mv_port_free_dma_mem(ap);
31961943
BR		 1335}
1336
05b308e1
BR		 1337/**
1338 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1339 * @qc: queued command whose SG list to source from
1340 *
1341 * Populate the SG list and mark the last entry.
1342 *
1343 * LOCKING:
1344 * Inherited from caller.
1345 */
6c08772e 1346static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1347{
1348 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1349 struct scatterlist *sg;
3be6cbd7 1350 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1351 unsigned int si;
31961943 1352
eb73d558 1353 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1354 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1355 dma_addr_t addr = sg_dma_address(sg);
1356 u32 sg_len = sg_dma_len(sg);
22374677 1357
4007b493
OJ		 1358 while (sg_len) {
1359 u32 offset = addr & 0xffff;
1360 u32 len = sg_len;
22374677 1361
4007b493
OJ		 1362 if ((offset + sg_len > 0x10000))
1363 len = 0x10000 - offset;
1364
1365 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1366 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1367 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1368
1369 sg_len -= len;
1370 addr += len;
1371
3be6cbd7 1372 last_sg = mv_sg;
4007b493 1373 mv_sg++;
4007b493 1374 }
31961943 1375 }
3be6cbd7
JG		 1376
1377 if (likely(last_sg))
1378 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1379}
1380
5796d1c4 1381static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1382{
559eedad 1383 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1384 (last ? CRQB_CMD_LAST : 0);
559eedad 1385 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1386}
1387
05b308e1
BR		 1388/**
1389 * mv_qc_prep - Host specific command preparation.
1390 * @qc: queued command to prepare
1391 *
1392 * This routine simply redirects to the general purpose routine
1393 * if command is not DMA. Else, it handles prep of the CRQB
1394 * (command request block), does some sanity checking, and calls
1395 * the SG load routine.
1396 *
1397 * LOCKING:
1398 * Inherited from caller.
1399 */
31961943
BR		 1400static void mv_qc_prep(struct ata_queued_cmd *qc)
1401{
1402 struct ata_port *ap = qc->ap;
1403 struct mv_port_priv *pp = ap->private_data;
e1469874 1404 __le16 *cw;
31961943
BR		 1405 struct ata_taskfile *tf;
1406 u16 flags = 0;
a6432436 1407 unsigned in_index;
31961943 1408
138bfdd0
ML		 1409 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1410 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1411 return;
20f733e7 1412
31961943
BR		 1413 /* Fill in command request block
1414 */
e4e7b892 1415 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1416 flags |= CRQB_FLAG_READ;
beec7dbc 1417 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1418 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1419 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1420
bdd4ddde 1421 /* get current queue index from software */
fcfb1f77 1422 in_index = pp->req_idx;
a6432436
ML		 1423
1424 pp->crqb[in_index].sg_addr =
eb73d558 1425 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1426 pp->crqb[in_index].sg_addr_hi =
eb73d558 1427 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1428 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1429
a6432436 1430 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1431 tf = &qc->tf;
1432
1433 /* Sadly, the CRQB cannot accomodate all registers--there are
1434 * only 11 bytes...so we must pick and choose required
1435 * registers based on the command. So, we drop feature and
1436 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 1437 * NCQ. NCQ will drop hob_nsect, which is not needed there
1438 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 1439 */
31961943
BR		 1440 switch (tf->command) {
1441 case ATA_CMD_READ:
1442 case ATA_CMD_READ_EXT:
1443 case ATA_CMD_WRITE:
1444 case ATA_CMD_WRITE_EXT:
c15d85c8 1445 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1446 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1447 break;
31961943
BR		 1448 case ATA_CMD_FPDMA_READ:
1449 case ATA_CMD_FPDMA_WRITE:
8b260248 1450 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1451 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1452 break;
31961943
BR		 1453 default:
1454 /* The only other commands EDMA supports in non-queued and
1455 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1456 * of which are defined/used by Linux. If we get here, this
1457 * driver needs work.
1458 *
1459 * FIXME: modify libata to give qc_prep a return value and
1460 * return error here.
1461 */
1462 BUG_ON(tf->command);
1463 break;
1464 }
1465 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1466 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1467 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1468 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1469 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1470 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1471 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1472 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1473 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1474
e4e7b892
JG		 1475 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1476 return;
1477 mv_fill_sg(qc);
1478}
1479
1480/**
1481 * mv_qc_prep_iie - Host specific command preparation.
1482 * @qc: queued command to prepare
1483 *
1484 * This routine simply redirects to the general purpose routine
1485 * if command is not DMA. Else, it handles prep of the CRQB
1486 * (command request block), does some sanity checking, and calls
1487 * the SG load routine.
1488 *
1489 * LOCKING:
1490 * Inherited from caller.
1491 */
1492static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1493{
1494 struct ata_port *ap = qc->ap;
1495 struct mv_port_priv *pp = ap->private_data;
1496 struct mv_crqb_iie *crqb;
1497 struct ata_taskfile *tf;
a6432436 1498 unsigned in_index;
e4e7b892
JG		 1499 u32 flags = 0;
1500
138bfdd0
ML		 1501 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1502 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1503 return;
1504
e12bef50 1505 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1506 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1507 flags |= CRQB_FLAG_READ;
1508
beec7dbc 1509 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1510 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1511 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1512 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1513
bdd4ddde 1514 /* get current queue index from software */
fcfb1f77 1515 in_index = pp->req_idx;
a6432436
ML		 1516
1517 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1518 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1519 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1520 crqb->flags = cpu_to_le32(flags);
1521
1522 tf = &qc->tf;
1523 crqb->ata_cmd[0] = cpu_to_le32(
1524 (tf->command << 16) |
1525 (tf->feature << 24)
1526 );
1527 crqb->ata_cmd[1] = cpu_to_le32(
1528 (tf->lbal << 0) |
1529 (tf->lbam << 8) |
1530 (tf->lbah << 16) |
1531 (tf->device << 24)
1532 );
1533 crqb->ata_cmd[2] = cpu_to_le32(
1534 (tf->hob_lbal << 0) |
1535 (tf->hob_lbam << 8) |
1536 (tf->hob_lbah << 16) |
1537 (tf->hob_feature << 24)
1538 );
1539 crqb->ata_cmd[3] = cpu_to_le32(
1540 (tf->nsect << 0) |
1541 (tf->hob_nsect << 8)
1542 );
1543
1544 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1545 return;
31961943
BR		 1546 mv_fill_sg(qc);
1547}
1548
05b308e1
BR		 1549/**
1550 * mv_qc_issue - Initiate a command to the host
1551 * @qc: queued command to start
1552 *
1553 * This routine simply redirects to the general purpose routine
1554 * if command is not DMA. Else, it sanity checks our local
1555 * caches of the request producer/consumer indices then enables
1556 * DMA and bumps the request producer index.
1557 *
1558 * LOCKING:
1559 * Inherited from caller.
1560 */
9a3d9eb0 1561static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1562{
c5d3e45a
JG		 1563 struct ata_port *ap = qc->ap;
1564 void __iomem *port_mmio = mv_ap_base(ap);
1565 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1566 u32 in_index;
31961943 1567
138bfdd0
ML		 1568 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1569 (qc->tf.protocol != ATA_PROT_NCQ)) {
c6112bd8
ML		 1570 static int limit_warnings = 10;
1571 /*
1572 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1573 *
1574 * Someday, we might implement special polling workarounds
1575 * for these, but it all seems rather unnecessary since we
1576 * normally use only DMA for commands which transfer more
1577 * than a single block of data.
1578 *
1579 * Much of the time, this could just work regardless.
1580 * So for now, just log the incident, and allow the attempt.
1581 */
c7843e8f 1582 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 1583 --limit_warnings;
1584 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1585 ": attempting PIO w/multiple DRQ: "
1586 "this may fail due to h/w errata\n");
1587 }
17c5aab5
ML		 1588 /*
1589 * We're about to send a non-EDMA capable command to the
31961943
BR		 1590 * port. Turn off EDMA so there won't be problems accessing
1591 * shadow block, etc registers.
1592 */
b562468c 1593 mv_stop_edma(ap);
88e675e1 1594 mv_enable_port_irqs(ap, ERR_IRQ);
e49856d8 1595 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1596 return ata_sff_qc_issue(qc);
31961943
BR		 1597 }
1598
72109168 1599 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1600
fcfb1f77
ML		 1601 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1602 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1603
1604 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1605 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1606 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1607
1608 return 0;
1609}
1610
8f767f8a
ML		 1611static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1612{
1613 struct mv_port_priv *pp = ap->private_data;
1614 struct ata_queued_cmd *qc;
1615
1616 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1617 return NULL;
1618 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1619 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1620 qc = NULL;
1621 return qc;
1622}
1623
29d187bb
ML		 1624static void mv_pmp_error_handler(struct ata_port *ap)
1625{
1626 unsigned int pmp, pmp_map;
1627 struct mv_port_priv *pp = ap->private_data;
1628
1629 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1630 /*
1631 * Perform NCQ error analysis on failed PMPs
1632 * before we freeze the port entirely.
1633 *
1634 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1635 */
1636 pmp_map = pp->delayed_eh_pmp_map;
1637 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1638 for (pmp = 0; pmp_map != 0; pmp++) {
1639 unsigned int this_pmp = (1 << pmp);
1640 if (pmp_map & this_pmp) {
1641 struct ata_link *link = &ap->pmp_link[pmp];
1642 pmp_map &= ~this_pmp;
1643 ata_eh_analyze_ncq_error(link);
1644 }
1645 }
1646 ata_port_freeze(ap);
1647 }
1648 sata_pmp_error_handler(ap);
1649}
1650
4c299ca3
ML		 1651static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1652{
1653 void __iomem *port_mmio = mv_ap_base(ap);
1654
1655 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1656}
1657
4c299ca3
ML		 1658static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1659{
1660 struct ata_eh_info *ehi;
1661 unsigned int pmp;
1662
1663 /*
1664 * Initialize EH info for PMPs which saw device errors
1665 */
1666 ehi = &ap->link.eh_info;
1667 for (pmp = 0; pmp_map != 0; pmp++) {
1668 unsigned int this_pmp = (1 << pmp);
1669 if (pmp_map & this_pmp) {
1670 struct ata_link *link = &ap->pmp_link[pmp];
1671
1672 pmp_map &= ~this_pmp;
1673 ehi = &link->eh_info;
1674 ata_ehi_clear_desc(ehi);
1675 ata_ehi_push_desc(ehi, "dev err");
1676 ehi->err_mask |= AC_ERR_DEV;
1677 ehi->action |= ATA_EH_RESET;
1678 ata_link_abort(link);
1679 }
1680 }
1681}
1682
06aaca3f
ML		 1683static int mv_req_q_empty(struct ata_port *ap)
1684{
1685 void __iomem *port_mmio = mv_ap_base(ap);
1686 u32 in_ptr, out_ptr;
1687
1688 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1689 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1690 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1691 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1692 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1693}
1694
4c299ca3
ML		 1695static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1696{
1697 struct mv_port_priv *pp = ap->private_data;
1698 int failed_links;
1699 unsigned int old_map, new_map;
1700
1701 /*
1702 * Device error during FBS+NCQ operation:
1703 *
1704 * Set a port flag to prevent further I/O being enqueued.
1705 * Leave the EDMA running to drain outstanding commands from this port.
1706 * Perform the post-mortem/EH only when all responses are complete.
1707 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1708 */
1709 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1710 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1711 pp->delayed_eh_pmp_map = 0;
1712 }
1713 old_map = pp->delayed_eh_pmp_map;
1714 new_map = old_map | mv_get_err_pmp_map(ap);
1715
1716 if (old_map != new_map) {
1717 pp->delayed_eh_pmp_map = new_map;
1718 mv_pmp_eh_prep(ap, new_map & ~old_map);
1719 }
c46938cc 1720 failed_links = hweight16(new_map);
4c299ca3
ML		 1721
1722 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1723 "failed_links=%d nr_active_links=%d\n",
1724 __func__, pp->delayed_eh_pmp_map,
1725 ap->qc_active, failed_links,
1726 ap->nr_active_links);
1727
06aaca3f 1728 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 1729 mv_process_crpb_entries(ap, pp);
1730 mv_stop_edma(ap);
1731 mv_eh_freeze(ap);
1732 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1733 return 1; /* handled */
1734 }
1735 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1736 return 1; /* handled */
1737}
1738
1739static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1740{
1741 /*
1742 * Possible future enhancement:
1743 *
1744 * FBS+non-NCQ operation is not yet implemented.
1745 * See related notes in mv_edma_cfg().
1746 *
1747 * Device error during FBS+non-NCQ operation:
1748 *
1749 * We need to snapshot the shadow registers for each failed command.
1750 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1751 */
1752 return 0; /* not handled */
1753}
1754
1755static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1756{
1757 struct mv_port_priv *pp = ap->private_data;
1758
1759 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1760 return 0; /* EDMA was not active: not handled */
1761 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1762 return 0; /* FBS was not active: not handled */
1763
1764 if (!(edma_err_cause & EDMA_ERR_DEV))
1765 return 0; /* non DEV error: not handled */
1766 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1767 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1768 return 0; /* other problems: not handled */
1769
1770 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1771 /*
1772 * EDMA should NOT have self-disabled for this case.
1773 * If it did, then something is wrong elsewhere,
1774 * and we cannot handle it here.
1775 */
1776 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1777 ata_port_printk(ap, KERN_WARNING,
1778 "%s: err_cause=0x%x pp_flags=0x%x\n",
1779 __func__, edma_err_cause, pp->pp_flags);
1780 return 0; /* not handled */
1781 }
1782 return mv_handle_fbs_ncq_dev_err(ap);
1783 } else {
1784 /*
1785 * EDMA should have self-disabled for this case.
1786 * If it did not, then something is wrong elsewhere,
1787 * and we cannot handle it here.
1788 */
1789 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1790 ata_port_printk(ap, KERN_WARNING,
1791 "%s: err_cause=0x%x pp_flags=0x%x\n",
1792 __func__, edma_err_cause, pp->pp_flags);
1793 return 0; /* not handled */
1794 }
1795 return mv_handle_fbs_non_ncq_dev_err(ap);
1796 }
1797 return 0; /* not handled */
1798}
1799
a9010329 1800static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1801{
8f767f8a 1802 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1803 char *when = "idle";
8f767f8a 1804
8f767f8a 1805 ata_ehi_clear_desc(ehi);
a9010329
ML		 1806 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1807 when = "disabled";
1808 } else if (edma_was_enabled) {
1809 when = "EDMA enabled";
8f767f8a
ML		 1810 } else {
1811 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1812 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1813 when = "polling";
8f767f8a 1814 }
a9010329 1815 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1816 ehi->err_mask |= AC_ERR_OTHER;
1817 ehi->action |= ATA_EH_RESET;
1818 ata_port_freeze(ap);
1819}
1820
05b308e1
BR		 1821/**
1822 * mv_err_intr - Handle error interrupts on the port
1823 * @ap: ATA channel to manipulate
1824 *
8d07379d
ML		 1825 * Most cases require a full reset of the chip's state machine,
1826 * which also performs a COMRESET.
1827 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1828 *
1829 * LOCKING:
1830 * Inherited from caller.
1831 */
37b9046a 1832static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1833{
1834 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 1835 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 1836 u32 fis_cause = 0;
bdd4ddde
JG		 1837 struct mv_port_priv *pp = ap->private_data;
1838 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1839 unsigned int action = 0, err_mask = 0;
9af5c9c9 1840 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1841 struct ata_queued_cmd *qc;
1842 int abort = 0;
20f733e7 1843
8d07379d 1844 /*
37b9046a 1845 * Read and clear the SError and err_cause bits.
e4006077
ML		 1846 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1847 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 1848 */
37b9046a
ML		 1849 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1850 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1851
bdd4ddde 1852 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 1853 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1854 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1855 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1856 }
8d07379d 1857 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1858
4c299ca3
ML		 1859 if (edma_err_cause & EDMA_ERR_DEV) {
1860 /*
1861 * Device errors during FIS-based switching operation
1862 * require special handling.
1863 */
1864 if (mv_handle_dev_err(ap, edma_err_cause))
1865 return;
1866 }
1867
37b9046a
ML		 1868 qc = mv_get_active_qc(ap);
1869 ata_ehi_clear_desc(ehi);
1870 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1871 edma_err_cause, pp->pp_flags);
e4006077 1872
c443c500 1873 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 1874 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 1875 if (fis_cause & SATA_FIS_IRQ_AN) {
1876 u32 ec = edma_err_cause &
1877 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1878 sata_async_notification(ap);
1879 if (!ec)
1880 return; /* Just an AN; no need for the nukes */
1881 ata_ehi_push_desc(ehi, "SDB notify");
1882 }
1883 }
bdd4ddde 1884 /*
352fab70 1885 * All generations share these EDMA error cause bits:
bdd4ddde 1886 */
37b9046a 1887 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1888 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1889 action |= ATA_EH_RESET;
1890 ata_ehi_push_desc(ehi, "dev error");
1891 }
bdd4ddde 1892 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1893 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1894 EDMA_ERR_INTRL_PAR)) {
1895 err_mask |= AC_ERR_ATA_BUS;
cf480626 1896 action |= ATA_EH_RESET;
b64bbc39 1897 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1898 }
1899 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1900 ata_ehi_hotplugged(ehi);
1901 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1902 "dev disconnect" : "dev connect");
cf480626 1903 action |= ATA_EH_RESET;
bdd4ddde
JG		 1904 }
1905
352fab70
ML		 1906 /*
1907 * Gen-I has a different SELF_DIS bit,
1908 * different FREEZE bits, and no SERR bit:
1909 */
ee9ccdf7 1910 if (IS_GEN_I(hpriv)) {
bdd4ddde 1911 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1912 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1913 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1914 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1915 }
1916 } else {
1917 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1918 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1919 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1920 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1921 }
bdd4ddde 1922 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1923 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1924 err_mask |= AC_ERR_ATA_BUS;
cf480626 1925 action |= ATA_EH_RESET;
bdd4ddde 1926 }
afb0edd9 1927 }
20f733e7 1928
bdd4ddde
JG		 1929 if (!err_mask) {
1930 err_mask = AC_ERR_OTHER;
cf480626 1931 action |= ATA_EH_RESET;
bdd4ddde
JG		 1932 }
1933
1934 ehi->serror |= serr;
1935 ehi->action |= action;
1936
1937 if (qc)
1938 qc->err_mask |= err_mask;
1939 else
1940 ehi->err_mask |= err_mask;
1941
37b9046a
ML		 1942 if (err_mask == AC_ERR_DEV) {
1943 /*
1944 * Cannot do ata_port_freeze() here,
1945 * because it would kill PIO access,
1946 * which is needed for further diagnosis.
1947 */
1948 mv_eh_freeze(ap);
1949 abort = 1;
1950 } else if (edma_err_cause & eh_freeze_mask) {
1951 /*
1952 * Note to self: ata_port_freeze() calls ata_port_abort()
1953 */
bdd4ddde 1954 ata_port_freeze(ap);
37b9046a
ML		 1955 } else {
1956 abort = 1;
1957 }
1958
1959 if (abort) {
1960 if (qc)
1961 ata_link_abort(qc->dev->link);
1962 else
1963 ata_port_abort(ap);
1964 }
bdd4ddde
JG		 1965}
1966
fcfb1f77
ML		 1967static void mv_process_crpb_response(struct ata_port *ap,
1968 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1969{
1970 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1971
1972 if (qc) {
1973 u8 ata_status;
1974 u16 edma_status = le16_to_cpu(response->flags);
1975 /*
1976 * edma_status from a response queue entry:
1977 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1978 * MSB is saved ATA status from command completion.
1979 */
1980 if (!ncq_enabled) {
1981 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1982 if (err_cause) {
1983 /*
1984 * Error will be seen/handled by mv_err_intr().
1985 * So do nothing at all here.
1986 */
1987 return;
1988 }
1989 }
1990 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 1991 if (!ac_err_mask(ata_status))
1992 ata_qc_complete(qc);
1993 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 1994 } else {
1995 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1996 __func__, tag);
1997 }
1998}
1999
2000static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2001{
2002 void __iomem *port_mmio = mv_ap_base(ap);
2003 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2004 u32 in_index;
bdd4ddde 2005 bool work_done = false;
fcfb1f77 2006 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2007
fcfb1f77 2008 /* Get the hardware queue position index */
bdd4ddde
JG		 2009 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2010 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2011
fcfb1f77
ML		 2012 /* Process new responses from since the last time we looked */
2013 while (in_index != pp->resp_idx) {
6c1153e0 2014 unsigned int tag;
fcfb1f77 2015 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2016
fcfb1f77 2017 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2018
fcfb1f77
ML		 2019 if (IS_GEN_I(hpriv)) {
2020 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2021 tag = ap->link.active_tag;
fcfb1f77
ML		 2022 } else {
2023 /* Gen II/IIE: get command tag from CRPB entry */
2024 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2025 }
fcfb1f77 2026 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2027 work_done = true;
bdd4ddde
JG		 2028 }
2029
352fab70 2030 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2031 if (work_done)
2032 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2033 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2034 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2035}
2036
a9010329
ML		 2037static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2038{
2039 struct mv_port_priv *pp;
2040 int edma_was_enabled;
2041
2042 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2043 mv_unexpected_intr(ap, 0);
2044 return;
2045 }
2046 /*
2047 * Grab a snapshot of the EDMA_EN flag setting,
2048 * so that we have a consistent view for this port,
2049 * even if something we call of our routines changes it.
2050 */
2051 pp = ap->private_data;
2052 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2053 /*
2054 * Process completed CRPB response(s) before other events.
2055 */
2056 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2057 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2058 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2059 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2060 }
2061 /*
2062 * Handle chip-reported errors, or continue on to handle PIO.
2063 */
2064 if (unlikely(port_cause & ERR_IRQ)) {
2065 mv_err_intr(ap);
2066 } else if (!edma_was_enabled) {
2067 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2068 if (qc)
2069 ata_sff_host_intr(ap, qc);
2070 else
2071 mv_unexpected_intr(ap, edma_was_enabled);
2072 }
2073}
2074
05b308e1
BR		 2075/**
2076 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2077 * @host: host specific structure
7368f919 2078 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2079 *
2080 * LOCKING:
2081 * Inherited from caller.
2082 */
7368f919 2083static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2084{
f351b2d6 2085 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2086 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2087 unsigned int handled = 0, port;
20f733e7 2088
a3718c1f 2089 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2090 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2091 unsigned int p, shift, hardport, port_cause;
2092
a3718c1f 2093 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2094 /*
eabd5eb1
ML		 2095 * Each hc within the host has its own hc_irq_cause register,
2096 * where the interrupting ports bits get ack'd.
a3718c1f 2097 */
eabd5eb1
ML		 2098 if (hardport == 0) { /* first port on this hc ? */
2099 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2100 u32 port_mask, ack_irqs;
2101 /*
2102 * Skip this entire hc if nothing pending for any ports
2103 */
2104 if (!hc_cause) {
2105 port += MV_PORTS_PER_HC - 1;
2106 continue;
2107 }
2108 /*
2109 * We don't need/want to read the hc_irq_cause register,
2110 * because doing so hurts performance, and
2111 * main_irq_cause already gives us everything we need.
2112 *
2113 * But we do have to *write* to the hc_irq_cause to ack
2114 * the ports that we are handling this time through.
2115 *
2116 * This requires that we create a bitmap for those
2117 * ports which interrupted us, and use that bitmap
2118 * to ack (only) those ports via hc_irq_cause.
2119 */
2120 ack_irqs = 0;
2121 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2122 if ((port + p) >= hpriv->n_ports)
2123 break;
2124 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2125 if (hc_cause & port_mask)
2126 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2127 }
a3718c1f 2128 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2129 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2130 handled = 1;
2131 }
8f767f8a 2132 /*
a9010329 2133 * Handle interrupts signalled for this port:
8f767f8a 2134 */
a9010329
ML		 2135 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2136 if (port_cause)
2137 mv_port_intr(ap, port_cause);
20f733e7 2138 }
a3718c1f 2139 return handled;
20f733e7
BR		 2140}
2141
a3718c1f 2142static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2143{
02a121da 2144 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2145 struct ata_port *ap;
2146 struct ata_queued_cmd *qc;
2147 struct ata_eh_info *ehi;
2148 unsigned int i, err_mask, printed = 0;
2149 u32 err_cause;
2150
02a121da 2151 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2152
2153 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2154 err_cause);
2155
2156 DPRINTK("All regs @ PCI error\n");
2157 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2158
02a121da 2159 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2160
2161 for (i = 0; i < host->n_ports; i++) {
2162 ap = host->ports[i];
936fd732 2163 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2164 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2165 ata_ehi_clear_desc(ehi);
2166 if (!printed++)
2167 ata_ehi_push_desc(ehi,
2168 "PCI err cause 0x%08x", err_cause);
2169 err_mask = AC_ERR_HOST_BUS;
cf480626 2170 ehi->action = ATA_EH_RESET;
9af5c9c9 2171 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2172 if (qc)
2173 qc->err_mask |= err_mask;
2174 else
2175 ehi->err_mask |= err_mask;
2176
2177 ata_port_freeze(ap);
2178 }
2179 }
a3718c1f 2180 return 1; /* handled */
bdd4ddde
JG		 2181}
2182
05b308e1 2183/**
c5d3e45a 2184 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2185 * @irq: unused
2186 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2187 *
2188 * Read the read only register to determine if any host
2189 * controllers have pending interrupts. If so, call lower level
2190 * routine to handle. Also check for PCI errors which are only
2191 * reported here.
2192 *
8b260248 2193 * LOCKING:
cca3974e 2194 * This routine holds the host lock while processing pending
05b308e1
BR		 2195 * interrupts.
2196 */
7d12e780 2197static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2198{
cca3974e 2199 struct ata_host *host = dev_instance;
f351b2d6 2200 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2201 unsigned int handled = 0;
96e2c487 2202 u32 main_irq_cause, pending_irqs;
20f733e7 2203
646a4da5 2204 spin_lock(&host->lock);
7368f919 2205 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2206 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2207 /*
2208 * Deal with cases where we either have nothing pending, or have read
2209 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2210 */
a44253d2 2211 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2212 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2213 handled = mv_pci_error(host, hpriv->base);
2214 else
a44253d2 2215 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2216 }
cca3974e 2217 spin_unlock(&host->lock);
20f733e7
BR		 2218 return IRQ_RETVAL(handled);
2219}
2220
c9d39130
JG		 2221static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2222{
2223 unsigned int ofs;
2224
2225 switch (sc_reg_in) {
2226 case SCR_STATUS:
2227 case SCR_ERROR:
2228 case SCR_CONTROL:
2229 ofs = sc_reg_in * sizeof(u32);
2230 break;
2231 default:
2232 ofs = 0xffffffffU;
2233 break;
2234 }
2235 return ofs;
2236}
2237
82ef04fb 2238static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 2239{
82ef04fb 2240 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2241 void __iomem *mmio = hpriv->base;
82ef04fb 2242 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2243 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2244
da3dbb17
TH		 2245 if (ofs != 0xffffffffU) {
2246 *val = readl(addr + ofs);
2247 return 0;
2248 } else
2249 return -EINVAL;
c9d39130
JG		 2250}
2251
82ef04fb 2252static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 2253{
82ef04fb 2254 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2255 void __iomem *mmio = hpriv->base;
82ef04fb 2256 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2257 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2258
da3dbb17 2259 if (ofs != 0xffffffffU) {
0d5ff566 2260 writelfl(val, addr + ofs);
da3dbb17
TH		 2261 return 0;
2262 } else
2263 return -EINVAL;
c9d39130
JG		 2264}
2265
7bb3c529 2266static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2267{
7bb3c529 2268 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2269 int early_5080;
2270
44c10138 2271 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2272
2273 if (!early_5080) {
2274 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2275 tmp |= (1 << 0);
2276 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2277 }
2278
7bb3c529 2279 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2280}
2281
2282static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2283{
8e7decdb 2284 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2285}
2286
47c2b677 2287static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2288 void __iomem *mmio)
2289{
c9d39130
JG		 2290 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2291 u32 tmp;
2292
2293 tmp = readl(phy_mmio + MV5_PHY_MODE);
2294
2295 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2296 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2297}
2298
47c2b677 2299static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2300{
522479fb
JG		 2301 u32 tmp;
2302
8e7decdb 2303 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2304
2305 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2306
2307 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2308 tmp |= ~(1 << 0);
2309 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2310}
2311
2a47ce06
JG		 2312static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2313 unsigned int port)
bca1c4eb 2314{
c9d39130
JG		 2315 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2316 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2317 u32 tmp;
2318 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2319
2320 if (fix_apm_sq) {
8e7decdb 2321 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2322 tmp |= (1 << 19);
8e7decdb 2323 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2324
8e7decdb 2325 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2326 tmp &= ~0x3;
2327 tmp |= 0x1;
8e7decdb 2328 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2329 }
2330
2331 tmp = readl(phy_mmio + MV5_PHY_MODE);
2332 tmp &= ~mask;
2333 tmp |= hpriv->signal[port].pre;
2334 tmp |= hpriv->signal[port].amps;
2335 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2336}
2337
c9d39130
JG		 2338
2339#undef ZERO
2340#define ZERO(reg) writel(0, port_mmio + (reg))
2341static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2342 unsigned int port)
2343{
2344 void __iomem *port_mmio = mv_port_base(mmio, port);
2345
e12bef50 2346 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2347
2348 ZERO(0x028); /* command */
2349 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2350 ZERO(0x004); /* timer */
2351 ZERO(0x008); /* irq err cause */
2352 ZERO(0x00c); /* irq err mask */
2353 ZERO(0x010); /* rq bah */
2354 ZERO(0x014); /* rq inp */
2355 ZERO(0x018); /* rq outp */
2356 ZERO(0x01c); /* respq bah */
2357 ZERO(0x024); /* respq outp */
2358 ZERO(0x020); /* respq inp */
2359 ZERO(0x02c); /* test control */
8e7decdb 2360 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2361}
2362#undef ZERO
2363
2364#define ZERO(reg) writel(0, hc_mmio + (reg))
2365static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2366 unsigned int hc)
47c2b677 2367{
c9d39130
JG		 2368 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2369 u32 tmp;
2370
2371 ZERO(0x00c);
2372 ZERO(0x010);
2373 ZERO(0x014);
2374 ZERO(0x018);
2375
2376 tmp = readl(hc_mmio + 0x20);
2377 tmp &= 0x1c1c1c1c;
2378 tmp |= 0x03030303;
2379 writel(tmp, hc_mmio + 0x20);
2380}
2381#undef ZERO
2382
2383static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2384 unsigned int n_hc)
2385{
2386 unsigned int hc, port;
2387
2388 for (hc = 0; hc < n_hc; hc++) {
2389 for (port = 0; port < MV_PORTS_PER_HC; port++)
2390 mv5_reset_hc_port(hpriv, mmio,
2391 (hc * MV_PORTS_PER_HC) + port);
2392
2393 mv5_reset_one_hc(hpriv, mmio, hc);
2394 }
2395
2396 return 0;
47c2b677
JG		 2397}
2398
101ffae2
JG		 2399#undef ZERO
2400#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2401static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2402{
02a121da 2403 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2404 u32 tmp;
2405
8e7decdb 2406 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2407 tmp &= 0xff00ffff;
8e7decdb 2408 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2409
2410 ZERO(MV_PCI_DISC_TIMER);
2411 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2412 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 2413 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2414 ZERO(hpriv->irq_cause_ofs);
2415 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2416 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2417 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2418 ZERO(MV_PCI_ERR_ATTRIBUTE);
2419 ZERO(MV_PCI_ERR_COMMAND);
2420}
2421#undef ZERO
2422
2423static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2424{
2425 u32 tmp;
2426
2427 mv5_reset_flash(hpriv, mmio);
2428
8e7decdb 2429 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2430 tmp &= 0x3;
2431 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2432 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2433}
2434
2435/**
2436 * mv6_reset_hc - Perform the 6xxx global soft reset
2437 * @mmio: base address of the HBA
2438 *
2439 * This routine only applies to 6xxx parts.
2440 *
2441 * LOCKING:
2442 * Inherited from caller.
2443 */
c9d39130
JG		 2444static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2445 unsigned int n_hc)
101ffae2
JG		 2446{
2447 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2448 int i, rc = 0;
2449 u32 t;
2450
2451 /* Following procedure defined in PCI "main command and status
2452 * register" table.
2453 */
2454 t = readl(reg);
2455 writel(t | STOP_PCI_MASTER, reg);
2456
2457 for (i = 0; i < 1000; i++) {
2458 udelay(1);
2459 t = readl(reg);
2dcb407e 2460 if (PCI_MASTER_EMPTY & t)
101ffae2 2461 break;
101ffae2
JG		 2462 }
2463 if (!(PCI_MASTER_EMPTY & t)) {
2464 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2465 rc = 1;
2466 goto done;
2467 }
2468
2469 /* set reset */
2470 i = 5;
2471 do {
2472 writel(t | GLOB_SFT_RST, reg);
2473 t = readl(reg);
2474 udelay(1);
2475 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2476
2477 if (!(GLOB_SFT_RST & t)) {
2478 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2479 rc = 1;
2480 goto done;
2481 }
2482
2483 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2484 i = 5;
2485 do {
2486 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2487 t = readl(reg);
2488 udelay(1);
2489 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2490
2491 if (GLOB_SFT_RST & t) {
2492 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2493 rc = 1;
2494 }
2495done:
2496 return rc;
2497}
2498
47c2b677 2499static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2500 void __iomem *mmio)
2501{
2502 void __iomem *port_mmio;
2503 u32 tmp;
2504
8e7decdb 2505 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2506 if ((tmp & (1 << 0)) == 0) {
47c2b677 2507 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2508 hpriv->signal[idx].pre = 0x1 << 5;
2509 return;
2510 }
2511
2512 port_mmio = mv_port_base(mmio, idx);
2513 tmp = readl(port_mmio + PHY_MODE2);
2514
2515 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2516 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2517}
2518
47c2b677 2519static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2520{
8e7decdb 2521 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2522}
2523
c9d39130 2524static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2525 unsigned int port)
bca1c4eb 2526{
c9d39130
JG		 2527 void __iomem *port_mmio = mv_port_base(mmio, port);
2528
bca1c4eb 2529 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2530 int fix_phy_mode2 =
2531 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2532 int fix_phy_mode4 =
47c2b677 2533 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 2534 u32 m2, m3;
47c2b677
JG		 2535
2536 if (fix_phy_mode2) {
2537 m2 = readl(port_mmio + PHY_MODE2);
2538 m2 &= ~(1 << 16);
2539 m2 |= (1 << 31);
2540 writel(m2, port_mmio + PHY_MODE2);
2541
2542 udelay(200);
2543
2544 m2 = readl(port_mmio + PHY_MODE2);
2545 m2 &= ~((1 << 16) | (1 << 31));
2546 writel(m2, port_mmio + PHY_MODE2);
2547
2548 udelay(200);
2549 }
2550
8c30a8b9
ML		 2551 /*
2552 * Gen-II/IIe PHY_MODE3 errata RM#2:
2553 * Achieves better receiver noise performance than the h/w default:
2554 */
2555 m3 = readl(port_mmio + PHY_MODE3);
2556 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 2557
0388a8c0
ML		 2558 /* Guideline 88F5182 (GL# SATA-S11) */
2559 if (IS_SOC(hpriv))
2560 m3 &= ~0x1c;
2561
bca1c4eb 2562 if (fix_phy_mode4) {
ba069e37
ML		 2563 u32 m4 = readl(port_mmio + PHY_MODE4);
2564 /*
2565 * Enforce reserved-bit restrictions on GenIIe devices only.
2566 * For earlier chipsets, force only the internal config field
2567 * (workaround for errata FEr SATA#10 part 1).
2568 */
8c30a8b9 2569 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 2570 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2571 else
2572 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 2573 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 2574 }
b406c7a6
ML		 2575 /*
2576 * Workaround for 60x1-B2 errata SATA#13:
2577 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2578 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2579 */
2580 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2581
2582 /* Revert values of pre-emphasis and signal amps to the saved ones */
2583 m2 = readl(port_mmio + PHY_MODE2);
2584
2585 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2586 m2 |= hpriv->signal[port].amps;
2587 m2 |= hpriv->signal[port].pre;
47c2b677 2588 m2 &= ~(1 << 16);
bca1c4eb 2589
e4e7b892
JG		 2590 /* according to mvSata 3.6.1, some IIE values are fixed */
2591 if (IS_GEN_IIE(hpriv)) {
2592 m2 &= ~0xC30FF01F;
2593 m2 |= 0x0000900F;
2594 }
2595
bca1c4eb
JG		 2596 writel(m2, port_mmio + PHY_MODE2);
2597}
2598
f351b2d6
SB		 2599/* TODO: use the generic LED interface to configure the SATA Presence */
2600/* & Acitivy LEDs on the board */
2601static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2602 void __iomem *mmio)
2603{
2604 return;
2605}
2606
2607static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2608 void __iomem *mmio)
2609{
2610 void __iomem *port_mmio;
2611 u32 tmp;
2612
2613 port_mmio = mv_port_base(mmio, idx);
2614 tmp = readl(port_mmio + PHY_MODE2);
2615
2616 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2617 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2618}
2619
2620#undef ZERO
2621#define ZERO(reg) writel(0, port_mmio + (reg))
2622static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2623 void __iomem *mmio, unsigned int port)
2624{
2625 void __iomem *port_mmio = mv_port_base(mmio, port);
2626
e12bef50 2627 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2628
2629 ZERO(0x028); /* command */
2630 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2631 ZERO(0x004); /* timer */
2632 ZERO(0x008); /* irq err cause */
2633 ZERO(0x00c); /* irq err mask */
2634 ZERO(0x010); /* rq bah */
2635 ZERO(0x014); /* rq inp */
2636 ZERO(0x018); /* rq outp */
2637 ZERO(0x01c); /* respq bah */
2638 ZERO(0x024); /* respq outp */
2639 ZERO(0x020); /* respq inp */
2640 ZERO(0x02c); /* test control */
8e7decdb 2641 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2642}
2643
2644#undef ZERO
2645
2646#define ZERO(reg) writel(0, hc_mmio + (reg))
2647static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2648 void __iomem *mmio)
2649{
2650 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2651
2652 ZERO(0x00c);
2653 ZERO(0x010);
2654 ZERO(0x014);
2655
2656}
2657
2658#undef ZERO
2659
2660static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2661 void __iomem *mmio, unsigned int n_hc)
2662{
2663 unsigned int port;
2664
2665 for (port = 0; port < hpriv->n_ports; port++)
2666 mv_soc_reset_hc_port(hpriv, mmio, port);
2667
2668 mv_soc_reset_one_hc(hpriv, mmio);
2669
2670 return 0;
2671}
2672
2673static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2674 void __iomem *mmio)
2675{
2676 return;
2677}
2678
2679static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2680{
2681 return;
2682}
2683
8e7decdb 2684static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2685{
8e7decdb 2686 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2687
8e7decdb 2688 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2689 if (want_gen2i)
8e7decdb
ML		 2690 ifcfg |= (1 << 7); /* enable gen2i speed */
2691 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2692}
2693
e12bef50 2694static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2695 unsigned int port_no)
2696{
2697 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2698
8e7decdb
ML		 2699 /*
2700 * The datasheet warns against setting EDMA_RESET when EDMA is active
2701 * (but doesn't say what the problem might be). So we first try
2702 * to disable the EDMA engine before doing the EDMA_RESET operation.
2703 */
0d8be5cb 2704 mv_stop_edma_engine(port_mmio);
8e7decdb 2705 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2706
b67a1064 2707 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2708 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2709 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2710 }
b67a1064 2711 /*
8e7decdb 2712 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2713 * link, and physical layers. It resets all SATA interface registers
2714 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2715 */
8e7decdb 2716 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2717 udelay(25); /* allow reset propagation */
c9d39130
JG		 2718 writelfl(0, port_mmio + EDMA_CMD_OFS);
2719
2720 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2721
ee9ccdf7 2722 if (IS_GEN_I(hpriv))
c9d39130
JG		 2723 mdelay(1);
2724}
2725
e49856d8 2726static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2727{
e49856d8
ML		 2728 if (sata_pmp_supported(ap)) {
2729 void __iomem *port_mmio = mv_ap_base(ap);
2730 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2731 int old = reg & 0xf;
22374677 2732
e49856d8
ML		 2733 if (old != pmp) {
2734 reg = (reg & ~0xf) | pmp;
2735 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2736 }
22374677 2737 }
20f733e7
BR		 2738}
2739
e49856d8
ML		 2740static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2741 unsigned long deadline)
22374677 2742{
e49856d8
ML		 2743 mv_pmp_select(link->ap, sata_srst_pmp(link));
2744 return sata_std_hardreset(link, class, deadline);
2745}
bdd4ddde 2746
e49856d8
ML		 2747static int mv_softreset(struct ata_link *link, unsigned int *class,
2748 unsigned long deadline)
2749{
2750 mv_pmp_select(link->ap, sata_srst_pmp(link));
2751 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2752}
2753
cc0680a5 2754static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2755 unsigned long deadline)
31961943 2756{
cc0680a5 2757 struct ata_port *ap = link->ap;
bdd4ddde 2758 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2759 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2760 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2761 int rc, attempts = 0, extra = 0;
2762 u32 sstatus;
2763 bool online;
31961943 2764
e12bef50 2765 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2766 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2767
0d8be5cb
ML		 2768 /* Workaround for errata FEr SATA#10 (part 2) */
2769 do {
17c5aab5
ML		 2770 const unsigned long *timing =
2771 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2772
17c5aab5
ML		 2773 rc = sata_link_hardreset(link, timing, deadline + extra,
2774 &online, NULL);
9dcffd99 2775 rc = online ? -EAGAIN : rc;
17c5aab5 2776 if (rc)
0d8be5cb 2777 return rc;
0d8be5cb
ML		 2778 sata_scr_read(link, SCR_STATUS, &sstatus);
2779 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2780 /* Force 1.5gb/s link speed and try again */
8e7decdb 2781 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2782 if (time_after(jiffies + HZ, deadline))
2783 extra = HZ; /* only extend it once, max */
2784 }
2785 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2786
17c5aab5 2787 return rc;
bdd4ddde
JG		 2788}
2789
bdd4ddde
JG		 2790static void mv_eh_freeze(struct ata_port *ap)
2791{
1cfd19ae 2792 mv_stop_edma(ap);
c4de573b 2793 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 2794}
2795
2796static void mv_eh_thaw(struct ata_port *ap)
2797{
f351b2d6 2798 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 2799 unsigned int port = ap->port_no;
2800 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 2801 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2802 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 2803 u32 hc_irq_cause;
bdd4ddde 2804
bdd4ddde
JG		 2805 /* clear EDMA errors on this port */
2806 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2807
2808 /* clear pending irq events */
cae6edc3 2809 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1cfd19ae 2810 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 2811
88e675e1 2812 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 2813}
2814
05b308e1
BR		 2815/**
2816 * mv_port_init - Perform some early initialization on a single port.
2817 * @port: libata data structure storing shadow register addresses
2818 * @port_mmio: base address of the port
2819 *
2820 * Initialize shadow register mmio addresses, clear outstanding
2821 * interrupts on the port, and unmask interrupts for the future
2822 * start of the port.
2823 *
2824 * LOCKING:
2825 * Inherited from caller.
2826 */
31961943 2827static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2828{
0d5ff566 2829 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2830 unsigned serr_ofs;
2831
8b260248 2832 /* PIO related setup
31961943
BR		 2833 */
2834 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2835 port->error_addr =
31961943
BR		 2836 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2837 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2838 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2839 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2840 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2841 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2842 port->status_addr =
31961943
BR		 2843 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2844 /* special case: control/altstatus doesn't have ATA_REG_ address */
2845 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2846
2847 /* unused: */
8d9db2d2 2848 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2849
31961943
BR		 2850 /* Clear any currently outstanding port interrupt conditions */
2851 serr_ofs = mv_scr_offset(SCR_ERROR);
2852 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2853 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2854
646a4da5
ML		 2855 /* unmask all non-transient EDMA error interrupts */
2856 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2857
8b260248 2858 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2859 readl(port_mmio + EDMA_CFG_OFS),
2860 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2861 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2862}
2863
616d4a98
ML		 2864static unsigned int mv_in_pcix_mode(struct ata_host *host)
2865{
2866 struct mv_host_priv *hpriv = host->private_data;
2867 void __iomem *mmio = hpriv->base;
2868 u32 reg;
2869
1f398472 2870 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98
ML		 2871 return 0; /* not PCI-X capable */
2872 reg = readl(mmio + MV_PCI_MODE_OFS);
2873 if ((reg & MV_PCI_MODE_MASK) == 0)
2874 return 0; /* conventional PCI mode */
2875 return 1; /* chip is in PCI-X mode */
2876}
2877
2878static int mv_pci_cut_through_okay(struct ata_host *host)
2879{
2880 struct mv_host_priv *hpriv = host->private_data;
2881 void __iomem *mmio = hpriv->base;
2882 u32 reg;
2883
2884 if (!mv_in_pcix_mode(host)) {
2885 reg = readl(mmio + PCI_COMMAND_OFS);
2886 if (reg & PCI_COMMAND_MRDTRIG)
2887 return 0; /* not okay */
2888 }
2889 return 1; /* okay */
2890}
2891
4447d351 2892static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2893{
4447d351
TH		 2894 struct pci_dev *pdev = to_pci_dev(host->dev);
2895 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2896 u32 hp_flags = hpriv->hp_flags;
2897
5796d1c4 2898 switch (board_idx) {
47c2b677
JG		 2899 case chip_5080:
2900 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2901 hp_flags |= MV_HP_GEN_I;
47c2b677 2902
44c10138 2903 switch (pdev->revision) {
47c2b677
JG		 2904 case 0x1:
2905 hp_flags |= MV_HP_ERRATA_50XXB0;
2906 break;
2907 case 0x3:
2908 hp_flags |= MV_HP_ERRATA_50XXB2;
2909 break;
2910 default:
2911 dev_printk(KERN_WARNING, &pdev->dev,
2912 "Applying 50XXB2 workarounds to unknown rev\n");
2913 hp_flags |= MV_HP_ERRATA_50XXB2;
2914 break;
2915 }
2916 break;
2917
bca1c4eb
JG		 2918 case chip_504x:
2919 case chip_508x:
47c2b677 2920 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2921 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2922
44c10138 2923 switch (pdev->revision) {
47c2b677
JG		 2924 case 0x0:
2925 hp_flags |= MV_HP_ERRATA_50XXB0;
2926 break;
2927 case 0x3:
2928 hp_flags |= MV_HP_ERRATA_50XXB2;
2929 break;
2930 default:
2931 dev_printk(KERN_WARNING, &pdev->dev,
2932 "Applying B2 workarounds to unknown rev\n");
2933 hp_flags |= MV_HP_ERRATA_50XXB2;
2934 break;
bca1c4eb
JG		 2935 }
2936 break;
2937
2938 case chip_604x:
2939 case chip_608x:
47c2b677 2940 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2941 hp_flags |= MV_HP_GEN_II;
47c2b677 2942
44c10138 2943 switch (pdev->revision) {
47c2b677
JG		 2944 case 0x7:
2945 hp_flags |= MV_HP_ERRATA_60X1B2;
2946 break;
2947 case 0x9:
2948 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2949 break;
2950 default:
2951 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2952 "Applying B2 workarounds to unknown rev\n");
2953 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2954 break;
2955 }
2956 break;
2957
e4e7b892 2958 case chip_7042:
616d4a98 2959 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2960 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2961 (pdev->device == 0x2300 || pdev->device == 0x2310))
2962 {
4e520033
ML		 2963 /*
2964 * Highpoint RocketRAID PCIe 23xx series cards:
2965 *
2966 * Unconfigured drives are treated as "Legacy"
2967 * by the BIOS, and it overwrites sector 8 with
2968 * a "Lgcy" metadata block prior to Linux boot.
2969 *
2970 * Configured drives (RAID or JBOD) leave sector 8
2971 * alone, but instead overwrite a high numbered
2972 * sector for the RAID metadata. This sector can
2973 * be determined exactly, by truncating the physical
2974 * drive capacity to a nice even GB value.
2975 *
2976 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2977 *
2978 * Warn the user, lest they think we're just buggy.
2979 */
2980 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2981 " BIOS CORRUPTS DATA on all attached drives,"
2982 " regardless of if/how they are configured."
2983 " BEWARE!\n");
2984 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2985 " use sectors 8-9 on \"Legacy\" drives,"
2986 " and avoid the final two gigabytes on"
2987 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2988 }
8e7decdb 2989 /* drop through */
e4e7b892
JG		 2990 case chip_6042:
2991 hpriv->ops = &mv6xxx_ops;
e4e7b892 2992 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2993 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2994 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2995
44c10138 2996 switch (pdev->revision) {
5cf73bfb 2997 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 2998 hp_flags |= MV_HP_ERRATA_60X1C0;
2999 break;
3000 default:
3001 dev_printk(KERN_WARNING, &pdev->dev,
3002 "Applying 60X1C0 workarounds to unknown rev\n");
3003 hp_flags |= MV_HP_ERRATA_60X1C0;
3004 break;
3005 }
3006 break;
f351b2d6
SB		 3007 case chip_soc:
3008 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3009 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3010 MV_HP_ERRATA_60X1C0;
f351b2d6 3011 break;
e4e7b892 3012
bca1c4eb 3013 default:
f351b2d6 3014 dev_printk(KERN_ERR, host->dev,
5796d1c4 3015 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3016 return 1;
3017 }
3018
3019 hpriv->hp_flags = hp_flags;
02a121da
ML		 3020 if (hp_flags & MV_HP_PCIE) {
3021 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3022 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3023 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3024 } else {
3025 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3026 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3027 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3028 }
bca1c4eb
JG		 3029
3030 return 0;
3031}
3032
05b308e1 3033/**
47c2b677 3034 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3035 * @host: ATA host to initialize
3036 * @board_idx: controller index
05b308e1
BR		 3037 *
3038 * If possible, do an early global reset of the host. Then do
3039 * our port init and clear/unmask all/relevant host interrupts.
3040 *
3041 * LOCKING:
3042 * Inherited from caller.
3043 */
4447d351 3044static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3045{
3046 int rc = 0, n_hc, port, hc;
4447d351 3047 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3048 void __iomem *mmio = hpriv->base;
47c2b677 3049
4447d351 3050 rc = mv_chip_id(host, board_idx);
bca1c4eb 3051 if (rc)
352fab70 3052 goto done;
f351b2d6 3053
1f398472 3054 if (IS_SOC(hpriv)) {
7368f919
ML		 3055 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3056 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
1f398472
ML		 3057 } else {
3058 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3059 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3060 }
352fab70
ML		 3061
3062 /* global interrupt mask: 0 == mask everything */
c4de573b 3063 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3064
4447d351 3065 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3066
4447d351 3067 for (port = 0; port < host->n_ports; port++)
47c2b677 3068 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3069
c9d39130 3070 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3071 if (rc)
20f733e7 3072 goto done;
20f733e7 3073
522479fb 3074 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3075 hpriv->ops->reset_bus(host, mmio);
47c2b677 3076 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3077
4447d351 3078 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3079 struct ata_port *ap = host->ports[port];
2a47ce06 3080 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3081
3082 mv_port_init(&ap->ioaddr, port_mmio);
3083
7bb3c529 3084#ifdef CONFIG_PCI
1f398472 3085 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3086 unsigned int offset = port_mmio - mmio;
3087 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3088 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3089 }
7bb3c529 3090#endif
20f733e7
BR		 3091 }
3092
3093 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3094 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3095
3096 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3097 "(before clear)=0x%08x\n", hc,
3098 readl(hc_mmio + HC_CFG_OFS),
3099 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3100
3101 /* Clear any currently outstanding hc interrupt conditions */
3102 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3103 }
3104
1f398472 3105 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3106 /* Clear any currently outstanding host interrupt conditions */
3107 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3108
f351b2d6
SB		 3109 /* and unmask interrupt generation for host regs */
3110 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2
ML		 3111
3112 /*
3113 * enable only global host interrupts for now.
3114 * The per-port interrupts get done later as ports are set up.
3115 */
c4de573b 3116 mv_set_main_irq_mask(host, 0, PCI_ERR);
f351b2d6
SB		 3117 }
3118done:
3119 return rc;
3120}
fb621e2f 3121
fbf14e2f
BB		 3122static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3123{
3124 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3125 MV_CRQB_Q_SZ, 0);
3126 if (!hpriv->crqb_pool)
3127 return -ENOMEM;
3128
3129 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3130 MV_CRPB_Q_SZ, 0);
3131 if (!hpriv->crpb_pool)
3132 return -ENOMEM;
3133
3134 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3135 MV_SG_TBL_SZ, 0);
3136 if (!hpriv->sg_tbl_pool)
3137 return -ENOMEM;
3138
3139 return 0;
3140}
3141
15a32632
LB		 3142static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3143 struct mbus_dram_target_info *dram)
3144{
3145 int i;
3146
3147 for (i = 0; i < 4; i++) {
3148 writel(0, hpriv->base + WINDOW_CTRL(i));
3149 writel(0, hpriv->base + WINDOW_BASE(i));
3150 }
3151
3152 for (i = 0; i < dram->num_cs; i++) {
3153 struct mbus_dram_window *cs = dram->cs + i;
3154
3155 writel(((cs->size - 1) & 0xffff0000) |
3156 (cs->mbus_attr << 8) |
3157 (dram->mbus_dram_target_id << 4) | 1,
3158 hpriv->base + WINDOW_CTRL(i));
3159 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3160 }
3161}
3162
f351b2d6
SB		 3163/**
3164 * mv_platform_probe - handle a positive probe of an soc Marvell
3165 * host
3166 * @pdev: platform device found
3167 *
3168 * LOCKING:
3169 * Inherited from caller.
3170 */
3171static int mv_platform_probe(struct platform_device *pdev)
3172{
3173 static int printed_version;
3174 const struct mv_sata_platform_data *mv_platform_data;
3175 const struct ata_port_info *ppi[] =
3176 { &mv_port_info[chip_soc], NULL };
3177 struct ata_host *host;
3178 struct mv_host_priv *hpriv;
3179 struct resource *res;
3180 int n_ports, rc;
20f733e7 3181
f351b2d6
SB		 3182 if (!printed_version++)
3183 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3184
f351b2d6
SB		 3185 /*
3186 * Simple resource validation ..
3187 */
3188 if (unlikely(pdev->num_resources != 2)) {
3189 dev_err(&pdev->dev, "invalid number of resources\n");
3190 return -EINVAL;
3191 }
3192
3193 /*
3194 * Get the register base first
3195 */
3196 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3197 if (res == NULL)
3198 return -EINVAL;
3199
3200 /* allocate host */
3201 mv_platform_data = pdev->dev.platform_data;
3202 n_ports = mv_platform_data->n_ports;
3203
3204 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3205 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3206
3207 if (!host || !hpriv)
3208 return -ENOMEM;
3209 host->private_data = hpriv;
3210 hpriv->n_ports = n_ports;
3211
3212 host->iomap = NULL;
f1cb0ea1
SB		 3213 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3214 res->end - res->start + 1);
f351b2d6
SB		 3215 hpriv->base -= MV_SATAHC0_REG_BASE;
3216
15a32632
LB		 3217 /*
3218 * (Re-)program MBUS remapping windows if we are asked to.
3219 */
3220 if (mv_platform_data->dram != NULL)
3221 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3222
fbf14e2f
BB		 3223 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3224 if (rc)
3225 return rc;
3226
f351b2d6
SB		 3227 /* initialize adapter */
3228 rc = mv_init_host(host, chip_soc);
3229 if (rc)
3230 return rc;
3231
3232 dev_printk(KERN_INFO, &pdev->dev,
3233 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3234 host->n_ports);
3235
3236 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3237 IRQF_SHARED, &mv6_sht);
3238}
3239
3240/*
3241 *
3242 * mv_platform_remove - unplug a platform interface
3243 * @pdev: platform device
3244 *
3245 * A platform bus SATA device has been unplugged. Perform the needed
3246 * cleanup. Also called on module unload for any active devices.
3247 */
3248static int __devexit mv_platform_remove(struct platform_device *pdev)
3249{
3250 struct device *dev = &pdev->dev;
3251 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3252
3253 ata_host_detach(host);
f351b2d6 3254 return 0;
20f733e7
BR		 3255}
3256
f351b2d6
SB		 3257static struct platform_driver mv_platform_driver = {
3258 .probe = mv_platform_probe,
3259 .remove = __devexit_p(mv_platform_remove),
3260 .driver = {
3261 .name = DRV_NAME,
3262 .owner = THIS_MODULE,
3263 },
3264};
3265
3266
7bb3c529 3267#ifdef CONFIG_PCI
f351b2d6
SB		 3268static int mv_pci_init_one(struct pci_dev *pdev,
3269 const struct pci_device_id *ent);
3270
7bb3c529
SB		 3271
3272static struct pci_driver mv_pci_driver = {
3273 .name = DRV_NAME,
3274 .id_table = mv_pci_tbl,
f351b2d6 3275 .probe = mv_pci_init_one,
7bb3c529
SB		 3276 .remove = ata_pci_remove_one,
3277};
3278
3279/*
3280 * module options
3281 */
3282static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3283
3284
3285/* move to PCI layer or libata core? */
3286static int pci_go_64(struct pci_dev *pdev)
3287{
3288 int rc;
3289
3290 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3291 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3292 if (rc) {
3293 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3294 if (rc) {
3295 dev_printk(KERN_ERR, &pdev->dev,
3296 "64-bit DMA enable failed\n");
3297 return rc;
3298 }
3299 }
3300 } else {
3301 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3302 if (rc) {
3303 dev_printk(KERN_ERR, &pdev->dev,
3304 "32-bit DMA enable failed\n");
3305 return rc;
3306 }
3307 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3308 if (rc) {
3309 dev_printk(KERN_ERR, &pdev->dev,
3310 "32-bit consistent DMA enable failed\n");
3311 return rc;
3312 }
3313 }
3314
3315 return rc;
3316}
3317
05b308e1
BR		 3318/**
3319 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3320 * @host: ATA host to print info about
05b308e1
BR		 3321 *
3322 * FIXME: complete this.
3323 *
3324 * LOCKING:
3325 * Inherited from caller.
3326 */
4447d351 3327static void mv_print_info(struct ata_host *host)
31961943 3328{
4447d351
TH		 3329 struct pci_dev *pdev = to_pci_dev(host->dev);
3330 struct mv_host_priv *hpriv = host->private_data;
44c10138 3331 u8 scc;
c1e4fe71 3332 const char *scc_s, *gen;
31961943
BR		 3333
3334 /* Use this to determine the HW stepping of the chip so we know
3335 * what errata to workaround
3336 */
31961943
BR		 3337 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3338 if (scc == 0)
3339 scc_s = "SCSI";
3340 else if (scc == 0x01)
3341 scc_s = "RAID";
3342 else
c1e4fe71
JG		 3343 scc_s = "?";
3344
3345 if (IS_GEN_I(hpriv))
3346 gen = "I";
3347 else if (IS_GEN_II(hpriv))
3348 gen = "II";
3349 else if (IS_GEN_IIE(hpriv))
3350 gen = "IIE";
3351 else
3352 gen = "?";
31961943 3353
a9524a76 3354 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3355 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3356 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3357 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3358}
3359
05b308e1 3360/**
f351b2d6 3361 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3362 * @pdev: PCI device found
3363 * @ent: PCI device ID entry for the matched host
3364 *
3365 * LOCKING:
3366 * Inherited from caller.
3367 */
f351b2d6
SB		 3368static int mv_pci_init_one(struct pci_dev *pdev,
3369 const struct pci_device_id *ent)
20f733e7 3370{
2dcb407e 3371 static int printed_version;
20f733e7 3372 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3373 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3374 struct ata_host *host;
3375 struct mv_host_priv *hpriv;
3376 int n_ports, rc;
20f733e7 3377
a9524a76
JG		 3378 if (!printed_version++)
3379 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3380
4447d351
TH		 3381 /* allocate host */
3382 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3383
3384 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3385 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3386 if (!host || !hpriv)
3387 return -ENOMEM;
3388 host->private_data = hpriv;
f351b2d6 3389 hpriv->n_ports = n_ports;
4447d351
TH		 3390
3391 /* acquire resources */
24dc5f33
TH		 3392 rc = pcim_enable_device(pdev);
3393 if (rc)
20f733e7 3394 return rc;
20f733e7 3395
0d5ff566
TH		 3396 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3397 if (rc == -EBUSY)
24dc5f33 3398 pcim_pin_device(pdev);
0d5ff566 3399 if (rc)
24dc5f33 3400 return rc;
4447d351 3401 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3402 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3403
d88184fb
JG		 3404 rc = pci_go_64(pdev);
3405 if (rc)
3406 return rc;
3407
da2fa9ba
ML		 3408 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3409 if (rc)
3410 return rc;
3411
20f733e7 3412 /* initialize adapter */
4447d351 3413 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3414 if (rc)
3415 return rc;
20f733e7 3416
31961943 3417 /* Enable interrupts */
6a59dcf8 3418 if (msi && pci_enable_msi(pdev))
31961943 3419 pci_intx(pdev, 1);
20f733e7 3420
31961943 3421 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3422 mv_print_info(host);
20f733e7 3423
4447d351 3424 pci_set_master(pdev);
ea8b4db9 3425 pci_try_set_mwi(pdev);
4447d351 3426 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3427 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3428}
7bb3c529 3429#endif
20f733e7 3430
f351b2d6
SB		 3431static int mv_platform_probe(struct platform_device *pdev);
3432static int __devexit mv_platform_remove(struct platform_device *pdev);
3433
20f733e7
BR		 3434static int __init mv_init(void)
3435{
7bb3c529
SB		 3436 int rc = -ENODEV;
3437#ifdef CONFIG_PCI
3438 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3439 if (rc < 0)
3440 return rc;
3441#endif
3442 rc = platform_driver_register(&mv_platform_driver);
3443
3444#ifdef CONFIG_PCI
3445 if (rc < 0)
3446 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3447#endif
3448 return rc;
20f733e7
BR		 3449}
3450
3451static void __exit mv_exit(void)
3452{
7bb3c529 3453#ifdef CONFIG_PCI
20f733e7 3454 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3455#endif
f351b2d6 3456 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3457}
3458
3459MODULE_AUTHOR("Brett Russ");
3460MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3461MODULE_LICENSE("GPL");
3462MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3463MODULE_VERSION(DRV_VERSION);
17c5aab5 3464MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3465
7bb3c529 3466#ifdef CONFIG_PCI
ddef9bb3
JG		 3467module_param(msi, int, 0444);
3468MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3469#endif
ddef9bb3 3470
20f733e7
BR		 3471module_init(mv_init);
3472module_exit(mv_exit);
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