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libata-sff: clean up BMDMA initialization
[net-next-2.6.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
40f21b11 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7 7 *
40f21b11
ML		 8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
20f733e7
BR		 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
4a05e209 28/*
85afb934
ML		 29 * sata_mv TODO list:
30 *
85afb934
ML		 31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
2b748a0a 33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
85afb934
ML		 34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
4a05e209 42
65ad7fef
ML		 43/*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
20f733e7
BR		 52#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/pci.h>
55#include <linux/init.h>
56#include <linux/blkdev.h>
57#include <linux/delay.h>
58#include <linux/interrupt.h>
8d8b6004 59#include <linux/dmapool.h>
20f733e7 60#include <linux/dma-mapping.h>
a9524a76 61#include <linux/device.h>
c77a2f4e 62#include <linux/clk.h>
f351b2d6
SB		 63#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
15a32632 65#include <linux/mbus.h>
c46938cc 66#include <linux/bitops.h>
5a0e3ad6 67#include <linux/gfp.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
cae5a29d 74#define DRV_VERSION "1.28"
20f733e7 75
40f21b11
ML		 76/*
77 * module options
78 */
79
80static int msi;
81#ifdef CONFIG_PCI
82module_param(msi, int, S_IRUGO);
83MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84#endif
85
2b748a0a
ML		 86static int irq_coalescing_io_count;
87module_param(irq_coalescing_io_count, int, S_IRUGO);
88MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
90
91static int irq_coalescing_usecs;
92module_param(irq_coalescing_usecs, int, S_IRUGO);
93MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
95
20f733e7
BR		 96enum {
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104
2b748a0a
ML		 105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109
20f733e7 110 MV_PCI_REG_BASE = 0,
615ab953 111
2b748a0a
ML		 112 /*
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
115 *
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 */
cae5a29d
ML		 119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
2b748a0a
ML		 121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122
cae5a29d
ML		 123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
2b748a0a
ML		 125
126 /*
127 * Registers for the (unused here) transaction coalescing feature:
128 */
cae5a29d
ML		 129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
2b748a0a 131
cae5a29d
ML		 132 SATAHC0_REG_BASE = 0x20000,
133 FLASH_CTL = 0x1046c,
134 GPIO_PORT_CTL = 0x104f0,
135 RESET_CFG = 0x180d8,
20f733e7
BR		 136
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141
31961943
BR		 142 MV_MAX_Q_DEPTH = 32,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 */
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 151 MV_MAX_SG_CT = 256,
31961943 152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 153
352fab70 154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 155 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 159
160 /* Host Flags */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
7bb3c529 162
c5d3e45a 163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91b1a84c 164 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
ad3aef51 165
91b1a84c 166 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 167
40f21b11
ML		 168 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
169 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
91b1a84c
ML		 170
171 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 172
31961943
BR		 173 CRQB_FLAG_READ = (1 << 0),
174 CRQB_TAG_SHIFT = 1,
c5d3e45a 175 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 176 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 177 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 178 CRQB_CMD_ADDR_SHIFT = 8,
179 CRQB_CMD_CS = (0x2 << 11),
180 CRQB_CMD_LAST = (1 << 15),
181
182 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 183 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
184 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 185
186 EPRD_FLAG_END_OF_TBL = (1 << 31),
187
20f733e7
BR		 188 /* PCI interface registers */
189
cae5a29d
ML		 190 MV_PCI_COMMAND = 0xc00,
191 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
192 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 193
cae5a29d 194 PCI_MAIN_CMD_STS = 0xd30,
20f733e7
BR		 195 STOP_PCI_MASTER = (1 << 2),
196 PCI_MASTER_EMPTY = (1 << 3),
197 GLOB_SFT_RST = (1 << 4),
198
cae5a29d 199 MV_PCI_MODE = 0xd00,
8e7decdb
ML		 200 MV_PCI_MODE_MASK = 0x30,
201
522479fb
JG		 202 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
203 MV_PCI_DISC_TIMER = 0xd04,
204 MV_PCI_MSI_TRIGGER = 0xc38,
205 MV_PCI_SERR_MASK = 0xc28,
cae5a29d 206 MV_PCI_XBAR_TMOUT = 0x1d04,
522479fb
JG		 207 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
208 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
209 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
210 MV_PCI_ERR_COMMAND = 0x1d50,
211
cae5a29d
ML		 212 PCI_IRQ_CAUSE = 0x1d58,
213 PCI_IRQ_MASK = 0x1d5c,
20f733e7
BR		 214 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
215
cae5a29d
ML		 216 PCIE_IRQ_CAUSE = 0x1900,
217 PCIE_IRQ_MASK = 0x1910,
646a4da5 218 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 219
7368f919 220 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
cae5a29d
ML		 221 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
222 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
223 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
224 SOC_HC_MAIN_IRQ_MASK = 0x20024,
40f21b11
ML		 225 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
226 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
20f733e7
BR		 227 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
228 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
2b748a0a
ML		 229 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
230 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
20f733e7 231 PCI_ERR = (1 << 18),
40f21b11
ML		 232 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
233 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
234 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
235 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
236 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
20f733e7
BR		 237 GPIO_INT = (1 << 22),
238 SELF_INT = (1 << 23),
239 TWSI_INT = (1 << 24),
240 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 241 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 242 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 243
244 /* SATAHC registers */
cae5a29d 245 HC_CFG = 0x00,
20f733e7 246
cae5a29d 247 HC_IRQ_CAUSE = 0x14,
352fab70
ML		 248 DMA_IRQ = (1 << 0), /* shift by port # */
249 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 250 DEV_IRQ = (1 << 8), /* shift by port # */
251
2b748a0a
ML		 252 /*
253 * Per-HC (Host-Controller) interrupt coalescing feature.
254 * This is present on all chip generations.
255 *
256 * Coalescing defers the interrupt until either the IO_THRESHOLD
257 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
258 */
cae5a29d
ML		 259 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
260 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
2b748a0a 261
cae5a29d 262 SOC_LED_CTRL = 0x2c,
000b344f
ML		 263 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
264 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
265 /* with dev activity LED */
266
20f733e7 267 /* Shadow block registers */
cae5a29d
ML		 268 SHD_BLK = 0x100,
269 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
20f733e7
BR		 270
271 /* SATA registers */
cae5a29d
ML		 272 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
273 SATA_ACTIVE = 0x350,
274 FIS_IRQ_CAUSE = 0x364,
275 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
17c5aab5 276
cae5a29d 277 LTMODE = 0x30c, /* requires read-after-write */
17c5aab5
ML		 278 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
279
cae5a29d 280 PHY_MODE2 = 0x330,
47c2b677 281 PHY_MODE3 = 0x310,
cae5a29d
ML		 282
283 PHY_MODE4 = 0x314, /* requires read-after-write */
ba069e37
ML		 284 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
285 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
286 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
287 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
288
cae5a29d
ML		 289 SATA_IFCTL = 0x344,
290 SATA_TESTCTL = 0x348,
291 SATA_IFSTAT = 0x34c,
292 VENDOR_UNIQUE_FIS = 0x35c,
17c5aab5 293
cae5a29d 294 FISCFG = 0x360,
8e7decdb
ML		 295 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
296 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 297
29b7e43c
MM		 298 PHY_MODE9_GEN2 = 0x398,
299 PHY_MODE9_GEN1 = 0x39c,
300 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
301
c9d39130 302 MV5_PHY_MODE = 0x74,
cae5a29d
ML		 303 MV5_LTMODE = 0x30,
304 MV5_PHY_CTL = 0x0C,
305 SATA_IFCFG = 0x050,
bca1c4eb
JG		 306
307 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 308
309 /* Port registers */
cae5a29d 310 EDMA_CFG = 0,
0c58912e
ML		 311 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
312 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
313 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
314 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
315 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 316 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
317 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7 318
cae5a29d
ML		 319 EDMA_ERR_IRQ_CAUSE = 0x8,
320 EDMA_ERR_IRQ_MASK = 0xc,
6c1153e0
JG		 321 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
322 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
323 EDMA_ERR_DEV = (1 << 2), /* device error */
324 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
325 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
326 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 327 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
328 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 329 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 330 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 331 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
332 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
333 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
334 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 335
6c1153e0 336 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 337 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
338 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
339 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
340 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
341
6c1153e0 342 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 343
6c1153e0 344 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 345 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
346 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
347 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
348 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
349 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
350
6c1153e0 351 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 352
6c1153e0 353 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 354 EDMA_ERR_OVERRUN_5 = (1 << 5),
355 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 356
357 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
358 EDMA_ERR_LNK_CTRL_RX_1 |
359 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 360 EDMA_ERR_LNK_CTRL_TX,
646a4da5 361
bdd4ddde
JG		 362 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
363 EDMA_ERR_PRD_PAR |
364 EDMA_ERR_DEV_DCON |
365 EDMA_ERR_DEV_CON |
366 EDMA_ERR_SERR |
367 EDMA_ERR_SELF_DIS |
6c1153e0 368 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 369 EDMA_ERR_CRPB_PAR |
370 EDMA_ERR_INTRL_PAR |
371 EDMA_ERR_IORDY |
372 EDMA_ERR_LNK_CTRL_RX_2 |
373 EDMA_ERR_LNK_DATA_RX |
374 EDMA_ERR_LNK_DATA_TX |
375 EDMA_ERR_TRANS_PROTO,
e12bef50 376
bdd4ddde
JG		 377 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
378 EDMA_ERR_PRD_PAR |
379 EDMA_ERR_DEV_DCON |
380 EDMA_ERR_DEV_CON |
381 EDMA_ERR_OVERRUN_5 |
382 EDMA_ERR_UNDERRUN_5 |
383 EDMA_ERR_SELF_DIS_5 |
6c1153e0 384 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 385 EDMA_ERR_CRPB_PAR |
386 EDMA_ERR_INTRL_PAR |
387 EDMA_ERR_IORDY,
20f733e7 388
cae5a29d
ML		 389 EDMA_REQ_Q_BASE_HI = 0x10,
390 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
31961943 391
cae5a29d 392 EDMA_REQ_Q_OUT_PTR = 0x18,
31961943
BR		 393 EDMA_REQ_Q_PTR_SHIFT = 5,
394
cae5a29d
ML		 395 EDMA_RSP_Q_BASE_HI = 0x1c,
396 EDMA_RSP_Q_IN_PTR = 0x20,
397 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
31961943
BR		 398 EDMA_RSP_Q_PTR_SHIFT = 3,
399
cae5a29d 400 EDMA_CMD = 0x28, /* EDMA command register */
0ea9e179
JG		 401 EDMA_EN = (1 << 0), /* enable EDMA */
402 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 403 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
404
cae5a29d 405 EDMA_STATUS = 0x30, /* EDMA engine status */
8e7decdb
ML		 406 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
407 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 408
cae5a29d
ML		 409 EDMA_IORDY_TMOUT = 0x34,
410 EDMA_ARB_CFG = 0x38,
8e7decdb 411
cae5a29d
ML		 412 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
413 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
da14265e 414
cae5a29d
ML		 415 BMDMA_CMD = 0x224, /* bmdma command register */
416 BMDMA_STATUS = 0x228, /* bmdma status register */
417 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
418 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
da14265e 419
31961943
BR		 420 /* Host private flags (hp_flags) */
421 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 422 MV_HP_ERRATA_50XXB0 = (1 << 1),
423 MV_HP_ERRATA_50XXB2 = (1 << 2),
424 MV_HP_ERRATA_60X1B2 = (1 << 3),
425 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 426 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
427 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
428 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 429 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 430 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 431 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
000b344f 432 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
20f733e7 433
31961943 434 /* Port private flags (pp_flags) */
0ea9e179 435 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 436 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 437 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 438 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
d16ab3f6 439 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
20f733e7
BR		 440};
441
ee9ccdf7
JG		 442#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
443#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 444#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 445#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 446#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 447
15a32632
LB		 448#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
449#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
450
095fec88 451enum {
baf14aa1
JG		 452 /* DMA boundary 0xffff is required by the s/g splitting
453 * we need on /length/ in mv_fill-sg().
454 */
455 MV_DMA_BOUNDARY = 0xffffU,
095fec88 456
0ea9e179
JG		 457 /* mask of register bits containing lower 32 bits
458 * of EDMA request queue DMA address
459 */
095fec88
JG		 460 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
461
0ea9e179 462 /* ditto, for response queue */
095fec88
JG		 463 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
464};
465
522479fb
JG		 466enum chip_type {
467 chip_504x,
468 chip_508x,
469 chip_5080,
470 chip_604x,
471 chip_608x,
e4e7b892
JG		 472 chip_6042,
473 chip_7042,
f351b2d6 474 chip_soc,
522479fb
JG		 475};
476
31961943
BR		 477/* Command ReQuest Block: 32B */
478struct mv_crqb {
e1469874
ML		 479 __le32 sg_addr;
480 __le32 sg_addr_hi;
481 __le16 ctrl_flags;
482 __le16 ata_cmd[11];
31961943 483};
20f733e7 484
e4e7b892 485struct mv_crqb_iie {
e1469874
ML		 486 __le32 addr;
487 __le32 addr_hi;
488 __le32 flags;
489 __le32 len;
490 __le32 ata_cmd[4];
e4e7b892
JG		 491};
492
31961943
BR		 493/* Command ResPonse Block: 8B */
494struct mv_crpb {
e1469874
ML		 495 __le16 id;
496 __le16 flags;
497 __le32 tmstmp;
20f733e7
BR		 498};
499
31961943
BR		 500/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
501struct mv_sg {
e1469874
ML		 502 __le32 addr;
503 __le32 flags_size;
504 __le32 addr_hi;
505 __le32 reserved;
31961943 506};
20f733e7 507
08da1759
ML		 508/*
509 * We keep a local cache of a few frequently accessed port
510 * registers here, to avoid having to read them (very slow)
511 * when switching between EDMA and non-EDMA modes.
512 */
513struct mv_cached_regs {
514 u32 fiscfg;
515 u32 ltmode;
516 u32 haltcond;
c01e8a23 517 u32 unknown_rsvd;
08da1759
ML		 518};
519
31961943
BR		 520struct mv_port_priv {
521 struct mv_crqb *crqb;
522 dma_addr_t crqb_dma;
523 struct mv_crpb *crpb;
524 dma_addr_t crpb_dma;
eb73d558
ML		 525 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
526 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 527
528 unsigned int req_idx;
529 unsigned int resp_idx;
530
31961943 531 u32 pp_flags;
08da1759 532 struct mv_cached_regs cached;
29d187bb 533 unsigned int delayed_eh_pmp_map;
31961943
BR		 534};
535
bca1c4eb
JG		 536struct mv_port_signal {
537 u32 amps;
538 u32 pre;
539};
540
02a121da
ML		 541struct mv_host_priv {
542 u32 hp_flags;
1bfeff03 543 unsigned int board_idx;
96e2c487 544 u32 main_irq_mask;
02a121da
ML		 545 struct mv_port_signal signal[8];
546 const struct mv_hw_ops *ops;
f351b2d6
SB		 547 int n_ports;
548 void __iomem *base;
7368f919
ML		 549 void __iomem *main_irq_cause_addr;
550 void __iomem *main_irq_mask_addr;
cae5a29d
ML		 551 u32 irq_cause_offset;
552 u32 irq_mask_offset;
02a121da 553 u32 unmask_all_irqs;
c77a2f4e
SB		 554
555#if defined(CONFIG_HAVE_CLK)
556 struct clk *clk;
557#endif
da2fa9ba
ML		 558 /*
559 * These consistent DMA memory pools give us guaranteed
560 * alignment for hardware-accessed data structures,
561 * and less memory waste in accomplishing the alignment.
562 */
563 struct dma_pool *crqb_pool;
564 struct dma_pool *crpb_pool;
565 struct dma_pool *sg_tbl_pool;
02a121da
ML		 566};
567
47c2b677 568struct mv_hw_ops {
2a47ce06
JG		 569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
570 unsigned int port);
47c2b677
JG		 571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
573 void __iomem *mmio);
c9d39130
JG		 574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
575 unsigned int n_hc);
522479fb 576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 578};
579
82ef04fb
TH		 580static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
581static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 584static int mv_port_start(struct ata_port *ap);
585static void mv_port_stop(struct ata_port *ap);
3e4a1391 586static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 587static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 588static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 589static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 590static int mv_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline);
bdd4ddde
JG		 592static void mv_eh_freeze(struct ata_port *ap);
593static void mv_eh_thaw(struct ata_port *ap);
f273827e 594static void mv6_dev_config(struct ata_device *dev);
20f733e7 595
2a47ce06
JG		 596static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
597 unsigned int port);
47c2b677
JG		 598static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
600 void __iomem *mmio);
c9d39130
JG		 601static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
602 unsigned int n_hc);
522479fb 603static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 604static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 605
2a47ce06
JG		 606static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port);
47c2b677
JG		 608static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
c9d39130
JG		 611static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
612 unsigned int n_hc);
522479fb 613static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 614static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
615 void __iomem *mmio);
616static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
617 void __iomem *mmio);
618static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619 void __iomem *mmio, unsigned int n_hc);
620static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
621 void __iomem *mmio);
622static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
29b7e43c
MM		 623static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624 void __iomem *mmio, unsigned int port);
7bb3c529 625static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 626static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 627 unsigned int port_no);
e12bef50 628static int mv_stop_edma(struct ata_port *ap);
b562468c 629static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 630static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 631
e49856d8
ML		 632static void mv_pmp_select(struct ata_port *ap, int pmp);
633static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
634 unsigned long deadline);
635static int mv_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
29d187bb 637static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 638static void mv_process_crpb_entries(struct ata_port *ap,
639 struct mv_port_priv *pp);
47c2b677 640
da14265e
ML		 641static void mv_sff_irq_clear(struct ata_port *ap);
642static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644static void mv_bmdma_start(struct ata_queued_cmd *qc);
645static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646static u8 mv_bmdma_status(struct ata_port *ap);
d16ab3f6 647static u8 mv_sff_check_status(struct ata_port *ap);
da14265e 648
eb73d558
ML		 649/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650 * because we have to allow room for worst case splitting of
651 * PRDs for 64K boundaries in mv_fill_sg().
652 */
c5d3e45a 653static struct scsi_host_template mv5_sht = {
68d1d07b 654 ATA_BASE_SHT(DRV_NAME),
baf14aa1 655 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 656 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 657};
658
659static struct scsi_host_template mv6_sht = {
68d1d07b 660 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 661 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 662 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 663 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 664};
665
029cfd6b
TH		 666static struct ata_port_operations mv5_ops = {
667 .inherits = &ata_sff_port_ops,
c9d39130 668
c96f1732
AC		 669 .lost_interrupt = ATA_OP_NULL,
670
3e4a1391 671 .qc_defer = mv_qc_defer,
c9d39130
JG		 672 .qc_prep = mv_qc_prep,
673 .qc_issue = mv_qc_issue,
c9d39130 674
bdd4ddde
JG		 675 .freeze = mv_eh_freeze,
676 .thaw = mv_eh_thaw,
a1efdaba 677 .hardreset = mv_hardreset,
a1efdaba 678 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 679 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 680
c9d39130
JG		 681 .scr_read = mv5_scr_read,
682 .scr_write = mv5_scr_write,
683
684 .port_start = mv_port_start,
685 .port_stop = mv_port_stop,
c9d39130
JG		 686};
687
029cfd6b 688static struct ata_port_operations mv6_ops = {
8930ff25
TH		 689 .inherits = &ata_bmdma_port_ops,
690
691 .lost_interrupt = ATA_OP_NULL,
692
693 .qc_defer = mv_qc_defer,
694 .qc_prep = mv_qc_prep,
695 .qc_issue = mv_qc_issue,
696
f273827e 697 .dev_config = mv6_dev_config,
20f733e7 698
8930ff25
TH		 699 .freeze = mv_eh_freeze,
700 .thaw = mv_eh_thaw,
701 .hardreset = mv_hardreset,
702 .softreset = mv_softreset,
e49856d8
ML		 703 .pmp_hardreset = mv_pmp_hardreset,
704 .pmp_softreset = mv_softreset,
29d187bb 705 .error_handler = mv_pmp_error_handler,
da14265e 706
8930ff25
TH		 707 .scr_read = mv_scr_read,
708 .scr_write = mv_scr_write,
709
40f21b11 710 .sff_check_status = mv_sff_check_status,
da14265e
ML		 711 .sff_irq_clear = mv_sff_irq_clear,
712 .check_atapi_dma = mv_check_atapi_dma,
713 .bmdma_setup = mv_bmdma_setup,
714 .bmdma_start = mv_bmdma_start,
715 .bmdma_stop = mv_bmdma_stop,
716 .bmdma_status = mv_bmdma_status,
8930ff25
TH		 717
718 .port_start = mv_port_start,
719 .port_stop = mv_port_stop,
20f733e7
BR		 720};
721
029cfd6b
TH		 722static struct ata_port_operations mv_iie_ops = {
723 .inherits = &mv6_ops,
724 .dev_config = ATA_OP_NULL,
e4e7b892 725 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 726};
727
98ac62de 728static const struct ata_port_info mv_port_info[] = {
20f733e7 729 { /* chip_504x */
91b1a84c 730 .flags = MV_GEN_I_FLAGS,
c361acbc 731 .pio_mask = ATA_PIO4,
bf6263a8 732 .udma_mask = ATA_UDMA6,
c9d39130 733 .port_ops = &mv5_ops,
20f733e7
BR		 734 },
735 { /* chip_508x */
91b1a84c 736 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 737 .pio_mask = ATA_PIO4,
bf6263a8 738 .udma_mask = ATA_UDMA6,
c9d39130 739 .port_ops = &mv5_ops,
20f733e7 740 },
47c2b677 741 { /* chip_5080 */
91b1a84c 742 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 743 .pio_mask = ATA_PIO4,
bf6263a8 744 .udma_mask = ATA_UDMA6,
c9d39130 745 .port_ops = &mv5_ops,
47c2b677 746 },
20f733e7 747 { /* chip_604x */
91b1a84c 748 .flags = MV_GEN_II_FLAGS,
c361acbc 749 .pio_mask = ATA_PIO4,
bf6263a8 750 .udma_mask = ATA_UDMA6,
c9d39130 751 .port_ops = &mv6_ops,
20f733e7
BR		 752 },
753 { /* chip_608x */
91b1a84c 754 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 755 .pio_mask = ATA_PIO4,
bf6263a8 756 .udma_mask = ATA_UDMA6,
c9d39130 757 .port_ops = &mv6_ops,
20f733e7 758 },
e4e7b892 759 { /* chip_6042 */
91b1a84c 760 .flags = MV_GEN_IIE_FLAGS,
c361acbc 761 .pio_mask = ATA_PIO4,
bf6263a8 762 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 763 .port_ops = &mv_iie_ops,
764 },
765 { /* chip_7042 */
91b1a84c 766 .flags = MV_GEN_IIE_FLAGS,
c361acbc 767 .pio_mask = ATA_PIO4,
bf6263a8 768 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 769 .port_ops = &mv_iie_ops,
770 },
f351b2d6 771 { /* chip_soc */
91b1a84c 772 .flags = MV_GEN_IIE_FLAGS,
c361acbc 773 .pio_mask = ATA_PIO4,
17c5aab5
ML		 774 .udma_mask = ATA_UDMA6,
775 .port_ops = &mv_iie_ops,
f351b2d6 776 },
20f733e7
BR		 777};
778
3b7d697d 779static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 780 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
781 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
782 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
783 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 784 /* RocketRAID 1720/174x have different identifiers */
785 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 786 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
787 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 788
789 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
790 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
791 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
792 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
793 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
794
795 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
796
d9f9c6bc
FA		 797 /* Adaptec 1430SA */
798 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
799
02a121da 800 /* Marvell 7042 support */
6a3d586d
MT		 801 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
802
02a121da
ML		 803 /* Highpoint RocketRAID PCIe series */
804 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
805 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
806
2d2744fc 807 { } /* terminate list */
20f733e7
BR		 808};
809
47c2b677
JG		 810static const struct mv_hw_ops mv5xxx_ops = {
811 .phy_errata = mv5_phy_errata,
812 .enable_leds = mv5_enable_leds,
813 .read_preamp = mv5_read_preamp,
814 .reset_hc = mv5_reset_hc,
522479fb
JG		 815 .reset_flash = mv5_reset_flash,
816 .reset_bus = mv5_reset_bus,
47c2b677
JG		 817};
818
819static const struct mv_hw_ops mv6xxx_ops = {
820 .phy_errata = mv6_phy_errata,
821 .enable_leds = mv6_enable_leds,
822 .read_preamp = mv6_read_preamp,
823 .reset_hc = mv6_reset_hc,
522479fb
JG		 824 .reset_flash = mv6_reset_flash,
825 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 826};
827
f351b2d6
SB		 828static const struct mv_hw_ops mv_soc_ops = {
829 .phy_errata = mv6_phy_errata,
830 .enable_leds = mv_soc_enable_leds,
831 .read_preamp = mv_soc_read_preamp,
832 .reset_hc = mv_soc_reset_hc,
833 .reset_flash = mv_soc_reset_flash,
834 .reset_bus = mv_soc_reset_bus,
835};
836
29b7e43c
MM		 837static const struct mv_hw_ops mv_soc_65n_ops = {
838 .phy_errata = mv_soc_65n_phy_errata,
839 .enable_leds = mv_soc_enable_leds,
840 .reset_hc = mv_soc_reset_hc,
841 .reset_flash = mv_soc_reset_flash,
842 .reset_bus = mv_soc_reset_bus,
843};
844
20f733e7
BR		 845/*
846 * Functions
847 */
848
849static inline void writelfl(unsigned long data, void __iomem *addr)
850{
851 writel(data, addr);
852 (void) readl(addr); /* flush to avoid PCI posted write */
853}
854
c9d39130
JG		 855static inline unsigned int mv_hc_from_port(unsigned int port)
856{
857 return port >> MV_PORT_HC_SHIFT;
858}
859
860static inline unsigned int mv_hardport_from_port(unsigned int port)
861{
862 return port & MV_PORT_MASK;
863}
864
1cfd19ae
ML		 865/*
866 * Consolidate some rather tricky bit shift calculations.
867 * This is hot-path stuff, so not a function.
868 * Simple code, with two return values, so macro rather than inline.
869 *
870 * port is the sole input, in range 0..7.
7368f919
ML		 871 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
872 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 873 *
874 * Note that port and hardport may be the same variable in some cases.
875 */
876#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
877{ \
878 shift = mv_hc_from_port(port) * HC_SHIFT; \
879 hardport = mv_hardport_from_port(port); \
880 shift += hardport * 2; \
881}
882
352fab70
ML		 883static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
884{
cae5a29d 885 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
352fab70
ML		 886}
887
c9d39130
JG		 888static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
889 unsigned int port)
890{
891 return mv_hc_base(base, mv_hc_from_port(port));
892}
893
20f733e7
BR		 894static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
895{
c9d39130 896 return mv_hc_base_from_port(base, port) +
8b260248 897 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 898 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 899}
900
e12bef50
ML		 901static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
902{
903 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
904 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
905
906 return hc_mmio + ofs;
907}
908
f351b2d6
SB		 909static inline void __iomem *mv_host_base(struct ata_host *host)
910{
911 struct mv_host_priv *hpriv = host->private_data;
912 return hpriv->base;
913}
914
20f733e7
BR		 915static inline void __iomem *mv_ap_base(struct ata_port *ap)
916{
f351b2d6 917 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 918}
919
cca3974e 920static inline int mv_get_hc_count(unsigned long port_flags)
31961943 921{
cca3974e 922 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 923}
924
08da1759
ML		 925/**
926 * mv_save_cached_regs - (re-)initialize cached port registers
927 * @ap: the port whose registers we are caching
928 *
929 * Initialize the local cache of port registers,
930 * so that reading them over and over again can
931 * be avoided on the hotter paths of this driver.
932 * This saves a few microseconds each time we switch
933 * to/from EDMA mode to perform (eg.) a drive cache flush.
934 */
935static void mv_save_cached_regs(struct ata_port *ap)
936{
937 void __iomem *port_mmio = mv_ap_base(ap);
938 struct mv_port_priv *pp = ap->private_data;
939
cae5a29d
ML		 940 pp->cached.fiscfg = readl(port_mmio + FISCFG);
941 pp->cached.ltmode = readl(port_mmio + LTMODE);
942 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
943 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
08da1759
ML		 944}
945
946/**
947 * mv_write_cached_reg - write to a cached port register
948 * @addr: hardware address of the register
949 * @old: pointer to cached value of the register
950 * @new: new value for the register
951 *
952 * Write a new value to a cached register,
953 * but only if the value is different from before.
954 */
955static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
956{
957 if (new != *old) {
12f3b6d7 958 unsigned long laddr;
08da1759 959 *old = new;
12f3b6d7
ML		 960 /*
961 * Workaround for 88SX60x1-B2 FEr SATA#13:
962 * Read-after-write is needed to prevent generating 64-bit
963 * write cycles on the PCI bus for SATA interface registers
964 * at offsets ending in 0x4 or 0xc.
965 *
966 * Looks like a lot of fuss, but it avoids an unnecessary
967 * +1 usec read-after-write delay for unaffected registers.
968 */
969 laddr = (long)addr & 0xffff;
970 if (laddr >= 0x300 && laddr <= 0x33c) {
971 laddr &= 0x000f;
972 if (laddr == 0x4 || laddr == 0xc) {
973 writelfl(new, addr); /* read after write */
974 return;
975 }
976 }
977 writel(new, addr); /* unaffected by the errata */
08da1759
ML		 978 }
979}
980
c5d3e45a
JG		 981static void mv_set_edma_ptrs(void __iomem *port_mmio,
982 struct mv_host_priv *hpriv,
983 struct mv_port_priv *pp)
984{
bdd4ddde
JG		 985 u32 index;
986
c5d3e45a
JG		 987 /*
988 * initialize request queue
989 */
fcfb1f77
ML		 990 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
991 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 992
c5d3e45a 993 WARN_ON(pp->crqb_dma & 0x3ff);
cae5a29d 994 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
bdd4ddde 995 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
cae5a29d
ML		 996 port_mmio + EDMA_REQ_Q_IN_PTR);
997 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
c5d3e45a
JG		 998
999 /*
1000 * initialize response queue
1001 */
fcfb1f77
ML		 1002 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1003 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 1004
c5d3e45a 1005 WARN_ON(pp->crpb_dma & 0xff);
cae5a29d
ML		 1006 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1007 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
bdd4ddde 1008 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
cae5a29d 1009 port_mmio + EDMA_RSP_Q_OUT_PTR);
c5d3e45a
JG		 1010}
1011
2b748a0a
ML		 1012static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1013{
1014 /*
1015 * When writing to the main_irq_mask in hardware,
1016 * we must ensure exclusivity between the interrupt coalescing bits
1017 * and the corresponding individual port DONE_IRQ bits.
1018 *
1019 * Note that this register is really an "IRQ enable" register,
1020 * not an "IRQ mask" register as Marvell's naming might suggest.
1021 */
1022 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1023 mask &= ~DONE_IRQ_0_3;
1024 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1025 mask &= ~DONE_IRQ_4_7;
1026 writelfl(mask, hpriv->main_irq_mask_addr);
1027}
1028
c4de573b
ML		 1029static void mv_set_main_irq_mask(struct ata_host *host,
1030 u32 disable_bits, u32 enable_bits)
1031{
1032 struct mv_host_priv *hpriv = host->private_data;
1033 u32 old_mask, new_mask;
1034
96e2c487 1035 old_mask = hpriv->main_irq_mask;
c4de573b 1036 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 1037 if (new_mask != old_mask) {
1038 hpriv->main_irq_mask = new_mask;
2b748a0a 1039 mv_write_main_irq_mask(new_mask, hpriv);
96e2c487 1040 }
c4de573b
ML		 1041}
1042
1043static void mv_enable_port_irqs(struct ata_port *ap,
1044 unsigned int port_bits)
1045{
1046 unsigned int shift, hardport, port = ap->port_no;
1047 u32 disable_bits, enable_bits;
1048
1049 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1050
1051 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1052 enable_bits = port_bits << shift;
1053 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1054}
1055
00b81235
ML		 1056static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1057 void __iomem *port_mmio,
1058 unsigned int port_irqs)
1059{
1060 struct mv_host_priv *hpriv = ap->host->private_data;
1061 int hardport = mv_hardport_from_port(ap->port_no);
1062 void __iomem *hc_mmio = mv_hc_base_from_port(
1063 mv_host_base(ap->host), ap->port_no);
1064 u32 hc_irq_cause;
1065
1066 /* clear EDMA event indicators, if any */
cae5a29d 1067 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
00b81235
ML		 1068
1069 /* clear pending irq events */
1070 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 1071 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
00b81235
ML		 1072
1073 /* clear FIS IRQ Cause */
1074 if (IS_GEN_IIE(hpriv))
cae5a29d 1075 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
00b81235
ML		 1076
1077 mv_enable_port_irqs(ap, port_irqs);
1078}
1079
2b748a0a
ML		 1080static void mv_set_irq_coalescing(struct ata_host *host,
1081 unsigned int count, unsigned int usecs)
1082{
1083 struct mv_host_priv *hpriv = host->private_data;
1084 void __iomem *mmio = hpriv->base, *hc_mmio;
1085 u32 coal_enable = 0;
1086 unsigned long flags;
6abf4678 1087 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
2b748a0a
ML		 1088 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1089 ALL_PORTS_COAL_DONE;
1090
1091 /* Disable IRQ coalescing if either threshold is zero */
1092 if (!usecs || !count) {
1093 clks = count = 0;
1094 } else {
1095 /* Respect maximum limits of the hardware */
1096 clks = usecs * COAL_CLOCKS_PER_USEC;
1097 if (clks > MAX_COAL_TIME_THRESHOLD)
1098 clks = MAX_COAL_TIME_THRESHOLD;
1099 if (count > MAX_COAL_IO_COUNT)
1100 count = MAX_COAL_IO_COUNT;
1101 }
1102
1103 spin_lock_irqsave(&host->lock, flags);
6abf4678 1104 mv_set_main_irq_mask(host, coal_disable, 0);
2b748a0a 1105
6abf4678 1106 if (is_dual_hc && !IS_GEN_I(hpriv)) {
2b748a0a 1107 /*
6abf4678
ML		 1108 * GEN_II/GEN_IIE with dual host controllers:
1109 * one set of global thresholds for the entire chip.
2b748a0a 1110 */
cae5a29d
ML		 1111 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1112 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
2b748a0a 1113 /* clear leftover coal IRQ bit */
cae5a29d 1114 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
6abf4678
ML		 1115 if (count)
1116 coal_enable = ALL_PORTS_COAL_DONE;
1117 clks = count = 0; /* force clearing of regular regs below */
2b748a0a 1118 }
6abf4678 1119
2b748a0a
ML		 1120 /*
1121 * All chips: independent thresholds for each HC on the chip.
1122 */
1123 hc_mmio = mv_hc_base_from_port(mmio, 0);
cae5a29d
ML		 1124 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1125 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1126 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1127 if (count)
1128 coal_enable |= PORTS_0_3_COAL_DONE;
1129 if (is_dual_hc) {
2b748a0a 1130 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
cae5a29d
ML		 1131 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1132 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1133 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1134 if (count)
1135 coal_enable |= PORTS_4_7_COAL_DONE;
2b748a0a 1136 }
2b748a0a 1137
6abf4678 1138 mv_set_main_irq_mask(host, 0, coal_enable);
2b748a0a
ML		 1139 spin_unlock_irqrestore(&host->lock, flags);
1140}
1141
05b308e1 1142/**
00b81235 1143 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 1144 * @base: port base address
1145 * @pp: port private data
1146 *
beec7dbc
TH		 1147 * Verify the local cache of the eDMA state is accurate with a
1148 * WARN_ON.
05b308e1
BR		 1149 *
1150 * LOCKING:
1151 * Inherited from caller.
1152 */
00b81235 1153static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 1154 struct mv_port_priv *pp, u8 protocol)
20f733e7 1155{
72109168
ML		 1156 int want_ncq = (protocol == ATA_PROT_NCQ);
1157
1158 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1159 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1160 if (want_ncq != using_ncq)
b562468c 1161 mv_stop_edma(ap);
72109168 1162 }
c5d3e45a 1163 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 1164 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 1165
00b81235 1166 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 1167
f630d562 1168 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 1169 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 1170
cae5a29d 1171 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
afb0edd9
BR		 1172 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1173 }
20f733e7
BR		 1174}
1175
9b2c4e0b
ML		 1176static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1177{
1178 void __iomem *port_mmio = mv_ap_base(ap);
1179 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1180 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1181 int i;
1182
1183 /*
1184 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 1185 * No idea what a good "timeout" value might be, but measurements
1186 * indicate that it often requires hundreds of microseconds
1187 * with two drives in-use. So we use the 15msec value above
1188 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 1189 */
1190 for (i = 0; i < timeout; ++i) {
cae5a29d 1191 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
9b2c4e0b
ML		 1192 if ((edma_stat & empty_idle) == empty_idle)
1193 break;
1194 udelay(per_loop);
1195 }
1196 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1197}
1198
05b308e1 1199/**
e12bef50 1200 * mv_stop_edma_engine - Disable eDMA engine
b562468c 1201 * @port_mmio: io base address
05b308e1
BR		 1202 *
1203 * LOCKING:
1204 * Inherited from caller.
1205 */
b562468c 1206static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 1207{
b562468c 1208 int i;
31961943 1209
b562468c 1210 /* Disable eDMA. The disable bit auto clears. */
cae5a29d 1211 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
8b260248 1212
b562468c
ML		 1213 /* Wait for the chip to confirm eDMA is off. */
1214 for (i = 10000; i > 0; i--) {
cae5a29d 1215 u32 reg = readl(port_mmio + EDMA_CMD);
4537deb5 1216 if (!(reg & EDMA_EN))
b562468c
ML		 1217 return 0;
1218 udelay(10);
31961943 1219 }
b562468c 1220 return -EIO;
20f733e7
BR		 1221}
1222
e12bef50 1223static int mv_stop_edma(struct ata_port *ap)
0ea9e179 1224{
b562468c
ML		 1225 void __iomem *port_mmio = mv_ap_base(ap);
1226 struct mv_port_priv *pp = ap->private_data;
66e57a2c 1227 int err = 0;
0ea9e179 1228
b562468c
ML		 1229 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1230 return 0;
1231 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 1232 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 1233 if (mv_stop_edma_engine(port_mmio)) {
1234 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
66e57a2c 1235 err = -EIO;
b562468c 1236 }
66e57a2c
ML		 1237 mv_edma_cfg(ap, 0, 0);
1238 return err;
0ea9e179
JG		 1239}
1240
8a70f8dc 1241#ifdef ATA_DEBUG
31961943 1242static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 1243{
31961943
BR		 1244 int b, w;
1245 for (b = 0; b < bytes; ) {
1246 DPRINTK("%p: ", start + b);
1247 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1248 printk("%08x ", readl(start + b));
31961943
BR		 1249 b += sizeof(u32);
1250 }
1251 printk("\n");
1252 }
31961943 1253}
8a70f8dc
JG		 1254#endif
1255
31961943
BR		 1256static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1257{
1258#ifdef ATA_DEBUG
1259 int b, w;
1260 u32 dw;
1261 for (b = 0; b < bytes; ) {
1262 DPRINTK("%02x: ", b);
1263 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1264 (void) pci_read_config_dword(pdev, b, &dw);
1265 printk("%08x ", dw);
31961943
BR		 1266 b += sizeof(u32);
1267 }
1268 printk("\n");
1269 }
1270#endif
1271}
1272static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1273 struct pci_dev *pdev)
1274{
1275#ifdef ATA_DEBUG
8b260248 1276 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1277 port >> MV_PORT_HC_SHIFT);
1278 void __iomem *port_base;
1279 int start_port, num_ports, p, start_hc, num_hcs, hc;
1280
1281 if (0 > port) {
1282 start_hc = start_port = 0;
1283 num_ports = 8; /* shld be benign for 4 port devs */
1284 num_hcs = 2;
1285 } else {
1286 start_hc = port >> MV_PORT_HC_SHIFT;
1287 start_port = port;
1288 num_ports = num_hcs = 1;
1289 }
8b260248 1290 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1291 num_ports > 1 ? num_ports - 1 : start_port);
1292
1293 if (NULL != pdev) {
1294 DPRINTK("PCI config space regs:\n");
1295 mv_dump_pci_cfg(pdev, 0x68);
1296 }
1297 DPRINTK("PCI regs:\n");
1298 mv_dump_mem(mmio_base+0xc00, 0x3c);
1299 mv_dump_mem(mmio_base+0xd00, 0x34);
1300 mv_dump_mem(mmio_base+0xf00, 0x4);
1301 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1302 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1303 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1304 DPRINTK("HC regs (HC %i):\n", hc);
1305 mv_dump_mem(hc_base, 0x1c);
1306 }
1307 for (p = start_port; p < start_port + num_ports; p++) {
1308 port_base = mv_port_base(mmio_base, p);
2dcb407e 1309 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1310 mv_dump_mem(port_base, 0x54);
2dcb407e 1311 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1312 mv_dump_mem(port_base+0x300, 0x60);
1313 }
1314#endif
20f733e7
BR		 1315}
1316
1317static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1318{
1319 unsigned int ofs;
1320
1321 switch (sc_reg_in) {
1322 case SCR_STATUS:
1323 case SCR_CONTROL:
1324 case SCR_ERROR:
cae5a29d 1325 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
20f733e7
BR		 1326 break;
1327 case SCR_ACTIVE:
cae5a29d 1328 ofs = SATA_ACTIVE; /* active is not with the others */
20f733e7
BR		 1329 break;
1330 default:
1331 ofs = 0xffffffffU;
1332 break;
1333 }
1334 return ofs;
1335}
1336
82ef04fb 1337static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1338{
1339 unsigned int ofs = mv_scr_offset(sc_reg_in);
1340
da3dbb17 1341 if (ofs != 0xffffffffU) {
82ef04fb 1342 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1343 return 0;
1344 } else
1345 return -EINVAL;
20f733e7
BR		 1346}
1347
82ef04fb 1348static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1349{
1350 unsigned int ofs = mv_scr_offset(sc_reg_in);
1351
da3dbb17 1352 if (ofs != 0xffffffffU) {
20091773
ML		 1353 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1354 if (sc_reg_in == SCR_CONTROL) {
1355 /*
1356 * Workaround for 88SX60x1 FEr SATA#26:
1357 *
1358 * COMRESETs have to take care not to accidently
1359 * put the drive to sleep when writing SCR_CONTROL.
1360 * Setting bits 12..15 prevents this problem.
1361 *
1362 * So if we see an outbound COMMRESET, set those bits.
1363 * Ditto for the followup write that clears the reset.
1364 *
1365 * The proprietary driver does this for
1366 * all chip versions, and so do we.
1367 */
1368 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1369 val |= 0xf000;
1370 }
1371 writelfl(val, addr);
da3dbb17
TH		 1372 return 0;
1373 } else
1374 return -EINVAL;
20f733e7
BR		 1375}
1376
f273827e
ML		 1377static void mv6_dev_config(struct ata_device *adev)
1378{
1379 /*
e49856d8
ML		 1380 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1381 *
1382 * Gen-II does not support NCQ over a port multiplier
1383 * (no FIS-based switching).
f273827e 1384 */
e49856d8 1385 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1386 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1387 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1388 ata_dev_printk(adev, KERN_INFO,
1389 "NCQ disabled for command-based switching\n");
352fab70 1390 }
e49856d8 1391 }
f273827e
ML		 1392}
1393
3e4a1391
ML		 1394static int mv_qc_defer(struct ata_queued_cmd *qc)
1395{
1396 struct ata_link *link = qc->dev->link;
1397 struct ata_port *ap = link->ap;
1398 struct mv_port_priv *pp = ap->private_data;
1399
29d187bb
ML		 1400 /*
1401 * Don't allow new commands if we're in a delayed EH state
1402 * for NCQ and/or FIS-based switching.
1403 */
1404 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1405 return ATA_DEFER_PORT;
159a7ff7
GG		 1406
1407 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1408 * can run concurrently.
1409 * set excl_link when we want to send a PIO command in DMA mode
1410 * or a non-NCQ command in NCQ mode.
1411 * When we receive a command from that link, and there are no
1412 * outstanding commands, mark a flag to clear excl_link and let
1413 * the command go through.
1414 */
1415 if (unlikely(ap->excl_link)) {
1416 if (link == ap->excl_link) {
1417 if (ap->nr_active_links)
1418 return ATA_DEFER_PORT;
1419 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1420 return 0;
1421 } else
1422 return ATA_DEFER_PORT;
1423 }
1424
3e4a1391
ML		 1425 /*
1426 * If the port is completely idle, then allow the new qc.
1427 */
1428 if (ap->nr_active_links == 0)
1429 return 0;
1430
4bdee6c5
TH		 1431 /*
1432 * The port is operating in host queuing mode (EDMA) with NCQ
1433 * enabled, allow multiple NCQ commands. EDMA also allows
1434 * queueing multiple DMA commands but libata core currently
1435 * doesn't allow it.
1436 */
1437 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
159a7ff7
GG		 1438 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1439 if (ata_is_ncq(qc->tf.protocol))
1440 return 0;
1441 else {
1442 ap->excl_link = link;
1443 return ATA_DEFER_PORT;
1444 }
1445 }
4bdee6c5 1446
3e4a1391
ML		 1447 return ATA_DEFER_PORT;
1448}
1449
08da1759 1450static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
e49856d8 1451{
08da1759
ML		 1452 struct mv_port_priv *pp = ap->private_data;
1453 void __iomem *port_mmio;
00f42eab 1454
08da1759
ML		 1455 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1456 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1457 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
00f42eab 1458
08da1759
ML		 1459 ltmode = *old_ltmode & ~LTMODE_BIT8;
1460 haltcond = *old_haltcond | EDMA_ERR_DEV;
00f42eab
ML		 1461
1462 if (want_fbs) {
08da1759
ML		 1463 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1464 ltmode = *old_ltmode | LTMODE_BIT8;
4c299ca3 1465 if (want_ncq)
08da1759 1466 haltcond &= ~EDMA_ERR_DEV;
4c299ca3 1467 else
08da1759
ML		 1468 fiscfg |= FISCFG_WAIT_DEV_ERR;
1469 } else {
1470 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
e49856d8 1471 }
00f42eab 1472
08da1759 1473 port_mmio = mv_ap_base(ap);
cae5a29d
ML		 1474 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1475 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1476 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
f273827e
ML		 1477}
1478
dd2890f6
ML		 1479static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1480{
1481 struct mv_host_priv *hpriv = ap->host->private_data;
1482 u32 old, new;
1483
1484 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
cae5a29d 1485 old = readl(hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1486 if (want_ncq)
1487 new = old | (1 << 22);
1488 else
1489 new = old & ~(1 << 22);
1490 if (new != old)
cae5a29d 1491 writel(new, hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1492}
1493
c01e8a23 1494/**
40f21b11
ML		 1495 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1496 * @ap: Port being initialized
c01e8a23
ML		 1497 *
1498 * There are two DMA modes on these chips: basic DMA, and EDMA.
1499 *
1500 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1501 * of basic DMA on the GEN_IIE versions of the chips.
1502 *
1503 * This bit survives EDMA resets, and must be set for basic DMA
1504 * to function, and should be cleared when EDMA is active.
1505 */
1506static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1507{
1508 struct mv_port_priv *pp = ap->private_data;
1509 u32 new, *old = &pp->cached.unknown_rsvd;
1510
1511 if (enable_bmdma)
1512 new = *old | 1;
1513 else
1514 new = *old & ~1;
cae5a29d 1515 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
c01e8a23
ML		 1516}
1517
000b344f
ML		 1518/*
1519 * SOC chips have an issue whereby the HDD LEDs don't always blink
1520 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1521 * of the SOC takes care of it, generating a steady blink rate when
1522 * any drive on the chip is active.
1523 *
1524 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1525 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1526 *
1527 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1528 * LED operation works then, and provides better (more accurate) feedback.
1529 *
1530 * Note that this code assumes that an SOC never has more than one HC onboard.
1531 */
1532static void mv_soc_led_blink_enable(struct ata_port *ap)
1533{
1534 struct ata_host *host = ap->host;
1535 struct mv_host_priv *hpriv = host->private_data;
1536 void __iomem *hc_mmio;
1537 u32 led_ctrl;
1538
1539 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1540 return;
1541 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1542 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1543 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1544 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1545}
1546
1547static void mv_soc_led_blink_disable(struct ata_port *ap)
1548{
1549 struct ata_host *host = ap->host;
1550 struct mv_host_priv *hpriv = host->private_data;
1551 void __iomem *hc_mmio;
1552 u32 led_ctrl;
1553 unsigned int port;
1554
1555 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1556 return;
1557
1558 /* disable led-blink only if no ports are using NCQ */
1559 for (port = 0; port < hpriv->n_ports; port++) {
1560 struct ata_port *this_ap = host->ports[port];
1561 struct mv_port_priv *pp = this_ap->private_data;
1562
1563 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1564 return;
1565 }
1566
1567 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1568 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1569 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1570 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1571}
1572
00b81235 1573static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1574{
0c58912e 1575 u32 cfg;
e12bef50
ML		 1576 struct mv_port_priv *pp = ap->private_data;
1577 struct mv_host_priv *hpriv = ap->host->private_data;
1578 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1579
1580 /* set up non-NCQ EDMA configuration */
0c58912e 1581 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
d16ab3f6
ML		 1582 pp->pp_flags &=
1583 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
e4e7b892 1584
0c58912e 1585 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1586 cfg |= (1 << 8); /* enab config burst size mask */
1587
dd2890f6 1588 else if (IS_GEN_II(hpriv)) {
e4e7b892 1589 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1590 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1591
dd2890f6 1592 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1593 int want_fbs = sata_pmp_attached(ap);
1594 /*
1595 * Possible future enhancement:
1596 *
1597 * The chip can use FBS with non-NCQ, if we allow it,
1598 * But first we need to have the error handling in place
1599 * for this mode (datasheet section 7.3.15.4.2.3).
1600 * So disallow non-NCQ FBS for now.
1601 */
1602 want_fbs &= want_ncq;
1603
08da1759 1604 mv_config_fbs(ap, want_ncq, want_fbs);
00f42eab
ML		 1605
1606 if (want_fbs) {
1607 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1608 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1609 }
1610
e728eabe 1611 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1612 if (want_edma) {
1613 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1614 if (!IS_SOC(hpriv))
1615 cfg |= (1 << 18); /* enab early completion */
1616 }
616d4a98
ML		 1617 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1618 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
c01e8a23 1619 mv_bmdma_enable_iie(ap, !want_edma);
000b344f
ML		 1620
1621 if (IS_SOC(hpriv)) {
1622 if (want_ncq)
1623 mv_soc_led_blink_enable(ap);
1624 else
1625 mv_soc_led_blink_disable(ap);
1626 }
e4e7b892
JG		 1627 }
1628
72109168
ML		 1629 if (want_ncq) {
1630 cfg |= EDMA_CFG_NCQ;
1631 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1632 }
72109168 1633
cae5a29d 1634 writelfl(cfg, port_mmio + EDMA_CFG);
e4e7b892
JG		 1635}
1636
da2fa9ba
ML		 1637static void mv_port_free_dma_mem(struct ata_port *ap)
1638{
1639 struct mv_host_priv *hpriv = ap->host->private_data;
1640 struct mv_port_priv *pp = ap->private_data;
eb73d558 1641 int tag;
da2fa9ba
ML		 1642
1643 if (pp->crqb) {
1644 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1645 pp->crqb = NULL;
1646 }
1647 if (pp->crpb) {
1648 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1649 pp->crpb = NULL;
1650 }
eb73d558
ML		 1651 /*
1652 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1653 * For later hardware, we have one unique sg_tbl per NCQ tag.
1654 */
1655 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1656 if (pp->sg_tbl[tag]) {
1657 if (tag == 0 || !IS_GEN_I(hpriv))
1658 dma_pool_free(hpriv->sg_tbl_pool,
1659 pp->sg_tbl[tag],
1660 pp->sg_tbl_dma[tag]);
1661 pp->sg_tbl[tag] = NULL;
1662 }
da2fa9ba
ML		 1663 }
1664}
1665
05b308e1
BR		 1666/**
1667 * mv_port_start - Port specific init/start routine.
1668 * @ap: ATA channel to manipulate
1669 *
1670 * Allocate and point to DMA memory, init port private memory,
1671 * zero indices.
1672 *
1673 * LOCKING:
1674 * Inherited from caller.
1675 */
31961943
BR		 1676static int mv_port_start(struct ata_port *ap)
1677{
cca3974e
JG		 1678 struct device *dev = ap->host->dev;
1679 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1680 struct mv_port_priv *pp;
933cb8e5 1681 unsigned long flags;
dde20207 1682 int tag;
31961943 1683
24dc5f33 1684 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1685 if (!pp)
24dc5f33 1686 return -ENOMEM;
da2fa9ba 1687 ap->private_data = pp;
31961943 1688
da2fa9ba
ML		 1689 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1690 if (!pp->crqb)
1691 return -ENOMEM;
1692 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1693
da2fa9ba
ML		 1694 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1695 if (!pp->crpb)
1696 goto out_port_free_dma_mem;
1697 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1698
3bd0a70e
ML		 1699 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1700 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1701 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1702 /*
1703 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1704 * For later hardware, we need one unique sg_tbl per NCQ tag.
1705 */
1706 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1707 if (tag == 0 || !IS_GEN_I(hpriv)) {
1708 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1709 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1710 if (!pp->sg_tbl[tag])
1711 goto out_port_free_dma_mem;
1712 } else {
1713 pp->sg_tbl[tag] = pp->sg_tbl[0];
1714 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1715 }
1716 }
933cb8e5
ML		 1717
1718 spin_lock_irqsave(ap->lock, flags);
08da1759 1719 mv_save_cached_regs(ap);
66e57a2c 1720 mv_edma_cfg(ap, 0, 0);
933cb8e5
ML		 1721 spin_unlock_irqrestore(ap->lock, flags);
1722
31961943 1723 return 0;
da2fa9ba
ML		 1724
1725out_port_free_dma_mem:
1726 mv_port_free_dma_mem(ap);
1727 return -ENOMEM;
31961943
BR		 1728}
1729
05b308e1
BR		 1730/**
1731 * mv_port_stop - Port specific cleanup/stop routine.
1732 * @ap: ATA channel to manipulate
1733 *
1734 * Stop DMA, cleanup port memory.
1735 *
1736 * LOCKING:
cca3974e 1737 * This routine uses the host lock to protect the DMA stop.
05b308e1 1738 */
31961943
BR		 1739static void mv_port_stop(struct ata_port *ap)
1740{
933cb8e5
ML		 1741 unsigned long flags;
1742
1743 spin_lock_irqsave(ap->lock, flags);
e12bef50 1744 mv_stop_edma(ap);
88e675e1 1745 mv_enable_port_irqs(ap, 0);
933cb8e5 1746 spin_unlock_irqrestore(ap->lock, flags);
da2fa9ba 1747 mv_port_free_dma_mem(ap);
31961943
BR		 1748}
1749
05b308e1
BR		 1750/**
1751 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1752 * @qc: queued command whose SG list to source from
1753 *
1754 * Populate the SG list and mark the last entry.
1755 *
1756 * LOCKING:
1757 * Inherited from caller.
1758 */
6c08772e 1759static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1760{
1761 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1762 struct scatterlist *sg;
3be6cbd7 1763 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1764 unsigned int si;
31961943 1765
eb73d558 1766 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1767 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1768 dma_addr_t addr = sg_dma_address(sg);
1769 u32 sg_len = sg_dma_len(sg);
22374677 1770
4007b493
OJ		 1771 while (sg_len) {
1772 u32 offset = addr & 0xffff;
1773 u32 len = sg_len;
22374677 1774
32cd11a6 1775 if (offset + len > 0x10000)
4007b493
OJ		 1776 len = 0x10000 - offset;
1777
1778 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1779 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1780 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1781 mv_sg->reserved = 0;
4007b493
OJ		 1782
1783 sg_len -= len;
1784 addr += len;
1785
3be6cbd7 1786 last_sg = mv_sg;
4007b493 1787 mv_sg++;
4007b493 1788 }
31961943 1789 }
3be6cbd7
JG		 1790
1791 if (likely(last_sg))
1792 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1793 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1794}
1795
5796d1c4 1796static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1797{
559eedad 1798 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1799 (last ? CRQB_CMD_LAST : 0);
559eedad 1800 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1801}
1802
da14265e
ML		 1803/**
1804 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1805 * @ap: Port associated with this ATA transaction.
1806 *
1807 * We need this only for ATAPI bmdma transactions,
1808 * as otherwise we experience spurious interrupts
1809 * after libata-sff handles the bmdma interrupts.
1810 */
1811static void mv_sff_irq_clear(struct ata_port *ap)
1812{
1813 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1814}
1815
1816/**
1817 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1818 * @qc: queued command to check for chipset/DMA compatibility.
1819 *
1820 * The bmdma engines cannot handle speculative data sizes
1821 * (bytecount under/over flow). So only allow DMA for
1822 * data transfer commands with known data sizes.
1823 *
1824 * LOCKING:
1825 * Inherited from caller.
1826 */
1827static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1828{
1829 struct scsi_cmnd *scmd = qc->scsicmd;
1830
1831 if (scmd) {
1832 switch (scmd->cmnd[0]) {
1833 case READ_6:
1834 case READ_10:
1835 case READ_12:
1836 case WRITE_6:
1837 case WRITE_10:
1838 case WRITE_12:
1839 case GPCMD_READ_CD:
1840 case GPCMD_SEND_DVD_STRUCTURE:
1841 case GPCMD_SEND_CUE_SHEET:
1842 return 0; /* DMA is safe */
1843 }
1844 }
1845 return -EOPNOTSUPP; /* use PIO instead */
1846}
1847
1848/**
1849 * mv_bmdma_setup - Set up BMDMA transaction
1850 * @qc: queued command to prepare DMA for.
1851 *
1852 * LOCKING:
1853 * Inherited from caller.
1854 */
1855static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1856{
1857 struct ata_port *ap = qc->ap;
1858 void __iomem *port_mmio = mv_ap_base(ap);
1859 struct mv_port_priv *pp = ap->private_data;
1860
1861 mv_fill_sg(qc);
1862
1863 /* clear all DMA cmd bits */
cae5a29d 1864 writel(0, port_mmio + BMDMA_CMD);
da14265e
ML		 1865
1866 /* load PRD table addr. */
1867 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
cae5a29d 1868 port_mmio + BMDMA_PRD_HIGH);
da14265e 1869 writelfl(pp->sg_tbl_dma[qc->tag],
cae5a29d 1870 port_mmio + BMDMA_PRD_LOW);
da14265e
ML		 1871
1872 /* issue r/w command */
1873 ap->ops->sff_exec_command(ap, &qc->tf);
1874}
1875
1876/**
1877 * mv_bmdma_start - Start a BMDMA transaction
1878 * @qc: queued command to start DMA on.
1879 *
1880 * LOCKING:
1881 * Inherited from caller.
1882 */
1883static void mv_bmdma_start(struct ata_queued_cmd *qc)
1884{
1885 struct ata_port *ap = qc->ap;
1886 void __iomem *port_mmio = mv_ap_base(ap);
1887 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1888 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1889
1890 /* start host DMA transaction */
cae5a29d 1891 writelfl(cmd, port_mmio + BMDMA_CMD);
da14265e
ML		 1892}
1893
1894/**
1895 * mv_bmdma_stop - Stop BMDMA transfer
1896 * @qc: queued command to stop DMA on.
1897 *
1898 * Clears the ATA_DMA_START flag in the bmdma control register
1899 *
1900 * LOCKING:
1901 * Inherited from caller.
1902 */
1903static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1904{
1905 struct ata_port *ap = qc->ap;
1906 void __iomem *port_mmio = mv_ap_base(ap);
1907 u32 cmd;
1908
1909 /* clear start/stop bit */
cae5a29d 1910 cmd = readl(port_mmio + BMDMA_CMD);
da14265e 1911 cmd &= ~ATA_DMA_START;
cae5a29d 1912 writelfl(cmd, port_mmio + BMDMA_CMD);
da14265e
ML		 1913
1914 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1915 ata_sff_dma_pause(ap);
1916}
1917
1918/**
1919 * mv_bmdma_status - Read BMDMA status
1920 * @ap: port for which to retrieve DMA status.
1921 *
1922 * Read and return equivalent of the sff BMDMA status register.
1923 *
1924 * LOCKING:
1925 * Inherited from caller.
1926 */
1927static u8 mv_bmdma_status(struct ata_port *ap)
1928{
1929 void __iomem *port_mmio = mv_ap_base(ap);
1930 u32 reg, status;
1931
1932 /*
1933 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1934 * and the ATA_DMA_INTR bit doesn't exist.
1935 */
cae5a29d 1936 reg = readl(port_mmio + BMDMA_STATUS);
da14265e
ML		 1937 if (reg & ATA_DMA_ACTIVE)
1938 status = ATA_DMA_ACTIVE;
1939 else
1940 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1941 return status;
1942}
1943
299b3f8d
ML		 1944static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1945{
1946 struct ata_taskfile *tf = &qc->tf;
1947 /*
1948 * Workaround for 88SX60x1 FEr SATA#24.
1949 *
1950 * Chip may corrupt WRITEs if multi_count >= 4kB.
1951 * Note that READs are unaffected.
1952 *
1953 * It's not clear if this errata really means "4K bytes",
1954 * or if it always happens for multi_count > 7
1955 * regardless of device sector_size.
1956 *
1957 * So, for safety, any write with multi_count > 7
1958 * gets converted here into a regular PIO write instead:
1959 */
1960 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1961 if (qc->dev->multi_count > 7) {
1962 switch (tf->command) {
1963 case ATA_CMD_WRITE_MULTI:
1964 tf->command = ATA_CMD_PIO_WRITE;
1965 break;
1966 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1967 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1968 /* fall through */
1969 case ATA_CMD_WRITE_MULTI_EXT:
1970 tf->command = ATA_CMD_PIO_WRITE_EXT;
1971 break;
1972 }
1973 }
1974 }
1975}
1976
05b308e1
BR		 1977/**
1978 * mv_qc_prep - Host specific command preparation.
1979 * @qc: queued command to prepare
1980 *
1981 * This routine simply redirects to the general purpose routine
1982 * if command is not DMA. Else, it handles prep of the CRQB
1983 * (command request block), does some sanity checking, and calls
1984 * the SG load routine.
1985 *
1986 * LOCKING:
1987 * Inherited from caller.
1988 */
31961943
BR		 1989static void mv_qc_prep(struct ata_queued_cmd *qc)
1990{
1991 struct ata_port *ap = qc->ap;
1992 struct mv_port_priv *pp = ap->private_data;
e1469874 1993 __le16 *cw;
8d2b450d 1994 struct ata_taskfile *tf = &qc->tf;
31961943 1995 u16 flags = 0;
a6432436 1996 unsigned in_index;
31961943 1997
299b3f8d
ML		 1998 switch (tf->protocol) {
1999 case ATA_PROT_DMA:
2000 case ATA_PROT_NCQ:
2001 break; /* continue below */
2002 case ATA_PROT_PIO:
2003 mv_rw_multi_errata_sata24(qc);
31961943 2004 return;
299b3f8d
ML		 2005 default:
2006 return;
2007 }
20f733e7 2008
31961943
BR		 2009 /* Fill in command request block
2010 */
8d2b450d 2011 if (!(tf->flags & ATA_TFLAG_WRITE))
31961943 2012 flags |= CRQB_FLAG_READ;
beec7dbc 2013 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 2014 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 2015 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 2016
bdd4ddde 2017 /* get current queue index from software */
fcfb1f77 2018 in_index = pp->req_idx;
a6432436
ML		 2019
2020 pp->crqb[in_index].sg_addr =
eb73d558 2021 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 2022 pp->crqb[in_index].sg_addr_hi =
eb73d558 2023 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 2024 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 2025
a6432436 2026 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 2027
2028 /* Sadly, the CRQB cannot accomodate all registers--there are
2029 * only 11 bytes...so we must pick and choose required
2030 * registers based on the command. So, we drop feature and
2031 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 2032 * NCQ. NCQ will drop hob_nsect, which is not needed there
2033 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 2034 */
31961943
BR		 2035 switch (tf->command) {
2036 case ATA_CMD_READ:
2037 case ATA_CMD_READ_EXT:
2038 case ATA_CMD_WRITE:
2039 case ATA_CMD_WRITE_EXT:
c15d85c8 2040 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 2041 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2042 break;
31961943
BR		 2043 case ATA_CMD_FPDMA_READ:
2044 case ATA_CMD_FPDMA_WRITE:
8b260248 2045 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 2046 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2047 break;
31961943
BR		 2048 default:
2049 /* The only other commands EDMA supports in non-queued and
2050 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2051 * of which are defined/used by Linux. If we get here, this
2052 * driver needs work.
2053 *
2054 * FIXME: modify libata to give qc_prep a return value and
2055 * return error here.
2056 */
2057 BUG_ON(tf->command);
2058 break;
2059 }
2060 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2061 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2062 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2063 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2064 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2065 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2066 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2067 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2068 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2069
e4e7b892
JG		 2070 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2071 return;
2072 mv_fill_sg(qc);
2073}
2074
2075/**
2076 * mv_qc_prep_iie - Host specific command preparation.
2077 * @qc: queued command to prepare
2078 *
2079 * This routine simply redirects to the general purpose routine
2080 * if command is not DMA. Else, it handles prep of the CRQB
2081 * (command request block), does some sanity checking, and calls
2082 * the SG load routine.
2083 *
2084 * LOCKING:
2085 * Inherited from caller.
2086 */
2087static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2088{
2089 struct ata_port *ap = qc->ap;
2090 struct mv_port_priv *pp = ap->private_data;
2091 struct mv_crqb_iie *crqb;
8d2b450d 2092 struct ata_taskfile *tf = &qc->tf;
a6432436 2093 unsigned in_index;
e4e7b892
JG		 2094 u32 flags = 0;
2095
8d2b450d
ML		 2096 if ((tf->protocol != ATA_PROT_DMA) &&
2097 (tf->protocol != ATA_PROT_NCQ))
e4e7b892
JG		 2098 return;
2099
e12bef50 2100 /* Fill in Gen IIE command request block */
8d2b450d 2101 if (!(tf->flags & ATA_TFLAG_WRITE))
e4e7b892
JG		 2102 flags |= CRQB_FLAG_READ;
2103
beec7dbc 2104 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 2105 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 2106 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 2107 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 2108
bdd4ddde 2109 /* get current queue index from software */
fcfb1f77 2110 in_index = pp->req_idx;
a6432436
ML		 2111
2112 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 2113 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2114 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 2115 crqb->flags = cpu_to_le32(flags);
2116
e4e7b892
JG		 2117 crqb->ata_cmd[0] = cpu_to_le32(
2118 (tf->command << 16) |
2119 (tf->feature << 24)
2120 );
2121 crqb->ata_cmd[1] = cpu_to_le32(
2122 (tf->lbal << 0) |
2123 (tf->lbam << 8) |
2124 (tf->lbah << 16) |
2125 (tf->device << 24)
2126 );
2127 crqb->ata_cmd[2] = cpu_to_le32(
2128 (tf->hob_lbal << 0) |
2129 (tf->hob_lbam << 8) |
2130 (tf->hob_lbah << 16) |
2131 (tf->hob_feature << 24)
2132 );
2133 crqb->ata_cmd[3] = cpu_to_le32(
2134 (tf->nsect << 0) |
2135 (tf->hob_nsect << 8)
2136 );
2137
2138 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 2139 return;
31961943
BR		 2140 mv_fill_sg(qc);
2141}
2142
d16ab3f6
ML		 2143/**
2144 * mv_sff_check_status - fetch device status, if valid
2145 * @ap: ATA port to fetch status from
2146 *
2147 * When using command issue via mv_qc_issue_fis(),
2148 * the initial ATA_BUSY state does not show up in the
2149 * ATA status (shadow) register. This can confuse libata!
2150 *
2151 * So we have a hook here to fake ATA_BUSY for that situation,
2152 * until the first time a BUSY, DRQ, or ERR bit is seen.
2153 *
2154 * The rest of the time, it simply returns the ATA status register.
2155 */
2156static u8 mv_sff_check_status(struct ata_port *ap)
2157{
2158 u8 stat = ioread8(ap->ioaddr.status_addr);
2159 struct mv_port_priv *pp = ap->private_data;
2160
2161 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2162 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2163 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2164 else
2165 stat = ATA_BUSY;
2166 }
2167 return stat;
2168}
2169
70f8b79c
ML		 2170/**
2171 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2172 * @fis: fis to be sent
2173 * @nwords: number of 32-bit words in the fis
2174 */
2175static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2176{
2177 void __iomem *port_mmio = mv_ap_base(ap);
2178 u32 ifctl, old_ifctl, ifstat;
2179 int i, timeout = 200, final_word = nwords - 1;
2180
2181 /* Initiate FIS transmission mode */
cae5a29d 2182 old_ifctl = readl(port_mmio + SATA_IFCTL);
70f8b79c 2183 ifctl = 0x100 | (old_ifctl & 0xf);
cae5a29d 2184 writelfl(ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2185
2186 /* Send all words of the FIS except for the final word */
2187 for (i = 0; i < final_word; ++i)
cae5a29d 2188 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2189
2190 /* Flag end-of-transmission, and then send the final word */
cae5a29d
ML		 2191 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2192 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2193
2194 /*
2195 * Wait for FIS transmission to complete.
2196 * This typically takes just a single iteration.
2197 */
2198 do {
cae5a29d 2199 ifstat = readl(port_mmio + SATA_IFSTAT);
70f8b79c
ML		 2200 } while (!(ifstat & 0x1000) && --timeout);
2201
2202 /* Restore original port configuration */
cae5a29d 2203 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2204
2205 /* See if it worked */
2206 if ((ifstat & 0x3000) != 0x1000) {
2207 ata_port_printk(ap, KERN_WARNING,
2208 "%s transmission error, ifstat=%08x\n",
2209 __func__, ifstat);
2210 return AC_ERR_OTHER;
2211 }
2212 return 0;
2213}
2214
2215/**
2216 * mv_qc_issue_fis - Issue a command directly as a FIS
2217 * @qc: queued command to start
2218 *
2219 * Note that the ATA shadow registers are not updated
2220 * after command issue, so the device will appear "READY"
2221 * if polled, even while it is BUSY processing the command.
2222 *
2223 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2224 *
2225 * Note: we don't get updated shadow regs on *completion*
2226 * of non-data commands. So avoid sending them via this function,
2227 * as they will appear to have completed immediately.
2228 *
2229 * GEN_IIE has special registers that we could get the result tf from,
2230 * but earlier chipsets do not. For now, we ignore those registers.
2231 */
2232static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2233{
2234 struct ata_port *ap = qc->ap;
2235 struct mv_port_priv *pp = ap->private_data;
2236 struct ata_link *link = qc->dev->link;
2237 u32 fis[5];
2238 int err = 0;
2239
2240 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
4c4a90fd 2241 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
70f8b79c
ML		 2242 if (err)
2243 return err;
2244
2245 switch (qc->tf.protocol) {
2246 case ATAPI_PROT_PIO:
2247 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2248 /* fall through */
2249 case ATAPI_PROT_NODATA:
2250 ap->hsm_task_state = HSM_ST_FIRST;
2251 break;
2252 case ATA_PROT_PIO:
2253 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2254 if (qc->tf.flags & ATA_TFLAG_WRITE)
2255 ap->hsm_task_state = HSM_ST_FIRST;
2256 else
2257 ap->hsm_task_state = HSM_ST;
2258 break;
2259 default:
2260 ap->hsm_task_state = HSM_ST_LAST;
2261 break;
2262 }
2263
2264 if (qc->tf.flags & ATA_TFLAG_POLLING)
2265 ata_pio_queue_task(ap, qc, 0);
2266 return 0;
2267}
2268
05b308e1
BR		 2269/**
2270 * mv_qc_issue - Initiate a command to the host
2271 * @qc: queued command to start
2272 *
2273 * This routine simply redirects to the general purpose routine
2274 * if command is not DMA. Else, it sanity checks our local
2275 * caches of the request producer/consumer indices then enables
2276 * DMA and bumps the request producer index.
2277 *
2278 * LOCKING:
2279 * Inherited from caller.
2280 */
9a3d9eb0 2281static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 2282{
f48765cc 2283 static int limit_warnings = 10;
c5d3e45a
JG		 2284 struct ata_port *ap = qc->ap;
2285 void __iomem *port_mmio = mv_ap_base(ap);
2286 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 2287 u32 in_index;
42ed893d 2288 unsigned int port_irqs;
f48765cc 2289
d16ab3f6
ML		 2290 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2291
f48765cc
ML		 2292 switch (qc->tf.protocol) {
2293 case ATA_PROT_DMA:
2294 case ATA_PROT_NCQ:
2295 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2296 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2297 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2298
2299 /* Write the request in pointer to kick the EDMA to life */
2300 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
cae5a29d 2301 port_mmio + EDMA_REQ_Q_IN_PTR);
f48765cc 2302 return 0;
31961943 2303
f48765cc 2304 case ATA_PROT_PIO:
c6112bd8
ML		 2305 /*
2306 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2307 *
2308 * Someday, we might implement special polling workarounds
2309 * for these, but it all seems rather unnecessary since we
2310 * normally use only DMA for commands which transfer more
2311 * than a single block of data.
2312 *
2313 * Much of the time, this could just work regardless.
2314 * So for now, just log the incident, and allow the attempt.
2315 */
c7843e8f 2316 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 2317 --limit_warnings;
2318 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
2319 ": attempting PIO w/multiple DRQ: "
2320 "this may fail due to h/w errata\n");
2321 }
f48765cc 2322 /* drop through */
42ed893d 2323 case ATA_PROT_NODATA:
f48765cc 2324 case ATAPI_PROT_PIO:
42ed893d
ML		 2325 case ATAPI_PROT_NODATA:
2326 if (ap->flags & ATA_FLAG_PIO_POLLING)
2327 qc->tf.flags |= ATA_TFLAG_POLLING;
2328 break;
31961943 2329 }
42ed893d
ML		 2330
2331 if (qc->tf.flags & ATA_TFLAG_POLLING)
2332 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2333 else
2334 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2335
2336 /*
2337 * We're about to send a non-EDMA capable command to the
2338 * port. Turn off EDMA so there won't be problems accessing
2339 * shadow block, etc registers.
2340 */
2341 mv_stop_edma(ap);
2342 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2343 mv_pmp_select(ap, qc->dev->link->pmp);
70f8b79c
ML		 2344
2345 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2346 struct mv_host_priv *hpriv = ap->host->private_data;
2347 /*
2348 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
40f21b11 2349 *
70f8b79c
ML		 2350 * After any NCQ error, the READ_LOG_EXT command
2351 * from libata-eh *must* use mv_qc_issue_fis().
2352 * Otherwise it might fail, due to chip errata.
2353 *
2354 * Rather than special-case it, we'll just *always*
2355 * use this method here for READ_LOG_EXT, making for
2356 * easier testing.
2357 */
2358 if (IS_GEN_II(hpriv))
2359 return mv_qc_issue_fis(qc);
2360 }
42ed893d 2361 return ata_sff_qc_issue(qc);
31961943
BR		 2362}
2363
8f767f8a
ML		 2364static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2365{
2366 struct mv_port_priv *pp = ap->private_data;
2367 struct ata_queued_cmd *qc;
2368
2369 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2370 return NULL;
2371 qc = ata_qc_from_tag(ap, ap->link.active_tag);
3e4ec344
TH		 2372 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2373 return qc;
2374 return NULL;
8f767f8a
ML		 2375}
2376
29d187bb
ML		 2377static void mv_pmp_error_handler(struct ata_port *ap)
2378{
2379 unsigned int pmp, pmp_map;
2380 struct mv_port_priv *pp = ap->private_data;
2381
2382 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2383 /*
2384 * Perform NCQ error analysis on failed PMPs
2385 * before we freeze the port entirely.
2386 *
2387 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2388 */
2389 pmp_map = pp->delayed_eh_pmp_map;
2390 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2391 for (pmp = 0; pmp_map != 0; pmp++) {
2392 unsigned int this_pmp = (1 << pmp);
2393 if (pmp_map & this_pmp) {
2394 struct ata_link *link = &ap->pmp_link[pmp];
2395 pmp_map &= ~this_pmp;
2396 ata_eh_analyze_ncq_error(link);
2397 }
2398 }
2399 ata_port_freeze(ap);
2400 }
2401 sata_pmp_error_handler(ap);
2402}
2403
4c299ca3
ML		 2404static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2405{
2406 void __iomem *port_mmio = mv_ap_base(ap);
2407
cae5a29d 2408 return readl(port_mmio + SATA_TESTCTL) >> 16;
4c299ca3
ML		 2409}
2410
4c299ca3
ML		 2411static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2412{
2413 struct ata_eh_info *ehi;
2414 unsigned int pmp;
2415
2416 /*
2417 * Initialize EH info for PMPs which saw device errors
2418 */
2419 ehi = &ap->link.eh_info;
2420 for (pmp = 0; pmp_map != 0; pmp++) {
2421 unsigned int this_pmp = (1 << pmp);
2422 if (pmp_map & this_pmp) {
2423 struct ata_link *link = &ap->pmp_link[pmp];
2424
2425 pmp_map &= ~this_pmp;
2426 ehi = &link->eh_info;
2427 ata_ehi_clear_desc(ehi);
2428 ata_ehi_push_desc(ehi, "dev err");
2429 ehi->err_mask |= AC_ERR_DEV;
2430 ehi->action |= ATA_EH_RESET;
2431 ata_link_abort(link);
2432 }
2433 }
2434}
2435
06aaca3f
ML		 2436static int mv_req_q_empty(struct ata_port *ap)
2437{
2438 void __iomem *port_mmio = mv_ap_base(ap);
2439 u32 in_ptr, out_ptr;
2440
cae5a29d 2441 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
06aaca3f 2442 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
cae5a29d 2443 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
06aaca3f
ML		 2444 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2445 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2446}
2447
4c299ca3
ML		 2448static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2449{
2450 struct mv_port_priv *pp = ap->private_data;
2451 int failed_links;
2452 unsigned int old_map, new_map;
2453
2454 /*
2455 * Device error during FBS+NCQ operation:
2456 *
2457 * Set a port flag to prevent further I/O being enqueued.
2458 * Leave the EDMA running to drain outstanding commands from this port.
2459 * Perform the post-mortem/EH only when all responses are complete.
2460 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2461 */
2462 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2463 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2464 pp->delayed_eh_pmp_map = 0;
2465 }
2466 old_map = pp->delayed_eh_pmp_map;
2467 new_map = old_map | mv_get_err_pmp_map(ap);
2468
2469 if (old_map != new_map) {
2470 pp->delayed_eh_pmp_map = new_map;
2471 mv_pmp_eh_prep(ap, new_map & ~old_map);
2472 }
c46938cc 2473 failed_links = hweight16(new_map);
4c299ca3
ML		 2474
2475 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2476 "failed_links=%d nr_active_links=%d\n",
2477 __func__, pp->delayed_eh_pmp_map,
2478 ap->qc_active, failed_links,
2479 ap->nr_active_links);
2480
06aaca3f 2481 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 2482 mv_process_crpb_entries(ap, pp);
2483 mv_stop_edma(ap);
2484 mv_eh_freeze(ap);
2485 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2486 return 1; /* handled */
2487 }
2488 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2489 return 1; /* handled */
2490}
2491
2492static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2493{
2494 /*
2495 * Possible future enhancement:
2496 *
2497 * FBS+non-NCQ operation is not yet implemented.
2498 * See related notes in mv_edma_cfg().
2499 *
2500 * Device error during FBS+non-NCQ operation:
2501 *
2502 * We need to snapshot the shadow registers for each failed command.
2503 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2504 */
2505 return 0; /* not handled */
2506}
2507
2508static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2509{
2510 struct mv_port_priv *pp = ap->private_data;
2511
2512 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2513 return 0; /* EDMA was not active: not handled */
2514 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2515 return 0; /* FBS was not active: not handled */
2516
2517 if (!(edma_err_cause & EDMA_ERR_DEV))
2518 return 0; /* non DEV error: not handled */
2519 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2520 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2521 return 0; /* other problems: not handled */
2522
2523 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2524 /*
2525 * EDMA should NOT have self-disabled for this case.
2526 * If it did, then something is wrong elsewhere,
2527 * and we cannot handle it here.
2528 */
2529 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2530 ata_port_printk(ap, KERN_WARNING,
2531 "%s: err_cause=0x%x pp_flags=0x%x\n",
2532 __func__, edma_err_cause, pp->pp_flags);
2533 return 0; /* not handled */
2534 }
2535 return mv_handle_fbs_ncq_dev_err(ap);
2536 } else {
2537 /*
2538 * EDMA should have self-disabled for this case.
2539 * If it did not, then something is wrong elsewhere,
2540 * and we cannot handle it here.
2541 */
2542 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2543 ata_port_printk(ap, KERN_WARNING,
2544 "%s: err_cause=0x%x pp_flags=0x%x\n",
2545 __func__, edma_err_cause, pp->pp_flags);
2546 return 0; /* not handled */
2547 }
2548 return mv_handle_fbs_non_ncq_dev_err(ap);
2549 }
2550 return 0; /* not handled */
2551}
2552
a9010329 2553static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2554{
8f767f8a 2555 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2556 char *when = "idle";
8f767f8a 2557
8f767f8a 2558 ata_ehi_clear_desc(ehi);
3e4ec344 2559 if (edma_was_enabled) {
a9010329 2560 when = "EDMA enabled";
8f767f8a
ML		 2561 } else {
2562 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2563 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2564 when = "polling";
8f767f8a 2565 }
a9010329 2566 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2567 ehi->err_mask |= AC_ERR_OTHER;
2568 ehi->action |= ATA_EH_RESET;
2569 ata_port_freeze(ap);
2570}
2571
05b308e1
BR		 2572/**
2573 * mv_err_intr - Handle error interrupts on the port
2574 * @ap: ATA channel to manipulate
2575 *
8d07379d
ML		 2576 * Most cases require a full reset of the chip's state machine,
2577 * which also performs a COMRESET.
2578 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2579 *
2580 * LOCKING:
2581 * Inherited from caller.
2582 */
37b9046a 2583static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2584{
2585 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2586 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2587 u32 fis_cause = 0;
bdd4ddde
JG		 2588 struct mv_port_priv *pp = ap->private_data;
2589 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2590 unsigned int action = 0, err_mask = 0;
9af5c9c9 2591 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2592 struct ata_queued_cmd *qc;
2593 int abort = 0;
20f733e7 2594
8d07379d 2595 /*
37b9046a 2596 * Read and clear the SError and err_cause bits.
e4006077
ML		 2597 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2598 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2599 */
37b9046a
ML		 2600 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2601 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2602
cae5a29d 2603 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
e4006077 2604 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
cae5a29d
ML		 2605 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2606 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
e4006077 2607 }
cae5a29d 2608 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde 2609
4c299ca3
ML		 2610 if (edma_err_cause & EDMA_ERR_DEV) {
2611 /*
2612 * Device errors during FIS-based switching operation
2613 * require special handling.
2614 */
2615 if (mv_handle_dev_err(ap, edma_err_cause))
2616 return;
2617 }
2618
37b9046a
ML		 2619 qc = mv_get_active_qc(ap);
2620 ata_ehi_clear_desc(ehi);
2621 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2622 edma_err_cause, pp->pp_flags);
e4006077 2623
c443c500 2624 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2625 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
cae5a29d 2626 if (fis_cause & FIS_IRQ_CAUSE_AN) {
c443c500
ML		 2627 u32 ec = edma_err_cause &
2628 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2629 sata_async_notification(ap);
2630 if (!ec)
2631 return; /* Just an AN; no need for the nukes */
2632 ata_ehi_push_desc(ehi, "SDB notify");
2633 }
2634 }
bdd4ddde 2635 /*
352fab70 2636 * All generations share these EDMA error cause bits:
bdd4ddde 2637 */
37b9046a 2638 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2639 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2640 action |= ATA_EH_RESET;
2641 ata_ehi_push_desc(ehi, "dev error");
2642 }
bdd4ddde 2643 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2644 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2645 EDMA_ERR_INTRL_PAR)) {
2646 err_mask |= AC_ERR_ATA_BUS;
cf480626 2647 action |= ATA_EH_RESET;
b64bbc39 2648 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2649 }
2650 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2651 ata_ehi_hotplugged(ehi);
2652 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2653 "dev disconnect" : "dev connect");
cf480626 2654 action |= ATA_EH_RESET;
bdd4ddde
JG		 2655 }
2656
352fab70
ML		 2657 /*
2658 * Gen-I has a different SELF_DIS bit,
2659 * different FREEZE bits, and no SERR bit:
2660 */
ee9ccdf7 2661 if (IS_GEN_I(hpriv)) {
bdd4ddde 2662 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2663 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2664 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2665 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2666 }
2667 } else {
2668 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2669 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2670 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2671 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2672 }
bdd4ddde 2673 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2674 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2675 err_mask |= AC_ERR_ATA_BUS;
cf480626 2676 action |= ATA_EH_RESET;
bdd4ddde 2677 }
afb0edd9 2678 }
20f733e7 2679
bdd4ddde
JG		 2680 if (!err_mask) {
2681 err_mask = AC_ERR_OTHER;
cf480626 2682 action |= ATA_EH_RESET;
bdd4ddde
JG		 2683 }
2684
2685 ehi->serror |= serr;
2686 ehi->action |= action;
2687
2688 if (qc)
2689 qc->err_mask |= err_mask;
2690 else
2691 ehi->err_mask |= err_mask;
2692
37b9046a
ML		 2693 if (err_mask == AC_ERR_DEV) {
2694 /*
2695 * Cannot do ata_port_freeze() here,
2696 * because it would kill PIO access,
2697 * which is needed for further diagnosis.
2698 */
2699 mv_eh_freeze(ap);
2700 abort = 1;
2701 } else if (edma_err_cause & eh_freeze_mask) {
2702 /*
2703 * Note to self: ata_port_freeze() calls ata_port_abort()
2704 */
bdd4ddde 2705 ata_port_freeze(ap);
37b9046a
ML		 2706 } else {
2707 abort = 1;
2708 }
2709
2710 if (abort) {
2711 if (qc)
2712 ata_link_abort(qc->dev->link);
2713 else
2714 ata_port_abort(ap);
2715 }
bdd4ddde
JG		 2716}
2717
fcfb1f77
ML		 2718static void mv_process_crpb_response(struct ata_port *ap,
2719 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2720{
2721 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2722
2723 if (qc) {
2724 u8 ata_status;
2725 u16 edma_status = le16_to_cpu(response->flags);
2726 /*
2727 * edma_status from a response queue entry:
cae5a29d 2728 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
fcfb1f77
ML		 2729 * MSB is saved ATA status from command completion.
2730 */
2731 if (!ncq_enabled) {
2732 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2733 if (err_cause) {
2734 /*
2735 * Error will be seen/handled by mv_err_intr().
2736 * So do nothing at all here.
2737 */
2738 return;
2739 }
2740 }
2741 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2742 if (!ac_err_mask(ata_status))
2743 ata_qc_complete(qc);
2744 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2745 } else {
2746 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2747 __func__, tag);
2748 }
2749}
2750
2751static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2752{
2753 void __iomem *port_mmio = mv_ap_base(ap);
2754 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2755 u32 in_index;
bdd4ddde 2756 bool work_done = false;
fcfb1f77 2757 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2758
fcfb1f77 2759 /* Get the hardware queue position index */
cae5a29d 2760 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
bdd4ddde
JG		 2761 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2762
fcfb1f77
ML		 2763 /* Process new responses from since the last time we looked */
2764 while (in_index != pp->resp_idx) {
6c1153e0 2765 unsigned int tag;
fcfb1f77 2766 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2767
fcfb1f77 2768 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2769
fcfb1f77
ML		 2770 if (IS_GEN_I(hpriv)) {
2771 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2772 tag = ap->link.active_tag;
fcfb1f77
ML		 2773 } else {
2774 /* Gen II/IIE: get command tag from CRPB entry */
2775 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2776 }
fcfb1f77 2777 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2778 work_done = true;
bdd4ddde
JG		 2779 }
2780
352fab70 2781 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2782 if (work_done)
2783 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2784 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
cae5a29d 2785 port_mmio + EDMA_RSP_Q_OUT_PTR);
20f733e7
BR		 2786}
2787
a9010329
ML		 2788static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2789{
2790 struct mv_port_priv *pp;
2791 int edma_was_enabled;
2792
a9010329
ML		 2793 /*
2794 * Grab a snapshot of the EDMA_EN flag setting,
2795 * so that we have a consistent view for this port,
2796 * even if something we call of our routines changes it.
2797 */
2798 pp = ap->private_data;
2799 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2800 /*
2801 * Process completed CRPB response(s) before other events.
2802 */
2803 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2804 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2805 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2806 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2807 }
2808 /*
2809 * Handle chip-reported errors, or continue on to handle PIO.
2810 */
2811 if (unlikely(port_cause & ERR_IRQ)) {
2812 mv_err_intr(ap);
2813 } else if (!edma_was_enabled) {
2814 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2815 if (qc)
2816 ata_sff_host_intr(ap, qc);
2817 else
2818 mv_unexpected_intr(ap, edma_was_enabled);
2819 }
2820}
2821
05b308e1
BR		 2822/**
2823 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2824 * @host: host specific structure
7368f919 2825 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2826 *
2827 * LOCKING:
2828 * Inherited from caller.
2829 */
7368f919 2830static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2831{
f351b2d6 2832 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2833 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2834 unsigned int handled = 0, port;
20f733e7 2835
2b748a0a
ML		 2836 /* If asserted, clear the "all ports" IRQ coalescing bit */
2837 if (main_irq_cause & ALL_PORTS_COAL_DONE)
cae5a29d 2838 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2b748a0a 2839
a3718c1f 2840 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2841 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2842 unsigned int p, shift, hardport, port_cause;
2843
a3718c1f 2844 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2845 /*
eabd5eb1
ML		 2846 * Each hc within the host has its own hc_irq_cause register,
2847 * where the interrupting ports bits get ack'd.
a3718c1f 2848 */
eabd5eb1
ML		 2849 if (hardport == 0) { /* first port on this hc ? */
2850 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2851 u32 port_mask, ack_irqs;
2852 /*
2853 * Skip this entire hc if nothing pending for any ports
2854 */
2855 if (!hc_cause) {
2856 port += MV_PORTS_PER_HC - 1;
2857 continue;
2858 }
2859 /*
2860 * We don't need/want to read the hc_irq_cause register,
2861 * because doing so hurts performance, and
2862 * main_irq_cause already gives us everything we need.
2863 *
2864 * But we do have to *write* to the hc_irq_cause to ack
2865 * the ports that we are handling this time through.
2866 *
2867 * This requires that we create a bitmap for those
2868 * ports which interrupted us, and use that bitmap
2869 * to ack (only) those ports via hc_irq_cause.
2870 */
2871 ack_irqs = 0;
2b748a0a
ML		 2872 if (hc_cause & PORTS_0_3_COAL_DONE)
2873 ack_irqs = HC_COAL_IRQ;
eabd5eb1
ML		 2874 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2875 if ((port + p) >= hpriv->n_ports)
2876 break;
2877 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2878 if (hc_cause & port_mask)
2879 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2880 }
a3718c1f 2881 hc_mmio = mv_hc_base_from_port(mmio, port);
cae5a29d 2882 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
a3718c1f
ML		 2883 handled = 1;
2884 }
8f767f8a 2885 /*
a9010329 2886 * Handle interrupts signalled for this port:
8f767f8a 2887 */
a9010329
ML		 2888 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2889 if (port_cause)
2890 mv_port_intr(ap, port_cause);
20f733e7 2891 }
a3718c1f 2892 return handled;
20f733e7
BR		 2893}
2894
a3718c1f 2895static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2896{
02a121da 2897 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2898 struct ata_port *ap;
2899 struct ata_queued_cmd *qc;
2900 struct ata_eh_info *ehi;
2901 unsigned int i, err_mask, printed = 0;
2902 u32 err_cause;
2903
cae5a29d 2904 err_cause = readl(mmio + hpriv->irq_cause_offset);
bdd4ddde
JG		 2905
2906 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2907 err_cause);
2908
2909 DPRINTK("All regs @ PCI error\n");
2910 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2911
cae5a29d 2912 writelfl(0, mmio + hpriv->irq_cause_offset);
bdd4ddde
JG		 2913
2914 for (i = 0; i < host->n_ports; i++) {
2915 ap = host->ports[i];
936fd732 2916 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2917 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2918 ata_ehi_clear_desc(ehi);
2919 if (!printed++)
2920 ata_ehi_push_desc(ehi,
2921 "PCI err cause 0x%08x", err_cause);
2922 err_mask = AC_ERR_HOST_BUS;
cf480626 2923 ehi->action = ATA_EH_RESET;
9af5c9c9 2924 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2925 if (qc)
2926 qc->err_mask |= err_mask;
2927 else
2928 ehi->err_mask |= err_mask;
2929
2930 ata_port_freeze(ap);
2931 }
2932 }
a3718c1f 2933 return 1; /* handled */
bdd4ddde
JG		 2934}
2935
05b308e1 2936/**
c5d3e45a 2937 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2938 * @irq: unused
2939 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2940 *
2941 * Read the read only register to determine if any host
2942 * controllers have pending interrupts. If so, call lower level
2943 * routine to handle. Also check for PCI errors which are only
2944 * reported here.
2945 *
8b260248 2946 * LOCKING:
cca3974e 2947 * This routine holds the host lock while processing pending
05b308e1
BR		 2948 * interrupts.
2949 */
7d12e780 2950static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2951{
cca3974e 2952 struct ata_host *host = dev_instance;
f351b2d6 2953 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2954 unsigned int handled = 0;
6d3c30ef 2955 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2956 u32 main_irq_cause, pending_irqs;
20f733e7 2957
646a4da5 2958 spin_lock(&host->lock);
6d3c30ef
ML		 2959
2960 /* for MSI: block new interrupts while in here */
2961 if (using_msi)
2b748a0a 2962 mv_write_main_irq_mask(0, hpriv);
6d3c30ef 2963
7368f919 2964 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2965 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2966 /*
2967 * Deal with cases where we either have nothing pending, or have read
2968 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2969 */
a44253d2 2970 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2971 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2972 handled = mv_pci_error(host, hpriv->base);
2973 else
a44253d2 2974 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2975 }
6d3c30ef
ML		 2976
2977 /* for MSI: unmask; interrupt cause bits will retrigger now */
2978 if (using_msi)
2b748a0a 2979 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
6d3c30ef 2980
9d51af7b
ML		 2981 spin_unlock(&host->lock);
2982
20f733e7
BR		 2983 return IRQ_RETVAL(handled);
2984}
2985
c9d39130
JG		 2986static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2987{
2988 unsigned int ofs;
2989
2990 switch (sc_reg_in) {
2991 case SCR_STATUS:
2992 case SCR_ERROR:
2993 case SCR_CONTROL:
2994 ofs = sc_reg_in * sizeof(u32);
2995 break;
2996 default:
2997 ofs = 0xffffffffU;
2998 break;
2999 }
3000 return ofs;
3001}
3002
82ef04fb 3003static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 3004{
82ef04fb 3005 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 3006 void __iomem *mmio = hpriv->base;
82ef04fb 3007 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 3008 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3009
da3dbb17
TH		 3010 if (ofs != 0xffffffffU) {
3011 *val = readl(addr + ofs);
3012 return 0;
3013 } else
3014 return -EINVAL;
c9d39130
JG		 3015}
3016
82ef04fb 3017static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 3018{
82ef04fb 3019 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 3020 void __iomem *mmio = hpriv->base;
82ef04fb 3021 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 3022 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3023
da3dbb17 3024 if (ofs != 0xffffffffU) {
0d5ff566 3025 writelfl(val, addr + ofs);
da3dbb17
TH		 3026 return 0;
3027 } else
3028 return -EINVAL;
c9d39130
JG		 3029}
3030
7bb3c529 3031static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 3032{
7bb3c529 3033 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 3034 int early_5080;
3035
44c10138 3036 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 3037
3038 if (!early_5080) {
3039 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3040 tmp |= (1 << 0);
3041 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3042 }
3043
7bb3c529 3044 mv_reset_pci_bus(host, mmio);
522479fb
JG		 3045}
3046
3047static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3048{
cae5a29d 3049 writel(0x0fcfffff, mmio + FLASH_CTL);
522479fb
JG		 3050}
3051
47c2b677 3052static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3053 void __iomem *mmio)
3054{
c9d39130
JG		 3055 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3056 u32 tmp;
3057
3058 tmp = readl(phy_mmio + MV5_PHY_MODE);
3059
3060 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3061 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 3062}
3063
47c2b677 3064static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3065{
522479fb
JG		 3066 u32 tmp;
3067
cae5a29d 3068 writel(0, mmio + GPIO_PORT_CTL);
522479fb
JG		 3069
3070 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3071
3072 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3073 tmp |= ~(1 << 0);
3074 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 3075}
3076
2a47ce06
JG		 3077static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3078 unsigned int port)
bca1c4eb 3079{
c9d39130
JG		 3080 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3081 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3082 u32 tmp;
3083 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3084
3085 if (fix_apm_sq) {
cae5a29d 3086 tmp = readl(phy_mmio + MV5_LTMODE);
c9d39130 3087 tmp |= (1 << 19);
cae5a29d 3088 writel(tmp, phy_mmio + MV5_LTMODE);
c9d39130 3089
cae5a29d 3090 tmp = readl(phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3091 tmp &= ~0x3;
3092 tmp |= 0x1;
cae5a29d 3093 writel(tmp, phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3094 }
3095
3096 tmp = readl(phy_mmio + MV5_PHY_MODE);
3097 tmp &= ~mask;
3098 tmp |= hpriv->signal[port].pre;
3099 tmp |= hpriv->signal[port].amps;
3100 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 3101}
3102
c9d39130
JG		 3103
3104#undef ZERO
3105#define ZERO(reg) writel(0, port_mmio + (reg))
3106static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3107 unsigned int port)
3108{
3109 void __iomem *port_mmio = mv_port_base(mmio, port);
3110
e12bef50 3111 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 3112
3113 ZERO(0x028); /* command */
cae5a29d 3114 writel(0x11f, port_mmio + EDMA_CFG);
c9d39130
JG		 3115 ZERO(0x004); /* timer */
3116 ZERO(0x008); /* irq err cause */
3117 ZERO(0x00c); /* irq err mask */
3118 ZERO(0x010); /* rq bah */
3119 ZERO(0x014); /* rq inp */
3120 ZERO(0x018); /* rq outp */
3121 ZERO(0x01c); /* respq bah */
3122 ZERO(0x024); /* respq outp */
3123 ZERO(0x020); /* respq inp */
3124 ZERO(0x02c); /* test control */
cae5a29d 3125 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
c9d39130
JG		 3126}
3127#undef ZERO
3128
3129#define ZERO(reg) writel(0, hc_mmio + (reg))
3130static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3131 unsigned int hc)
47c2b677 3132{
c9d39130
JG		 3133 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3134 u32 tmp;
3135
3136 ZERO(0x00c);
3137 ZERO(0x010);
3138 ZERO(0x014);
3139 ZERO(0x018);
3140
3141 tmp = readl(hc_mmio + 0x20);
3142 tmp &= 0x1c1c1c1c;
3143 tmp |= 0x03030303;
3144 writel(tmp, hc_mmio + 0x20);
3145}
3146#undef ZERO
3147
3148static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3149 unsigned int n_hc)
3150{
3151 unsigned int hc, port;
3152
3153 for (hc = 0; hc < n_hc; hc++) {
3154 for (port = 0; port < MV_PORTS_PER_HC; port++)
3155 mv5_reset_hc_port(hpriv, mmio,
3156 (hc * MV_PORTS_PER_HC) + port);
3157
3158 mv5_reset_one_hc(hpriv, mmio, hc);
3159 }
3160
3161 return 0;
47c2b677
JG		 3162}
3163
101ffae2
JG		 3164#undef ZERO
3165#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 3166static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 3167{
02a121da 3168 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 3169 u32 tmp;
3170
cae5a29d 3171 tmp = readl(mmio + MV_PCI_MODE);
101ffae2 3172 tmp &= 0xff00ffff;
cae5a29d 3173 writel(tmp, mmio + MV_PCI_MODE);
101ffae2
JG		 3174
3175 ZERO(MV_PCI_DISC_TIMER);
3176 ZERO(MV_PCI_MSI_TRIGGER);
cae5a29d 3177 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
101ffae2 3178 ZERO(MV_PCI_SERR_MASK);
cae5a29d
ML		 3179 ZERO(hpriv->irq_cause_offset);
3180 ZERO(hpriv->irq_mask_offset);
101ffae2
JG		 3181 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3182 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3183 ZERO(MV_PCI_ERR_ATTRIBUTE);
3184 ZERO(MV_PCI_ERR_COMMAND);
3185}
3186#undef ZERO
3187
3188static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3189{
3190 u32 tmp;
3191
3192 mv5_reset_flash(hpriv, mmio);
3193
cae5a29d 3194 tmp = readl(mmio + GPIO_PORT_CTL);
101ffae2
JG		 3195 tmp &= 0x3;
3196 tmp |= (1 << 5) | (1 << 6);
cae5a29d 3197 writel(tmp, mmio + GPIO_PORT_CTL);
101ffae2
JG		 3198}
3199
3200/**
3201 * mv6_reset_hc - Perform the 6xxx global soft reset
3202 * @mmio: base address of the HBA
3203 *
3204 * This routine only applies to 6xxx parts.
3205 *
3206 * LOCKING:
3207 * Inherited from caller.
3208 */
c9d39130
JG		 3209static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3210 unsigned int n_hc)
101ffae2 3211{
cae5a29d 3212 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
101ffae2
JG		 3213 int i, rc = 0;
3214 u32 t;
3215
3216 /* Following procedure defined in PCI "main command and status
3217 * register" table.
3218 */
3219 t = readl(reg);
3220 writel(t | STOP_PCI_MASTER, reg);
3221
3222 for (i = 0; i < 1000; i++) {
3223 udelay(1);
3224 t = readl(reg);
2dcb407e 3225 if (PCI_MASTER_EMPTY & t)
101ffae2 3226 break;
101ffae2
JG		 3227 }
3228 if (!(PCI_MASTER_EMPTY & t)) {
3229 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3230 rc = 1;
3231 goto done;
3232 }
3233
3234 /* set reset */
3235 i = 5;
3236 do {
3237 writel(t | GLOB_SFT_RST, reg);
3238 t = readl(reg);
3239 udelay(1);
3240 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3241
3242 if (!(GLOB_SFT_RST & t)) {
3243 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3244 rc = 1;
3245 goto done;
3246 }
3247
3248 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3249 i = 5;
3250 do {
3251 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3252 t = readl(reg);
3253 udelay(1);
3254 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3255
3256 if (GLOB_SFT_RST & t) {
3257 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3258 rc = 1;
3259 }
3260done:
3261 return rc;
3262}
3263
47c2b677 3264static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3265 void __iomem *mmio)
3266{
3267 void __iomem *port_mmio;
3268 u32 tmp;
3269
cae5a29d 3270 tmp = readl(mmio + RESET_CFG);
ba3fe8fb 3271 if ((tmp & (1 << 0)) == 0) {
47c2b677 3272 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 3273 hpriv->signal[idx].pre = 0x1 << 5;
3274 return;
3275 }
3276
3277 port_mmio = mv_port_base(mmio, idx);
3278 tmp = readl(port_mmio + PHY_MODE2);
3279
3280 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3281 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3282}
3283
47c2b677 3284static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3285{
cae5a29d 3286 writel(0x00000060, mmio + GPIO_PORT_CTL);
ba3fe8fb
JG		 3287}
3288
c9d39130 3289static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 3290 unsigned int port)
bca1c4eb 3291{
c9d39130
JG		 3292 void __iomem *port_mmio = mv_port_base(mmio, port);
3293
bca1c4eb 3294 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 3295 int fix_phy_mode2 =
3296 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 3297 int fix_phy_mode4 =
47c2b677 3298 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 3299 u32 m2, m3;
47c2b677
JG		 3300
3301 if (fix_phy_mode2) {
3302 m2 = readl(port_mmio + PHY_MODE2);
3303 m2 &= ~(1 << 16);
3304 m2 |= (1 << 31);
3305 writel(m2, port_mmio + PHY_MODE2);
3306
3307 udelay(200);
3308
3309 m2 = readl(port_mmio + PHY_MODE2);
3310 m2 &= ~((1 << 16) | (1 << 31));
3311 writel(m2, port_mmio + PHY_MODE2);
3312
3313 udelay(200);
3314 }
3315
8c30a8b9
ML		 3316 /*
3317 * Gen-II/IIe PHY_MODE3 errata RM#2:
3318 * Achieves better receiver noise performance than the h/w default:
3319 */
3320 m3 = readl(port_mmio + PHY_MODE3);
3321 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 3322
0388a8c0
ML		 3323 /* Guideline 88F5182 (GL# SATA-S11) */
3324 if (IS_SOC(hpriv))
3325 m3 &= ~0x1c;
3326
bca1c4eb 3327 if (fix_phy_mode4) {
ba069e37
ML		 3328 u32 m4 = readl(port_mmio + PHY_MODE4);
3329 /*
3330 * Enforce reserved-bit restrictions on GenIIe devices only.
3331 * For earlier chipsets, force only the internal config field
3332 * (workaround for errata FEr SATA#10 part 1).
3333 */
8c30a8b9 3334 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 3335 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3336 else
3337 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 3338 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 3339 }
b406c7a6
ML		 3340 /*
3341 * Workaround for 60x1-B2 errata SATA#13:
3342 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3343 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
ba68460b 3344 * Or ensure we use writelfl() when writing PHY_MODE4.
b406c7a6
ML		 3345 */
3346 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 3347
3348 /* Revert values of pre-emphasis and signal amps to the saved ones */
3349 m2 = readl(port_mmio + PHY_MODE2);
3350
3351 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 3352 m2 |= hpriv->signal[port].amps;
3353 m2 |= hpriv->signal[port].pre;
47c2b677 3354 m2 &= ~(1 << 16);
bca1c4eb 3355
e4e7b892
JG		 3356 /* according to mvSata 3.6.1, some IIE values are fixed */
3357 if (IS_GEN_IIE(hpriv)) {
3358 m2 &= ~0xC30FF01F;
3359 m2 |= 0x0000900F;
3360 }
3361
bca1c4eb
JG		 3362 writel(m2, port_mmio + PHY_MODE2);
3363}
3364
f351b2d6
SB		 3365/* TODO: use the generic LED interface to configure the SATA Presence */
3366/* & Acitivy LEDs on the board */
3367static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3368 void __iomem *mmio)
3369{
3370 return;
3371}
3372
3373static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3374 void __iomem *mmio)
3375{
3376 void __iomem *port_mmio;
3377 u32 tmp;
3378
3379 port_mmio = mv_port_base(mmio, idx);
3380 tmp = readl(port_mmio + PHY_MODE2);
3381
3382 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3383 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3384}
3385
3386#undef ZERO
3387#define ZERO(reg) writel(0, port_mmio + (reg))
3388static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3389 void __iomem *mmio, unsigned int port)
3390{
3391 void __iomem *port_mmio = mv_port_base(mmio, port);
3392
e12bef50 3393 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 3394
3395 ZERO(0x028); /* command */
cae5a29d 3396 writel(0x101f, port_mmio + EDMA_CFG);
f351b2d6
SB		 3397 ZERO(0x004); /* timer */
3398 ZERO(0x008); /* irq err cause */
3399 ZERO(0x00c); /* irq err mask */
3400 ZERO(0x010); /* rq bah */
3401 ZERO(0x014); /* rq inp */
3402 ZERO(0x018); /* rq outp */
3403 ZERO(0x01c); /* respq bah */
3404 ZERO(0x024); /* respq outp */
3405 ZERO(0x020); /* respq inp */
3406 ZERO(0x02c); /* test control */
d7b0c143 3407 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
f351b2d6
SB		 3408}
3409
3410#undef ZERO
3411
3412#define ZERO(reg) writel(0, hc_mmio + (reg))
3413static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3414 void __iomem *mmio)
3415{
3416 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3417
3418 ZERO(0x00c);
3419 ZERO(0x010);
3420 ZERO(0x014);
3421
3422}
3423
3424#undef ZERO
3425
3426static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3427 void __iomem *mmio, unsigned int n_hc)
3428{
3429 unsigned int port;
3430
3431 for (port = 0; port < hpriv->n_ports; port++)
3432 mv_soc_reset_hc_port(hpriv, mmio, port);
3433
3434 mv_soc_reset_one_hc(hpriv, mmio);
3435
3436 return 0;
3437}
3438
3439static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3440 void __iomem *mmio)
3441{
3442 return;
3443}
3444
3445static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3446{
3447 return;
3448}
3449
29b7e43c
MM		 3450static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3451 void __iomem *mmio, unsigned int port)
3452{
3453 void __iomem *port_mmio = mv_port_base(mmio, port);
3454 u32 reg;
3455
3456 reg = readl(port_mmio + PHY_MODE3);
3457 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3458 reg |= (0x1 << 27);
3459 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3460 reg |= (0x1 << 29);
3461 writel(reg, port_mmio + PHY_MODE3);
3462
3463 reg = readl(port_mmio + PHY_MODE4);
3464 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3465 reg |= (0x1 << 16);
3466 writel(reg, port_mmio + PHY_MODE4);
3467
3468 reg = readl(port_mmio + PHY_MODE9_GEN2);
3469 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3470 reg |= 0x8;
3471 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3472 writel(reg, port_mmio + PHY_MODE9_GEN2);
3473
3474 reg = readl(port_mmio + PHY_MODE9_GEN1);
3475 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3476 reg |= 0x8;
3477 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3478 writel(reg, port_mmio + PHY_MODE9_GEN1);
3479}
3480
3481/**
3482 * soc_is_65 - check if the soc is 65 nano device
3483 *
3484 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3485 * register, this register should contain non-zero value and it exists only
3486 * in the 65 nano devices, when reading it from older devices we get 0.
3487 */
3488static bool soc_is_65n(struct mv_host_priv *hpriv)
3489{
3490 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3491
3492 if (readl(port0_mmio + PHYCFG_OFS))
3493 return true;
3494 return false;
3495}
3496
8e7decdb 3497static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 3498{
cae5a29d 3499 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
b67a1064 3500
8e7decdb 3501 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 3502 if (want_gen2i)
8e7decdb 3503 ifcfg |= (1 << 7); /* enable gen2i speed */
cae5a29d 3504 writelfl(ifcfg, port_mmio + SATA_IFCFG);
b67a1064
ML		 3505}
3506
e12bef50 3507static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 3508 unsigned int port_no)
3509{
3510 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3511
8e7decdb
ML		 3512 /*
3513 * The datasheet warns against setting EDMA_RESET when EDMA is active
3514 * (but doesn't say what the problem might be). So we first try
3515 * to disable the EDMA engine before doing the EDMA_RESET operation.
3516 */
0d8be5cb 3517 mv_stop_edma_engine(port_mmio);
cae5a29d 3518 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
c9d39130 3519
b67a1064 3520 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 3521 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3522 mv_setup_ifcfg(port_mmio, 1);
c9d39130 3523 }
b67a1064 3524 /*
8e7decdb 3525 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064 3526 * link, and physical layers. It resets all SATA interface registers
cae5a29d 3527 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
c9d39130 3528 */
cae5a29d 3529 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
b67a1064 3530 udelay(25); /* allow reset propagation */
cae5a29d 3531 writelfl(0, port_mmio + EDMA_CMD);
c9d39130
JG		 3532
3533 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3534
ee9ccdf7 3535 if (IS_GEN_I(hpriv))
c9d39130
JG		 3536 mdelay(1);
3537}
3538
e49856d8 3539static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 3540{
e49856d8
ML		 3541 if (sata_pmp_supported(ap)) {
3542 void __iomem *port_mmio = mv_ap_base(ap);
cae5a29d 3543 u32 reg = readl(port_mmio + SATA_IFCTL);
e49856d8 3544 int old = reg & 0xf;
22374677 3545
e49856d8
ML		 3546 if (old != pmp) {
3547 reg = (reg & ~0xf) | pmp;
cae5a29d 3548 writelfl(reg, port_mmio + SATA_IFCTL);
e49856d8 3549 }
22374677 3550 }
20f733e7
BR		 3551}
3552
e49856d8
ML		 3553static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3554 unsigned long deadline)
22374677 3555{
e49856d8
ML		 3556 mv_pmp_select(link->ap, sata_srst_pmp(link));
3557 return sata_std_hardreset(link, class, deadline);
3558}
bdd4ddde 3559
e49856d8
ML		 3560static int mv_softreset(struct ata_link *link, unsigned int *class,
3561 unsigned long deadline)
3562{
3563 mv_pmp_select(link->ap, sata_srst_pmp(link));
3564 return ata_sff_softreset(link, class, deadline);
22374677
JG		 3565}
3566
cc0680a5 3567static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 3568 unsigned long deadline)
31961943 3569{
cc0680a5 3570 struct ata_port *ap = link->ap;
bdd4ddde 3571 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 3572 struct mv_port_priv *pp = ap->private_data;
f351b2d6 3573 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 3574 int rc, attempts = 0, extra = 0;
3575 u32 sstatus;
3576 bool online;
31961943 3577
e12bef50 3578 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 3579 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
d16ab3f6
ML		 3580 pp->pp_flags &=
3581 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
bdd4ddde 3582
0d8be5cb
ML		 3583 /* Workaround for errata FEr SATA#10 (part 2) */
3584 do {
17c5aab5
ML		 3585 const unsigned long *timing =
3586 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 3587
17c5aab5
ML		 3588 rc = sata_link_hardreset(link, timing, deadline + extra,
3589 &online, NULL);
9dcffd99 3590 rc = online ? -EAGAIN : rc;
17c5aab5 3591 if (rc)
0d8be5cb 3592 return rc;
0d8be5cb
ML		 3593 sata_scr_read(link, SCR_STATUS, &sstatus);
3594 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3595 /* Force 1.5gb/s link speed and try again */
8e7decdb 3596 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 3597 if (time_after(jiffies + HZ, deadline))
3598 extra = HZ; /* only extend it once, max */
3599 }
3600 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
08da1759 3601 mv_save_cached_regs(ap);
66e57a2c 3602 mv_edma_cfg(ap, 0, 0);
bdd4ddde 3603
17c5aab5 3604 return rc;
bdd4ddde
JG		 3605}
3606
bdd4ddde
JG		 3607static void mv_eh_freeze(struct ata_port *ap)
3608{
1cfd19ae 3609 mv_stop_edma(ap);
c4de573b 3610 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3611}
3612
3613static void mv_eh_thaw(struct ata_port *ap)
3614{
f351b2d6 3615 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3616 unsigned int port = ap->port_no;
3617 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3618 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3619 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3620 u32 hc_irq_cause;
bdd4ddde 3621
bdd4ddde 3622 /* clear EDMA errors on this port */
cae5a29d 3623 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde
JG		 3624
3625 /* clear pending irq events */
cae6edc3 3626 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 3627 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
bdd4ddde 3628
88e675e1 3629 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3630}
3631
05b308e1
BR		 3632/**
3633 * mv_port_init - Perform some early initialization on a single port.
3634 * @port: libata data structure storing shadow register addresses
3635 * @port_mmio: base address of the port
3636 *
3637 * Initialize shadow register mmio addresses, clear outstanding
3638 * interrupts on the port, and unmask interrupts for the future
3639 * start of the port.
3640 *
3641 * LOCKING:
3642 * Inherited from caller.
3643 */
31961943 3644static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3645{
cae5a29d 3646 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
31961943 3647
8b260248 3648 /* PIO related setup
31961943
BR		 3649 */
3650 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3651 port->error_addr =
31961943
BR		 3652 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3653 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3654 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3655 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3656 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3657 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3658 port->status_addr =
31961943
BR		 3659 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3660 /* special case: control/altstatus doesn't have ATA_REG_ address */
cae5a29d 3661 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
31961943 3662
31961943 3663 /* Clear any currently outstanding port interrupt conditions */
cae5a29d
ML		 3664 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3665 writelfl(readl(serr), serr);
3666 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
31961943 3667
646a4da5 3668 /* unmask all non-transient EDMA error interrupts */
cae5a29d 3669 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
20f733e7 3670
8b260248 3671 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
cae5a29d
ML		 3672 readl(port_mmio + EDMA_CFG),
3673 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3674 readl(port_mmio + EDMA_ERR_IRQ_MASK));
20f733e7
BR		 3675}
3676
616d4a98
ML		 3677static unsigned int mv_in_pcix_mode(struct ata_host *host)
3678{
3679 struct mv_host_priv *hpriv = host->private_data;
3680 void __iomem *mmio = hpriv->base;
3681 u32 reg;
3682
1f398472 3683 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98 3684 return 0; /* not PCI-X capable */
cae5a29d 3685 reg = readl(mmio + MV_PCI_MODE);
616d4a98
ML		 3686 if ((reg & MV_PCI_MODE_MASK) == 0)
3687 return 0; /* conventional PCI mode */
3688 return 1; /* chip is in PCI-X mode */
3689}
3690
3691static int mv_pci_cut_through_okay(struct ata_host *host)
3692{
3693 struct mv_host_priv *hpriv = host->private_data;
3694 void __iomem *mmio = hpriv->base;
3695 u32 reg;
3696
3697 if (!mv_in_pcix_mode(host)) {
cae5a29d
ML		 3698 reg = readl(mmio + MV_PCI_COMMAND);
3699 if (reg & MV_PCI_COMMAND_MRDTRIG)
616d4a98
ML		 3700 return 0; /* not okay */
3701 }
3702 return 1; /* okay */
3703}
3704
65ad7fef
ML		 3705static void mv_60x1b2_errata_pci7(struct ata_host *host)
3706{
3707 struct mv_host_priv *hpriv = host->private_data;
3708 void __iomem *mmio = hpriv->base;
3709
3710 /* workaround for 60x1-B2 errata PCI#7 */
3711 if (mv_in_pcix_mode(host)) {
cae5a29d
ML		 3712 u32 reg = readl(mmio + MV_PCI_COMMAND);
3713 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
65ad7fef
ML		 3714 }
3715}
3716
4447d351 3717static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3718{
4447d351
TH		 3719 struct pci_dev *pdev = to_pci_dev(host->dev);
3720 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3721 u32 hp_flags = hpriv->hp_flags;
3722
5796d1c4 3723 switch (board_idx) {
47c2b677
JG		 3724 case chip_5080:
3725 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3726 hp_flags |= MV_HP_GEN_I;
47c2b677 3727
44c10138 3728 switch (pdev->revision) {
47c2b677
JG		 3729 case 0x1:
3730 hp_flags |= MV_HP_ERRATA_50XXB0;
3731 break;
3732 case 0x3:
3733 hp_flags |= MV_HP_ERRATA_50XXB2;
3734 break;
3735 default:
3736 dev_printk(KERN_WARNING, &pdev->dev,
3737 "Applying 50XXB2 workarounds to unknown rev\n");
3738 hp_flags |= MV_HP_ERRATA_50XXB2;
3739 break;
3740 }
3741 break;
3742
bca1c4eb
JG		 3743 case chip_504x:
3744 case chip_508x:
47c2b677 3745 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3746 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3747
44c10138 3748 switch (pdev->revision) {
47c2b677
JG		 3749 case 0x0:
3750 hp_flags |= MV_HP_ERRATA_50XXB0;
3751 break;
3752 case 0x3:
3753 hp_flags |= MV_HP_ERRATA_50XXB2;
3754 break;
3755 default:
3756 dev_printk(KERN_WARNING, &pdev->dev,
3757 "Applying B2 workarounds to unknown rev\n");
3758 hp_flags |= MV_HP_ERRATA_50XXB2;
3759 break;
bca1c4eb
JG		 3760 }
3761 break;
3762
3763 case chip_604x:
3764 case chip_608x:
47c2b677 3765 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3766 hp_flags |= MV_HP_GEN_II;
47c2b677 3767
44c10138 3768 switch (pdev->revision) {
47c2b677 3769 case 0x7:
65ad7fef 3770 mv_60x1b2_errata_pci7(host);
47c2b677
JG		 3771 hp_flags |= MV_HP_ERRATA_60X1B2;
3772 break;
3773 case 0x9:
3774 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3775 break;
3776 default:
3777 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 3778 "Applying B2 workarounds to unknown rev\n");
3779 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3780 break;
3781 }
3782 break;
3783
e4e7b892 3784 case chip_7042:
616d4a98 3785 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3786 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3787 (pdev->device == 0x2300 || pdev->device == 0x2310))
3788 {
4e520033
ML		 3789 /*
3790 * Highpoint RocketRAID PCIe 23xx series cards:
3791 *
3792 * Unconfigured drives are treated as "Legacy"
3793 * by the BIOS, and it overwrites sector 8 with
3794 * a "Lgcy" metadata block prior to Linux boot.
3795 *
3796 * Configured drives (RAID or JBOD) leave sector 8
3797 * alone, but instead overwrite a high numbered
3798 * sector for the RAID metadata. This sector can
3799 * be determined exactly, by truncating the physical
3800 * drive capacity to a nice even GB value.
3801 *
3802 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3803 *
3804 * Warn the user, lest they think we're just buggy.
3805 */
3806 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3807 " BIOS CORRUPTS DATA on all attached drives,"
3808 " regardless of if/how they are configured."
3809 " BEWARE!\n");
3810 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3811 " use sectors 8-9 on \"Legacy\" drives,"
3812 " and avoid the final two gigabytes on"
3813 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3814 }
8e7decdb 3815 /* drop through */
e4e7b892
JG		 3816 case chip_6042:
3817 hpriv->ops = &mv6xxx_ops;
e4e7b892 3818 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3819 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3820 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3821
44c10138 3822 switch (pdev->revision) {
5cf73bfb 3823 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3824 hp_flags |= MV_HP_ERRATA_60X1C0;
3825 break;
3826 default:
3827 dev_printk(KERN_WARNING, &pdev->dev,
3828 "Applying 60X1C0 workarounds to unknown rev\n");
3829 hp_flags |= MV_HP_ERRATA_60X1C0;
3830 break;
3831 }
3832 break;
f351b2d6 3833 case chip_soc:
29b7e43c
MM		 3834 if (soc_is_65n(hpriv))
3835 hpriv->ops = &mv_soc_65n_ops;
3836 else
3837 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3838 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3839 MV_HP_ERRATA_60X1C0;
f351b2d6 3840 break;
e4e7b892 3841
bca1c4eb 3842 default:
f351b2d6 3843 dev_printk(KERN_ERR, host->dev,
5796d1c4 3844 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3845 return 1;
3846 }
3847
3848 hpriv->hp_flags = hp_flags;
02a121da 3849 if (hp_flags & MV_HP_PCIE) {
cae5a29d
ML		 3850 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3851 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
02a121da
ML		 3852 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3853 } else {
cae5a29d
ML		 3854 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3855 hpriv->irq_mask_offset = PCI_IRQ_MASK;
02a121da
ML		 3856 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3857 }
bca1c4eb
JG		 3858
3859 return 0;
3860}
3861
05b308e1 3862/**
47c2b677 3863 * mv_init_host - Perform some early initialization of the host.
4447d351 3864 * @host: ATA host to initialize
05b308e1
BR		 3865 *
3866 * If possible, do an early global reset of the host. Then do
3867 * our port init and clear/unmask all/relevant host interrupts.
3868 *
3869 * LOCKING:
3870 * Inherited from caller.
3871 */
1bfeff03 3872static int mv_init_host(struct ata_host *host)
20f733e7
BR		 3873{
3874 int rc = 0, n_hc, port, hc;
4447d351 3875 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3876 void __iomem *mmio = hpriv->base;
47c2b677 3877
1bfeff03 3878 rc = mv_chip_id(host, hpriv->board_idx);
bca1c4eb 3879 if (rc)
352fab70 3880 goto done;
f351b2d6 3881
1f398472 3882 if (IS_SOC(hpriv)) {
cae5a29d
ML		 3883 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3884 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
1f398472 3885 } else {
cae5a29d
ML		 3886 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3887 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
f351b2d6 3888 }
352fab70 3889
5d0fb2e7
TR		 3890 /* initialize shadow irq mask with register's value */
3891 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3892
352fab70 3893 /* global interrupt mask: 0 == mask everything */
c4de573b 3894 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3895
4447d351 3896 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3897
4447d351 3898 for (port = 0; port < host->n_ports; port++)
29b7e43c
MM		 3899 if (hpriv->ops->read_preamp)
3900 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3901
c9d39130 3902 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3903 if (rc)
20f733e7 3904 goto done;
20f733e7 3905
522479fb 3906 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3907 hpriv->ops->reset_bus(host, mmio);
47c2b677 3908 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3909
4447d351 3910 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3911 struct ata_port *ap = host->ports[port];
2a47ce06 3912 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3913
3914 mv_port_init(&ap->ioaddr, port_mmio);
20f733e7
BR		 3915 }
3916
3917 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3918 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3919
3920 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3921 "(before clear)=0x%08x\n", hc,
cae5a29d
ML		 3922 readl(hc_mmio + HC_CFG),
3923 readl(hc_mmio + HC_IRQ_CAUSE));
31961943
BR		 3924
3925 /* Clear any currently outstanding hc interrupt conditions */
cae5a29d 3926 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
20f733e7
BR		 3927 }
3928
44c65d16
ML		 3929 if (!IS_SOC(hpriv)) {
3930 /* Clear any currently outstanding host interrupt conditions */
cae5a29d 3931 writelfl(0, mmio + hpriv->irq_cause_offset);
31961943 3932
44c65d16 3933 /* and unmask interrupt generation for host regs */
cae5a29d 3934 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
44c65d16 3935 }
51de32d2 3936
6be96ac1
ML		 3937 /*
3938 * enable only global host interrupts for now.
3939 * The per-port interrupts get done later as ports are set up.
3940 */
3941 mv_set_main_irq_mask(host, 0, PCI_ERR);
2b748a0a
ML		 3942 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3943 irq_coalescing_usecs);
f351b2d6
SB		 3944done:
3945 return rc;
3946}
fb621e2f 3947
fbf14e2f
BB		 3948static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3949{
3950 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3951 MV_CRQB_Q_SZ, 0);
3952 if (!hpriv->crqb_pool)
3953 return -ENOMEM;
3954
3955 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3956 MV_CRPB_Q_SZ, 0);
3957 if (!hpriv->crpb_pool)
3958 return -ENOMEM;
3959
3960 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3961 MV_SG_TBL_SZ, 0);
3962 if (!hpriv->sg_tbl_pool)
3963 return -ENOMEM;
3964
3965 return 0;
3966}
3967
15a32632
LB		 3968static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3969 struct mbus_dram_target_info *dram)
3970{
3971 int i;
3972
3973 for (i = 0; i < 4; i++) {
3974 writel(0, hpriv->base + WINDOW_CTRL(i));
3975 writel(0, hpriv->base + WINDOW_BASE(i));
3976 }
3977
3978 for (i = 0; i < dram->num_cs; i++) {
3979 struct mbus_dram_window *cs = dram->cs + i;
3980
3981 writel(((cs->size - 1) & 0xffff0000) |
3982 (cs->mbus_attr << 8) |
3983 (dram->mbus_dram_target_id << 4) | 1,
3984 hpriv->base + WINDOW_CTRL(i));
3985 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3986 }
3987}
3988
f351b2d6
SB		 3989/**
3990 * mv_platform_probe - handle a positive probe of an soc Marvell
3991 * host
3992 * @pdev: platform device found
3993 *
3994 * LOCKING:
3995 * Inherited from caller.
3996 */
3997static int mv_platform_probe(struct platform_device *pdev)
3998{
3999 static int printed_version;
4000 const struct mv_sata_platform_data *mv_platform_data;
4001 const struct ata_port_info *ppi[] =
4002 { &mv_port_info[chip_soc], NULL };
4003 struct ata_host *host;
4004 struct mv_host_priv *hpriv;
4005 struct resource *res;
4006 int n_ports, rc;
20f733e7 4007
f351b2d6
SB		 4008 if (!printed_version++)
4009 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 4010
f351b2d6
SB		 4011 /*
4012 * Simple resource validation ..
4013 */
4014 if (unlikely(pdev->num_resources != 2)) {
4015 dev_err(&pdev->dev, "invalid number of resources\n");
4016 return -EINVAL;
4017 }
4018
4019 /*
4020 * Get the register base first
4021 */
4022 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4023 if (res == NULL)
4024 return -EINVAL;
4025
4026 /* allocate host */
4027 mv_platform_data = pdev->dev.platform_data;
4028 n_ports = mv_platform_data->n_ports;
4029
4030 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4031 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4032
4033 if (!host || !hpriv)
4034 return -ENOMEM;
4035 host->private_data = hpriv;
4036 hpriv->n_ports = n_ports;
1bfeff03 4037 hpriv->board_idx = chip_soc;
f351b2d6
SB		 4038
4039 host->iomap = NULL;
f1cb0ea1 4040 hpriv->base = devm_ioremap(&pdev->dev, res->start,
041b5eac 4041 resource_size(res));
cae5a29d 4042 hpriv->base -= SATAHC0_REG_BASE;
f351b2d6 4043
c77a2f4e
SB		 4044#if defined(CONFIG_HAVE_CLK)
4045 hpriv->clk = clk_get(&pdev->dev, NULL);
4046 if (IS_ERR(hpriv->clk))
4047 dev_notice(&pdev->dev, "cannot get clkdev\n");
4048 else
4049 clk_enable(hpriv->clk);
4050#endif
4051
15a32632
LB		 4052 /*
4053 * (Re-)program MBUS remapping windows if we are asked to.
4054 */
4055 if (mv_platform_data->dram != NULL)
4056 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4057
fbf14e2f
BB		 4058 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4059 if (rc)
c77a2f4e 4060 goto err;
fbf14e2f 4061
f351b2d6 4062 /* initialize adapter */
1bfeff03 4063 rc = mv_init_host(host);
f351b2d6 4064 if (rc)
c77a2f4e 4065 goto err;
f351b2d6
SB		 4066
4067 dev_printk(KERN_INFO, &pdev->dev,
4068 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
4069 host->n_ports);
4070
4071 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4072 IRQF_SHARED, &mv6_sht);
c77a2f4e
SB		 4073err:
4074#if defined(CONFIG_HAVE_CLK)
4075 if (!IS_ERR(hpriv->clk)) {
4076 clk_disable(hpriv->clk);
4077 clk_put(hpriv->clk);
4078 }
4079#endif
4080
4081 return rc;
f351b2d6
SB		 4082}
4083
4084/*
4085 *
4086 * mv_platform_remove - unplug a platform interface
4087 * @pdev: platform device
4088 *
4089 * A platform bus SATA device has been unplugged. Perform the needed
4090 * cleanup. Also called on module unload for any active devices.
4091 */
4092static int __devexit mv_platform_remove(struct platform_device *pdev)
4093{
4094 struct device *dev = &pdev->dev;
4095 struct ata_host *host = dev_get_drvdata(dev);
c77a2f4e
SB		 4096#if defined(CONFIG_HAVE_CLK)
4097 struct mv_host_priv *hpriv = host->private_data;
4098#endif
f351b2d6 4099 ata_host_detach(host);
c77a2f4e
SB		 4100
4101#if defined(CONFIG_HAVE_CLK)
4102 if (!IS_ERR(hpriv->clk)) {
4103 clk_disable(hpriv->clk);
4104 clk_put(hpriv->clk);
4105 }
4106#endif
f351b2d6 4107 return 0;
20f733e7
BR		 4108}
4109
6481f2b5
SB		 4110#ifdef CONFIG_PM
4111static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4112{
4113 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4114 if (host)
4115 return ata_host_suspend(host, state);
4116 else
4117 return 0;
4118}
4119
4120static int mv_platform_resume(struct platform_device *pdev)
4121{
4122 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4123 int ret;
4124
4125 if (host) {
4126 struct mv_host_priv *hpriv = host->private_data;
4127 const struct mv_sata_platform_data *mv_platform_data = \
4128 pdev->dev.platform_data;
4129 /*
4130 * (Re-)program MBUS remapping windows if we are asked to.
4131 */
4132 if (mv_platform_data->dram != NULL)
4133 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4134
4135 /* initialize adapter */
1bfeff03 4136 ret = mv_init_host(host);
6481f2b5
SB		 4137 if (ret) {
4138 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4139 return ret;
4140 }
4141 ata_host_resume(host);
4142 }
4143
4144 return 0;
4145}
4146#else
4147#define mv_platform_suspend NULL
4148#define mv_platform_resume NULL
4149#endif
4150
f351b2d6
SB		 4151static struct platform_driver mv_platform_driver = {
4152 .probe = mv_platform_probe,
4153 .remove = __devexit_p(mv_platform_remove),
6481f2b5
SB		 4154 .suspend = mv_platform_suspend,
4155 .resume = mv_platform_resume,
f351b2d6
SB		 4156 .driver = {
4157 .name = DRV_NAME,
4158 .owner = THIS_MODULE,
4159 },
4160};
4161
4162
7bb3c529 4163#ifdef CONFIG_PCI
f351b2d6
SB		 4164static int mv_pci_init_one(struct pci_dev *pdev,
4165 const struct pci_device_id *ent);
b2dec48c
SB		 4166#ifdef CONFIG_PM
4167static int mv_pci_device_resume(struct pci_dev *pdev);
4168#endif
f351b2d6 4169
7bb3c529
SB		 4170
4171static struct pci_driver mv_pci_driver = {
4172 .name = DRV_NAME,
4173 .id_table = mv_pci_tbl,
f351b2d6 4174 .probe = mv_pci_init_one,
7bb3c529 4175 .remove = ata_pci_remove_one,
b2dec48c
SB		 4176#ifdef CONFIG_PM
4177 .suspend = ata_pci_device_suspend,
4178 .resume = mv_pci_device_resume,
4179#endif
4180
7bb3c529
SB		 4181};
4182
7bb3c529
SB		 4183/* move to PCI layer or libata core? */
4184static int pci_go_64(struct pci_dev *pdev)
4185{
4186 int rc;
4187
6a35528a
YH		 4188 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4189 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
7bb3c529 4190 if (rc) {
284901a9 4191 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529
SB		 4192 if (rc) {
4193 dev_printk(KERN_ERR, &pdev->dev,
4194 "64-bit DMA enable failed\n");
4195 return rc;
4196 }
4197 }
4198 } else {
284901a9 4199 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529
SB		 4200 if (rc) {
4201 dev_printk(KERN_ERR, &pdev->dev,
4202 "32-bit DMA enable failed\n");
4203 return rc;
4204 }
284901a9 4205 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529
SB		 4206 if (rc) {
4207 dev_printk(KERN_ERR, &pdev->dev,
4208 "32-bit consistent DMA enable failed\n");
4209 return rc;
4210 }
4211 }
4212
4213 return rc;
4214}
4215
05b308e1
BR		 4216/**
4217 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 4218 * @host: ATA host to print info about
05b308e1
BR		 4219 *
4220 * FIXME: complete this.
4221 *
4222 * LOCKING:
4223 * Inherited from caller.
4224 */
4447d351 4225static void mv_print_info(struct ata_host *host)
31961943 4226{
4447d351
TH		 4227 struct pci_dev *pdev = to_pci_dev(host->dev);
4228 struct mv_host_priv *hpriv = host->private_data;
44c10138 4229 u8 scc;
c1e4fe71 4230 const char *scc_s, *gen;
31961943
BR		 4231
4232 /* Use this to determine the HW stepping of the chip so we know
4233 * what errata to workaround
4234 */
31961943
BR		 4235 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4236 if (scc == 0)
4237 scc_s = "SCSI";
4238 else if (scc == 0x01)
4239 scc_s = "RAID";
4240 else
c1e4fe71
JG		 4241 scc_s = "?";
4242
4243 if (IS_GEN_I(hpriv))
4244 gen = "I";
4245 else if (IS_GEN_II(hpriv))
4246 gen = "II";
4247 else if (IS_GEN_IIE(hpriv))
4248 gen = "IIE";
4249 else
4250 gen = "?";
31961943 4251
a9524a76 4252 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 4253 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4254 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 4255 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4256}
4257
05b308e1 4258/**
f351b2d6 4259 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 4260 * @pdev: PCI device found
4261 * @ent: PCI device ID entry for the matched host
4262 *
4263 * LOCKING:
4264 * Inherited from caller.
4265 */
f351b2d6
SB		 4266static int mv_pci_init_one(struct pci_dev *pdev,
4267 const struct pci_device_id *ent)
20f733e7 4268{
2dcb407e 4269 static int printed_version;
20f733e7 4270 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 4271 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4272 struct ata_host *host;
4273 struct mv_host_priv *hpriv;
c4bc7d73 4274 int n_ports, port, rc;
20f733e7 4275
a9524a76
JG		 4276 if (!printed_version++)
4277 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 4278
4447d351
TH		 4279 /* allocate host */
4280 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4281
4282 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4283 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4284 if (!host || !hpriv)
4285 return -ENOMEM;
4286 host->private_data = hpriv;
f351b2d6 4287 hpriv->n_ports = n_ports;
1bfeff03 4288 hpriv->board_idx = board_idx;
4447d351
TH		 4289
4290 /* acquire resources */
24dc5f33
TH		 4291 rc = pcim_enable_device(pdev);
4292 if (rc)
20f733e7 4293 return rc;
20f733e7 4294
0d5ff566
TH		 4295 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4296 if (rc == -EBUSY)
24dc5f33 4297 pcim_pin_device(pdev);
0d5ff566 4298 if (rc)
24dc5f33 4299 return rc;
4447d351 4300 host->iomap = pcim_iomap_table(pdev);
f351b2d6 4301 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 4302
d88184fb
JG		 4303 rc = pci_go_64(pdev);
4304 if (rc)
4305 return rc;
4306
da2fa9ba
ML		 4307 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4308 if (rc)
4309 return rc;
4310
c4bc7d73
SB		 4311 for (port = 0; port < host->n_ports; port++) {
4312 struct ata_port *ap = host->ports[port];
4313 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4314 unsigned int offset = port_mmio - hpriv->base;
4315
4316 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4317 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4318 }
4319
20f733e7 4320 /* initialize adapter */
1bfeff03 4321 rc = mv_init_host(host);
24dc5f33
TH		 4322 if (rc)
4323 return rc;
20f733e7 4324
6d3c30ef
ML		 4325 /* Enable message-switched interrupts, if requested */
4326 if (msi && pci_enable_msi(pdev) == 0)
4327 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 4328
31961943 4329 mv_dump_pci_cfg(pdev, 0x68);
4447d351 4330 mv_print_info(host);
20f733e7 4331
4447d351 4332 pci_set_master(pdev);
ea8b4db9 4333 pci_try_set_mwi(pdev);
4447d351 4334 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 4335 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 4336}
b2dec48c
SB		 4337
4338#ifdef CONFIG_PM
4339static int mv_pci_device_resume(struct pci_dev *pdev)
4340{
4341 struct ata_host *host = dev_get_drvdata(&pdev->dev);
4342 int rc;
4343
4344 rc = ata_pci_device_do_resume(pdev);
4345 if (rc)
4346 return rc;
4347
4348 /* initialize adapter */
4349 rc = mv_init_host(host);
4350 if (rc)
4351 return rc;
4352
4353 ata_host_resume(host);
4354
4355 return 0;
4356}
4357#endif
7bb3c529 4358#endif
20f733e7 4359
f351b2d6
SB		 4360static int mv_platform_probe(struct platform_device *pdev);
4361static int __devexit mv_platform_remove(struct platform_device *pdev);
4362
20f733e7
BR		 4363static int __init mv_init(void)
4364{
7bb3c529
SB		 4365 int rc = -ENODEV;
4366#ifdef CONFIG_PCI
4367 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 4368 if (rc < 0)
4369 return rc;
4370#endif
4371 rc = platform_driver_register(&mv_platform_driver);
4372
4373#ifdef CONFIG_PCI
4374 if (rc < 0)
4375 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 4376#endif
4377 return rc;
20f733e7
BR		 4378}
4379
4380static void __exit mv_exit(void)
4381{
7bb3c529 4382#ifdef CONFIG_PCI
20f733e7 4383 pci_unregister_driver(&mv_pci_driver);
7bb3c529 4384#endif
f351b2d6 4385 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 4386}
4387
4388MODULE_AUTHOR("Brett Russ");
4389MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4390MODULE_LICENSE("GPL");
4391MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4392MODULE_VERSION(DRV_VERSION);
17c5aab5 4393MODULE_ALIAS("platform:" DRV_NAME);
20f733e7
BR		 4394
4395module_init(mv_init);
4396module_exit(mv_exit);
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