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sata_mv wait for empty+idle
[net-next-2.6.git] / drivers / ata / sata_mv.c
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20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
1fd2e1c2 74#define DRV_VERSION "1.20"
20f733e7
BR		 75
76enum {
77 /* BAR's are enumerated in terms of pci_resource_start() terms */
78 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
79 MV_IO_BAR = 2, /* offset 0x18: IO space */
80 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
81
82 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
83 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
84
85 MV_PCI_REG_BASE = 0,
86 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 87 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
88 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
89 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
90 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
91 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
92
20f733e7 93 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
31961943
BR		 103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 112 MV_MAX_SG_CT = 256,
31961943 113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 114
352fab70 115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 116 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
123 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 124 /* SoC integrated controllers, no PCI interface */
e12bef50 125 MV_FLAG_SOC = (1 << 28),
7bb3c529 126
c5d3e45a 127 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 128 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
129 ATA_FLAG_PIO_POLLING,
47c2b677 130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 131
31961943
BR		 132 CRQB_FLAG_READ = (1 << 0),
133 CRQB_TAG_SHIFT = 1,
c5d3e45a 134 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 135 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 136 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 137 CRQB_CMD_ADDR_SHIFT = 8,
138 CRQB_CMD_CS = (0x2 << 11),
139 CRQB_CMD_LAST = (1 << 15),
140
141 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 142 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
143 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 144
145 EPRD_FLAG_END_OF_TBL = (1 << 31),
146
20f733e7
BR		 147 /* PCI interface registers */
148
31961943 149 PCI_COMMAND_OFS = 0xc00,
8e7decdb 150 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 151
20f733e7
BR		 152 PCI_MAIN_CMD_STS_OFS = 0xd30,
153 STOP_PCI_MASTER = (1 << 2),
154 PCI_MASTER_EMPTY = (1 << 3),
155 GLOB_SFT_RST = (1 << 4),
156
8e7decdb
ML		 157 MV_PCI_MODE_OFS = 0xd00,
158 MV_PCI_MODE_MASK = 0x30,
159
522479fb
JG		 160 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
161 MV_PCI_DISC_TIMER = 0xd04,
162 MV_PCI_MSI_TRIGGER = 0xc38,
163 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 164 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 165 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
166 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
167 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
168 MV_PCI_ERR_COMMAND = 0x1d50,
169
02a121da
ML		 170 PCI_IRQ_CAUSE_OFS = 0x1d58,
171 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 172 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
173
02a121da
ML		 174 PCIE_IRQ_CAUSE_OFS = 0x1900,
175 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 176 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 177
7368f919
ML		 178 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
179 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
180 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
181 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
182 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 183 ERR_IRQ = (1 << 0), /* shift by port # */
184 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 185 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
186 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
187 PCI_ERR = (1 << 18),
188 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
189 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 190 PORTS_0_3_COAL_DONE = (1 << 8),
191 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 192 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
193 GPIO_INT = (1 << 22),
194 SELF_INT = (1 << 23),
195 TWSI_INT = (1 << 24),
196 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 197 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 198 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
8b260248 199 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
f9f7fe01 200 PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
20f733e7
BR		 201 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
202 HC_MAIN_RSVD),
fb621e2f
JG		 203 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
204 HC_MAIN_RSVD_5),
f351b2d6 205 HC_MAIN_MASKED_IRQS_SOC = (PORTS_0_3_COAL_DONE | HC_MAIN_RSVD_SOC),
20f733e7
BR		 206
207 /* SATAHC registers */
208 HC_CFG_OFS = 0,
209
210 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 211 DMA_IRQ = (1 << 0), /* shift by port # */
212 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 213 DEV_IRQ = (1 << 8), /* shift by port # */
214
215 /* Shadow block registers */
31961943
BR		 216 SHD_BLK_OFS = 0x100,
217 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 218
219 /* SATA registers */
220 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
221 SATA_ACTIVE_OFS = 0x350,
0c58912e 222 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
17c5aab5 223
e12bef50 224 LTMODE_OFS = 0x30c,
17c5aab5
ML		 225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
47c2b677 227 PHY_MODE3 = 0x310,
bca1c4eb
JG		 228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
e12bef50 230 SATA_IFCTL_OFS = 0x344,
8e7decdb 231 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 234
8e7decdb
ML		 235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 238
c9d39130 239 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 243
244 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
0c58912e
ML		 248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 272
6c1153e0 273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
6c1153e0 279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 280
6c1153e0 281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
6c1153e0 288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 289
6c1153e0 290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 297 EDMA_ERR_LNK_CTRL_TX,
646a4da5 298
bdd4ddde
JG		 299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
6c1153e0 305 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
e12bef50 313
bdd4ddde
JG		 314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
6c1153e0 321 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
20f733e7 325
31961943
BR		 326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
0ea9e179
JG		 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 345
8e7decdb
ML		 346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 350
352fab70
ML		 351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
31961943
BR		 353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 359 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 365
31961943 366 /* Port private flags (pp_flags) */
0ea9e179 367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
20f733e7
BR		 369};
370
ee9ccdf7
JG		 371#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
372#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 373#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 374#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 375#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 376
15a32632
LB		 377#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
378#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
379
095fec88 380enum {
baf14aa1
JG		 381 /* DMA boundary 0xffff is required by the s/g splitting
382 * we need on /length/ in mv_fill-sg().
383 */
384 MV_DMA_BOUNDARY = 0xffffU,
095fec88 385
0ea9e179
JG		 386 /* mask of register bits containing lower 32 bits
387 * of EDMA request queue DMA address
388 */
095fec88
JG		 389 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
390
0ea9e179 391 /* ditto, for response queue */
095fec88
JG		 392 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
393};
394
522479fb
JG		 395enum chip_type {
396 chip_504x,
397 chip_508x,
398 chip_5080,
399 chip_604x,
400 chip_608x,
e4e7b892
JG		 401 chip_6042,
402 chip_7042,
f351b2d6 403 chip_soc,
522479fb
JG		 404};
405
31961943
BR		 406/* Command ReQuest Block: 32B */
407struct mv_crqb {
e1469874
ML		 408 __le32 sg_addr;
409 __le32 sg_addr_hi;
410 __le16 ctrl_flags;
411 __le16 ata_cmd[11];
31961943 412};
20f733e7 413
e4e7b892 414struct mv_crqb_iie {
e1469874
ML		 415 __le32 addr;
416 __le32 addr_hi;
417 __le32 flags;
418 __le32 len;
419 __le32 ata_cmd[4];
e4e7b892
JG		 420};
421
31961943
BR		 422/* Command ResPonse Block: 8B */
423struct mv_crpb {
e1469874
ML		 424 __le16 id;
425 __le16 flags;
426 __le32 tmstmp;
20f733e7
BR		 427};
428
31961943
BR		 429/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
430struct mv_sg {
e1469874
ML		 431 __le32 addr;
432 __le32 flags_size;
433 __le32 addr_hi;
434 __le32 reserved;
31961943 435};
20f733e7 436
31961943
BR		 437struct mv_port_priv {
438 struct mv_crqb *crqb;
439 dma_addr_t crqb_dma;
440 struct mv_crpb *crpb;
441 dma_addr_t crpb_dma;
eb73d558
ML		 442 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
443 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 444
445 unsigned int req_idx;
446 unsigned int resp_idx;
447
31961943
BR		 448 u32 pp_flags;
449};
450
bca1c4eb
JG		 451struct mv_port_signal {
452 u32 amps;
453 u32 pre;
454};
455
02a121da
ML		 456struct mv_host_priv {
457 u32 hp_flags;
458 struct mv_port_signal signal[8];
459 const struct mv_hw_ops *ops;
f351b2d6
SB		 460 int n_ports;
461 void __iomem *base;
7368f919
ML		 462 void __iomem *main_irq_cause_addr;
463 void __iomem *main_irq_mask_addr;
02a121da
ML		 464 u32 irq_cause_ofs;
465 u32 irq_mask_ofs;
466 u32 unmask_all_irqs;
da2fa9ba
ML		 467 /*
468 * These consistent DMA memory pools give us guaranteed
469 * alignment for hardware-accessed data structures,
470 * and less memory waste in accomplishing the alignment.
471 */
472 struct dma_pool *crqb_pool;
473 struct dma_pool *crpb_pool;
474 struct dma_pool *sg_tbl_pool;
02a121da
ML		 475};
476
47c2b677 477struct mv_hw_ops {
2a47ce06
JG		 478 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
479 unsigned int port);
47c2b677
JG		 480 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
481 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
482 void __iomem *mmio);
c9d39130
JG		 483 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
484 unsigned int n_hc);
522479fb 485 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 486 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 487};
488
da3dbb17
TH		 489static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
490static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
491static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
492static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 493static int mv_port_start(struct ata_port *ap);
494static void mv_port_stop(struct ata_port *ap);
495static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 496static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 497static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 498static int mv_hardreset(struct ata_link *link, unsigned int *class,
499 unsigned long deadline);
bdd4ddde
JG		 500static void mv_eh_freeze(struct ata_port *ap);
501static void mv_eh_thaw(struct ata_port *ap);
f273827e 502static void mv6_dev_config(struct ata_device *dev);
20f733e7 503
2a47ce06
JG		 504static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
505 unsigned int port);
47c2b677
JG		 506static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
507static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
508 void __iomem *mmio);
c9d39130
JG		 509static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
510 unsigned int n_hc);
522479fb 511static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 512static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 513
2a47ce06
JG		 514static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
515 unsigned int port);
47c2b677
JG		 516static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
517static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
518 void __iomem *mmio);
c9d39130
JG		 519static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
520 unsigned int n_hc);
522479fb 521static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 522static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
523 void __iomem *mmio);
524static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
525 void __iomem *mmio);
526static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
527 void __iomem *mmio, unsigned int n_hc);
528static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
529 void __iomem *mmio);
530static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 531static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 532static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 533 unsigned int port_no);
e12bef50 534static int mv_stop_edma(struct ata_port *ap);
b562468c 535static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 536static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 537
e49856d8
ML		 538static void mv_pmp_select(struct ata_port *ap, int pmp);
539static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
540 unsigned long deadline);
541static int mv_softreset(struct ata_link *link, unsigned int *class,
542 unsigned long deadline);
47c2b677 543
eb73d558
ML		 544/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
545 * because we have to allow room for worst case splitting of
546 * PRDs for 64K boundaries in mv_fill_sg().
547 */
c5d3e45a 548static struct scsi_host_template mv5_sht = {
68d1d07b 549 ATA_BASE_SHT(DRV_NAME),
baf14aa1 550 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 551 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 552};
553
554static struct scsi_host_template mv6_sht = {
68d1d07b 555 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 556 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 557 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 558 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 559};
560
029cfd6b
TH		 561static struct ata_port_operations mv5_ops = {
562 .inherits = &ata_sff_port_ops,
c9d39130
JG		 563
564 .qc_prep = mv_qc_prep,
565 .qc_issue = mv_qc_issue,
c9d39130 566
bdd4ddde
JG		 567 .freeze = mv_eh_freeze,
568 .thaw = mv_eh_thaw,
a1efdaba 569 .hardreset = mv_hardreset,
a1efdaba 570 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 571 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 572
c9d39130
JG		 573 .scr_read = mv5_scr_read,
574 .scr_write = mv5_scr_write,
575
576 .port_start = mv_port_start,
577 .port_stop = mv_port_stop,
c9d39130
JG		 578};
579
029cfd6b
TH		 580static struct ata_port_operations mv6_ops = {
581 .inherits = &mv5_ops,
e49856d8 582 .qc_defer = sata_pmp_qc_defer_cmd_switch,
f273827e 583 .dev_config = mv6_dev_config,
20f733e7
BR		 584 .scr_read = mv_scr_read,
585 .scr_write = mv_scr_write,
586
e49856d8
ML		 587 .pmp_hardreset = mv_pmp_hardreset,
588 .pmp_softreset = mv_softreset,
589 .softreset = mv_softreset,
590 .error_handler = sata_pmp_error_handler,
20f733e7
BR		 591};
592
029cfd6b
TH		 593static struct ata_port_operations mv_iie_ops = {
594 .inherits = &mv6_ops,
e49856d8 595 .qc_defer = ata_std_qc_defer, /* FIS-based switching */
029cfd6b 596 .dev_config = ATA_OP_NULL,
e4e7b892 597 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 598};
599
98ac62de 600static const struct ata_port_info mv_port_info[] = {
20f733e7 601 { /* chip_504x */
cca3974e 602 .flags = MV_COMMON_FLAGS,
31961943 603 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 604 .udma_mask = ATA_UDMA6,
c9d39130 605 .port_ops = &mv5_ops,
20f733e7
BR		 606 },
607 { /* chip_508x */
c5d3e45a 608 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 609 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 610 .udma_mask = ATA_UDMA6,
c9d39130 611 .port_ops = &mv5_ops,
20f733e7 612 },
47c2b677 613 { /* chip_5080 */
c5d3e45a 614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 615 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 616 .udma_mask = ATA_UDMA6,
c9d39130 617 .port_ops = &mv5_ops,
47c2b677 618 },
20f733e7 619 { /* chip_604x */
138bfdd0 620 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 621 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 622 ATA_FLAG_NCQ,
31961943 623 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 624 .udma_mask = ATA_UDMA6,
c9d39130 625 .port_ops = &mv6_ops,
20f733e7
BR		 626 },
627 { /* chip_608x */
c5d3e45a 628 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 629 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 630 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 631 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 632 .udma_mask = ATA_UDMA6,
c9d39130 633 .port_ops = &mv6_ops,
20f733e7 634 },
e4e7b892 635 { /* chip_6042 */
138bfdd0 636 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 637 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 638 ATA_FLAG_NCQ,
e4e7b892 639 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 640 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 641 .port_ops = &mv_iie_ops,
642 },
643 { /* chip_7042 */
138bfdd0 644 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 645 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 646 ATA_FLAG_NCQ,
e4e7b892 647 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 648 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 649 .port_ops = &mv_iie_ops,
650 },
f351b2d6 651 { /* chip_soc */
02c1f32f 652 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 653 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
02c1f32f 654 ATA_FLAG_NCQ | MV_FLAG_SOC,
17c5aab5
ML		 655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
f351b2d6 658 },
20f733e7
BR		 659};
660
3b7d697d 661static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 666 /* RocketRAID 1740/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
668 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 669
670 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
673 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
674 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
675
676 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
677
d9f9c6bc
FA		 678 /* Adaptec 1430SA */
679 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
680
02a121da 681 /* Marvell 7042 support */
6a3d586d
MT		 682 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
683
02a121da
ML		 684 /* Highpoint RocketRAID PCIe series */
685 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
686 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
687
2d2744fc 688 { } /* terminate list */
20f733e7
BR		 689};
690
47c2b677
JG		 691static const struct mv_hw_ops mv5xxx_ops = {
692 .phy_errata = mv5_phy_errata,
693 .enable_leds = mv5_enable_leds,
694 .read_preamp = mv5_read_preamp,
695 .reset_hc = mv5_reset_hc,
522479fb
JG		 696 .reset_flash = mv5_reset_flash,
697 .reset_bus = mv5_reset_bus,
47c2b677
JG		 698};
699
700static const struct mv_hw_ops mv6xxx_ops = {
701 .phy_errata = mv6_phy_errata,
702 .enable_leds = mv6_enable_leds,
703 .read_preamp = mv6_read_preamp,
704 .reset_hc = mv6_reset_hc,
522479fb
JG		 705 .reset_flash = mv6_reset_flash,
706 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 707};
708
f351b2d6
SB		 709static const struct mv_hw_ops mv_soc_ops = {
710 .phy_errata = mv6_phy_errata,
711 .enable_leds = mv_soc_enable_leds,
712 .read_preamp = mv_soc_read_preamp,
713 .reset_hc = mv_soc_reset_hc,
714 .reset_flash = mv_soc_reset_flash,
715 .reset_bus = mv_soc_reset_bus,
716};
717
20f733e7
BR		 718/*
719 * Functions
720 */
721
722static inline void writelfl(unsigned long data, void __iomem *addr)
723{
724 writel(data, addr);
725 (void) readl(addr); /* flush to avoid PCI posted write */
726}
727
c9d39130
JG		 728static inline unsigned int mv_hc_from_port(unsigned int port)
729{
730 return port >> MV_PORT_HC_SHIFT;
731}
732
733static inline unsigned int mv_hardport_from_port(unsigned int port)
734{
735 return port & MV_PORT_MASK;
736}
737
1cfd19ae
ML		 738/*
739 * Consolidate some rather tricky bit shift calculations.
740 * This is hot-path stuff, so not a function.
741 * Simple code, with two return values, so macro rather than inline.
742 *
743 * port is the sole input, in range 0..7.
7368f919
ML		 744 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
745 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 746 *
747 * Note that port and hardport may be the same variable in some cases.
748 */
749#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
750{ \
751 shift = mv_hc_from_port(port) * HC_SHIFT; \
752 hardport = mv_hardport_from_port(port); \
753 shift += hardport * 2; \
754}
755
352fab70
ML		 756static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
757{
758 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
759}
760
c9d39130
JG		 761static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
762 unsigned int port)
763{
764 return mv_hc_base(base, mv_hc_from_port(port));
765}
766
20f733e7
BR		 767static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
768{
c9d39130 769 return mv_hc_base_from_port(base, port) +
8b260248 770 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 771 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 772}
773
e12bef50
ML		 774static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
775{
776 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
777 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
778
779 return hc_mmio + ofs;
780}
781
f351b2d6
SB		 782static inline void __iomem *mv_host_base(struct ata_host *host)
783{
784 struct mv_host_priv *hpriv = host->private_data;
785 return hpriv->base;
786}
787
20f733e7
BR		 788static inline void __iomem *mv_ap_base(struct ata_port *ap)
789{
f351b2d6 790 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 791}
792
cca3974e 793static inline int mv_get_hc_count(unsigned long port_flags)
31961943 794{
cca3974e 795 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 796}
797
c5d3e45a
JG		 798static void mv_set_edma_ptrs(void __iomem *port_mmio,
799 struct mv_host_priv *hpriv,
800 struct mv_port_priv *pp)
801{
bdd4ddde
JG		 802 u32 index;
803
c5d3e45a
JG		 804 /*
805 * initialize request queue
806 */
fcfb1f77
ML		 807 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
808 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 809
c5d3e45a
JG		 810 WARN_ON(pp->crqb_dma & 0x3ff);
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
814
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 816 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
818 else
bdd4ddde 819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 820
821 /*
822 * initialize response queue
823 */
fcfb1f77
ML		 824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 826
c5d3e45a
JG		 827 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
829
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 831 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
833 else
bdd4ddde 834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 835
bdd4ddde 836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 838}
839
05b308e1
BR		 840/**
841 * mv_start_dma - Enable eDMA engine
842 * @base: port base address
843 * @pp: port private data
844 *
beec7dbc
TH		 845 * Verify the local cache of the eDMA state is accurate with a
846 * WARN_ON.
05b308e1
BR		 847 *
848 * LOCKING:
849 * Inherited from caller.
850 */
0c58912e 851static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 852 struct mv_port_priv *pp, u8 protocol)
20f733e7 853{
72109168
ML		 854 int want_ncq = (protocol == ATA_PROT_NCQ);
855
856 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
857 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
858 if (want_ncq != using_ncq)
b562468c 859 mv_stop_edma(ap);
72109168 860 }
c5d3e45a 861 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 862 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 863 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 864 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 865 mv_host_base(ap->host), hardport);
0c58912e
ML		 866 u32 hc_irq_cause, ipending;
867
bdd4ddde 868 /* clear EDMA event indicators, if any */
f630d562 869 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 870
0c58912e
ML		 871 /* clear EDMA interrupt indicator, if any */
872 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 873 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 874 if (hc_irq_cause & ipending) {
875 writelfl(hc_irq_cause & ~ipending,
876 hc_mmio + HC_IRQ_CAUSE_OFS);
877 }
878
e12bef50 879 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 880
881 /* clear FIS IRQ Cause */
882 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
883
f630d562 884 mv_set_edma_ptrs(port_mmio, hpriv, pp);
bdd4ddde 885
f630d562 886 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 887 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
888 }
20f733e7
BR		 889}
890
9b2c4e0b
ML		 891static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
892{
893 void __iomem *port_mmio = mv_ap_base(ap);
894 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
895 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
896 int i;
897
898 /*
899 * Wait for the EDMA engine to finish transactions in progress.
900 */
901 for (i = 0; i < timeout; ++i) {
902 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
903 if ((edma_stat & empty_idle) == empty_idle)
904 break;
905 udelay(per_loop);
906 }
907 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
908}
909
05b308e1 910/**
e12bef50 911 * mv_stop_edma_engine - Disable eDMA engine
b562468c 912 * @port_mmio: io base address
05b308e1
BR		 913 *
914 * LOCKING:
915 * Inherited from caller.
916 */
b562468c 917static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 918{
b562468c 919 int i;
31961943 920
b562468c
ML		 921 /* Disable eDMA. The disable bit auto clears. */
922 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 923
b562468c
ML		 924 /* Wait for the chip to confirm eDMA is off. */
925 for (i = 10000; i > 0; i--) {
926 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 927 if (!(reg & EDMA_EN))
b562468c
ML		 928 return 0;
929 udelay(10);
31961943 930 }
b562468c 931 return -EIO;
20f733e7
BR		 932}
933
e12bef50 934static int mv_stop_edma(struct ata_port *ap)
0ea9e179 935{
b562468c
ML		 936 void __iomem *port_mmio = mv_ap_base(ap);
937 struct mv_port_priv *pp = ap->private_data;
0ea9e179 938
b562468c
ML		 939 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
940 return 0;
941 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 942 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 943 if (mv_stop_edma_engine(port_mmio)) {
944 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
945 return -EIO;
946 }
947 return 0;
0ea9e179
JG		 948}
949
8a70f8dc 950#ifdef ATA_DEBUG
31961943 951static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 952{
31961943
BR		 953 int b, w;
954 for (b = 0; b < bytes; ) {
955 DPRINTK("%p: ", start + b);
956 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 957 printk("%08x ", readl(start + b));
31961943
BR		 958 b += sizeof(u32);
959 }
960 printk("\n");
961 }
31961943 962}
8a70f8dc
JG		 963#endif
964
31961943
BR		 965static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
966{
967#ifdef ATA_DEBUG
968 int b, w;
969 u32 dw;
970 for (b = 0; b < bytes; ) {
971 DPRINTK("%02x: ", b);
972 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 973 (void) pci_read_config_dword(pdev, b, &dw);
974 printk("%08x ", dw);
31961943
BR		 975 b += sizeof(u32);
976 }
977 printk("\n");
978 }
979#endif
980}
981static void mv_dump_all_regs(void __iomem *mmio_base, int port,
982 struct pci_dev *pdev)
983{
984#ifdef ATA_DEBUG
8b260248 985 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 986 port >> MV_PORT_HC_SHIFT);
987 void __iomem *port_base;
988 int start_port, num_ports, p, start_hc, num_hcs, hc;
989
990 if (0 > port) {
991 start_hc = start_port = 0;
992 num_ports = 8; /* shld be benign for 4 port devs */
993 num_hcs = 2;
994 } else {
995 start_hc = port >> MV_PORT_HC_SHIFT;
996 start_port = port;
997 num_ports = num_hcs = 1;
998 }
8b260248 999 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1000 num_ports > 1 ? num_ports - 1 : start_port);
1001
1002 if (NULL != pdev) {
1003 DPRINTK("PCI config space regs:\n");
1004 mv_dump_pci_cfg(pdev, 0x68);
1005 }
1006 DPRINTK("PCI regs:\n");
1007 mv_dump_mem(mmio_base+0xc00, 0x3c);
1008 mv_dump_mem(mmio_base+0xd00, 0x34);
1009 mv_dump_mem(mmio_base+0xf00, 0x4);
1010 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1011 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1012 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1013 DPRINTK("HC regs (HC %i):\n", hc);
1014 mv_dump_mem(hc_base, 0x1c);
1015 }
1016 for (p = start_port; p < start_port + num_ports; p++) {
1017 port_base = mv_port_base(mmio_base, p);
2dcb407e 1018 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1019 mv_dump_mem(port_base, 0x54);
2dcb407e 1020 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1021 mv_dump_mem(port_base+0x300, 0x60);
1022 }
1023#endif
20f733e7
BR		 1024}
1025
1026static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1027{
1028 unsigned int ofs;
1029
1030 switch (sc_reg_in) {
1031 case SCR_STATUS:
1032 case SCR_CONTROL:
1033 case SCR_ERROR:
1034 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1035 break;
1036 case SCR_ACTIVE:
1037 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1038 break;
1039 default:
1040 ofs = 0xffffffffU;
1041 break;
1042 }
1043 return ofs;
1044}
1045
da3dbb17 1046static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1047{
1048 unsigned int ofs = mv_scr_offset(sc_reg_in);
1049
da3dbb17
TH		 1050 if (ofs != 0xffffffffU) {
1051 *val = readl(mv_ap_base(ap) + ofs);
1052 return 0;
1053 } else
1054 return -EINVAL;
20f733e7
BR		 1055}
1056
da3dbb17 1057static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1058{
1059 unsigned int ofs = mv_scr_offset(sc_reg_in);
1060
da3dbb17 1061 if (ofs != 0xffffffffU) {
20f733e7 1062 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1063 return 0;
1064 } else
1065 return -EINVAL;
20f733e7
BR		 1066}
1067
f273827e
ML		 1068static void mv6_dev_config(struct ata_device *adev)
1069{
1070 /*
e49856d8
ML		 1071 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1072 *
1073 * Gen-II does not support NCQ over a port multiplier
1074 * (no FIS-based switching).
1075 *
f273827e
ML		 1076 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1077 * See mv_qc_prep() for more info.
1078 */
e49856d8 1079 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1080 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1081 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1082 ata_dev_printk(adev, KERN_INFO,
1083 "NCQ disabled for command-based switching\n");
1084 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1085 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1086 ata_dev_printk(adev, KERN_INFO,
1087 "max_sectors limited to %u for NCQ\n",
1088 adev->max_sectors);
1089 }
e49856d8 1090 }
f273827e
ML		 1091}
1092
e49856d8
ML		 1093static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
1094{
8e7decdb 1095 u32 old_fiscfg, new_fiscfg, old_ltmode, new_ltmode;
e49856d8
ML		 1096 /*
1097 * Various bit settings required for operation
1098 * in FIS-based switching (fbs) mode on GenIIe:
1099 */
8e7decdb 1100 old_fiscfg = readl(port_mmio + FISCFG_OFS);
e49856d8
ML		 1101 old_ltmode = readl(port_mmio + LTMODE_OFS);
1102 if (enable_fbs) {
8e7decdb 1103 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
e49856d8
ML		 1104 new_ltmode = old_ltmode | LTMODE_BIT8;
1105 } else { /* disable fbs */
8e7decdb 1106 new_fiscfg = old_fiscfg & ~FISCFG_SINGLE_SYNC;
e49856d8
ML		 1107 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1108 }
8e7decdb
ML		 1109 if (new_fiscfg != old_fiscfg)
1110 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1111 if (new_ltmode != old_ltmode)
1112 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
f273827e
ML		 1113}
1114
e12bef50 1115static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1116{
0c58912e 1117 u32 cfg;
e12bef50
ML		 1118 struct mv_port_priv *pp = ap->private_data;
1119 struct mv_host_priv *hpriv = ap->host->private_data;
1120 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1121
1122 /* set up non-NCQ EDMA configuration */
0c58912e 1123 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
e4e7b892 1124
0c58912e 1125 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1126 cfg |= (1 << 8); /* enab config burst size mask */
1127
0c58912e 1128 else if (IS_GEN_II(hpriv))
e4e7b892
JG		 1129 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1130
1131 else if (IS_GEN_IIE(hpriv)) {
e728eabe
JG		 1132 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1133 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1134 if (HAS_PCI(ap->host))
1135 cfg |= (1 << 18); /* enab early completion */
1136 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1137 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e49856d8
ML		 1138
1139 if (want_ncq && sata_pmp_attached(ap)) {
1140 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1141 mv_config_fbs(port_mmio, 1);
1142 } else {
1143 mv_config_fbs(port_mmio, 0);
1144 }
e4e7b892
JG		 1145 }
1146
72109168
ML		 1147 if (want_ncq) {
1148 cfg |= EDMA_CFG_NCQ;
1149 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1150 } else
1151 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1152
e4e7b892
JG		 1153 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1154}
1155
da2fa9ba
ML		 1156static void mv_port_free_dma_mem(struct ata_port *ap)
1157{
1158 struct mv_host_priv *hpriv = ap->host->private_data;
1159 struct mv_port_priv *pp = ap->private_data;
eb73d558 1160 int tag;
da2fa9ba
ML		 1161
1162 if (pp->crqb) {
1163 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1164 pp->crqb = NULL;
1165 }
1166 if (pp->crpb) {
1167 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1168 pp->crpb = NULL;
1169 }
eb73d558
ML		 1170 /*
1171 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1172 * For later hardware, we have one unique sg_tbl per NCQ tag.
1173 */
1174 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1175 if (pp->sg_tbl[tag]) {
1176 if (tag == 0 || !IS_GEN_I(hpriv))
1177 dma_pool_free(hpriv->sg_tbl_pool,
1178 pp->sg_tbl[tag],
1179 pp->sg_tbl_dma[tag]);
1180 pp->sg_tbl[tag] = NULL;
1181 }
da2fa9ba
ML		 1182 }
1183}
1184
05b308e1
BR		 1185/**
1186 * mv_port_start - Port specific init/start routine.
1187 * @ap: ATA channel to manipulate
1188 *
1189 * Allocate and point to DMA memory, init port private memory,
1190 * zero indices.
1191 *
1192 * LOCKING:
1193 * Inherited from caller.
1194 */
31961943
BR		 1195static int mv_port_start(struct ata_port *ap)
1196{
cca3974e
JG		 1197 struct device *dev = ap->host->dev;
1198 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1199 struct mv_port_priv *pp;
dde20207 1200 int tag;
31961943 1201
24dc5f33 1202 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1203 if (!pp)
24dc5f33 1204 return -ENOMEM;
da2fa9ba 1205 ap->private_data = pp;
31961943 1206
da2fa9ba
ML		 1207 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1208 if (!pp->crqb)
1209 return -ENOMEM;
1210 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1211
da2fa9ba
ML		 1212 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1213 if (!pp->crpb)
1214 goto out_port_free_dma_mem;
1215 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1216
eb73d558
ML		 1217 /*
1218 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1219 * For later hardware, we need one unique sg_tbl per NCQ tag.
1220 */
1221 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1222 if (tag == 0 || !IS_GEN_I(hpriv)) {
1223 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1224 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1225 if (!pp->sg_tbl[tag])
1226 goto out_port_free_dma_mem;
1227 } else {
1228 pp->sg_tbl[tag] = pp->sg_tbl[0];
1229 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1230 }
1231 }
31961943 1232 return 0;
da2fa9ba
ML		 1233
1234out_port_free_dma_mem:
1235 mv_port_free_dma_mem(ap);
1236 return -ENOMEM;
31961943
BR		 1237}
1238
05b308e1
BR		 1239/**
1240 * mv_port_stop - Port specific cleanup/stop routine.
1241 * @ap: ATA channel to manipulate
1242 *
1243 * Stop DMA, cleanup port memory.
1244 *
1245 * LOCKING:
cca3974e 1246 * This routine uses the host lock to protect the DMA stop.
05b308e1 1247 */
31961943
BR		 1248static void mv_port_stop(struct ata_port *ap)
1249{
e12bef50 1250 mv_stop_edma(ap);
da2fa9ba 1251 mv_port_free_dma_mem(ap);
31961943
BR		 1252}
1253
05b308e1
BR		 1254/**
1255 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1256 * @qc: queued command whose SG list to source from
1257 *
1258 * Populate the SG list and mark the last entry.
1259 *
1260 * LOCKING:
1261 * Inherited from caller.
1262 */
6c08772e 1263static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1264{
1265 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1266 struct scatterlist *sg;
3be6cbd7 1267 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1268 unsigned int si;
31961943 1269
eb73d558 1270 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1271 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1272 dma_addr_t addr = sg_dma_address(sg);
1273 u32 sg_len = sg_dma_len(sg);
22374677 1274
4007b493
OJ		 1275 while (sg_len) {
1276 u32 offset = addr & 0xffff;
1277 u32 len = sg_len;
22374677 1278
4007b493
OJ		 1279 if ((offset + sg_len > 0x10000))
1280 len = 0x10000 - offset;
1281
1282 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1283 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1284 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1285
1286 sg_len -= len;
1287 addr += len;
1288
3be6cbd7 1289 last_sg = mv_sg;
4007b493 1290 mv_sg++;
4007b493 1291 }
31961943 1292 }
3be6cbd7
JG		 1293
1294 if (likely(last_sg))
1295 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1296}
1297
5796d1c4 1298static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1299{
559eedad 1300 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1301 (last ? CRQB_CMD_LAST : 0);
559eedad 1302 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1303}
1304
05b308e1
BR		 1305/**
1306 * mv_qc_prep - Host specific command preparation.
1307 * @qc: queued command to prepare
1308 *
1309 * This routine simply redirects to the general purpose routine
1310 * if command is not DMA. Else, it handles prep of the CRQB
1311 * (command request block), does some sanity checking, and calls
1312 * the SG load routine.
1313 *
1314 * LOCKING:
1315 * Inherited from caller.
1316 */
31961943
BR		 1317static void mv_qc_prep(struct ata_queued_cmd *qc)
1318{
1319 struct ata_port *ap = qc->ap;
1320 struct mv_port_priv *pp = ap->private_data;
e1469874 1321 __le16 *cw;
31961943
BR		 1322 struct ata_taskfile *tf;
1323 u16 flags = 0;
a6432436 1324 unsigned in_index;
31961943 1325
138bfdd0
ML		 1326 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1327 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1328 return;
20f733e7 1329
31961943
BR		 1330 /* Fill in command request block
1331 */
e4e7b892 1332 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1333 flags |= CRQB_FLAG_READ;
beec7dbc 1334 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1335 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1336 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1337
bdd4ddde 1338 /* get current queue index from software */
fcfb1f77 1339 in_index = pp->req_idx;
a6432436
ML		 1340
1341 pp->crqb[in_index].sg_addr =
eb73d558 1342 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1343 pp->crqb[in_index].sg_addr_hi =
eb73d558 1344 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1345 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1346
a6432436 1347 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1348 tf = &qc->tf;
1349
1350 /* Sadly, the CRQB cannot accomodate all registers--there are
1351 * only 11 bytes...so we must pick and choose required
1352 * registers based on the command. So, we drop feature and
1353 * hob_feature for [RW] DMA commands, but they are needed for
1354 * NCQ. NCQ will drop hob_nsect.
20f733e7 1355 */
31961943
BR		 1356 switch (tf->command) {
1357 case ATA_CMD_READ:
1358 case ATA_CMD_READ_EXT:
1359 case ATA_CMD_WRITE:
1360 case ATA_CMD_WRITE_EXT:
c15d85c8 1361 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1362 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1363 break;
31961943
BR		 1364 case ATA_CMD_FPDMA_READ:
1365 case ATA_CMD_FPDMA_WRITE:
8b260248 1366 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1367 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1368 break;
31961943
BR		 1369 default:
1370 /* The only other commands EDMA supports in non-queued and
1371 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1372 * of which are defined/used by Linux. If we get here, this
1373 * driver needs work.
1374 *
1375 * FIXME: modify libata to give qc_prep a return value and
1376 * return error here.
1377 */
1378 BUG_ON(tf->command);
1379 break;
1380 }
1381 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1382 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1383 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1384 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1385 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1386 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1387 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1388 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1389 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1390
e4e7b892
JG		 1391 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1392 return;
1393 mv_fill_sg(qc);
1394}
1395
1396/**
1397 * mv_qc_prep_iie - Host specific command preparation.
1398 * @qc: queued command to prepare
1399 *
1400 * This routine simply redirects to the general purpose routine
1401 * if command is not DMA. Else, it handles prep of the CRQB
1402 * (command request block), does some sanity checking, and calls
1403 * the SG load routine.
1404 *
1405 * LOCKING:
1406 * Inherited from caller.
1407 */
1408static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1409{
1410 struct ata_port *ap = qc->ap;
1411 struct mv_port_priv *pp = ap->private_data;
1412 struct mv_crqb_iie *crqb;
1413 struct ata_taskfile *tf;
a6432436 1414 unsigned in_index;
e4e7b892
JG		 1415 u32 flags = 0;
1416
138bfdd0
ML		 1417 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1418 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1419 return;
1420
e12bef50 1421 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1422 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1423 flags |= CRQB_FLAG_READ;
1424
beec7dbc 1425 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1426 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1427 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1428 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1429
bdd4ddde 1430 /* get current queue index from software */
fcfb1f77 1431 in_index = pp->req_idx;
a6432436
ML		 1432
1433 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1434 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1435 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1436 crqb->flags = cpu_to_le32(flags);
1437
1438 tf = &qc->tf;
1439 crqb->ata_cmd[0] = cpu_to_le32(
1440 (tf->command << 16) |
1441 (tf->feature << 24)
1442 );
1443 crqb->ata_cmd[1] = cpu_to_le32(
1444 (tf->lbal << 0) |
1445 (tf->lbam << 8) |
1446 (tf->lbah << 16) |
1447 (tf->device << 24)
1448 );
1449 crqb->ata_cmd[2] = cpu_to_le32(
1450 (tf->hob_lbal << 0) |
1451 (tf->hob_lbam << 8) |
1452 (tf->hob_lbah << 16) |
1453 (tf->hob_feature << 24)
1454 );
1455 crqb->ata_cmd[3] = cpu_to_le32(
1456 (tf->nsect << 0) |
1457 (tf->hob_nsect << 8)
1458 );
1459
1460 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1461 return;
31961943
BR		 1462 mv_fill_sg(qc);
1463}
1464
05b308e1
BR		 1465/**
1466 * mv_qc_issue - Initiate a command to the host
1467 * @qc: queued command to start
1468 *
1469 * This routine simply redirects to the general purpose routine
1470 * if command is not DMA. Else, it sanity checks our local
1471 * caches of the request producer/consumer indices then enables
1472 * DMA and bumps the request producer index.
1473 *
1474 * LOCKING:
1475 * Inherited from caller.
1476 */
9a3d9eb0 1477static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1478{
c5d3e45a
JG		 1479 struct ata_port *ap = qc->ap;
1480 void __iomem *port_mmio = mv_ap_base(ap);
1481 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1482 u32 in_index;
31961943 1483
138bfdd0
ML		 1484 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1485 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1486 /*
1487 * We're about to send a non-EDMA capable command to the
31961943
BR		 1488 * port. Turn off EDMA so there won't be problems accessing
1489 * shadow block, etc registers.
1490 */
b562468c 1491 mv_stop_edma(ap);
e49856d8 1492 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1493 return ata_sff_qc_issue(qc);
31961943
BR		 1494 }
1495
72109168 1496 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1497
fcfb1f77
ML		 1498 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1499 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1500
1501 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1502 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1503 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1504
1505 return 0;
1506}
1507
8f767f8a
ML		 1508static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1509{
1510 struct mv_port_priv *pp = ap->private_data;
1511 struct ata_queued_cmd *qc;
1512
1513 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1514 return NULL;
1515 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1516 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1517 qc = NULL;
1518 return qc;
1519}
1520
1521static void mv_unexpected_intr(struct ata_port *ap)
1522{
1523 struct mv_port_priv *pp = ap->private_data;
1524 struct ata_eh_info *ehi = &ap->link.eh_info;
1525 char *when = "";
1526
1527 /*
1528 * We got a device interrupt from something that
1529 * was supposed to be using EDMA or polling.
1530 */
1531 ata_ehi_clear_desc(ehi);
1532 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1533 when = " while EDMA enabled";
1534 } else {
1535 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1536 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1537 when = " while polling";
1538 }
1539 ata_ehi_push_desc(ehi, "unexpected device interrupt%s", when);
1540 ehi->err_mask |= AC_ERR_OTHER;
1541 ehi->action |= ATA_EH_RESET;
1542 ata_port_freeze(ap);
1543}
1544
05b308e1
BR		 1545/**
1546 * mv_err_intr - Handle error interrupts on the port
1547 * @ap: ATA channel to manipulate
8d07379d 1548 * @qc: affected command (non-NCQ), or NULL
05b308e1 1549 *
8d07379d
ML		 1550 * Most cases require a full reset of the chip's state machine,
1551 * which also performs a COMRESET.
1552 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1553 *
1554 * LOCKING:
1555 * Inherited from caller.
1556 */
bdd4ddde 1557static void mv_err_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
31961943
BR		 1558{
1559 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde
JG		 1560 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1561 struct mv_port_priv *pp = ap->private_data;
1562 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1563 unsigned int action = 0, err_mask = 0;
9af5c9c9 1564 struct ata_eh_info *ehi = &ap->link.eh_info;
20f733e7 1565
bdd4ddde 1566 ata_ehi_clear_desc(ehi);
20f733e7 1567
8d07379d
ML		 1568 /*
1569 * Read and clear the err_cause bits. This won't actually
1570 * clear for some errors (eg. SError), but we will be doing
1571 * a hard reset in those cases regardless, which *will* clear it.
1572 */
bdd4ddde 1573 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
8d07379d 1574 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1575
352fab70 1576 ata_ehi_push_desc(ehi, "edma_err_cause=%08x", edma_err_cause);
bdd4ddde
JG		 1577
1578 /*
352fab70 1579 * All generations share these EDMA error cause bits:
bdd4ddde 1580 */
bdd4ddde
JG		 1581 if (edma_err_cause & EDMA_ERR_DEV)
1582 err_mask |= AC_ERR_DEV;
1583 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1584 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1585 EDMA_ERR_INTRL_PAR)) {
1586 err_mask |= AC_ERR_ATA_BUS;
cf480626 1587 action |= ATA_EH_RESET;
b64bbc39 1588 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1589 }
1590 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1591 ata_ehi_hotplugged(ehi);
1592 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1593 "dev disconnect" : "dev connect");
cf480626 1594 action |= ATA_EH_RESET;
bdd4ddde
JG		 1595 }
1596
352fab70
ML		 1597 /*
1598 * Gen-I has a different SELF_DIS bit,
1599 * different FREEZE bits, and no SERR bit:
1600 */
ee9ccdf7 1601 if (IS_GEN_I(hpriv)) {
bdd4ddde 1602 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1603 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1604 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1605 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1606 }
1607 } else {
1608 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1609 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1610 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1611 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1612 }
bdd4ddde 1613 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1614 /*
1615 * Ensure that we read our own SCR, not a pmp link SCR:
1616 */
1617 ap->ops->scr_read(ap, SCR_ERROR, &serr);
1618 /*
1619 * Don't clear SError here; leave it for libata-eh:
1620 */
1621 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1622 err_mask |= AC_ERR_ATA_BUS;
cf480626 1623 action |= ATA_EH_RESET;
bdd4ddde 1624 }
afb0edd9 1625 }
20f733e7 1626
bdd4ddde
JG		 1627 if (!err_mask) {
1628 err_mask = AC_ERR_OTHER;
cf480626 1629 action |= ATA_EH_RESET;
bdd4ddde
JG		 1630 }
1631
1632 ehi->serror |= serr;
1633 ehi->action |= action;
1634
1635 if (qc)
1636 qc->err_mask |= err_mask;
1637 else
1638 ehi->err_mask |= err_mask;
1639
1640 if (edma_err_cause & eh_freeze_mask)
1641 ata_port_freeze(ap);
1642 else
1643 ata_port_abort(ap);
1644}
1645
fcfb1f77
ML		 1646static void mv_process_crpb_response(struct ata_port *ap,
1647 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1648{
1649 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1650
1651 if (qc) {
1652 u8 ata_status;
1653 u16 edma_status = le16_to_cpu(response->flags);
1654 /*
1655 * edma_status from a response queue entry:
1656 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1657 * MSB is saved ATA status from command completion.
1658 */
1659 if (!ncq_enabled) {
1660 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1661 if (err_cause) {
1662 /*
1663 * Error will be seen/handled by mv_err_intr().
1664 * So do nothing at all here.
1665 */
1666 return;
1667 }
1668 }
1669 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
1670 qc->err_mask |= ac_err_mask(ata_status);
1671 ata_qc_complete(qc);
1672 } else {
1673 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
1674 __func__, tag);
1675 }
1676}
1677
1678static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 1679{
1680 void __iomem *port_mmio = mv_ap_base(ap);
1681 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 1682 u32 in_index;
bdd4ddde 1683 bool work_done = false;
fcfb1f77 1684 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 1685
fcfb1f77 1686 /* Get the hardware queue position index */
bdd4ddde
JG		 1687 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1688 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1689
fcfb1f77
ML		 1690 /* Process new responses from since the last time we looked */
1691 while (in_index != pp->resp_idx) {
6c1153e0 1692 unsigned int tag;
fcfb1f77 1693 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 1694
fcfb1f77 1695 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 1696
fcfb1f77
ML		 1697 if (IS_GEN_I(hpriv)) {
1698 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 1699 tag = ap->link.active_tag;
fcfb1f77
ML		 1700 } else {
1701 /* Gen II/IIE: get command tag from CRPB entry */
1702 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 1703 }
fcfb1f77 1704 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 1705 work_done = true;
bdd4ddde
JG		 1706 }
1707
352fab70 1708 /* Update the software queue position index in hardware */
bdd4ddde
JG		 1709 if (work_done)
1710 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 1711 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 1712 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 1713}
1714
05b308e1
BR		 1715/**
1716 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 1717 * @host: host specific structure
7368f919 1718 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 1719 *
1720 * LOCKING:
1721 * Inherited from caller.
1722 */
7368f919 1723static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 1724{
f351b2d6 1725 struct mv_host_priv *hpriv = host->private_data;
a3718c1f
ML		 1726 void __iomem *mmio = hpriv->base, *hc_mmio = NULL;
1727 u32 hc_irq_cause = 0;
1728 unsigned int handled = 0, port;
20f733e7 1729
a3718c1f 1730 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 1731 struct ata_port *ap = host->ports[port];
8f71efe2 1732 struct mv_port_priv *pp;
a3718c1f
ML		 1733 unsigned int shift, hardport, port_cause;
1734 /*
1735 * When we move to the second hc, flag our cached
1736 * copies of hc_mmio (and hc_irq_cause) as invalid again.
1737 */
1738 if (port == MV_PORTS_PER_HC)
1739 hc_mmio = NULL;
1740 /*
1741 * Do nothing if port is not interrupting or is disabled:
1742 */
1743 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
7368f919 1744 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
a3718c1f 1745 if (!port_cause || !ap || (ap->flags & ATA_FLAG_DISABLED))
a2c91a88 1746 continue;
a3718c1f
ML		 1747 /*
1748 * Each hc within the host has its own hc_irq_cause register.
1749 * We defer reading it until we know we need it, right now:
1750 *
1751 * FIXME later: we don't really need to read this register
1752 * (some logic changes required below if we go that way),
1753 * because it doesn't tell us anything new. But we do need
1754 * to write to it, outside the top of this loop,
1755 * to reset the interrupt triggers for next time.
1756 */
1757 if (!hc_mmio) {
1758 hc_mmio = mv_hc_base_from_port(mmio, port);
1759 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1760 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1761 handled = 1;
1762 }
8f767f8a
ML		 1763 /*
1764 * Process completed CRPB response(s) before other events.
1765 */
a3718c1f 1766 pp = ap->private_data;
8f767f8a
ML		 1767 if (hc_irq_cause & (DMA_IRQ << hardport)) {
1768 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN)
fcfb1f77 1769 mv_process_crpb_entries(ap, pp);
8f767f8a
ML		 1770 }
1771 /*
1772 * Handle chip-reported errors, or continue on to handle PIO.
1773 */
1774 if (unlikely(port_cause & ERR_IRQ)) {
1775 mv_err_intr(ap, mv_get_active_qc(ap));
1776 } else if (hc_irq_cause & (DEV_IRQ << hardport)) {
1777 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
1778 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
1779 if (qc) {
1780 ata_sff_host_intr(ap, qc);
1781 continue;
1782 }
1783 }
1784 mv_unexpected_intr(ap);
20f733e7
BR		 1785 }
1786 }
a3718c1f 1787 return handled;
20f733e7
BR		 1788}
1789
a3718c1f 1790static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 1791{
02a121da 1792 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 1793 struct ata_port *ap;
1794 struct ata_queued_cmd *qc;
1795 struct ata_eh_info *ehi;
1796 unsigned int i, err_mask, printed = 0;
1797 u32 err_cause;
1798
02a121da 1799 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1800
1801 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
1802 err_cause);
1803
1804 DPRINTK("All regs @ PCI error\n");
1805 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1806
02a121da 1807 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 1808
1809 for (i = 0; i < host->n_ports; i++) {
1810 ap = host->ports[i];
936fd732 1811 if (!ata_link_offline(&ap->link)) {
9af5c9c9 1812 ehi = &ap->link.eh_info;
bdd4ddde
JG		 1813 ata_ehi_clear_desc(ehi);
1814 if (!printed++)
1815 ata_ehi_push_desc(ehi,
1816 "PCI err cause 0x%08x", err_cause);
1817 err_mask = AC_ERR_HOST_BUS;
cf480626 1818 ehi->action = ATA_EH_RESET;
9af5c9c9 1819 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 1820 if (qc)
1821 qc->err_mask |= err_mask;
1822 else
1823 ehi->err_mask |= err_mask;
1824
1825 ata_port_freeze(ap);
1826 }
1827 }
a3718c1f 1828 return 1; /* handled */
bdd4ddde
JG		 1829}
1830
05b308e1 1831/**
c5d3e45a 1832 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 1833 * @irq: unused
1834 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 1835 *
1836 * Read the read only register to determine if any host
1837 * controllers have pending interrupts. If so, call lower level
1838 * routine to handle. Also check for PCI errors which are only
1839 * reported here.
1840 *
8b260248 1841 * LOCKING:
cca3974e 1842 * This routine holds the host lock while processing pending
05b308e1
BR		 1843 * interrupts.
1844 */
7d12e780 1845static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 1846{
cca3974e 1847 struct ata_host *host = dev_instance;
f351b2d6 1848 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 1849 unsigned int handled = 0;
7368f919 1850 u32 main_irq_cause, main_irq_mask;
20f733e7 1851
646a4da5 1852 spin_lock(&host->lock);
7368f919
ML		 1853 main_irq_cause = readl(hpriv->main_irq_cause_addr);
1854 main_irq_mask = readl(hpriv->main_irq_mask_addr);
352fab70
ML		 1855 /*
1856 * Deal with cases where we either have nothing pending, or have read
1857 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 1858 */
7368f919
ML		 1859 if ((main_irq_cause & main_irq_mask) && (main_irq_cause != 0xffffffffU)) {
1860 if (unlikely((main_irq_cause & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 1861 handled = mv_pci_error(host, hpriv->base);
1862 else
7368f919 1863 handled = mv_host_intr(host, main_irq_cause);
bdd4ddde 1864 }
cca3974e 1865 spin_unlock(&host->lock);
20f733e7
BR		 1866 return IRQ_RETVAL(handled);
1867}
1868
c9d39130
JG		 1869static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1870{
1871 unsigned int ofs;
1872
1873 switch (sc_reg_in) {
1874 case SCR_STATUS:
1875 case SCR_ERROR:
1876 case SCR_CONTROL:
1877 ofs = sc_reg_in * sizeof(u32);
1878 break;
1879 default:
1880 ofs = 0xffffffffU;
1881 break;
1882 }
1883 return ofs;
1884}
1885
da3dbb17 1886static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 1887{
f351b2d6
SB		 1888 struct mv_host_priv *hpriv = ap->host->private_data;
1889 void __iomem *mmio = hpriv->base;
0d5ff566 1890 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1891 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1892
da3dbb17
TH		 1893 if (ofs != 0xffffffffU) {
1894 *val = readl(addr + ofs);
1895 return 0;
1896 } else
1897 return -EINVAL;
c9d39130
JG		 1898}
1899
da3dbb17 1900static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 1901{
f351b2d6
SB		 1902 struct mv_host_priv *hpriv = ap->host->private_data;
1903 void __iomem *mmio = hpriv->base;
0d5ff566 1904 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 1905 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1906
da3dbb17 1907 if (ofs != 0xffffffffU) {
0d5ff566 1908 writelfl(val, addr + ofs);
da3dbb17
TH		 1909 return 0;
1910 } else
1911 return -EINVAL;
c9d39130
JG		 1912}
1913
7bb3c529 1914static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 1915{
7bb3c529 1916 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 1917 int early_5080;
1918
44c10138 1919 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 1920
1921 if (!early_5080) {
1922 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1923 tmp |= (1 << 0);
1924 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1925 }
1926
7bb3c529 1927 mv_reset_pci_bus(host, mmio);
522479fb
JG		 1928}
1929
1930static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1931{
8e7decdb 1932 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 1933}
1934
47c2b677 1935static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 1936 void __iomem *mmio)
1937{
c9d39130
JG		 1938 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1939 u32 tmp;
1940
1941 tmp = readl(phy_mmio + MV5_PHY_MODE);
1942
1943 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1944 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 1945}
1946
47c2b677 1947static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 1948{
522479fb
JG		 1949 u32 tmp;
1950
8e7decdb 1951 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 1952
1953 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1954
1955 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1956 tmp |= ~(1 << 0);
1957 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 1958}
1959
2a47ce06
JG		 1960static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1961 unsigned int port)
bca1c4eb 1962{
c9d39130
JG		 1963 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1964 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1965 u32 tmp;
1966 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1967
1968 if (fix_apm_sq) {
8e7decdb 1969 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 1970 tmp |= (1 << 19);
8e7decdb 1971 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 1972
8e7decdb 1973 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 1974 tmp &= ~0x3;
1975 tmp |= 0x1;
8e7decdb 1976 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 1977 }
1978
1979 tmp = readl(phy_mmio + MV5_PHY_MODE);
1980 tmp &= ~mask;
1981 tmp |= hpriv->signal[port].pre;
1982 tmp |= hpriv->signal[port].amps;
1983 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 1984}
1985
c9d39130
JG		 1986
1987#undef ZERO
1988#define ZERO(reg) writel(0, port_mmio + (reg))
1989static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1990 unsigned int port)
1991{
1992 void __iomem *port_mmio = mv_port_base(mmio, port);
1993
e12bef50 1994 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 1995
1996 ZERO(0x028); /* command */
1997 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1998 ZERO(0x004); /* timer */
1999 ZERO(0x008); /* irq err cause */
2000 ZERO(0x00c); /* irq err mask */
2001 ZERO(0x010); /* rq bah */
2002 ZERO(0x014); /* rq inp */
2003 ZERO(0x018); /* rq outp */
2004 ZERO(0x01c); /* respq bah */
2005 ZERO(0x024); /* respq outp */
2006 ZERO(0x020); /* respq inp */
2007 ZERO(0x02c); /* test control */
8e7decdb 2008 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2009}
2010#undef ZERO
2011
2012#define ZERO(reg) writel(0, hc_mmio + (reg))
2013static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2014 unsigned int hc)
47c2b677 2015{
c9d39130
JG		 2016 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2017 u32 tmp;
2018
2019 ZERO(0x00c);
2020 ZERO(0x010);
2021 ZERO(0x014);
2022 ZERO(0x018);
2023
2024 tmp = readl(hc_mmio + 0x20);
2025 tmp &= 0x1c1c1c1c;
2026 tmp |= 0x03030303;
2027 writel(tmp, hc_mmio + 0x20);
2028}
2029#undef ZERO
2030
2031static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2032 unsigned int n_hc)
2033{
2034 unsigned int hc, port;
2035
2036 for (hc = 0; hc < n_hc; hc++) {
2037 for (port = 0; port < MV_PORTS_PER_HC; port++)
2038 mv5_reset_hc_port(hpriv, mmio,
2039 (hc * MV_PORTS_PER_HC) + port);
2040
2041 mv5_reset_one_hc(hpriv, mmio, hc);
2042 }
2043
2044 return 0;
47c2b677
JG		 2045}
2046
101ffae2
JG		 2047#undef ZERO
2048#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2049static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2050{
02a121da 2051 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2052 u32 tmp;
2053
8e7decdb 2054 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2055 tmp &= 0xff00ffff;
8e7decdb 2056 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2057
2058 ZERO(MV_PCI_DISC_TIMER);
2059 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2060 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
7368f919 2061 ZERO(PCI_HC_MAIN_IRQ_MASK_OFS);
101ffae2 2062 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2063 ZERO(hpriv->irq_cause_ofs);
2064 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2065 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2066 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2067 ZERO(MV_PCI_ERR_ATTRIBUTE);
2068 ZERO(MV_PCI_ERR_COMMAND);
2069}
2070#undef ZERO
2071
2072static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2073{
2074 u32 tmp;
2075
2076 mv5_reset_flash(hpriv, mmio);
2077
8e7decdb 2078 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2079 tmp &= 0x3;
2080 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2081 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2082}
2083
2084/**
2085 * mv6_reset_hc - Perform the 6xxx global soft reset
2086 * @mmio: base address of the HBA
2087 *
2088 * This routine only applies to 6xxx parts.
2089 *
2090 * LOCKING:
2091 * Inherited from caller.
2092 */
c9d39130
JG		 2093static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2094 unsigned int n_hc)
101ffae2
JG		 2095{
2096 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2097 int i, rc = 0;
2098 u32 t;
2099
2100 /* Following procedure defined in PCI "main command and status
2101 * register" table.
2102 */
2103 t = readl(reg);
2104 writel(t | STOP_PCI_MASTER, reg);
2105
2106 for (i = 0; i < 1000; i++) {
2107 udelay(1);
2108 t = readl(reg);
2dcb407e 2109 if (PCI_MASTER_EMPTY & t)
101ffae2 2110 break;
101ffae2
JG		 2111 }
2112 if (!(PCI_MASTER_EMPTY & t)) {
2113 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2114 rc = 1;
2115 goto done;
2116 }
2117
2118 /* set reset */
2119 i = 5;
2120 do {
2121 writel(t | GLOB_SFT_RST, reg);
2122 t = readl(reg);
2123 udelay(1);
2124 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2125
2126 if (!(GLOB_SFT_RST & t)) {
2127 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2128 rc = 1;
2129 goto done;
2130 }
2131
2132 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2133 i = 5;
2134 do {
2135 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2136 t = readl(reg);
2137 udelay(1);
2138 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2139
2140 if (GLOB_SFT_RST & t) {
2141 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2142 rc = 1;
2143 }
2144done:
2145 return rc;
2146}
2147
47c2b677 2148static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2149 void __iomem *mmio)
2150{
2151 void __iomem *port_mmio;
2152 u32 tmp;
2153
8e7decdb 2154 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2155 if ((tmp & (1 << 0)) == 0) {
47c2b677 2156 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2157 hpriv->signal[idx].pre = 0x1 << 5;
2158 return;
2159 }
2160
2161 port_mmio = mv_port_base(mmio, idx);
2162 tmp = readl(port_mmio + PHY_MODE2);
2163
2164 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2165 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2166}
2167
47c2b677 2168static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2169{
8e7decdb 2170 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2171}
2172
c9d39130 2173static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2174 unsigned int port)
bca1c4eb 2175{
c9d39130
JG		 2176 void __iomem *port_mmio = mv_port_base(mmio, port);
2177
bca1c4eb 2178 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2179 int fix_phy_mode2 =
2180 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2181 int fix_phy_mode4 =
47c2b677
JG		 2182 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2183 u32 m2, tmp;
2184
2185 if (fix_phy_mode2) {
2186 m2 = readl(port_mmio + PHY_MODE2);
2187 m2 &= ~(1 << 16);
2188 m2 |= (1 << 31);
2189 writel(m2, port_mmio + PHY_MODE2);
2190
2191 udelay(200);
2192
2193 m2 = readl(port_mmio + PHY_MODE2);
2194 m2 &= ~((1 << 16) | (1 << 31));
2195 writel(m2, port_mmio + PHY_MODE2);
2196
2197 udelay(200);
2198 }
2199
2200 /* who knows what this magic does */
2201 tmp = readl(port_mmio + PHY_MODE3);
2202 tmp &= ~0x7F800000;
2203 tmp |= 0x2A800000;
2204 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2205
2206 if (fix_phy_mode4) {
47c2b677 2207 u32 m4;
bca1c4eb
JG		 2208
2209 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2210
2211 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2212 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2213
e12bef50 2214 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2215 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2216
2217 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2218
2219 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2220 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2221 }
2222
2223 /* Revert values of pre-emphasis and signal amps to the saved ones */
2224 m2 = readl(port_mmio + PHY_MODE2);
2225
2226 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2227 m2 |= hpriv->signal[port].amps;
2228 m2 |= hpriv->signal[port].pre;
47c2b677 2229 m2 &= ~(1 << 16);
bca1c4eb 2230
e4e7b892
JG		 2231 /* according to mvSata 3.6.1, some IIE values are fixed */
2232 if (IS_GEN_IIE(hpriv)) {
2233 m2 &= ~0xC30FF01F;
2234 m2 |= 0x0000900F;
2235 }
2236
bca1c4eb
JG		 2237 writel(m2, port_mmio + PHY_MODE2);
2238}
2239
f351b2d6
SB		 2240/* TODO: use the generic LED interface to configure the SATA Presence */
2241/* & Acitivy LEDs on the board */
2242static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2243 void __iomem *mmio)
2244{
2245 return;
2246}
2247
2248static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2249 void __iomem *mmio)
2250{
2251 void __iomem *port_mmio;
2252 u32 tmp;
2253
2254 port_mmio = mv_port_base(mmio, idx);
2255 tmp = readl(port_mmio + PHY_MODE2);
2256
2257 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2258 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2259}
2260
2261#undef ZERO
2262#define ZERO(reg) writel(0, port_mmio + (reg))
2263static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2264 void __iomem *mmio, unsigned int port)
2265{
2266 void __iomem *port_mmio = mv_port_base(mmio, port);
2267
e12bef50 2268 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2269
2270 ZERO(0x028); /* command */
2271 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2272 ZERO(0x004); /* timer */
2273 ZERO(0x008); /* irq err cause */
2274 ZERO(0x00c); /* irq err mask */
2275 ZERO(0x010); /* rq bah */
2276 ZERO(0x014); /* rq inp */
2277 ZERO(0x018); /* rq outp */
2278 ZERO(0x01c); /* respq bah */
2279 ZERO(0x024); /* respq outp */
2280 ZERO(0x020); /* respq inp */
2281 ZERO(0x02c); /* test control */
8e7decdb 2282 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2283}
2284
2285#undef ZERO
2286
2287#define ZERO(reg) writel(0, hc_mmio + (reg))
2288static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2289 void __iomem *mmio)
2290{
2291 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2292
2293 ZERO(0x00c);
2294 ZERO(0x010);
2295 ZERO(0x014);
2296
2297}
2298
2299#undef ZERO
2300
2301static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2302 void __iomem *mmio, unsigned int n_hc)
2303{
2304 unsigned int port;
2305
2306 for (port = 0; port < hpriv->n_ports; port++)
2307 mv_soc_reset_hc_port(hpriv, mmio, port);
2308
2309 mv_soc_reset_one_hc(hpriv, mmio);
2310
2311 return 0;
2312}
2313
2314static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2315 void __iomem *mmio)
2316{
2317 return;
2318}
2319
2320static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2321{
2322 return;
2323}
2324
8e7decdb 2325static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2326{
8e7decdb 2327 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2328
8e7decdb 2329 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2330 if (want_gen2i)
8e7decdb
ML		 2331 ifcfg |= (1 << 7); /* enable gen2i speed */
2332 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2333}
2334
e12bef50 2335static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2336 unsigned int port_no)
2337{
2338 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2339
8e7decdb
ML		 2340 /*
2341 * The datasheet warns against setting EDMA_RESET when EDMA is active
2342 * (but doesn't say what the problem might be). So we first try
2343 * to disable the EDMA engine before doing the EDMA_RESET operation.
2344 */
0d8be5cb 2345 mv_stop_edma_engine(port_mmio);
8e7decdb 2346 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2347
b67a1064 2348 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2349 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2350 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2351 }
b67a1064 2352 /*
8e7decdb 2353 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2354 * link, and physical layers. It resets all SATA interface registers
2355 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2356 */
8e7decdb 2357 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2358 udelay(25); /* allow reset propagation */
c9d39130
JG		 2359 writelfl(0, port_mmio + EDMA_CMD_OFS);
2360
2361 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2362
ee9ccdf7 2363 if (IS_GEN_I(hpriv))
c9d39130
JG		 2364 mdelay(1);
2365}
2366
e49856d8 2367static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2368{
e49856d8
ML		 2369 if (sata_pmp_supported(ap)) {
2370 void __iomem *port_mmio = mv_ap_base(ap);
2371 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2372 int old = reg & 0xf;
22374677 2373
e49856d8
ML		 2374 if (old != pmp) {
2375 reg = (reg & ~0xf) | pmp;
2376 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2377 }
22374677 2378 }
20f733e7
BR		 2379}
2380
e49856d8
ML		 2381static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2382 unsigned long deadline)
22374677 2383{
e49856d8
ML		 2384 mv_pmp_select(link->ap, sata_srst_pmp(link));
2385 return sata_std_hardreset(link, class, deadline);
2386}
bdd4ddde 2387
e49856d8
ML		 2388static int mv_softreset(struct ata_link *link, unsigned int *class,
2389 unsigned long deadline)
2390{
2391 mv_pmp_select(link->ap, sata_srst_pmp(link));
2392 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2393}
2394
cc0680a5 2395static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2396 unsigned long deadline)
31961943 2397{
cc0680a5 2398 struct ata_port *ap = link->ap;
bdd4ddde 2399 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2400 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2401 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2402 int rc, attempts = 0, extra = 0;
2403 u32 sstatus;
2404 bool online;
31961943 2405
e12bef50 2406 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2407 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2408
0d8be5cb
ML		 2409 /* Workaround for errata FEr SATA#10 (part 2) */
2410 do {
17c5aab5
ML		 2411 const unsigned long *timing =
2412 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2413
17c5aab5
ML		 2414 rc = sata_link_hardreset(link, timing, deadline + extra,
2415 &online, NULL);
2416 if (rc)
0d8be5cb 2417 return rc;
0d8be5cb
ML		 2418 sata_scr_read(link, SCR_STATUS, &sstatus);
2419 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2420 /* Force 1.5gb/s link speed and try again */
8e7decdb 2421 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2422 if (time_after(jiffies + HZ, deadline))
2423 extra = HZ; /* only extend it once, max */
2424 }
2425 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2426
17c5aab5 2427 return rc;
bdd4ddde
JG		 2428}
2429
bdd4ddde
JG		 2430static void mv_eh_freeze(struct ata_port *ap)
2431{
f351b2d6 2432 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae 2433 unsigned int shift, hardport, port = ap->port_no;
7368f919 2434 u32 main_irq_mask;
bdd4ddde
JG		 2435
2436 /* FIXME: handle coalescing completion events properly */
2437
1cfd19ae
ML		 2438 mv_stop_edma(ap);
2439 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2440
bdd4ddde 2441 /* disable assertion of portN err, done events */
7368f919
ML		 2442 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2443 main_irq_mask &= ~((DONE_IRQ | ERR_IRQ) << shift);
2444 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
bdd4ddde
JG		 2445}
2446
2447static void mv_eh_thaw(struct ata_port *ap)
2448{
f351b2d6 2449 struct mv_host_priv *hpriv = ap->host->private_data;
1cfd19ae
ML		 2450 unsigned int shift, hardport, port = ap->port_no;
2451 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2452 void __iomem *port_mmio = mv_ap_base(ap);
7368f919 2453 u32 main_irq_mask, hc_irq_cause;
bdd4ddde
JG		 2454
2455 /* FIXME: handle coalescing completion events properly */
2456
1cfd19ae 2457 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
bdd4ddde 2458
bdd4ddde
JG		 2459 /* clear EDMA errors on this port */
2460 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2461
2462 /* clear pending irq events */
2463 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2464 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2465 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde
JG		 2466
2467 /* enable assertion of portN err, done events */
7368f919
ML		 2468 main_irq_mask = readl(hpriv->main_irq_mask_addr);
2469 main_irq_mask |= ((DONE_IRQ | ERR_IRQ) << shift);
2470 writelfl(main_irq_mask, hpriv->main_irq_mask_addr);
31961943
BR		 2471}
2472
05b308e1
BR		 2473/**
2474 * mv_port_init - Perform some early initialization on a single port.
2475 * @port: libata data structure storing shadow register addresses
2476 * @port_mmio: base address of the port
2477 *
2478 * Initialize shadow register mmio addresses, clear outstanding
2479 * interrupts on the port, and unmask interrupts for the future
2480 * start of the port.
2481 *
2482 * LOCKING:
2483 * Inherited from caller.
2484 */
31961943 2485static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2486{
0d5ff566 2487 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2488 unsigned serr_ofs;
2489
8b260248 2490 /* PIO related setup
31961943
BR		 2491 */
2492 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2493 port->error_addr =
31961943
BR		 2494 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2495 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2496 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2497 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2498 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2499 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2500 port->status_addr =
31961943
BR		 2501 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2502 /* special case: control/altstatus doesn't have ATA_REG_ address */
2503 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2504
2505 /* unused: */
8d9db2d2 2506 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2507
31961943
BR		 2508 /* Clear any currently outstanding port interrupt conditions */
2509 serr_ofs = mv_scr_offset(SCR_ERROR);
2510 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2511 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2512
646a4da5
ML		 2513 /* unmask all non-transient EDMA error interrupts */
2514 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2515
8b260248 2516 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2517 readl(port_mmio + EDMA_CFG_OFS),
2518 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2519 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2520}
2521
616d4a98
ML		 2522static unsigned int mv_in_pcix_mode(struct ata_host *host)
2523{
2524 struct mv_host_priv *hpriv = host->private_data;
2525 void __iomem *mmio = hpriv->base;
2526 u32 reg;
2527
2528 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2529 return 0; /* not PCI-X capable */
2530 reg = readl(mmio + MV_PCI_MODE_OFS);
2531 if ((reg & MV_PCI_MODE_MASK) == 0)
2532 return 0; /* conventional PCI mode */
2533 return 1; /* chip is in PCI-X mode */
2534}
2535
2536static int mv_pci_cut_through_okay(struct ata_host *host)
2537{
2538 struct mv_host_priv *hpriv = host->private_data;
2539 void __iomem *mmio = hpriv->base;
2540 u32 reg;
2541
2542 if (!mv_in_pcix_mode(host)) {
2543 reg = readl(mmio + PCI_COMMAND_OFS);
2544 if (reg & PCI_COMMAND_MRDTRIG)
2545 return 0; /* not okay */
2546 }
2547 return 1; /* okay */
2548}
2549
4447d351 2550static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2551{
4447d351
TH		 2552 struct pci_dev *pdev = to_pci_dev(host->dev);
2553 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2554 u32 hp_flags = hpriv->hp_flags;
2555
5796d1c4 2556 switch (board_idx) {
47c2b677
JG		 2557 case chip_5080:
2558 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2559 hp_flags |= MV_HP_GEN_I;
47c2b677 2560
44c10138 2561 switch (pdev->revision) {
47c2b677
JG		 2562 case 0x1:
2563 hp_flags |= MV_HP_ERRATA_50XXB0;
2564 break;
2565 case 0x3:
2566 hp_flags |= MV_HP_ERRATA_50XXB2;
2567 break;
2568 default:
2569 dev_printk(KERN_WARNING, &pdev->dev,
2570 "Applying 50XXB2 workarounds to unknown rev\n");
2571 hp_flags |= MV_HP_ERRATA_50XXB2;
2572 break;
2573 }
2574 break;
2575
bca1c4eb
JG		 2576 case chip_504x:
2577 case chip_508x:
47c2b677 2578 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2579 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2580
44c10138 2581 switch (pdev->revision) {
47c2b677
JG		 2582 case 0x0:
2583 hp_flags |= MV_HP_ERRATA_50XXB0;
2584 break;
2585 case 0x3:
2586 hp_flags |= MV_HP_ERRATA_50XXB2;
2587 break;
2588 default:
2589 dev_printk(KERN_WARNING, &pdev->dev,
2590 "Applying B2 workarounds to unknown rev\n");
2591 hp_flags |= MV_HP_ERRATA_50XXB2;
2592 break;
bca1c4eb
JG		 2593 }
2594 break;
2595
2596 case chip_604x:
2597 case chip_608x:
47c2b677 2598 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2599 hp_flags |= MV_HP_GEN_II;
47c2b677 2600
44c10138 2601 switch (pdev->revision) {
47c2b677
JG		 2602 case 0x7:
2603 hp_flags |= MV_HP_ERRATA_60X1B2;
2604 break;
2605 case 0x9:
2606 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2607 break;
2608 default:
2609 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2610 "Applying B2 workarounds to unknown rev\n");
2611 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2612 break;
2613 }
2614 break;
2615
e4e7b892 2616 case chip_7042:
616d4a98 2617 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2618 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2619 (pdev->device == 0x2300 || pdev->device == 0x2310))
2620 {
4e520033
ML		 2621 /*
2622 * Highpoint RocketRAID PCIe 23xx series cards:
2623 *
2624 * Unconfigured drives are treated as "Legacy"
2625 * by the BIOS, and it overwrites sector 8 with
2626 * a "Lgcy" metadata block prior to Linux boot.
2627 *
2628 * Configured drives (RAID or JBOD) leave sector 8
2629 * alone, but instead overwrite a high numbered
2630 * sector for the RAID metadata. This sector can
2631 * be determined exactly, by truncating the physical
2632 * drive capacity to a nice even GB value.
2633 *
2634 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2635 *
2636 * Warn the user, lest they think we're just buggy.
2637 */
2638 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2639 " BIOS CORRUPTS DATA on all attached drives,"
2640 " regardless of if/how they are configured."
2641 " BEWARE!\n");
2642 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2643 " use sectors 8-9 on \"Legacy\" drives,"
2644 " and avoid the final two gigabytes on"
2645 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2646 }
8e7decdb 2647 /* drop through */
e4e7b892
JG		 2648 case chip_6042:
2649 hpriv->ops = &mv6xxx_ops;
e4e7b892 2650 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 2651 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
2652 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 2653
44c10138 2654 switch (pdev->revision) {
e4e7b892
JG		 2655 case 0x0:
2656 hp_flags |= MV_HP_ERRATA_XX42A0;
2657 break;
2658 case 0x1:
2659 hp_flags |= MV_HP_ERRATA_60X1C0;
2660 break;
2661 default:
2662 dev_printk(KERN_WARNING, &pdev->dev,
2663 "Applying 60X1C0 workarounds to unknown rev\n");
2664 hp_flags |= MV_HP_ERRATA_60X1C0;
2665 break;
2666 }
2667 break;
f351b2d6
SB		 2668 case chip_soc:
2669 hpriv->ops = &mv_soc_ops;
2670 hp_flags |= MV_HP_ERRATA_60X1C0;
2671 break;
e4e7b892 2672
bca1c4eb 2673 default:
f351b2d6 2674 dev_printk(KERN_ERR, host->dev,
5796d1c4 2675 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 2676 return 1;
2677 }
2678
2679 hpriv->hp_flags = hp_flags;
02a121da
ML		 2680 if (hp_flags & MV_HP_PCIE) {
2681 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
2682 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
2683 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
2684 } else {
2685 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
2686 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
2687 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
2688 }
bca1c4eb
JG		 2689
2690 return 0;
2691}
2692
05b308e1 2693/**
47c2b677 2694 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 2695 * @host: ATA host to initialize
2696 * @board_idx: controller index
05b308e1
BR		 2697 *
2698 * If possible, do an early global reset of the host. Then do
2699 * our port init and clear/unmask all/relevant host interrupts.
2700 *
2701 * LOCKING:
2702 * Inherited from caller.
2703 */
4447d351 2704static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 2705{
2706 int rc = 0, n_hc, port, hc;
4447d351 2707 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 2708 void __iomem *mmio = hpriv->base;
47c2b677 2709
4447d351 2710 rc = mv_chip_id(host, board_idx);
bca1c4eb 2711 if (rc)
352fab70 2712 goto done;
f351b2d6
SB		 2713
2714 if (HAS_PCI(host)) {
7368f919
ML		 2715 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
2716 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2717 } else {
7368f919
ML		 2718 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
2719 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 2720 }
352fab70
ML		 2721
2722 /* global interrupt mask: 0 == mask everything */
7368f919 2723 writel(0, hpriv->main_irq_mask_addr);
bca1c4eb 2724
4447d351 2725 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 2726
4447d351 2727 for (port = 0; port < host->n_ports; port++)
47c2b677 2728 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 2729
c9d39130 2730 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 2731 if (rc)
20f733e7 2732 goto done;
20f733e7 2733
522479fb 2734 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 2735 hpriv->ops->reset_bus(host, mmio);
47c2b677 2736 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 2737
4447d351 2738 for (port = 0; port < host->n_ports; port++) {
cbcdd875 2739 struct ata_port *ap = host->ports[port];
2a47ce06 2740 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 2741
2742 mv_port_init(&ap->ioaddr, port_mmio);
2743
7bb3c529 2744#ifdef CONFIG_PCI
f351b2d6
SB		 2745 if (HAS_PCI(host)) {
2746 unsigned int offset = port_mmio - mmio;
2747 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
2748 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
2749 }
7bb3c529 2750#endif
20f733e7
BR		 2751 }
2752
2753 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 2754 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2755
2756 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2757 "(before clear)=0x%08x\n", hc,
2758 readl(hc_mmio + HC_CFG_OFS),
2759 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2760
2761 /* Clear any currently outstanding hc interrupt conditions */
2762 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 2763 }
2764
f351b2d6
SB		 2765 if (HAS_PCI(host)) {
2766 /* Clear any currently outstanding host interrupt conditions */
2767 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 2768
f351b2d6
SB		 2769 /* and unmask interrupt generation for host regs */
2770 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
2771 if (IS_GEN_I(hpriv))
2772 writelfl(~HC_MAIN_MASKED_IRQS_5,
7368f919 2773 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2774 else
2775 writelfl(~HC_MAIN_MASKED_IRQS,
7368f919 2776 hpriv->main_irq_mask_addr);
f351b2d6
SB		 2777
2778 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2779 "PCI int cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2780 readl(hpriv->main_irq_cause_addr),
2781 readl(hpriv->main_irq_mask_addr),
f351b2d6
SB		 2782 readl(mmio + hpriv->irq_cause_ofs),
2783 readl(mmio + hpriv->irq_mask_ofs));
2784 } else {
2785 writelfl(~HC_MAIN_MASKED_IRQS_SOC,
7368f919 2786 hpriv->main_irq_mask_addr);
f351b2d6 2787 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x\n",
7368f919
ML		 2788 readl(hpriv->main_irq_cause_addr),
2789 readl(hpriv->main_irq_mask_addr));
f351b2d6
SB		 2790 }
2791done:
2792 return rc;
2793}
fb621e2f 2794
fbf14e2f
BB		 2795static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
2796{
2797 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
2798 MV_CRQB_Q_SZ, 0);
2799 if (!hpriv->crqb_pool)
2800 return -ENOMEM;
2801
2802 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
2803 MV_CRPB_Q_SZ, 0);
2804 if (!hpriv->crpb_pool)
2805 return -ENOMEM;
2806
2807 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
2808 MV_SG_TBL_SZ, 0);
2809 if (!hpriv->sg_tbl_pool)
2810 return -ENOMEM;
2811
2812 return 0;
2813}
2814
15a32632
LB		 2815static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
2816 struct mbus_dram_target_info *dram)
2817{
2818 int i;
2819
2820 for (i = 0; i < 4; i++) {
2821 writel(0, hpriv->base + WINDOW_CTRL(i));
2822 writel(0, hpriv->base + WINDOW_BASE(i));
2823 }
2824
2825 for (i = 0; i < dram->num_cs; i++) {
2826 struct mbus_dram_window *cs = dram->cs + i;
2827
2828 writel(((cs->size - 1) & 0xffff0000) |
2829 (cs->mbus_attr << 8) |
2830 (dram->mbus_dram_target_id << 4) | 1,
2831 hpriv->base + WINDOW_CTRL(i));
2832 writel(cs->base, hpriv->base + WINDOW_BASE(i));
2833 }
2834}
2835
f351b2d6
SB		 2836/**
2837 * mv_platform_probe - handle a positive probe of an soc Marvell
2838 * host
2839 * @pdev: platform device found
2840 *
2841 * LOCKING:
2842 * Inherited from caller.
2843 */
2844static int mv_platform_probe(struct platform_device *pdev)
2845{
2846 static int printed_version;
2847 const struct mv_sata_platform_data *mv_platform_data;
2848 const struct ata_port_info *ppi[] =
2849 { &mv_port_info[chip_soc], NULL };
2850 struct ata_host *host;
2851 struct mv_host_priv *hpriv;
2852 struct resource *res;
2853 int n_ports, rc;
20f733e7 2854
f351b2d6
SB		 2855 if (!printed_version++)
2856 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 2857
f351b2d6
SB		 2858 /*
2859 * Simple resource validation ..
2860 */
2861 if (unlikely(pdev->num_resources != 2)) {
2862 dev_err(&pdev->dev, "invalid number of resources\n");
2863 return -EINVAL;
2864 }
2865
2866 /*
2867 * Get the register base first
2868 */
2869 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2870 if (res == NULL)
2871 return -EINVAL;
2872
2873 /* allocate host */
2874 mv_platform_data = pdev->dev.platform_data;
2875 n_ports = mv_platform_data->n_ports;
2876
2877 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2878 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
2879
2880 if (!host || !hpriv)
2881 return -ENOMEM;
2882 host->private_data = hpriv;
2883 hpriv->n_ports = n_ports;
2884
2885 host->iomap = NULL;
f1cb0ea1
SB		 2886 hpriv->base = devm_ioremap(&pdev->dev, res->start,
2887 res->end - res->start + 1);
f351b2d6
SB		 2888 hpriv->base -= MV_SATAHC0_REG_BASE;
2889
15a32632
LB		 2890 /*
2891 * (Re-)program MBUS remapping windows if we are asked to.
2892 */
2893 if (mv_platform_data->dram != NULL)
2894 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
2895
fbf14e2f
BB		 2896 rc = mv_create_dma_pools(hpriv, &pdev->dev);
2897 if (rc)
2898 return rc;
2899
f351b2d6
SB		 2900 /* initialize adapter */
2901 rc = mv_init_host(host, chip_soc);
2902 if (rc)
2903 return rc;
2904
2905 dev_printk(KERN_INFO, &pdev->dev,
2906 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
2907 host->n_ports);
2908
2909 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
2910 IRQF_SHARED, &mv6_sht);
2911}
2912
2913/*
2914 *
2915 * mv_platform_remove - unplug a platform interface
2916 * @pdev: platform device
2917 *
2918 * A platform bus SATA device has been unplugged. Perform the needed
2919 * cleanup. Also called on module unload for any active devices.
2920 */
2921static int __devexit mv_platform_remove(struct platform_device *pdev)
2922{
2923 struct device *dev = &pdev->dev;
2924 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 2925
2926 ata_host_detach(host);
f351b2d6 2927 return 0;
20f733e7
BR		 2928}
2929
f351b2d6
SB		 2930static struct platform_driver mv_platform_driver = {
2931 .probe = mv_platform_probe,
2932 .remove = __devexit_p(mv_platform_remove),
2933 .driver = {
2934 .name = DRV_NAME,
2935 .owner = THIS_MODULE,
2936 },
2937};
2938
2939
7bb3c529 2940#ifdef CONFIG_PCI
f351b2d6
SB		 2941static int mv_pci_init_one(struct pci_dev *pdev,
2942 const struct pci_device_id *ent);
2943
7bb3c529
SB		 2944
2945static struct pci_driver mv_pci_driver = {
2946 .name = DRV_NAME,
2947 .id_table = mv_pci_tbl,
f351b2d6 2948 .probe = mv_pci_init_one,
7bb3c529
SB		 2949 .remove = ata_pci_remove_one,
2950};
2951
2952/*
2953 * module options
2954 */
2955static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
2956
2957
2958/* move to PCI layer or libata core? */
2959static int pci_go_64(struct pci_dev *pdev)
2960{
2961 int rc;
2962
2963 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2964 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2965 if (rc) {
2966 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2967 if (rc) {
2968 dev_printk(KERN_ERR, &pdev->dev,
2969 "64-bit DMA enable failed\n");
2970 return rc;
2971 }
2972 }
2973 } else {
2974 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2975 if (rc) {
2976 dev_printk(KERN_ERR, &pdev->dev,
2977 "32-bit DMA enable failed\n");
2978 return rc;
2979 }
2980 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2981 if (rc) {
2982 dev_printk(KERN_ERR, &pdev->dev,
2983 "32-bit consistent DMA enable failed\n");
2984 return rc;
2985 }
2986 }
2987
2988 return rc;
2989}
2990
05b308e1
BR		 2991/**
2992 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 2993 * @host: ATA host to print info about
05b308e1
BR		 2994 *
2995 * FIXME: complete this.
2996 *
2997 * LOCKING:
2998 * Inherited from caller.
2999 */
4447d351 3000static void mv_print_info(struct ata_host *host)
31961943 3001{
4447d351
TH		 3002 struct pci_dev *pdev = to_pci_dev(host->dev);
3003 struct mv_host_priv *hpriv = host->private_data;
44c10138 3004 u8 scc;
c1e4fe71 3005 const char *scc_s, *gen;
31961943
BR		 3006
3007 /* Use this to determine the HW stepping of the chip so we know
3008 * what errata to workaround
3009 */
31961943
BR		 3010 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3011 if (scc == 0)
3012 scc_s = "SCSI";
3013 else if (scc == 0x01)
3014 scc_s = "RAID";
3015 else
c1e4fe71
JG		 3016 scc_s = "?";
3017
3018 if (IS_GEN_I(hpriv))
3019 gen = "I";
3020 else if (IS_GEN_II(hpriv))
3021 gen = "II";
3022 else if (IS_GEN_IIE(hpriv))
3023 gen = "IIE";
3024 else
3025 gen = "?";
31961943 3026
a9524a76 3027 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3028 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3029 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3030 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3031}
3032
05b308e1 3033/**
f351b2d6 3034 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3035 * @pdev: PCI device found
3036 * @ent: PCI device ID entry for the matched host
3037 *
3038 * LOCKING:
3039 * Inherited from caller.
3040 */
f351b2d6
SB		 3041static int mv_pci_init_one(struct pci_dev *pdev,
3042 const struct pci_device_id *ent)
20f733e7 3043{
2dcb407e 3044 static int printed_version;
20f733e7 3045 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3046 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3047 struct ata_host *host;
3048 struct mv_host_priv *hpriv;
3049 int n_ports, rc;
20f733e7 3050
a9524a76
JG		 3051 if (!printed_version++)
3052 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3053
4447d351
TH		 3054 /* allocate host */
3055 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3056
3057 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3058 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3059 if (!host || !hpriv)
3060 return -ENOMEM;
3061 host->private_data = hpriv;
f351b2d6 3062 hpriv->n_ports = n_ports;
4447d351
TH		 3063
3064 /* acquire resources */
24dc5f33
TH		 3065 rc = pcim_enable_device(pdev);
3066 if (rc)
20f733e7 3067 return rc;
20f733e7 3068
0d5ff566
TH		 3069 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3070 if (rc == -EBUSY)
24dc5f33 3071 pcim_pin_device(pdev);
0d5ff566 3072 if (rc)
24dc5f33 3073 return rc;
4447d351 3074 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3075 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3076
d88184fb
JG		 3077 rc = pci_go_64(pdev);
3078 if (rc)
3079 return rc;
3080
da2fa9ba
ML		 3081 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3082 if (rc)
3083 return rc;
3084
20f733e7 3085 /* initialize adapter */
4447d351 3086 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3087 if (rc)
3088 return rc;
20f733e7 3089
31961943 3090 /* Enable interrupts */
6a59dcf8 3091 if (msi && pci_enable_msi(pdev))
31961943 3092 pci_intx(pdev, 1);
20f733e7 3093
31961943 3094 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3095 mv_print_info(host);
20f733e7 3096
4447d351 3097 pci_set_master(pdev);
ea8b4db9 3098 pci_try_set_mwi(pdev);
4447d351 3099 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3100 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3101}
7bb3c529 3102#endif
20f733e7 3103
f351b2d6
SB		 3104static int mv_platform_probe(struct platform_device *pdev);
3105static int __devexit mv_platform_remove(struct platform_device *pdev);
3106
20f733e7
BR		 3107static int __init mv_init(void)
3108{
7bb3c529
SB		 3109 int rc = -ENODEV;
3110#ifdef CONFIG_PCI
3111 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3112 if (rc < 0)
3113 return rc;
3114#endif
3115 rc = platform_driver_register(&mv_platform_driver);
3116
3117#ifdef CONFIG_PCI
3118 if (rc < 0)
3119 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3120#endif
3121 return rc;
20f733e7
BR		 3122}
3123
3124static void __exit mv_exit(void)
3125{
7bb3c529 3126#ifdef CONFIG_PCI
20f733e7 3127 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3128#endif
f351b2d6 3129 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3130}
3131
3132MODULE_AUTHOR("Brett Russ");
3133MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3134MODULE_LICENSE("GPL");
3135MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3136MODULE_VERSION(DRV_VERSION);
17c5aab5 3137MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3138
7bb3c529 3139#ifdef CONFIG_PCI
ddef9bb3
JG		 3140module_param(msi, int, 0444);
3141MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3142#endif
ddef9bb3 3143
20f733e7
BR		 3144module_init(mv_init);
3145module_exit(mv_exit);
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