]>
Commit | Line | Data |
---|---|---|
20f733e7 BR |
1 | /* |
2 | * sata_mv.c - Marvell SATA support | |
3 | * | |
40f21b11 | 4 | * Copyright 2008-2009: Marvell Corporation, all rights reserved. |
8b260248 | 5 | * Copyright 2005: EMC Corporation, all rights reserved. |
e2b1be56 | 6 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
20f733e7 | 7 | * |
40f21b11 ML |
8 | * Originally written by Brett Russ. |
9 | * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. | |
10 | * | |
20f733e7 BR |
11 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; version 2 of the License. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
27 | ||
4a05e209 | 28 | /* |
85afb934 ML |
29 | * sata_mv TODO list: |
30 | * | |
85afb934 ML |
31 | * --> Develop a low-power-consumption strategy, and implement it. |
32 | * | |
2b748a0a | 33 | * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. |
85afb934 ML |
34 | * |
35 | * --> [Experiment, Marvell value added] Is it possible to use target | |
36 | * mode to cross-connect two Linux boxes with Marvell cards? If so, | |
37 | * creating LibATA target mode support would be very interesting. | |
38 | * | |
39 | * Target mode, for those without docs, is the ability to directly | |
40 | * connect two SATA ports. | |
41 | */ | |
4a05e209 | 42 | |
65ad7fef ML |
43 | /* |
44 | * 80x1-B2 errata PCI#11: | |
45 | * | |
46 | * Users of the 6041/6081 Rev.B2 chips (current is C0) | |
47 | * should be careful to insert those cards only onto PCI-X bus #0, | |
48 | * and only in device slots 0..7, not higher. The chips may not | |
49 | * work correctly otherwise (note: this is a pretty rare condition). | |
50 | */ | |
51 | ||
20f733e7 BR |
52 | #include <linux/kernel.h> |
53 | #include <linux/module.h> | |
54 | #include <linux/pci.h> | |
55 | #include <linux/init.h> | |
56 | #include <linux/blkdev.h> | |
57 | #include <linux/delay.h> | |
58 | #include <linux/interrupt.h> | |
8d8b6004 | 59 | #include <linux/dmapool.h> |
20f733e7 | 60 | #include <linux/dma-mapping.h> |
a9524a76 | 61 | #include <linux/device.h> |
f351b2d6 SB |
62 | #include <linux/platform_device.h> |
63 | #include <linux/ata_platform.h> | |
15a32632 | 64 | #include <linux/mbus.h> |
c46938cc | 65 | #include <linux/bitops.h> |
20f733e7 | 66 | #include <scsi/scsi_host.h> |
193515d5 | 67 | #include <scsi/scsi_cmnd.h> |
6c08772e | 68 | #include <scsi/scsi_device.h> |
20f733e7 | 69 | #include <linux/libata.h> |
20f733e7 BR |
70 | |
71 | #define DRV_NAME "sata_mv" | |
2b748a0a | 72 | #define DRV_VERSION "1.27" |
20f733e7 | 73 | |
40f21b11 ML |
74 | /* |
75 | * module options | |
76 | */ | |
77 | ||
78 | static int msi; | |
79 | #ifdef CONFIG_PCI | |
80 | module_param(msi, int, S_IRUGO); | |
81 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); | |
82 | #endif | |
83 | ||
2b748a0a ML |
84 | static int irq_coalescing_io_count; |
85 | module_param(irq_coalescing_io_count, int, S_IRUGO); | |
86 | MODULE_PARM_DESC(irq_coalescing_io_count, | |
87 | "IRQ coalescing I/O count threshold (0..255)"); | |
88 | ||
89 | static int irq_coalescing_usecs; | |
90 | module_param(irq_coalescing_usecs, int, S_IRUGO); | |
91 | MODULE_PARM_DESC(irq_coalescing_usecs, | |
92 | "IRQ coalescing time threshold in usecs"); | |
93 | ||
20f733e7 BR |
94 | enum { |
95 | /* BAR's are enumerated in terms of pci_resource_start() terms */ | |
96 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ | |
97 | MV_IO_BAR = 2, /* offset 0x18: IO space */ | |
98 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ | |
99 | ||
100 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ | |
101 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ | |
102 | ||
2b748a0a ML |
103 | /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ |
104 | COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ | |
105 | MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ | |
106 | MAX_COAL_IO_COUNT = 255, /* completed I/O count */ | |
107 | ||
20f733e7 | 108 | MV_PCI_REG_BASE = 0, |
615ab953 | 109 | |
2b748a0a ML |
110 | /* |
111 | * Per-chip ("all ports") interrupt coalescing feature. | |
112 | * This is only for GEN_II / GEN_IIE hardware. | |
113 | * | |
114 | * Coalescing defers the interrupt until either the IO_THRESHOLD | |
115 | * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. | |
116 | */ | |
117 | MV_COAL_REG_BASE = 0x18000, | |
118 | MV_IRQ_COAL_CAUSE = (MV_COAL_REG_BASE + 0x08), | |
119 | ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ | |
120 | ||
121 | MV_IRQ_COAL_IO_THRESHOLD = (MV_COAL_REG_BASE + 0xcc), | |
122 | MV_IRQ_COAL_TIME_THRESHOLD = (MV_COAL_REG_BASE + 0xd0), | |
123 | ||
124 | /* | |
125 | * Registers for the (unused here) transaction coalescing feature: | |
126 | */ | |
127 | MV_TRAN_COAL_CAUSE_LO = (MV_COAL_REG_BASE + 0x88), | |
128 | MV_TRAN_COAL_CAUSE_HI = (MV_COAL_REG_BASE + 0x8c), | |
129 | ||
20f733e7 | 130 | MV_SATAHC0_REG_BASE = 0x20000, |
8e7decdb ML |
131 | MV_FLASH_CTL_OFS = 0x1046c, |
132 | MV_GPIO_PORT_CTL_OFS = 0x104f0, | |
133 | MV_RESET_CFG_OFS = 0x180d8, | |
20f733e7 BR |
134 | |
135 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
136 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
137 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ | |
138 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, | |
139 | ||
31961943 BR |
140 | MV_MAX_Q_DEPTH = 32, |
141 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, | |
142 | ||
143 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB | |
144 | * CRPB needs alignment on a 256B boundary. Size == 256B | |
31961943 BR |
145 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B |
146 | */ | |
147 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), | |
148 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), | |
da2fa9ba | 149 | MV_MAX_SG_CT = 256, |
31961943 | 150 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
31961943 | 151 | |
352fab70 | 152 | /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ |
20f733e7 | 153 | MV_PORT_HC_SHIFT = 2, |
352fab70 ML |
154 | MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ |
155 | /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ | |
156 | MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ | |
20f733e7 BR |
157 | |
158 | /* Host Flags */ | |
159 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ | |
7bb3c529 | 160 | |
c5d3e45a | 161 | MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
91b1a84c | 162 | ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING, |
ad3aef51 | 163 | |
91b1a84c | 164 | MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, |
20f733e7 | 165 | |
40f21b11 ML |
166 | MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | |
167 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, | |
91b1a84c ML |
168 | |
169 | MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, | |
ad3aef51 | 170 | |
31961943 BR |
171 | CRQB_FLAG_READ = (1 << 0), |
172 | CRQB_TAG_SHIFT = 1, | |
c5d3e45a | 173 | CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ |
e12bef50 | 174 | CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ |
c5d3e45a | 175 | CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ |
31961943 BR |
176 | CRQB_CMD_ADDR_SHIFT = 8, |
177 | CRQB_CMD_CS = (0x2 << 11), | |
178 | CRQB_CMD_LAST = (1 << 15), | |
179 | ||
180 | CRPB_FLAG_STATUS_SHIFT = 8, | |
c5d3e45a JG |
181 | CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ |
182 | CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ | |
31961943 BR |
183 | |
184 | EPRD_FLAG_END_OF_TBL = (1 << 31), | |
185 | ||
20f733e7 BR |
186 | /* PCI interface registers */ |
187 | ||
31961943 | 188 | PCI_COMMAND_OFS = 0xc00, |
65ad7fef | 189 | PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ |
8e7decdb | 190 | PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ |
31961943 | 191 | |
20f733e7 BR |
192 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
193 | STOP_PCI_MASTER = (1 << 2), | |
194 | PCI_MASTER_EMPTY = (1 << 3), | |
195 | GLOB_SFT_RST = (1 << 4), | |
196 | ||
8e7decdb ML |
197 | MV_PCI_MODE_OFS = 0xd00, |
198 | MV_PCI_MODE_MASK = 0x30, | |
199 | ||
522479fb JG |
200 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, |
201 | MV_PCI_DISC_TIMER = 0xd04, | |
202 | MV_PCI_MSI_TRIGGER = 0xc38, | |
203 | MV_PCI_SERR_MASK = 0xc28, | |
8e7decdb | 204 | MV_PCI_XBAR_TMOUT_OFS = 0x1d04, |
522479fb JG |
205 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, |
206 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, | |
207 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, | |
208 | MV_PCI_ERR_COMMAND = 0x1d50, | |
209 | ||
02a121da ML |
210 | PCI_IRQ_CAUSE_OFS = 0x1d58, |
211 | PCI_IRQ_MASK_OFS = 0x1d5c, | |
20f733e7 BR |
212 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
213 | ||
02a121da ML |
214 | PCIE_IRQ_CAUSE_OFS = 0x1900, |
215 | PCIE_IRQ_MASK_OFS = 0x1910, | |
646a4da5 | 216 | PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ |
02a121da | 217 | |
7368f919 ML |
218 | /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ |
219 | PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, | |
220 | PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64, | |
221 | SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020, | |
222 | SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024, | |
40f21b11 ML |
223 | ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ |
224 | DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ | |
20f733e7 BR |
225 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ |
226 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ | |
2b748a0a ML |
227 | DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ |
228 | DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ | |
20f733e7 | 229 | PCI_ERR = (1 << 18), |
40f21b11 ML |
230 | TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ |
231 | TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ | |
232 | PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ | |
233 | PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ | |
234 | ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ | |
20f733e7 BR |
235 | GPIO_INT = (1 << 22), |
236 | SELF_INT = (1 << 23), | |
237 | TWSI_INT = (1 << 24), | |
238 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ | |
fb621e2f | 239 | HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ |
e12bef50 | 240 | HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ |
20f733e7 BR |
241 | |
242 | /* SATAHC registers */ | |
243 | HC_CFG_OFS = 0, | |
244 | ||
245 | HC_IRQ_CAUSE_OFS = 0x14, | |
352fab70 ML |
246 | DMA_IRQ = (1 << 0), /* shift by port # */ |
247 | HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ | |
20f733e7 BR |
248 | DEV_IRQ = (1 << 8), /* shift by port # */ |
249 | ||
2b748a0a ML |
250 | /* |
251 | * Per-HC (Host-Controller) interrupt coalescing feature. | |
252 | * This is present on all chip generations. | |
253 | * | |
254 | * Coalescing defers the interrupt until either the IO_THRESHOLD | |
255 | * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. | |
256 | */ | |
257 | HC_IRQ_COAL_IO_THRESHOLD_OFS = 0x000c, | |
258 | HC_IRQ_COAL_TIME_THRESHOLD_OFS = 0x0010, | |
259 | ||
000b344f ML |
260 | SOC_LED_CTRL_OFS = 0x2c, |
261 | SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ | |
262 | SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ | |
263 | /* with dev activity LED */ | |
264 | ||
20f733e7 | 265 | /* Shadow block registers */ |
31961943 BR |
266 | SHD_BLK_OFS = 0x100, |
267 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ | |
20f733e7 BR |
268 | |
269 | /* SATA registers */ | |
270 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ | |
271 | SATA_ACTIVE_OFS = 0x350, | |
0c58912e | 272 | SATA_FIS_IRQ_CAUSE_OFS = 0x364, |
c443c500 | 273 | SATA_FIS_IRQ_AN = (1 << 9), /* async notification */ |
17c5aab5 | 274 | |
ba68460b | 275 | LTMODE_OFS = 0x30c, /* requires read-after-write */ |
17c5aab5 ML |
276 | LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ |
277 | ||
ba68460b ML |
278 | PHY_MODE2_OFS = 0x330, |
279 | PHY_MODE3_OFS = 0x310, | |
280 | PHY_MODE4_OFS = 0x314, /* requires read-after-write */ | |
ba069e37 ML |
281 | PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ |
282 | PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ | |
283 | PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ | |
284 | PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ | |
285 | ||
e12bef50 | 286 | SATA_IFCTL_OFS = 0x344, |
8e7decdb | 287 | SATA_TESTCTL_OFS = 0x348, |
e12bef50 ML |
288 | SATA_IFSTAT_OFS = 0x34c, |
289 | VENDOR_UNIQUE_FIS_OFS = 0x35c, | |
17c5aab5 | 290 | |
8e7decdb ML |
291 | FISCFG_OFS = 0x360, |
292 | FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ | |
293 | FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ | |
17c5aab5 | 294 | |
c9d39130 | 295 | MV5_PHY_MODE = 0x74, |
8e7decdb ML |
296 | MV5_LTMODE_OFS = 0x30, |
297 | MV5_PHY_CTL_OFS = 0x0C, | |
298 | SATA_INTERFACE_CFG_OFS = 0x050, | |
bca1c4eb JG |
299 | |
300 | MV_M2_PREAMP_MASK = 0x7e0, | |
20f733e7 BR |
301 | |
302 | /* Port registers */ | |
303 | EDMA_CFG_OFS = 0, | |
0c58912e ML |
304 | EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ |
305 | EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ | |
306 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ | |
307 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ | |
308 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ | |
e12bef50 ML |
309 | EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ |
310 | EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ | |
20f733e7 BR |
311 | |
312 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, | |
313 | EDMA_ERR_IRQ_MASK_OFS = 0xc, | |
6c1153e0 JG |
314 | EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ |
315 | EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ | |
316 | EDMA_ERR_DEV = (1 << 2), /* device error */ | |
317 | EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ | |
318 | EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ | |
319 | EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ | |
c5d3e45a JG |
320 | EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ |
321 | EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ | |
6c1153e0 | 322 | EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ |
c5d3e45a | 323 | EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ |
6c1153e0 JG |
324 | EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ |
325 | EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ | |
326 | EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ | |
327 | EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ | |
646a4da5 | 328 | |
6c1153e0 | 329 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ |
646a4da5 ML |
330 | EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ |
331 | EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ | |
332 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ | |
333 | EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ | |
334 | ||
6c1153e0 | 335 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ |
646a4da5 | 336 | |
6c1153e0 | 337 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ |
646a4da5 ML |
338 | EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ |
339 | EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ | |
340 | EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ | |
341 | EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ | |
342 | EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ | |
343 | ||
6c1153e0 | 344 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ |
646a4da5 | 345 | |
6c1153e0 | 346 | EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ |
c5d3e45a JG |
347 | EDMA_ERR_OVERRUN_5 = (1 << 5), |
348 | EDMA_ERR_UNDERRUN_5 = (1 << 6), | |
646a4da5 ML |
349 | |
350 | EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | | |
351 | EDMA_ERR_LNK_CTRL_RX_1 | | |
352 | EDMA_ERR_LNK_CTRL_RX_3 | | |
85afb934 | 353 | EDMA_ERR_LNK_CTRL_TX, |
646a4da5 | 354 | |
bdd4ddde JG |
355 | EDMA_EH_FREEZE = EDMA_ERR_D_PAR | |
356 | EDMA_ERR_PRD_PAR | | |
357 | EDMA_ERR_DEV_DCON | | |
358 | EDMA_ERR_DEV_CON | | |
359 | EDMA_ERR_SERR | | |
360 | EDMA_ERR_SELF_DIS | | |
6c1153e0 | 361 | EDMA_ERR_CRQB_PAR | |
bdd4ddde JG |
362 | EDMA_ERR_CRPB_PAR | |
363 | EDMA_ERR_INTRL_PAR | | |
364 | EDMA_ERR_IORDY | | |
365 | EDMA_ERR_LNK_CTRL_RX_2 | | |
366 | EDMA_ERR_LNK_DATA_RX | | |
367 | EDMA_ERR_LNK_DATA_TX | | |
368 | EDMA_ERR_TRANS_PROTO, | |
e12bef50 | 369 | |
bdd4ddde JG |
370 | EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | |
371 | EDMA_ERR_PRD_PAR | | |
372 | EDMA_ERR_DEV_DCON | | |
373 | EDMA_ERR_DEV_CON | | |
374 | EDMA_ERR_OVERRUN_5 | | |
375 | EDMA_ERR_UNDERRUN_5 | | |
376 | EDMA_ERR_SELF_DIS_5 | | |
6c1153e0 | 377 | EDMA_ERR_CRQB_PAR | |
bdd4ddde JG |
378 | EDMA_ERR_CRPB_PAR | |
379 | EDMA_ERR_INTRL_PAR | | |
380 | EDMA_ERR_IORDY, | |
20f733e7 | 381 | |
31961943 BR |
382 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
383 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ | |
31961943 BR |
384 | |
385 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, | |
386 | EDMA_REQ_Q_PTR_SHIFT = 5, | |
387 | ||
388 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, | |
389 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, | |
390 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ | |
31961943 BR |
391 | EDMA_RSP_Q_PTR_SHIFT = 3, |
392 | ||
0ea9e179 JG |
393 | EDMA_CMD_OFS = 0x28, /* EDMA command register */ |
394 | EDMA_EN = (1 << 0), /* enable EDMA */ | |
395 | EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ | |
8e7decdb ML |
396 | EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ |
397 | ||
398 | EDMA_STATUS_OFS = 0x30, /* EDMA engine status */ | |
399 | EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ | |
400 | EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ | |
20f733e7 | 401 | |
8e7decdb ML |
402 | EDMA_IORDY_TMOUT_OFS = 0x34, |
403 | EDMA_ARB_CFG_OFS = 0x38, | |
404 | ||
405 | EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */ | |
c01e8a23 | 406 | EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */ |
da14265e ML |
407 | |
408 | BMDMA_CMD_OFS = 0x224, /* bmdma command register */ | |
409 | BMDMA_STATUS_OFS = 0x228, /* bmdma status register */ | |
410 | BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */ | |
411 | BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */ | |
412 | ||
31961943 BR |
413 | /* Host private flags (hp_flags) */ |
414 | MV_HP_FLAG_MSI = (1 << 0), | |
47c2b677 JG |
415 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
416 | MV_HP_ERRATA_50XXB2 = (1 << 2), | |
417 | MV_HP_ERRATA_60X1B2 = (1 << 3), | |
418 | MV_HP_ERRATA_60X1C0 = (1 << 4), | |
0ea9e179 JG |
419 | MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ |
420 | MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ | |
421 | MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ | |
02a121da | 422 | MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ |
616d4a98 | 423 | MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ |
1f398472 | 424 | MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ |
000b344f | 425 | MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ |
20f733e7 | 426 | |
31961943 | 427 | /* Port private flags (pp_flags) */ |
0ea9e179 | 428 | MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ |
72109168 | 429 | MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ |
00f42eab | 430 | MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ |
29d187bb | 431 | MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ |
d16ab3f6 | 432 | MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ |
20f733e7 BR |
433 | }; |
434 | ||
ee9ccdf7 JG |
435 | #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) |
436 | #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) | |
e4e7b892 | 437 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
8e7decdb | 438 | #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) |
1f398472 | 439 | #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) |
bca1c4eb | 440 | |
15a32632 LB |
441 | #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) |
442 | #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) | |
443 | ||
095fec88 | 444 | enum { |
baf14aa1 JG |
445 | /* DMA boundary 0xffff is required by the s/g splitting |
446 | * we need on /length/ in mv_fill-sg(). | |
447 | */ | |
448 | MV_DMA_BOUNDARY = 0xffffU, | |
095fec88 | 449 | |
0ea9e179 JG |
450 | /* mask of register bits containing lower 32 bits |
451 | * of EDMA request queue DMA address | |
452 | */ | |
095fec88 JG |
453 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, |
454 | ||
0ea9e179 | 455 | /* ditto, for response queue */ |
095fec88 JG |
456 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, |
457 | }; | |
458 | ||
522479fb JG |
459 | enum chip_type { |
460 | chip_504x, | |
461 | chip_508x, | |
462 | chip_5080, | |
463 | chip_604x, | |
464 | chip_608x, | |
e4e7b892 JG |
465 | chip_6042, |
466 | chip_7042, | |
f351b2d6 | 467 | chip_soc, |
522479fb JG |
468 | }; |
469 | ||
31961943 BR |
470 | /* Command ReQuest Block: 32B */ |
471 | struct mv_crqb { | |
e1469874 ML |
472 | __le32 sg_addr; |
473 | __le32 sg_addr_hi; | |
474 | __le16 ctrl_flags; | |
475 | __le16 ata_cmd[11]; | |
31961943 | 476 | }; |
20f733e7 | 477 | |
e4e7b892 | 478 | struct mv_crqb_iie { |
e1469874 ML |
479 | __le32 addr; |
480 | __le32 addr_hi; | |
481 | __le32 flags; | |
482 | __le32 len; | |
483 | __le32 ata_cmd[4]; | |
e4e7b892 JG |
484 | }; |
485 | ||
31961943 BR |
486 | /* Command ResPonse Block: 8B */ |
487 | struct mv_crpb { | |
e1469874 ML |
488 | __le16 id; |
489 | __le16 flags; | |
490 | __le32 tmstmp; | |
20f733e7 BR |
491 | }; |
492 | ||
31961943 BR |
493 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
494 | struct mv_sg { | |
e1469874 ML |
495 | __le32 addr; |
496 | __le32 flags_size; | |
497 | __le32 addr_hi; | |
498 | __le32 reserved; | |
31961943 | 499 | }; |
20f733e7 | 500 | |
08da1759 ML |
501 | /* |
502 | * We keep a local cache of a few frequently accessed port | |
503 | * registers here, to avoid having to read them (very slow) | |
504 | * when switching between EDMA and non-EDMA modes. | |
505 | */ | |
506 | struct mv_cached_regs { | |
507 | u32 fiscfg; | |
508 | u32 ltmode; | |
509 | u32 haltcond; | |
c01e8a23 | 510 | u32 unknown_rsvd; |
08da1759 ML |
511 | }; |
512 | ||
31961943 BR |
513 | struct mv_port_priv { |
514 | struct mv_crqb *crqb; | |
515 | dma_addr_t crqb_dma; | |
516 | struct mv_crpb *crpb; | |
517 | dma_addr_t crpb_dma; | |
eb73d558 ML |
518 | struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; |
519 | dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; | |
bdd4ddde JG |
520 | |
521 | unsigned int req_idx; | |
522 | unsigned int resp_idx; | |
523 | ||
31961943 | 524 | u32 pp_flags; |
08da1759 | 525 | struct mv_cached_regs cached; |
29d187bb | 526 | unsigned int delayed_eh_pmp_map; |
31961943 BR |
527 | }; |
528 | ||
bca1c4eb JG |
529 | struct mv_port_signal { |
530 | u32 amps; | |
531 | u32 pre; | |
532 | }; | |
533 | ||
02a121da ML |
534 | struct mv_host_priv { |
535 | u32 hp_flags; | |
96e2c487 | 536 | u32 main_irq_mask; |
02a121da ML |
537 | struct mv_port_signal signal[8]; |
538 | const struct mv_hw_ops *ops; | |
f351b2d6 SB |
539 | int n_ports; |
540 | void __iomem *base; | |
7368f919 ML |
541 | void __iomem *main_irq_cause_addr; |
542 | void __iomem *main_irq_mask_addr; | |
02a121da ML |
543 | u32 irq_cause_ofs; |
544 | u32 irq_mask_ofs; | |
545 | u32 unmask_all_irqs; | |
da2fa9ba ML |
546 | /* |
547 | * These consistent DMA memory pools give us guaranteed | |
548 | * alignment for hardware-accessed data structures, | |
549 | * and less memory waste in accomplishing the alignment. | |
550 | */ | |
551 | struct dma_pool *crqb_pool; | |
552 | struct dma_pool *crpb_pool; | |
553 | struct dma_pool *sg_tbl_pool; | |
02a121da ML |
554 | }; |
555 | ||
47c2b677 | 556 | struct mv_hw_ops { |
2a47ce06 JG |
557 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
558 | unsigned int port); | |
47c2b677 JG |
559 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
560 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, | |
561 | void __iomem *mmio); | |
c9d39130 JG |
562 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
563 | unsigned int n_hc); | |
522479fb | 564 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
7bb3c529 | 565 | void (*reset_bus)(struct ata_host *host, void __iomem *mmio); |
47c2b677 JG |
566 | }; |
567 | ||
82ef04fb TH |
568 | static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); |
569 | static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); | |
570 | static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); | |
571 | static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); | |
31961943 BR |
572 | static int mv_port_start(struct ata_port *ap); |
573 | static void mv_port_stop(struct ata_port *ap); | |
3e4a1391 | 574 | static int mv_qc_defer(struct ata_queued_cmd *qc); |
31961943 | 575 | static void mv_qc_prep(struct ata_queued_cmd *qc); |
e4e7b892 | 576 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
9a3d9eb0 | 577 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
a1efdaba TH |
578 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
579 | unsigned long deadline); | |
bdd4ddde JG |
580 | static void mv_eh_freeze(struct ata_port *ap); |
581 | static void mv_eh_thaw(struct ata_port *ap); | |
f273827e | 582 | static void mv6_dev_config(struct ata_device *dev); |
20f733e7 | 583 | |
2a47ce06 JG |
584 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
585 | unsigned int port); | |
47c2b677 JG |
586 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
587 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, | |
588 | void __iomem *mmio); | |
c9d39130 JG |
589 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
590 | unsigned int n_hc); | |
522479fb | 591 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
7bb3c529 | 592 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); |
47c2b677 | 593 | |
2a47ce06 JG |
594 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
595 | unsigned int port); | |
47c2b677 JG |
596 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
597 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, | |
598 | void __iomem *mmio); | |
c9d39130 JG |
599 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
600 | unsigned int n_hc); | |
522479fb | 601 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
f351b2d6 SB |
602 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, |
603 | void __iomem *mmio); | |
604 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, | |
605 | void __iomem *mmio); | |
606 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, | |
607 | void __iomem *mmio, unsigned int n_hc); | |
608 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, | |
609 | void __iomem *mmio); | |
610 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); | |
7bb3c529 | 611 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); |
e12bef50 | 612 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
c9d39130 | 613 | unsigned int port_no); |
e12bef50 | 614 | static int mv_stop_edma(struct ata_port *ap); |
b562468c | 615 | static int mv_stop_edma_engine(void __iomem *port_mmio); |
00b81235 | 616 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); |
47c2b677 | 617 | |
e49856d8 ML |
618 | static void mv_pmp_select(struct ata_port *ap, int pmp); |
619 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, | |
620 | unsigned long deadline); | |
621 | static int mv_softreset(struct ata_link *link, unsigned int *class, | |
622 | unsigned long deadline); | |
29d187bb | 623 | static void mv_pmp_error_handler(struct ata_port *ap); |
4c299ca3 ML |
624 | static void mv_process_crpb_entries(struct ata_port *ap, |
625 | struct mv_port_priv *pp); | |
47c2b677 | 626 | |
da14265e ML |
627 | static void mv_sff_irq_clear(struct ata_port *ap); |
628 | static int mv_check_atapi_dma(struct ata_queued_cmd *qc); | |
629 | static void mv_bmdma_setup(struct ata_queued_cmd *qc); | |
630 | static void mv_bmdma_start(struct ata_queued_cmd *qc); | |
631 | static void mv_bmdma_stop(struct ata_queued_cmd *qc); | |
632 | static u8 mv_bmdma_status(struct ata_port *ap); | |
d16ab3f6 | 633 | static u8 mv_sff_check_status(struct ata_port *ap); |
da14265e | 634 | |
eb73d558 ML |
635 | /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below |
636 | * because we have to allow room for worst case splitting of | |
637 | * PRDs for 64K boundaries in mv_fill_sg(). | |
638 | */ | |
c5d3e45a | 639 | static struct scsi_host_template mv5_sht = { |
68d1d07b | 640 | ATA_BASE_SHT(DRV_NAME), |
baf14aa1 | 641 | .sg_tablesize = MV_MAX_SG_CT / 2, |
c5d3e45a | 642 | .dma_boundary = MV_DMA_BOUNDARY, |
c5d3e45a JG |
643 | }; |
644 | ||
645 | static struct scsi_host_template mv6_sht = { | |
68d1d07b | 646 | ATA_NCQ_SHT(DRV_NAME), |
138bfdd0 | 647 | .can_queue = MV_MAX_Q_DEPTH - 1, |
baf14aa1 | 648 | .sg_tablesize = MV_MAX_SG_CT / 2, |
20f733e7 | 649 | .dma_boundary = MV_DMA_BOUNDARY, |
20f733e7 BR |
650 | }; |
651 | ||
029cfd6b TH |
652 | static struct ata_port_operations mv5_ops = { |
653 | .inherits = &ata_sff_port_ops, | |
c9d39130 | 654 | |
c96f1732 AC |
655 | .lost_interrupt = ATA_OP_NULL, |
656 | ||
3e4a1391 | 657 | .qc_defer = mv_qc_defer, |
c9d39130 JG |
658 | .qc_prep = mv_qc_prep, |
659 | .qc_issue = mv_qc_issue, | |
c9d39130 | 660 | |
bdd4ddde JG |
661 | .freeze = mv_eh_freeze, |
662 | .thaw = mv_eh_thaw, | |
a1efdaba | 663 | .hardreset = mv_hardreset, |
a1efdaba | 664 | .error_handler = ata_std_error_handler, /* avoid SFF EH */ |
029cfd6b | 665 | .post_internal_cmd = ATA_OP_NULL, |
bdd4ddde | 666 | |
c9d39130 JG |
667 | .scr_read = mv5_scr_read, |
668 | .scr_write = mv5_scr_write, | |
669 | ||
670 | .port_start = mv_port_start, | |
671 | .port_stop = mv_port_stop, | |
c9d39130 JG |
672 | }; |
673 | ||
029cfd6b TH |
674 | static struct ata_port_operations mv6_ops = { |
675 | .inherits = &mv5_ops, | |
f273827e | 676 | .dev_config = mv6_dev_config, |
20f733e7 BR |
677 | .scr_read = mv_scr_read, |
678 | .scr_write = mv_scr_write, | |
679 | ||
e49856d8 ML |
680 | .pmp_hardreset = mv_pmp_hardreset, |
681 | .pmp_softreset = mv_softreset, | |
682 | .softreset = mv_softreset, | |
29d187bb | 683 | .error_handler = mv_pmp_error_handler, |
da14265e | 684 | |
40f21b11 | 685 | .sff_check_status = mv_sff_check_status, |
da14265e ML |
686 | .sff_irq_clear = mv_sff_irq_clear, |
687 | .check_atapi_dma = mv_check_atapi_dma, | |
688 | .bmdma_setup = mv_bmdma_setup, | |
689 | .bmdma_start = mv_bmdma_start, | |
690 | .bmdma_stop = mv_bmdma_stop, | |
691 | .bmdma_status = mv_bmdma_status, | |
20f733e7 BR |
692 | }; |
693 | ||
029cfd6b TH |
694 | static struct ata_port_operations mv_iie_ops = { |
695 | .inherits = &mv6_ops, | |
696 | .dev_config = ATA_OP_NULL, | |
e4e7b892 | 697 | .qc_prep = mv_qc_prep_iie, |
e4e7b892 JG |
698 | }; |
699 | ||
98ac62de | 700 | static const struct ata_port_info mv_port_info[] = { |
20f733e7 | 701 | { /* chip_504x */ |
91b1a84c | 702 | .flags = MV_GEN_I_FLAGS, |
c361acbc | 703 | .pio_mask = ATA_PIO4, |
bf6263a8 | 704 | .udma_mask = ATA_UDMA6, |
c9d39130 | 705 | .port_ops = &mv5_ops, |
20f733e7 BR |
706 | }, |
707 | { /* chip_508x */ | |
91b1a84c | 708 | .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 709 | .pio_mask = ATA_PIO4, |
bf6263a8 | 710 | .udma_mask = ATA_UDMA6, |
c9d39130 | 711 | .port_ops = &mv5_ops, |
20f733e7 | 712 | }, |
47c2b677 | 713 | { /* chip_5080 */ |
91b1a84c | 714 | .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 715 | .pio_mask = ATA_PIO4, |
bf6263a8 | 716 | .udma_mask = ATA_UDMA6, |
c9d39130 | 717 | .port_ops = &mv5_ops, |
47c2b677 | 718 | }, |
20f733e7 | 719 | { /* chip_604x */ |
91b1a84c | 720 | .flags = MV_GEN_II_FLAGS, |
c361acbc | 721 | .pio_mask = ATA_PIO4, |
bf6263a8 | 722 | .udma_mask = ATA_UDMA6, |
c9d39130 | 723 | .port_ops = &mv6_ops, |
20f733e7 BR |
724 | }, |
725 | { /* chip_608x */ | |
91b1a84c | 726 | .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 727 | .pio_mask = ATA_PIO4, |
bf6263a8 | 728 | .udma_mask = ATA_UDMA6, |
c9d39130 | 729 | .port_ops = &mv6_ops, |
20f733e7 | 730 | }, |
e4e7b892 | 731 | { /* chip_6042 */ |
91b1a84c | 732 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 733 | .pio_mask = ATA_PIO4, |
bf6263a8 | 734 | .udma_mask = ATA_UDMA6, |
e4e7b892 JG |
735 | .port_ops = &mv_iie_ops, |
736 | }, | |
737 | { /* chip_7042 */ | |
91b1a84c | 738 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 739 | .pio_mask = ATA_PIO4, |
bf6263a8 | 740 | .udma_mask = ATA_UDMA6, |
e4e7b892 JG |
741 | .port_ops = &mv_iie_ops, |
742 | }, | |
f351b2d6 | 743 | { /* chip_soc */ |
91b1a84c | 744 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 745 | .pio_mask = ATA_PIO4, |
17c5aab5 ML |
746 | .udma_mask = ATA_UDMA6, |
747 | .port_ops = &mv_iie_ops, | |
f351b2d6 | 748 | }, |
20f733e7 BR |
749 | }; |
750 | ||
3b7d697d | 751 | static const struct pci_device_id mv_pci_tbl[] = { |
2d2744fc JG |
752 | { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, |
753 | { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, | |
754 | { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, | |
755 | { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, | |
46c5784c ML |
756 | /* RocketRAID 1720/174x have different identifiers */ |
757 | { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, | |
4462254a ML |
758 | { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, |
759 | { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, | |
2d2744fc JG |
760 | |
761 | { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, | |
762 | { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, | |
763 | { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, | |
764 | { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, | |
765 | { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, | |
766 | ||
767 | { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, | |
768 | ||
d9f9c6bc FA |
769 | /* Adaptec 1430SA */ |
770 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, | |
771 | ||
02a121da | 772 | /* Marvell 7042 support */ |
6a3d586d MT |
773 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
774 | ||
02a121da ML |
775 | /* Highpoint RocketRAID PCIe series */ |
776 | { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, | |
777 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, | |
778 | ||
2d2744fc | 779 | { } /* terminate list */ |
20f733e7 BR |
780 | }; |
781 | ||
47c2b677 JG |
782 | static const struct mv_hw_ops mv5xxx_ops = { |
783 | .phy_errata = mv5_phy_errata, | |
784 | .enable_leds = mv5_enable_leds, | |
785 | .read_preamp = mv5_read_preamp, | |
786 | .reset_hc = mv5_reset_hc, | |
522479fb JG |
787 | .reset_flash = mv5_reset_flash, |
788 | .reset_bus = mv5_reset_bus, | |
47c2b677 JG |
789 | }; |
790 | ||
791 | static const struct mv_hw_ops mv6xxx_ops = { | |
792 | .phy_errata = mv6_phy_errata, | |
793 | .enable_leds = mv6_enable_leds, | |
794 | .read_preamp = mv6_read_preamp, | |
795 | .reset_hc = mv6_reset_hc, | |
522479fb JG |
796 | .reset_flash = mv6_reset_flash, |
797 | .reset_bus = mv_reset_pci_bus, | |
47c2b677 JG |
798 | }; |
799 | ||
f351b2d6 SB |
800 | static const struct mv_hw_ops mv_soc_ops = { |
801 | .phy_errata = mv6_phy_errata, | |
802 | .enable_leds = mv_soc_enable_leds, | |
803 | .read_preamp = mv_soc_read_preamp, | |
804 | .reset_hc = mv_soc_reset_hc, | |
805 | .reset_flash = mv_soc_reset_flash, | |
806 | .reset_bus = mv_soc_reset_bus, | |
807 | }; | |
808 | ||
20f733e7 BR |
809 | /* |
810 | * Functions | |
811 | */ | |
812 | ||
813 | static inline void writelfl(unsigned long data, void __iomem *addr) | |
814 | { | |
815 | writel(data, addr); | |
816 | (void) readl(addr); /* flush to avoid PCI posted write */ | |
817 | } | |
818 | ||
c9d39130 JG |
819 | static inline unsigned int mv_hc_from_port(unsigned int port) |
820 | { | |
821 | return port >> MV_PORT_HC_SHIFT; | |
822 | } | |
823 | ||
824 | static inline unsigned int mv_hardport_from_port(unsigned int port) | |
825 | { | |
826 | return port & MV_PORT_MASK; | |
827 | } | |
828 | ||
1cfd19ae ML |
829 | /* |
830 | * Consolidate some rather tricky bit shift calculations. | |
831 | * This is hot-path stuff, so not a function. | |
832 | * Simple code, with two return values, so macro rather than inline. | |
833 | * | |
834 | * port is the sole input, in range 0..7. | |
7368f919 ML |
835 | * shift is one output, for use with main_irq_cause / main_irq_mask registers. |
836 | * hardport is the other output, in range 0..3. | |
1cfd19ae ML |
837 | * |
838 | * Note that port and hardport may be the same variable in some cases. | |
839 | */ | |
840 | #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ | |
841 | { \ | |
842 | shift = mv_hc_from_port(port) * HC_SHIFT; \ | |
843 | hardport = mv_hardport_from_port(port); \ | |
844 | shift += hardport * 2; \ | |
845 | } | |
846 | ||
352fab70 ML |
847 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
848 | { | |
849 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); | |
850 | } | |
851 | ||
c9d39130 JG |
852 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, |
853 | unsigned int port) | |
854 | { | |
855 | return mv_hc_base(base, mv_hc_from_port(port)); | |
856 | } | |
857 | ||
20f733e7 BR |
858 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
859 | { | |
c9d39130 | 860 | return mv_hc_base_from_port(base, port) + |
8b260248 | 861 | MV_SATAHC_ARBTR_REG_SZ + |
c9d39130 | 862 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
20f733e7 BR |
863 | } |
864 | ||
e12bef50 ML |
865 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
866 | { | |
867 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); | |
868 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; | |
869 | ||
870 | return hc_mmio + ofs; | |
871 | } | |
872 | ||
f351b2d6 SB |
873 | static inline void __iomem *mv_host_base(struct ata_host *host) |
874 | { | |
875 | struct mv_host_priv *hpriv = host->private_data; | |
876 | return hpriv->base; | |
877 | } | |
878 | ||
20f733e7 BR |
879 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
880 | { | |
f351b2d6 | 881 | return mv_port_base(mv_host_base(ap->host), ap->port_no); |
20f733e7 BR |
882 | } |
883 | ||
cca3974e | 884 | static inline int mv_get_hc_count(unsigned long port_flags) |
31961943 | 885 | { |
cca3974e | 886 | return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
31961943 BR |
887 | } |
888 | ||
08da1759 ML |
889 | /** |
890 | * mv_save_cached_regs - (re-)initialize cached port registers | |
891 | * @ap: the port whose registers we are caching | |
892 | * | |
893 | * Initialize the local cache of port registers, | |
894 | * so that reading them over and over again can | |
895 | * be avoided on the hotter paths of this driver. | |
896 | * This saves a few microseconds each time we switch | |
897 | * to/from EDMA mode to perform (eg.) a drive cache flush. | |
898 | */ | |
899 | static void mv_save_cached_regs(struct ata_port *ap) | |
900 | { | |
901 | void __iomem *port_mmio = mv_ap_base(ap); | |
902 | struct mv_port_priv *pp = ap->private_data; | |
903 | ||
904 | pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS); | |
905 | pp->cached.ltmode = readl(port_mmio + LTMODE_OFS); | |
906 | pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS); | |
c01e8a23 | 907 | pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS); |
08da1759 ML |
908 | } |
909 | ||
910 | /** | |
911 | * mv_write_cached_reg - write to a cached port register | |
912 | * @addr: hardware address of the register | |
913 | * @old: pointer to cached value of the register | |
914 | * @new: new value for the register | |
915 | * | |
916 | * Write a new value to a cached register, | |
917 | * but only if the value is different from before. | |
918 | */ | |
919 | static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) | |
920 | { | |
921 | if (new != *old) { | |
12f3b6d7 | 922 | unsigned long laddr; |
08da1759 | 923 | *old = new; |
12f3b6d7 ML |
924 | /* |
925 | * Workaround for 88SX60x1-B2 FEr SATA#13: | |
926 | * Read-after-write is needed to prevent generating 64-bit | |
927 | * write cycles on the PCI bus for SATA interface registers | |
928 | * at offsets ending in 0x4 or 0xc. | |
929 | * | |
930 | * Looks like a lot of fuss, but it avoids an unnecessary | |
931 | * +1 usec read-after-write delay for unaffected registers. | |
932 | */ | |
933 | laddr = (long)addr & 0xffff; | |
934 | if (laddr >= 0x300 && laddr <= 0x33c) { | |
935 | laddr &= 0x000f; | |
936 | if (laddr == 0x4 || laddr == 0xc) { | |
937 | writelfl(new, addr); /* read after write */ | |
938 | return; | |
939 | } | |
940 | } | |
941 | writel(new, addr); /* unaffected by the errata */ | |
08da1759 ML |
942 | } |
943 | } | |
944 | ||
c5d3e45a JG |
945 | static void mv_set_edma_ptrs(void __iomem *port_mmio, |
946 | struct mv_host_priv *hpriv, | |
947 | struct mv_port_priv *pp) | |
948 | { | |
bdd4ddde JG |
949 | u32 index; |
950 | ||
c5d3e45a JG |
951 | /* |
952 | * initialize request queue | |
953 | */ | |
fcfb1f77 ML |
954 | pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
955 | index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; | |
bdd4ddde | 956 | |
c5d3e45a JG |
957 | WARN_ON(pp->crqb_dma & 0x3ff); |
958 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); | |
bdd4ddde | 959 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, |
c5d3e45a | 960 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
5cf73bfb | 961 | writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); |
c5d3e45a JG |
962 | |
963 | /* | |
964 | * initialize response queue | |
965 | */ | |
fcfb1f77 ML |
966 | pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
967 | index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; | |
bdd4ddde | 968 | |
c5d3e45a JG |
969 | WARN_ON(pp->crpb_dma & 0xff); |
970 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); | |
5cf73bfb | 971 | writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); |
bdd4ddde | 972 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, |
c5d3e45a | 973 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
c5d3e45a JG |
974 | } |
975 | ||
2b748a0a ML |
976 | static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) |
977 | { | |
978 | /* | |
979 | * When writing to the main_irq_mask in hardware, | |
980 | * we must ensure exclusivity between the interrupt coalescing bits | |
981 | * and the corresponding individual port DONE_IRQ bits. | |
982 | * | |
983 | * Note that this register is really an "IRQ enable" register, | |
984 | * not an "IRQ mask" register as Marvell's naming might suggest. | |
985 | */ | |
986 | if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) | |
987 | mask &= ~DONE_IRQ_0_3; | |
988 | if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) | |
989 | mask &= ~DONE_IRQ_4_7; | |
990 | writelfl(mask, hpriv->main_irq_mask_addr); | |
991 | } | |
992 | ||
c4de573b ML |
993 | static void mv_set_main_irq_mask(struct ata_host *host, |
994 | u32 disable_bits, u32 enable_bits) | |
995 | { | |
996 | struct mv_host_priv *hpriv = host->private_data; | |
997 | u32 old_mask, new_mask; | |
998 | ||
96e2c487 | 999 | old_mask = hpriv->main_irq_mask; |
c4de573b | 1000 | new_mask = (old_mask & ~disable_bits) | enable_bits; |
96e2c487 ML |
1001 | if (new_mask != old_mask) { |
1002 | hpriv->main_irq_mask = new_mask; | |
2b748a0a | 1003 | mv_write_main_irq_mask(new_mask, hpriv); |
96e2c487 | 1004 | } |
c4de573b ML |
1005 | } |
1006 | ||
1007 | static void mv_enable_port_irqs(struct ata_port *ap, | |
1008 | unsigned int port_bits) | |
1009 | { | |
1010 | unsigned int shift, hardport, port = ap->port_no; | |
1011 | u32 disable_bits, enable_bits; | |
1012 | ||
1013 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); | |
1014 | ||
1015 | disable_bits = (DONE_IRQ | ERR_IRQ) << shift; | |
1016 | enable_bits = port_bits << shift; | |
1017 | mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); | |
1018 | } | |
1019 | ||
00b81235 ML |
1020 | static void mv_clear_and_enable_port_irqs(struct ata_port *ap, |
1021 | void __iomem *port_mmio, | |
1022 | unsigned int port_irqs) | |
1023 | { | |
1024 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1025 | int hardport = mv_hardport_from_port(ap->port_no); | |
1026 | void __iomem *hc_mmio = mv_hc_base_from_port( | |
1027 | mv_host_base(ap->host), ap->port_no); | |
1028 | u32 hc_irq_cause; | |
1029 | ||
1030 | /* clear EDMA event indicators, if any */ | |
1031 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1032 | ||
1033 | /* clear pending irq events */ | |
1034 | hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); | |
1035 | writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); | |
1036 | ||
1037 | /* clear FIS IRQ Cause */ | |
1038 | if (IS_GEN_IIE(hpriv)) | |
1039 | writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); | |
1040 | ||
1041 | mv_enable_port_irqs(ap, port_irqs); | |
1042 | } | |
1043 | ||
2b748a0a ML |
1044 | static void mv_set_irq_coalescing(struct ata_host *host, |
1045 | unsigned int count, unsigned int usecs) | |
1046 | { | |
1047 | struct mv_host_priv *hpriv = host->private_data; | |
1048 | void __iomem *mmio = hpriv->base, *hc_mmio; | |
1049 | u32 coal_enable = 0; | |
1050 | unsigned long flags; | |
6abf4678 | 1051 | unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; |
2b748a0a ML |
1052 | const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
1053 | ALL_PORTS_COAL_DONE; | |
1054 | ||
1055 | /* Disable IRQ coalescing if either threshold is zero */ | |
1056 | if (!usecs || !count) { | |
1057 | clks = count = 0; | |
1058 | } else { | |
1059 | /* Respect maximum limits of the hardware */ | |
1060 | clks = usecs * COAL_CLOCKS_PER_USEC; | |
1061 | if (clks > MAX_COAL_TIME_THRESHOLD) | |
1062 | clks = MAX_COAL_TIME_THRESHOLD; | |
1063 | if (count > MAX_COAL_IO_COUNT) | |
1064 | count = MAX_COAL_IO_COUNT; | |
1065 | } | |
1066 | ||
1067 | spin_lock_irqsave(&host->lock, flags); | |
6abf4678 | 1068 | mv_set_main_irq_mask(host, coal_disable, 0); |
2b748a0a | 1069 | |
6abf4678 | 1070 | if (is_dual_hc && !IS_GEN_I(hpriv)) { |
2b748a0a | 1071 | /* |
6abf4678 ML |
1072 | * GEN_II/GEN_IIE with dual host controllers: |
1073 | * one set of global thresholds for the entire chip. | |
2b748a0a ML |
1074 | */ |
1075 | writel(clks, mmio + MV_IRQ_COAL_TIME_THRESHOLD); | |
1076 | writel(count, mmio + MV_IRQ_COAL_IO_THRESHOLD); | |
1077 | /* clear leftover coal IRQ bit */ | |
6abf4678 ML |
1078 | writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE); |
1079 | if (count) | |
1080 | coal_enable = ALL_PORTS_COAL_DONE; | |
1081 | clks = count = 0; /* force clearing of regular regs below */ | |
2b748a0a | 1082 | } |
6abf4678 | 1083 | |
2b748a0a ML |
1084 | /* |
1085 | * All chips: independent thresholds for each HC on the chip. | |
1086 | */ | |
1087 | hc_mmio = mv_hc_base_from_port(mmio, 0); | |
1088 | writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS); | |
1089 | writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS); | |
6abf4678 ML |
1090 | writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS); |
1091 | if (count) | |
1092 | coal_enable |= PORTS_0_3_COAL_DONE; | |
1093 | if (is_dual_hc) { | |
2b748a0a ML |
1094 | hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); |
1095 | writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD_OFS); | |
1096 | writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD_OFS); | |
6abf4678 ML |
1097 | writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE_OFS); |
1098 | if (count) | |
1099 | coal_enable |= PORTS_4_7_COAL_DONE; | |
2b748a0a | 1100 | } |
2b748a0a | 1101 | |
6abf4678 | 1102 | mv_set_main_irq_mask(host, 0, coal_enable); |
2b748a0a ML |
1103 | spin_unlock_irqrestore(&host->lock, flags); |
1104 | } | |
1105 | ||
05b308e1 | 1106 | /** |
00b81235 | 1107 | * mv_start_edma - Enable eDMA engine |
05b308e1 BR |
1108 | * @base: port base address |
1109 | * @pp: port private data | |
1110 | * | |
beec7dbc TH |
1111 | * Verify the local cache of the eDMA state is accurate with a |
1112 | * WARN_ON. | |
05b308e1 BR |
1113 | * |
1114 | * LOCKING: | |
1115 | * Inherited from caller. | |
1116 | */ | |
00b81235 | 1117 | static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, |
72109168 | 1118 | struct mv_port_priv *pp, u8 protocol) |
20f733e7 | 1119 | { |
72109168 ML |
1120 | int want_ncq = (protocol == ATA_PROT_NCQ); |
1121 | ||
1122 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { | |
1123 | int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); | |
1124 | if (want_ncq != using_ncq) | |
b562468c | 1125 | mv_stop_edma(ap); |
72109168 | 1126 | } |
c5d3e45a | 1127 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { |
0c58912e | 1128 | struct mv_host_priv *hpriv = ap->host->private_data; |
0c58912e | 1129 | |
00b81235 | 1130 | mv_edma_cfg(ap, want_ncq, 1); |
0c58912e | 1131 | |
f630d562 | 1132 | mv_set_edma_ptrs(port_mmio, hpriv, pp); |
00b81235 | 1133 | mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); |
bdd4ddde | 1134 | |
f630d562 | 1135 | writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS); |
afb0edd9 BR |
1136 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; |
1137 | } | |
20f733e7 BR |
1138 | } |
1139 | ||
9b2c4e0b ML |
1140 | static void mv_wait_for_edma_empty_idle(struct ata_port *ap) |
1141 | { | |
1142 | void __iomem *port_mmio = mv_ap_base(ap); | |
1143 | const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); | |
1144 | const int per_loop = 5, timeout = (15 * 1000 / per_loop); | |
1145 | int i; | |
1146 | ||
1147 | /* | |
1148 | * Wait for the EDMA engine to finish transactions in progress. | |
c46938cc ML |
1149 | * No idea what a good "timeout" value might be, but measurements |
1150 | * indicate that it often requires hundreds of microseconds | |
1151 | * with two drives in-use. So we use the 15msec value above | |
1152 | * as a rough guess at what even more drives might require. | |
9b2c4e0b ML |
1153 | */ |
1154 | for (i = 0; i < timeout; ++i) { | |
1155 | u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS); | |
1156 | if ((edma_stat & empty_idle) == empty_idle) | |
1157 | break; | |
1158 | udelay(per_loop); | |
1159 | } | |
1160 | /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */ | |
1161 | } | |
1162 | ||
05b308e1 | 1163 | /** |
e12bef50 | 1164 | * mv_stop_edma_engine - Disable eDMA engine |
b562468c | 1165 | * @port_mmio: io base address |
05b308e1 BR |
1166 | * |
1167 | * LOCKING: | |
1168 | * Inherited from caller. | |
1169 | */ | |
b562468c | 1170 | static int mv_stop_edma_engine(void __iomem *port_mmio) |
20f733e7 | 1171 | { |
b562468c | 1172 | int i; |
31961943 | 1173 | |
b562468c ML |
1174 | /* Disable eDMA. The disable bit auto clears. */ |
1175 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); | |
8b260248 | 1176 | |
b562468c ML |
1177 | /* Wait for the chip to confirm eDMA is off. */ |
1178 | for (i = 10000; i > 0; i--) { | |
1179 | u32 reg = readl(port_mmio + EDMA_CMD_OFS); | |
4537deb5 | 1180 | if (!(reg & EDMA_EN)) |
b562468c ML |
1181 | return 0; |
1182 | udelay(10); | |
31961943 | 1183 | } |
b562468c | 1184 | return -EIO; |
20f733e7 BR |
1185 | } |
1186 | ||
e12bef50 | 1187 | static int mv_stop_edma(struct ata_port *ap) |
0ea9e179 | 1188 | { |
b562468c ML |
1189 | void __iomem *port_mmio = mv_ap_base(ap); |
1190 | struct mv_port_priv *pp = ap->private_data; | |
66e57a2c | 1191 | int err = 0; |
0ea9e179 | 1192 | |
b562468c ML |
1193 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) |
1194 | return 0; | |
1195 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
9b2c4e0b | 1196 | mv_wait_for_edma_empty_idle(ap); |
b562468c ML |
1197 | if (mv_stop_edma_engine(port_mmio)) { |
1198 | ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n"); | |
66e57a2c | 1199 | err = -EIO; |
b562468c | 1200 | } |
66e57a2c ML |
1201 | mv_edma_cfg(ap, 0, 0); |
1202 | return err; | |
0ea9e179 JG |
1203 | } |
1204 | ||
8a70f8dc | 1205 | #ifdef ATA_DEBUG |
31961943 | 1206 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
20f733e7 | 1207 | { |
31961943 BR |
1208 | int b, w; |
1209 | for (b = 0; b < bytes; ) { | |
1210 | DPRINTK("%p: ", start + b); | |
1211 | for (w = 0; b < bytes && w < 4; w++) { | |
2dcb407e | 1212 | printk("%08x ", readl(start + b)); |
31961943 BR |
1213 | b += sizeof(u32); |
1214 | } | |
1215 | printk("\n"); | |
1216 | } | |
31961943 | 1217 | } |
8a70f8dc JG |
1218 | #endif |
1219 | ||
31961943 BR |
1220 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
1221 | { | |
1222 | #ifdef ATA_DEBUG | |
1223 | int b, w; | |
1224 | u32 dw; | |
1225 | for (b = 0; b < bytes; ) { | |
1226 | DPRINTK("%02x: ", b); | |
1227 | for (w = 0; b < bytes && w < 4; w++) { | |
2dcb407e JG |
1228 | (void) pci_read_config_dword(pdev, b, &dw); |
1229 | printk("%08x ", dw); | |
31961943 BR |
1230 | b += sizeof(u32); |
1231 | } | |
1232 | printk("\n"); | |
1233 | } | |
1234 | #endif | |
1235 | } | |
1236 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, | |
1237 | struct pci_dev *pdev) | |
1238 | { | |
1239 | #ifdef ATA_DEBUG | |
8b260248 | 1240 | void __iomem *hc_base = mv_hc_base(mmio_base, |
31961943 BR |
1241 | port >> MV_PORT_HC_SHIFT); |
1242 | void __iomem *port_base; | |
1243 | int start_port, num_ports, p, start_hc, num_hcs, hc; | |
1244 | ||
1245 | if (0 > port) { | |
1246 | start_hc = start_port = 0; | |
1247 | num_ports = 8; /* shld be benign for 4 port devs */ | |
1248 | num_hcs = 2; | |
1249 | } else { | |
1250 | start_hc = port >> MV_PORT_HC_SHIFT; | |
1251 | start_port = port; | |
1252 | num_ports = num_hcs = 1; | |
1253 | } | |
8b260248 | 1254 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
31961943 BR |
1255 | num_ports > 1 ? num_ports - 1 : start_port); |
1256 | ||
1257 | if (NULL != pdev) { | |
1258 | DPRINTK("PCI config space regs:\n"); | |
1259 | mv_dump_pci_cfg(pdev, 0x68); | |
1260 | } | |
1261 | DPRINTK("PCI regs:\n"); | |
1262 | mv_dump_mem(mmio_base+0xc00, 0x3c); | |
1263 | mv_dump_mem(mmio_base+0xd00, 0x34); | |
1264 | mv_dump_mem(mmio_base+0xf00, 0x4); | |
1265 | mv_dump_mem(mmio_base+0x1d00, 0x6c); | |
1266 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { | |
d220c37e | 1267 | hc_base = mv_hc_base(mmio_base, hc); |
31961943 BR |
1268 | DPRINTK("HC regs (HC %i):\n", hc); |
1269 | mv_dump_mem(hc_base, 0x1c); | |
1270 | } | |
1271 | for (p = start_port; p < start_port + num_ports; p++) { | |
1272 | port_base = mv_port_base(mmio_base, p); | |
2dcb407e | 1273 | DPRINTK("EDMA regs (port %i):\n", p); |
31961943 | 1274 | mv_dump_mem(port_base, 0x54); |
2dcb407e | 1275 | DPRINTK("SATA regs (port %i):\n", p); |
31961943 BR |
1276 | mv_dump_mem(port_base+0x300, 0x60); |
1277 | } | |
1278 | #endif | |
20f733e7 BR |
1279 | } |
1280 | ||
1281 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) | |
1282 | { | |
1283 | unsigned int ofs; | |
1284 | ||
1285 | switch (sc_reg_in) { | |
1286 | case SCR_STATUS: | |
1287 | case SCR_CONTROL: | |
1288 | case SCR_ERROR: | |
1289 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); | |
1290 | break; | |
1291 | case SCR_ACTIVE: | |
1292 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ | |
1293 | break; | |
1294 | default: | |
1295 | ofs = 0xffffffffU; | |
1296 | break; | |
1297 | } | |
1298 | return ofs; | |
1299 | } | |
1300 | ||
82ef04fb | 1301 | static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) |
20f733e7 BR |
1302 | { |
1303 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
1304 | ||
da3dbb17 | 1305 | if (ofs != 0xffffffffU) { |
82ef04fb | 1306 | *val = readl(mv_ap_base(link->ap) + ofs); |
da3dbb17 TH |
1307 | return 0; |
1308 | } else | |
1309 | return -EINVAL; | |
20f733e7 BR |
1310 | } |
1311 | ||
82ef04fb | 1312 | static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) |
20f733e7 BR |
1313 | { |
1314 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
1315 | ||
da3dbb17 | 1316 | if (ofs != 0xffffffffU) { |
20091773 ML |
1317 | void __iomem *addr = mv_ap_base(link->ap) + ofs; |
1318 | if (sc_reg_in == SCR_CONTROL) { | |
1319 | /* | |
1320 | * Workaround for 88SX60x1 FEr SATA#26: | |
1321 | * | |
1322 | * COMRESETs have to take care not to accidently | |
1323 | * put the drive to sleep when writing SCR_CONTROL. | |
1324 | * Setting bits 12..15 prevents this problem. | |
1325 | * | |
1326 | * So if we see an outbound COMMRESET, set those bits. | |
1327 | * Ditto for the followup write that clears the reset. | |
1328 | * | |
1329 | * The proprietary driver does this for | |
1330 | * all chip versions, and so do we. | |
1331 | */ | |
1332 | if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) | |
1333 | val |= 0xf000; | |
1334 | } | |
1335 | writelfl(val, addr); | |
da3dbb17 TH |
1336 | return 0; |
1337 | } else | |
1338 | return -EINVAL; | |
20f733e7 BR |
1339 | } |
1340 | ||
f273827e ML |
1341 | static void mv6_dev_config(struct ata_device *adev) |
1342 | { | |
1343 | /* | |
e49856d8 ML |
1344 | * Deal with Gen-II ("mv6") hardware quirks/restrictions: |
1345 | * | |
1346 | * Gen-II does not support NCQ over a port multiplier | |
1347 | * (no FIS-based switching). | |
f273827e | 1348 | */ |
e49856d8 | 1349 | if (adev->flags & ATA_DFLAG_NCQ) { |
352fab70 | 1350 | if (sata_pmp_attached(adev->link->ap)) { |
e49856d8 | 1351 | adev->flags &= ~ATA_DFLAG_NCQ; |
352fab70 ML |
1352 | ata_dev_printk(adev, KERN_INFO, |
1353 | "NCQ disabled for command-based switching\n"); | |
352fab70 | 1354 | } |
e49856d8 | 1355 | } |
f273827e ML |
1356 | } |
1357 | ||
3e4a1391 ML |
1358 | static int mv_qc_defer(struct ata_queued_cmd *qc) |
1359 | { | |
1360 | struct ata_link *link = qc->dev->link; | |
1361 | struct ata_port *ap = link->ap; | |
1362 | struct mv_port_priv *pp = ap->private_data; | |
1363 | ||
29d187bb ML |
1364 | /* |
1365 | * Don't allow new commands if we're in a delayed EH state | |
1366 | * for NCQ and/or FIS-based switching. | |
1367 | */ | |
1368 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) | |
1369 | return ATA_DEFER_PORT; | |
3e4a1391 ML |
1370 | /* |
1371 | * If the port is completely idle, then allow the new qc. | |
1372 | */ | |
1373 | if (ap->nr_active_links == 0) | |
1374 | return 0; | |
1375 | ||
4bdee6c5 TH |
1376 | /* |
1377 | * The port is operating in host queuing mode (EDMA) with NCQ | |
1378 | * enabled, allow multiple NCQ commands. EDMA also allows | |
1379 | * queueing multiple DMA commands but libata core currently | |
1380 | * doesn't allow it. | |
1381 | */ | |
1382 | if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && | |
1383 | (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol)) | |
1384 | return 0; | |
1385 | ||
3e4a1391 ML |
1386 | return ATA_DEFER_PORT; |
1387 | } | |
1388 | ||
08da1759 | 1389 | static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) |
e49856d8 | 1390 | { |
08da1759 ML |
1391 | struct mv_port_priv *pp = ap->private_data; |
1392 | void __iomem *port_mmio; | |
00f42eab | 1393 | |
08da1759 ML |
1394 | u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; |
1395 | u32 ltmode, *old_ltmode = &pp->cached.ltmode; | |
1396 | u32 haltcond, *old_haltcond = &pp->cached.haltcond; | |
00f42eab | 1397 | |
08da1759 ML |
1398 | ltmode = *old_ltmode & ~LTMODE_BIT8; |
1399 | haltcond = *old_haltcond | EDMA_ERR_DEV; | |
00f42eab ML |
1400 | |
1401 | if (want_fbs) { | |
08da1759 ML |
1402 | fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; |
1403 | ltmode = *old_ltmode | LTMODE_BIT8; | |
4c299ca3 | 1404 | if (want_ncq) |
08da1759 | 1405 | haltcond &= ~EDMA_ERR_DEV; |
4c299ca3 | 1406 | else |
08da1759 ML |
1407 | fiscfg |= FISCFG_WAIT_DEV_ERR; |
1408 | } else { | |
1409 | fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); | |
e49856d8 | 1410 | } |
00f42eab | 1411 | |
08da1759 ML |
1412 | port_mmio = mv_ap_base(ap); |
1413 | mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg); | |
1414 | mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode); | |
1415 | mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond); | |
f273827e ML |
1416 | } |
1417 | ||
dd2890f6 ML |
1418 | static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) |
1419 | { | |
1420 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1421 | u32 old, new; | |
1422 | ||
1423 | /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ | |
1424 | old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS); | |
1425 | if (want_ncq) | |
1426 | new = old | (1 << 22); | |
1427 | else | |
1428 | new = old & ~(1 << 22); | |
1429 | if (new != old) | |
1430 | writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS); | |
1431 | } | |
1432 | ||
c01e8a23 | 1433 | /** |
40f21b11 ML |
1434 | * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma |
1435 | * @ap: Port being initialized | |
c01e8a23 ML |
1436 | * |
1437 | * There are two DMA modes on these chips: basic DMA, and EDMA. | |
1438 | * | |
1439 | * Bit-0 of the "EDMA RESERVED" register enables/disables use | |
1440 | * of basic DMA on the GEN_IIE versions of the chips. | |
1441 | * | |
1442 | * This bit survives EDMA resets, and must be set for basic DMA | |
1443 | * to function, and should be cleared when EDMA is active. | |
1444 | */ | |
1445 | static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) | |
1446 | { | |
1447 | struct mv_port_priv *pp = ap->private_data; | |
1448 | u32 new, *old = &pp->cached.unknown_rsvd; | |
1449 | ||
1450 | if (enable_bmdma) | |
1451 | new = *old | 1; | |
1452 | else | |
1453 | new = *old & ~1; | |
1454 | mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new); | |
1455 | } | |
1456 | ||
000b344f ML |
1457 | /* |
1458 | * SOC chips have an issue whereby the HDD LEDs don't always blink | |
1459 | * during I/O when NCQ is enabled. Enabling a special "LED blink" mode | |
1460 | * of the SOC takes care of it, generating a steady blink rate when | |
1461 | * any drive on the chip is active. | |
1462 | * | |
1463 | * Unfortunately, the blink mode is a global hardware setting for the SOC, | |
1464 | * so we must use it whenever at least one port on the SOC has NCQ enabled. | |
1465 | * | |
1466 | * We turn "LED blink" off when NCQ is not in use anywhere, because the normal | |
1467 | * LED operation works then, and provides better (more accurate) feedback. | |
1468 | * | |
1469 | * Note that this code assumes that an SOC never has more than one HC onboard. | |
1470 | */ | |
1471 | static void mv_soc_led_blink_enable(struct ata_port *ap) | |
1472 | { | |
1473 | struct ata_host *host = ap->host; | |
1474 | struct mv_host_priv *hpriv = host->private_data; | |
1475 | void __iomem *hc_mmio; | |
1476 | u32 led_ctrl; | |
1477 | ||
1478 | if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) | |
1479 | return; | |
1480 | hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; | |
1481 | hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); | |
1482 | led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS); | |
1483 | writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS); | |
1484 | } | |
1485 | ||
1486 | static void mv_soc_led_blink_disable(struct ata_port *ap) | |
1487 | { | |
1488 | struct ata_host *host = ap->host; | |
1489 | struct mv_host_priv *hpriv = host->private_data; | |
1490 | void __iomem *hc_mmio; | |
1491 | u32 led_ctrl; | |
1492 | unsigned int port; | |
1493 | ||
1494 | if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) | |
1495 | return; | |
1496 | ||
1497 | /* disable led-blink only if no ports are using NCQ */ | |
1498 | for (port = 0; port < hpriv->n_ports; port++) { | |
1499 | struct ata_port *this_ap = host->ports[port]; | |
1500 | struct mv_port_priv *pp = this_ap->private_data; | |
1501 | ||
1502 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) | |
1503 | return; | |
1504 | } | |
1505 | ||
1506 | hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; | |
1507 | hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); | |
1508 | led_ctrl = readl(hc_mmio + SOC_LED_CTRL_OFS); | |
1509 | writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL_OFS); | |
1510 | } | |
1511 | ||
00b81235 | 1512 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) |
e4e7b892 | 1513 | { |
0c58912e | 1514 | u32 cfg; |
e12bef50 ML |
1515 | struct mv_port_priv *pp = ap->private_data; |
1516 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1517 | void __iomem *port_mmio = mv_ap_base(ap); | |
e4e7b892 JG |
1518 | |
1519 | /* set up non-NCQ EDMA configuration */ | |
0c58912e | 1520 | cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ |
d16ab3f6 ML |
1521 | pp->pp_flags &= |
1522 | ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); | |
e4e7b892 | 1523 | |
0c58912e | 1524 | if (IS_GEN_I(hpriv)) |
e4e7b892 JG |
1525 | cfg |= (1 << 8); /* enab config burst size mask */ |
1526 | ||
dd2890f6 | 1527 | else if (IS_GEN_II(hpriv)) { |
e4e7b892 | 1528 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
dd2890f6 | 1529 | mv_60x1_errata_sata25(ap, want_ncq); |
e4e7b892 | 1530 | |
dd2890f6 | 1531 | } else if (IS_GEN_IIE(hpriv)) { |
00f42eab ML |
1532 | int want_fbs = sata_pmp_attached(ap); |
1533 | /* | |
1534 | * Possible future enhancement: | |
1535 | * | |
1536 | * The chip can use FBS with non-NCQ, if we allow it, | |
1537 | * But first we need to have the error handling in place | |
1538 | * for this mode (datasheet section 7.3.15.4.2.3). | |
1539 | * So disallow non-NCQ FBS for now. | |
1540 | */ | |
1541 | want_fbs &= want_ncq; | |
1542 | ||
08da1759 | 1543 | mv_config_fbs(ap, want_ncq, want_fbs); |
00f42eab ML |
1544 | |
1545 | if (want_fbs) { | |
1546 | pp->pp_flags |= MV_PP_FLAG_FBS_EN; | |
1547 | cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ | |
1548 | } | |
1549 | ||
e728eabe | 1550 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
00b81235 ML |
1551 | if (want_edma) { |
1552 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ | |
1553 | if (!IS_SOC(hpriv)) | |
1554 | cfg |= (1 << 18); /* enab early completion */ | |
1555 | } | |
616d4a98 ML |
1556 | if (hpriv->hp_flags & MV_HP_CUT_THROUGH) |
1557 | cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ | |
c01e8a23 | 1558 | mv_bmdma_enable_iie(ap, !want_edma); |
000b344f ML |
1559 | |
1560 | if (IS_SOC(hpriv)) { | |
1561 | if (want_ncq) | |
1562 | mv_soc_led_blink_enable(ap); | |
1563 | else | |
1564 | mv_soc_led_blink_disable(ap); | |
1565 | } | |
e4e7b892 JG |
1566 | } |
1567 | ||
72109168 ML |
1568 | if (want_ncq) { |
1569 | cfg |= EDMA_CFG_NCQ; | |
1570 | pp->pp_flags |= MV_PP_FLAG_NCQ_EN; | |
00b81235 | 1571 | } |
72109168 | 1572 | |
e4e7b892 JG |
1573 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); |
1574 | } | |
1575 | ||
da2fa9ba ML |
1576 | static void mv_port_free_dma_mem(struct ata_port *ap) |
1577 | { | |
1578 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1579 | struct mv_port_priv *pp = ap->private_data; | |
eb73d558 | 1580 | int tag; |
da2fa9ba ML |
1581 | |
1582 | if (pp->crqb) { | |
1583 | dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); | |
1584 | pp->crqb = NULL; | |
1585 | } | |
1586 | if (pp->crpb) { | |
1587 | dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); | |
1588 | pp->crpb = NULL; | |
1589 | } | |
eb73d558 ML |
1590 | /* |
1591 | * For GEN_I, there's no NCQ, so we have only a single sg_tbl. | |
1592 | * For later hardware, we have one unique sg_tbl per NCQ tag. | |
1593 | */ | |
1594 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { | |
1595 | if (pp->sg_tbl[tag]) { | |
1596 | if (tag == 0 || !IS_GEN_I(hpriv)) | |
1597 | dma_pool_free(hpriv->sg_tbl_pool, | |
1598 | pp->sg_tbl[tag], | |
1599 | pp->sg_tbl_dma[tag]); | |
1600 | pp->sg_tbl[tag] = NULL; | |
1601 | } | |
da2fa9ba ML |
1602 | } |
1603 | } | |
1604 | ||
05b308e1 BR |
1605 | /** |
1606 | * mv_port_start - Port specific init/start routine. | |
1607 | * @ap: ATA channel to manipulate | |
1608 | * | |
1609 | * Allocate and point to DMA memory, init port private memory, | |
1610 | * zero indices. | |
1611 | * | |
1612 | * LOCKING: | |
1613 | * Inherited from caller. | |
1614 | */ | |
31961943 BR |
1615 | static int mv_port_start(struct ata_port *ap) |
1616 | { | |
cca3974e JG |
1617 | struct device *dev = ap->host->dev; |
1618 | struct mv_host_priv *hpriv = ap->host->private_data; | |
31961943 | 1619 | struct mv_port_priv *pp; |
933cb8e5 | 1620 | unsigned long flags; |
dde20207 | 1621 | int tag; |
31961943 | 1622 | |
24dc5f33 | 1623 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
6037d6bb | 1624 | if (!pp) |
24dc5f33 | 1625 | return -ENOMEM; |
da2fa9ba | 1626 | ap->private_data = pp; |
31961943 | 1627 | |
da2fa9ba ML |
1628 | pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); |
1629 | if (!pp->crqb) | |
1630 | return -ENOMEM; | |
1631 | memset(pp->crqb, 0, MV_CRQB_Q_SZ); | |
31961943 | 1632 | |
da2fa9ba ML |
1633 | pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); |
1634 | if (!pp->crpb) | |
1635 | goto out_port_free_dma_mem; | |
1636 | memset(pp->crpb, 0, MV_CRPB_Q_SZ); | |
31961943 | 1637 | |
3bd0a70e ML |
1638 | /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ |
1639 | if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) | |
1640 | ap->flags |= ATA_FLAG_AN; | |
eb73d558 ML |
1641 | /* |
1642 | * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. | |
1643 | * For later hardware, we need one unique sg_tbl per NCQ tag. | |
1644 | */ | |
1645 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { | |
1646 | if (tag == 0 || !IS_GEN_I(hpriv)) { | |
1647 | pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, | |
1648 | GFP_KERNEL, &pp->sg_tbl_dma[tag]); | |
1649 | if (!pp->sg_tbl[tag]) | |
1650 | goto out_port_free_dma_mem; | |
1651 | } else { | |
1652 | pp->sg_tbl[tag] = pp->sg_tbl[0]; | |
1653 | pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; | |
1654 | } | |
1655 | } | |
933cb8e5 ML |
1656 | |
1657 | spin_lock_irqsave(ap->lock, flags); | |
08da1759 | 1658 | mv_save_cached_regs(ap); |
66e57a2c | 1659 | mv_edma_cfg(ap, 0, 0); |
933cb8e5 ML |
1660 | spin_unlock_irqrestore(ap->lock, flags); |
1661 | ||
31961943 | 1662 | return 0; |
da2fa9ba ML |
1663 | |
1664 | out_port_free_dma_mem: | |
1665 | mv_port_free_dma_mem(ap); | |
1666 | return -ENOMEM; | |
31961943 BR |
1667 | } |
1668 | ||
05b308e1 BR |
1669 | /** |
1670 | * mv_port_stop - Port specific cleanup/stop routine. | |
1671 | * @ap: ATA channel to manipulate | |
1672 | * | |
1673 | * Stop DMA, cleanup port memory. | |
1674 | * | |
1675 | * LOCKING: | |
cca3974e | 1676 | * This routine uses the host lock to protect the DMA stop. |
05b308e1 | 1677 | */ |
31961943 BR |
1678 | static void mv_port_stop(struct ata_port *ap) |
1679 | { | |
933cb8e5 ML |
1680 | unsigned long flags; |
1681 | ||
1682 | spin_lock_irqsave(ap->lock, flags); | |
e12bef50 | 1683 | mv_stop_edma(ap); |
88e675e1 | 1684 | mv_enable_port_irqs(ap, 0); |
933cb8e5 | 1685 | spin_unlock_irqrestore(ap->lock, flags); |
da2fa9ba | 1686 | mv_port_free_dma_mem(ap); |
31961943 BR |
1687 | } |
1688 | ||
05b308e1 BR |
1689 | /** |
1690 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries | |
1691 | * @qc: queued command whose SG list to source from | |
1692 | * | |
1693 | * Populate the SG list and mark the last entry. | |
1694 | * | |
1695 | * LOCKING: | |
1696 | * Inherited from caller. | |
1697 | */ | |
6c08772e | 1698 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
31961943 BR |
1699 | { |
1700 | struct mv_port_priv *pp = qc->ap->private_data; | |
972c26bd | 1701 | struct scatterlist *sg; |
3be6cbd7 | 1702 | struct mv_sg *mv_sg, *last_sg = NULL; |
ff2aeb1e | 1703 | unsigned int si; |
31961943 | 1704 | |
eb73d558 | 1705 | mv_sg = pp->sg_tbl[qc->tag]; |
ff2aeb1e | 1706 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
d88184fb JG |
1707 | dma_addr_t addr = sg_dma_address(sg); |
1708 | u32 sg_len = sg_dma_len(sg); | |
22374677 | 1709 | |
4007b493 OJ |
1710 | while (sg_len) { |
1711 | u32 offset = addr & 0xffff; | |
1712 | u32 len = sg_len; | |
22374677 | 1713 | |
32cd11a6 | 1714 | if (offset + len > 0x10000) |
4007b493 OJ |
1715 | len = 0x10000 - offset; |
1716 | ||
1717 | mv_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1718 | mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
6c08772e | 1719 | mv_sg->flags_size = cpu_to_le32(len & 0xffff); |
32cd11a6 | 1720 | mv_sg->reserved = 0; |
4007b493 OJ |
1721 | |
1722 | sg_len -= len; | |
1723 | addr += len; | |
1724 | ||
3be6cbd7 | 1725 | last_sg = mv_sg; |
4007b493 | 1726 | mv_sg++; |
4007b493 | 1727 | } |
31961943 | 1728 | } |
3be6cbd7 JG |
1729 | |
1730 | if (likely(last_sg)) | |
1731 | last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); | |
32cd11a6 | 1732 | mb(); /* ensure data structure is visible to the chipset */ |
31961943 BR |
1733 | } |
1734 | ||
5796d1c4 | 1735 | static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) |
31961943 | 1736 | { |
559eedad | 1737 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | |
31961943 | 1738 | (last ? CRQB_CMD_LAST : 0); |
559eedad | 1739 | *cmdw = cpu_to_le16(tmp); |
31961943 BR |
1740 | } |
1741 | ||
da14265e ML |
1742 | /** |
1743 | * mv_sff_irq_clear - Clear hardware interrupt after DMA. | |
1744 | * @ap: Port associated with this ATA transaction. | |
1745 | * | |
1746 | * We need this only for ATAPI bmdma transactions, | |
1747 | * as otherwise we experience spurious interrupts | |
1748 | * after libata-sff handles the bmdma interrupts. | |
1749 | */ | |
1750 | static void mv_sff_irq_clear(struct ata_port *ap) | |
1751 | { | |
1752 | mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); | |
1753 | } | |
1754 | ||
1755 | /** | |
1756 | * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. | |
1757 | * @qc: queued command to check for chipset/DMA compatibility. | |
1758 | * | |
1759 | * The bmdma engines cannot handle speculative data sizes | |
1760 | * (bytecount under/over flow). So only allow DMA for | |
1761 | * data transfer commands with known data sizes. | |
1762 | * | |
1763 | * LOCKING: | |
1764 | * Inherited from caller. | |
1765 | */ | |
1766 | static int mv_check_atapi_dma(struct ata_queued_cmd *qc) | |
1767 | { | |
1768 | struct scsi_cmnd *scmd = qc->scsicmd; | |
1769 | ||
1770 | if (scmd) { | |
1771 | switch (scmd->cmnd[0]) { | |
1772 | case READ_6: | |
1773 | case READ_10: | |
1774 | case READ_12: | |
1775 | case WRITE_6: | |
1776 | case WRITE_10: | |
1777 | case WRITE_12: | |
1778 | case GPCMD_READ_CD: | |
1779 | case GPCMD_SEND_DVD_STRUCTURE: | |
1780 | case GPCMD_SEND_CUE_SHEET: | |
1781 | return 0; /* DMA is safe */ | |
1782 | } | |
1783 | } | |
1784 | return -EOPNOTSUPP; /* use PIO instead */ | |
1785 | } | |
1786 | ||
1787 | /** | |
1788 | * mv_bmdma_setup - Set up BMDMA transaction | |
1789 | * @qc: queued command to prepare DMA for. | |
1790 | * | |
1791 | * LOCKING: | |
1792 | * Inherited from caller. | |
1793 | */ | |
1794 | static void mv_bmdma_setup(struct ata_queued_cmd *qc) | |
1795 | { | |
1796 | struct ata_port *ap = qc->ap; | |
1797 | void __iomem *port_mmio = mv_ap_base(ap); | |
1798 | struct mv_port_priv *pp = ap->private_data; | |
1799 | ||
1800 | mv_fill_sg(qc); | |
1801 | ||
1802 | /* clear all DMA cmd bits */ | |
1803 | writel(0, port_mmio + BMDMA_CMD_OFS); | |
1804 | ||
1805 | /* load PRD table addr. */ | |
1806 | writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16, | |
1807 | port_mmio + BMDMA_PRD_HIGH_OFS); | |
1808 | writelfl(pp->sg_tbl_dma[qc->tag], | |
1809 | port_mmio + BMDMA_PRD_LOW_OFS); | |
1810 | ||
1811 | /* issue r/w command */ | |
1812 | ap->ops->sff_exec_command(ap, &qc->tf); | |
1813 | } | |
1814 | ||
1815 | /** | |
1816 | * mv_bmdma_start - Start a BMDMA transaction | |
1817 | * @qc: queued command to start DMA on. | |
1818 | * | |
1819 | * LOCKING: | |
1820 | * Inherited from caller. | |
1821 | */ | |
1822 | static void mv_bmdma_start(struct ata_queued_cmd *qc) | |
1823 | { | |
1824 | struct ata_port *ap = qc->ap; | |
1825 | void __iomem *port_mmio = mv_ap_base(ap); | |
1826 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
1827 | u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; | |
1828 | ||
1829 | /* start host DMA transaction */ | |
1830 | writelfl(cmd, port_mmio + BMDMA_CMD_OFS); | |
1831 | } | |
1832 | ||
1833 | /** | |
1834 | * mv_bmdma_stop - Stop BMDMA transfer | |
1835 | * @qc: queued command to stop DMA on. | |
1836 | * | |
1837 | * Clears the ATA_DMA_START flag in the bmdma control register | |
1838 | * | |
1839 | * LOCKING: | |
1840 | * Inherited from caller. | |
1841 | */ | |
1842 | static void mv_bmdma_stop(struct ata_queued_cmd *qc) | |
1843 | { | |
1844 | struct ata_port *ap = qc->ap; | |
1845 | void __iomem *port_mmio = mv_ap_base(ap); | |
1846 | u32 cmd; | |
1847 | ||
1848 | /* clear start/stop bit */ | |
1849 | cmd = readl(port_mmio + BMDMA_CMD_OFS); | |
1850 | cmd &= ~ATA_DMA_START; | |
1851 | writelfl(cmd, port_mmio + BMDMA_CMD_OFS); | |
1852 | ||
1853 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
1854 | ata_sff_dma_pause(ap); | |
1855 | } | |
1856 | ||
1857 | /** | |
1858 | * mv_bmdma_status - Read BMDMA status | |
1859 | * @ap: port for which to retrieve DMA status. | |
1860 | * | |
1861 | * Read and return equivalent of the sff BMDMA status register. | |
1862 | * | |
1863 | * LOCKING: | |
1864 | * Inherited from caller. | |
1865 | */ | |
1866 | static u8 mv_bmdma_status(struct ata_port *ap) | |
1867 | { | |
1868 | void __iomem *port_mmio = mv_ap_base(ap); | |
1869 | u32 reg, status; | |
1870 | ||
1871 | /* | |
1872 | * Other bits are valid only if ATA_DMA_ACTIVE==0, | |
1873 | * and the ATA_DMA_INTR bit doesn't exist. | |
1874 | */ | |
1875 | reg = readl(port_mmio + BMDMA_STATUS_OFS); | |
1876 | if (reg & ATA_DMA_ACTIVE) | |
1877 | status = ATA_DMA_ACTIVE; | |
1878 | else | |
1879 | status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; | |
1880 | return status; | |
1881 | } | |
1882 | ||
05b308e1 BR |
1883 | /** |
1884 | * mv_qc_prep - Host specific command preparation. | |
1885 | * @qc: queued command to prepare | |
1886 | * | |
1887 | * This routine simply redirects to the general purpose routine | |
1888 | * if command is not DMA. Else, it handles prep of the CRQB | |
1889 | * (command request block), does some sanity checking, and calls | |
1890 | * the SG load routine. | |
1891 | * | |
1892 | * LOCKING: | |
1893 | * Inherited from caller. | |
1894 | */ | |
31961943 BR |
1895 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
1896 | { | |
1897 | struct ata_port *ap = qc->ap; | |
1898 | struct mv_port_priv *pp = ap->private_data; | |
e1469874 | 1899 | __le16 *cw; |
31961943 BR |
1900 | struct ata_taskfile *tf; |
1901 | u16 flags = 0; | |
a6432436 | 1902 | unsigned in_index; |
31961943 | 1903 | |
138bfdd0 ML |
1904 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
1905 | (qc->tf.protocol != ATA_PROT_NCQ)) | |
31961943 | 1906 | return; |
20f733e7 | 1907 | |
31961943 BR |
1908 | /* Fill in command request block |
1909 | */ | |
e4e7b892 | 1910 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
31961943 | 1911 | flags |= CRQB_FLAG_READ; |
beec7dbc | 1912 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
31961943 | 1913 | flags |= qc->tag << CRQB_TAG_SHIFT; |
e49856d8 | 1914 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
31961943 | 1915 | |
bdd4ddde | 1916 | /* get current queue index from software */ |
fcfb1f77 | 1917 | in_index = pp->req_idx; |
a6432436 ML |
1918 | |
1919 | pp->crqb[in_index].sg_addr = | |
eb73d558 | 1920 | cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
a6432436 | 1921 | pp->crqb[in_index].sg_addr_hi = |
eb73d558 | 1922 | cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); |
a6432436 | 1923 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); |
31961943 | 1924 | |
a6432436 | 1925 | cw = &pp->crqb[in_index].ata_cmd[0]; |
31961943 BR |
1926 | tf = &qc->tf; |
1927 | ||
1928 | /* Sadly, the CRQB cannot accomodate all registers--there are | |
1929 | * only 11 bytes...so we must pick and choose required | |
1930 | * registers based on the command. So, we drop feature and | |
1931 | * hob_feature for [RW] DMA commands, but they are needed for | |
cd12e1f7 ML |
1932 | * NCQ. NCQ will drop hob_nsect, which is not needed there |
1933 | * (nsect is used only for the tag; feat/hob_feat hold true nsect). | |
20f733e7 | 1934 | */ |
31961943 BR |
1935 | switch (tf->command) { |
1936 | case ATA_CMD_READ: | |
1937 | case ATA_CMD_READ_EXT: | |
1938 | case ATA_CMD_WRITE: | |
1939 | case ATA_CMD_WRITE_EXT: | |
c15d85c8 | 1940 | case ATA_CMD_WRITE_FUA_EXT: |
31961943 BR |
1941 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
1942 | break; | |
31961943 BR |
1943 | case ATA_CMD_FPDMA_READ: |
1944 | case ATA_CMD_FPDMA_WRITE: | |
8b260248 | 1945 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
31961943 BR |
1946 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
1947 | break; | |
31961943 BR |
1948 | default: |
1949 | /* The only other commands EDMA supports in non-queued and | |
1950 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none | |
1951 | * of which are defined/used by Linux. If we get here, this | |
1952 | * driver needs work. | |
1953 | * | |
1954 | * FIXME: modify libata to give qc_prep a return value and | |
1955 | * return error here. | |
1956 | */ | |
1957 | BUG_ON(tf->command); | |
1958 | break; | |
1959 | } | |
1960 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); | |
1961 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); | |
1962 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); | |
1963 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); | |
1964 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); | |
1965 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); | |
1966 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); | |
1967 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); | |
1968 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ | |
1969 | ||
e4e7b892 JG |
1970 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
1971 | return; | |
1972 | mv_fill_sg(qc); | |
1973 | } | |
1974 | ||
1975 | /** | |
1976 | * mv_qc_prep_iie - Host specific command preparation. | |
1977 | * @qc: queued command to prepare | |
1978 | * | |
1979 | * This routine simply redirects to the general purpose routine | |
1980 | * if command is not DMA. Else, it handles prep of the CRQB | |
1981 | * (command request block), does some sanity checking, and calls | |
1982 | * the SG load routine. | |
1983 | * | |
1984 | * LOCKING: | |
1985 | * Inherited from caller. | |
1986 | */ | |
1987 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) | |
1988 | { | |
1989 | struct ata_port *ap = qc->ap; | |
1990 | struct mv_port_priv *pp = ap->private_data; | |
1991 | struct mv_crqb_iie *crqb; | |
1992 | struct ata_taskfile *tf; | |
a6432436 | 1993 | unsigned in_index; |
e4e7b892 JG |
1994 | u32 flags = 0; |
1995 | ||
138bfdd0 ML |
1996 | if ((qc->tf.protocol != ATA_PROT_DMA) && |
1997 | (qc->tf.protocol != ATA_PROT_NCQ)) | |
e4e7b892 JG |
1998 | return; |
1999 | ||
e12bef50 | 2000 | /* Fill in Gen IIE command request block */ |
e4e7b892 JG |
2001 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
2002 | flags |= CRQB_FLAG_READ; | |
2003 | ||
beec7dbc | 2004 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
e4e7b892 | 2005 | flags |= qc->tag << CRQB_TAG_SHIFT; |
8c0aeb4a | 2006 | flags |= qc->tag << CRQB_HOSTQ_SHIFT; |
e49856d8 | 2007 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
e4e7b892 | 2008 | |
bdd4ddde | 2009 | /* get current queue index from software */ |
fcfb1f77 | 2010 | in_index = pp->req_idx; |
a6432436 ML |
2011 | |
2012 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; | |
eb73d558 ML |
2013 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff); |
2014 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16); | |
e4e7b892 JG |
2015 | crqb->flags = cpu_to_le32(flags); |
2016 | ||
2017 | tf = &qc->tf; | |
2018 | crqb->ata_cmd[0] = cpu_to_le32( | |
2019 | (tf->command << 16) | | |
2020 | (tf->feature << 24) | |
2021 | ); | |
2022 | crqb->ata_cmd[1] = cpu_to_le32( | |
2023 | (tf->lbal << 0) | | |
2024 | (tf->lbam << 8) | | |
2025 | (tf->lbah << 16) | | |
2026 | (tf->device << 24) | |
2027 | ); | |
2028 | crqb->ata_cmd[2] = cpu_to_le32( | |
2029 | (tf->hob_lbal << 0) | | |
2030 | (tf->hob_lbam << 8) | | |
2031 | (tf->hob_lbah << 16) | | |
2032 | (tf->hob_feature << 24) | |
2033 | ); | |
2034 | crqb->ata_cmd[3] = cpu_to_le32( | |
2035 | (tf->nsect << 0) | | |
2036 | (tf->hob_nsect << 8) | |
2037 | ); | |
2038 | ||
2039 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
31961943 | 2040 | return; |
31961943 BR |
2041 | mv_fill_sg(qc); |
2042 | } | |
2043 | ||
d16ab3f6 ML |
2044 | /** |
2045 | * mv_sff_check_status - fetch device status, if valid | |
2046 | * @ap: ATA port to fetch status from | |
2047 | * | |
2048 | * When using command issue via mv_qc_issue_fis(), | |
2049 | * the initial ATA_BUSY state does not show up in the | |
2050 | * ATA status (shadow) register. This can confuse libata! | |
2051 | * | |
2052 | * So we have a hook here to fake ATA_BUSY for that situation, | |
2053 | * until the first time a BUSY, DRQ, or ERR bit is seen. | |
2054 | * | |
2055 | * The rest of the time, it simply returns the ATA status register. | |
2056 | */ | |
2057 | static u8 mv_sff_check_status(struct ata_port *ap) | |
2058 | { | |
2059 | u8 stat = ioread8(ap->ioaddr.status_addr); | |
2060 | struct mv_port_priv *pp = ap->private_data; | |
2061 | ||
2062 | if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { | |
2063 | if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) | |
2064 | pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; | |
2065 | else | |
2066 | stat = ATA_BUSY; | |
2067 | } | |
2068 | return stat; | |
2069 | } | |
2070 | ||
70f8b79c ML |
2071 | /** |
2072 | * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register | |
2073 | * @fis: fis to be sent | |
2074 | * @nwords: number of 32-bit words in the fis | |
2075 | */ | |
2076 | static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) | |
2077 | { | |
2078 | void __iomem *port_mmio = mv_ap_base(ap); | |
2079 | u32 ifctl, old_ifctl, ifstat; | |
2080 | int i, timeout = 200, final_word = nwords - 1; | |
2081 | ||
2082 | /* Initiate FIS transmission mode */ | |
2083 | old_ifctl = readl(port_mmio + SATA_IFCTL_OFS); | |
2084 | ifctl = 0x100 | (old_ifctl & 0xf); | |
2085 | writelfl(ifctl, port_mmio + SATA_IFCTL_OFS); | |
2086 | ||
2087 | /* Send all words of the FIS except for the final word */ | |
2088 | for (i = 0; i < final_word; ++i) | |
2089 | writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS); | |
2090 | ||
2091 | /* Flag end-of-transmission, and then send the final word */ | |
2092 | writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS); | |
2093 | writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS); | |
2094 | ||
2095 | /* | |
2096 | * Wait for FIS transmission to complete. | |
2097 | * This typically takes just a single iteration. | |
2098 | */ | |
2099 | do { | |
2100 | ifstat = readl(port_mmio + SATA_IFSTAT_OFS); | |
2101 | } while (!(ifstat & 0x1000) && --timeout); | |
2102 | ||
2103 | /* Restore original port configuration */ | |
2104 | writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS); | |
2105 | ||
2106 | /* See if it worked */ | |
2107 | if ((ifstat & 0x3000) != 0x1000) { | |
2108 | ata_port_printk(ap, KERN_WARNING, | |
2109 | "%s transmission error, ifstat=%08x\n", | |
2110 | __func__, ifstat); | |
2111 | return AC_ERR_OTHER; | |
2112 | } | |
2113 | return 0; | |
2114 | } | |
2115 | ||
2116 | /** | |
2117 | * mv_qc_issue_fis - Issue a command directly as a FIS | |
2118 | * @qc: queued command to start | |
2119 | * | |
2120 | * Note that the ATA shadow registers are not updated | |
2121 | * after command issue, so the device will appear "READY" | |
2122 | * if polled, even while it is BUSY processing the command. | |
2123 | * | |
2124 | * So we use a status hook to fake ATA_BUSY until the drive changes state. | |
2125 | * | |
2126 | * Note: we don't get updated shadow regs on *completion* | |
2127 | * of non-data commands. So avoid sending them via this function, | |
2128 | * as they will appear to have completed immediately. | |
2129 | * | |
2130 | * GEN_IIE has special registers that we could get the result tf from, | |
2131 | * but earlier chipsets do not. For now, we ignore those registers. | |
2132 | */ | |
2133 | static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) | |
2134 | { | |
2135 | struct ata_port *ap = qc->ap; | |
2136 | struct mv_port_priv *pp = ap->private_data; | |
2137 | struct ata_link *link = qc->dev->link; | |
2138 | u32 fis[5]; | |
2139 | int err = 0; | |
2140 | ||
2141 | ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); | |
2142 | err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0])); | |
2143 | if (err) | |
2144 | return err; | |
2145 | ||
2146 | switch (qc->tf.protocol) { | |
2147 | case ATAPI_PROT_PIO: | |
2148 | pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; | |
2149 | /* fall through */ | |
2150 | case ATAPI_PROT_NODATA: | |
2151 | ap->hsm_task_state = HSM_ST_FIRST; | |
2152 | break; | |
2153 | case ATA_PROT_PIO: | |
2154 | pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; | |
2155 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
2156 | ap->hsm_task_state = HSM_ST_FIRST; | |
2157 | else | |
2158 | ap->hsm_task_state = HSM_ST; | |
2159 | break; | |
2160 | default: | |
2161 | ap->hsm_task_state = HSM_ST_LAST; | |
2162 | break; | |
2163 | } | |
2164 | ||
2165 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
2166 | ata_pio_queue_task(ap, qc, 0); | |
2167 | return 0; | |
2168 | } | |
2169 | ||
05b308e1 BR |
2170 | /** |
2171 | * mv_qc_issue - Initiate a command to the host | |
2172 | * @qc: queued command to start | |
2173 | * | |
2174 | * This routine simply redirects to the general purpose routine | |
2175 | * if command is not DMA. Else, it sanity checks our local | |
2176 | * caches of the request producer/consumer indices then enables | |
2177 | * DMA and bumps the request producer index. | |
2178 | * | |
2179 | * LOCKING: | |
2180 | * Inherited from caller. | |
2181 | */ | |
9a3d9eb0 | 2182 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
31961943 | 2183 | { |
f48765cc | 2184 | static int limit_warnings = 10; |
c5d3e45a JG |
2185 | struct ata_port *ap = qc->ap; |
2186 | void __iomem *port_mmio = mv_ap_base(ap); | |
2187 | struct mv_port_priv *pp = ap->private_data; | |
bdd4ddde | 2188 | u32 in_index; |
42ed893d | 2189 | unsigned int port_irqs; |
f48765cc | 2190 | |
d16ab3f6 ML |
2191 | pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ |
2192 | ||
f48765cc ML |
2193 | switch (qc->tf.protocol) { |
2194 | case ATA_PROT_DMA: | |
2195 | case ATA_PROT_NCQ: | |
2196 | mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); | |
2197 | pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; | |
2198 | in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; | |
2199 | ||
2200 | /* Write the request in pointer to kick the EDMA to life */ | |
2201 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, | |
2202 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | |
2203 | return 0; | |
31961943 | 2204 | |
f48765cc | 2205 | case ATA_PROT_PIO: |
c6112bd8 ML |
2206 | /* |
2207 | * Errata SATA#16, SATA#24: warn if multiple DRQs expected. | |
2208 | * | |
2209 | * Someday, we might implement special polling workarounds | |
2210 | * for these, but it all seems rather unnecessary since we | |
2211 | * normally use only DMA for commands which transfer more | |
2212 | * than a single block of data. | |
2213 | * | |
2214 | * Much of the time, this could just work regardless. | |
2215 | * So for now, just log the incident, and allow the attempt. | |
2216 | */ | |
c7843e8f | 2217 | if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { |
c6112bd8 ML |
2218 | --limit_warnings; |
2219 | ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME | |
2220 | ": attempting PIO w/multiple DRQ: " | |
2221 | "this may fail due to h/w errata\n"); | |
2222 | } | |
f48765cc | 2223 | /* drop through */ |
42ed893d | 2224 | case ATA_PROT_NODATA: |
f48765cc | 2225 | case ATAPI_PROT_PIO: |
42ed893d ML |
2226 | case ATAPI_PROT_NODATA: |
2227 | if (ap->flags & ATA_FLAG_PIO_POLLING) | |
2228 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
2229 | break; | |
31961943 | 2230 | } |
42ed893d ML |
2231 | |
2232 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
2233 | port_irqs = ERR_IRQ; /* mask device interrupt when polling */ | |
2234 | else | |
2235 | port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ | |
2236 | ||
2237 | /* | |
2238 | * We're about to send a non-EDMA capable command to the | |
2239 | * port. Turn off EDMA so there won't be problems accessing | |
2240 | * shadow block, etc registers. | |
2241 | */ | |
2242 | mv_stop_edma(ap); | |
2243 | mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); | |
2244 | mv_pmp_select(ap, qc->dev->link->pmp); | |
70f8b79c ML |
2245 | |
2246 | if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { | |
2247 | struct mv_host_priv *hpriv = ap->host->private_data; | |
2248 | /* | |
2249 | * Workaround for 88SX60x1 FEr SATA#25 (part 2). | |
40f21b11 | 2250 | * |
70f8b79c ML |
2251 | * After any NCQ error, the READ_LOG_EXT command |
2252 | * from libata-eh *must* use mv_qc_issue_fis(). | |
2253 | * Otherwise it might fail, due to chip errata. | |
2254 | * | |
2255 | * Rather than special-case it, we'll just *always* | |
2256 | * use this method here for READ_LOG_EXT, making for | |
2257 | * easier testing. | |
2258 | */ | |
2259 | if (IS_GEN_II(hpriv)) | |
2260 | return mv_qc_issue_fis(qc); | |
2261 | } | |
42ed893d | 2262 | return ata_sff_qc_issue(qc); |
31961943 BR |
2263 | } |
2264 | ||
8f767f8a ML |
2265 | static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) |
2266 | { | |
2267 | struct mv_port_priv *pp = ap->private_data; | |
2268 | struct ata_queued_cmd *qc; | |
2269 | ||
2270 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) | |
2271 | return NULL; | |
2272 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
95db5051 ML |
2273 | if (qc) { |
2274 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
2275 | qc = NULL; | |
2276 | else if (!(qc->flags & ATA_QCFLAG_ACTIVE)) | |
2277 | qc = NULL; | |
2278 | } | |
8f767f8a ML |
2279 | return qc; |
2280 | } | |
2281 | ||
29d187bb ML |
2282 | static void mv_pmp_error_handler(struct ata_port *ap) |
2283 | { | |
2284 | unsigned int pmp, pmp_map; | |
2285 | struct mv_port_priv *pp = ap->private_data; | |
2286 | ||
2287 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { | |
2288 | /* | |
2289 | * Perform NCQ error analysis on failed PMPs | |
2290 | * before we freeze the port entirely. | |
2291 | * | |
2292 | * The failed PMPs are marked earlier by mv_pmp_eh_prep(). | |
2293 | */ | |
2294 | pmp_map = pp->delayed_eh_pmp_map; | |
2295 | pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; | |
2296 | for (pmp = 0; pmp_map != 0; pmp++) { | |
2297 | unsigned int this_pmp = (1 << pmp); | |
2298 | if (pmp_map & this_pmp) { | |
2299 | struct ata_link *link = &ap->pmp_link[pmp]; | |
2300 | pmp_map &= ~this_pmp; | |
2301 | ata_eh_analyze_ncq_error(link); | |
2302 | } | |
2303 | } | |
2304 | ata_port_freeze(ap); | |
2305 | } | |
2306 | sata_pmp_error_handler(ap); | |
2307 | } | |
2308 | ||
4c299ca3 ML |
2309 | static unsigned int mv_get_err_pmp_map(struct ata_port *ap) |
2310 | { | |
2311 | void __iomem *port_mmio = mv_ap_base(ap); | |
2312 | ||
2313 | return readl(port_mmio + SATA_TESTCTL_OFS) >> 16; | |
2314 | } | |
2315 | ||
4c299ca3 ML |
2316 | static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) |
2317 | { | |
2318 | struct ata_eh_info *ehi; | |
2319 | unsigned int pmp; | |
2320 | ||
2321 | /* | |
2322 | * Initialize EH info for PMPs which saw device errors | |
2323 | */ | |
2324 | ehi = &ap->link.eh_info; | |
2325 | for (pmp = 0; pmp_map != 0; pmp++) { | |
2326 | unsigned int this_pmp = (1 << pmp); | |
2327 | if (pmp_map & this_pmp) { | |
2328 | struct ata_link *link = &ap->pmp_link[pmp]; | |
2329 | ||
2330 | pmp_map &= ~this_pmp; | |
2331 | ehi = &link->eh_info; | |
2332 | ata_ehi_clear_desc(ehi); | |
2333 | ata_ehi_push_desc(ehi, "dev err"); | |
2334 | ehi->err_mask |= AC_ERR_DEV; | |
2335 | ehi->action |= ATA_EH_RESET; | |
2336 | ata_link_abort(link); | |
2337 | } | |
2338 | } | |
2339 | } | |
2340 | ||
06aaca3f ML |
2341 | static int mv_req_q_empty(struct ata_port *ap) |
2342 | { | |
2343 | void __iomem *port_mmio = mv_ap_base(ap); | |
2344 | u32 in_ptr, out_ptr; | |
2345 | ||
2346 | in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS) | |
2347 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; | |
2348 | out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) | |
2349 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; | |
2350 | return (in_ptr == out_ptr); /* 1 == queue_is_empty */ | |
2351 | } | |
2352 | ||
4c299ca3 ML |
2353 | static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) |
2354 | { | |
2355 | struct mv_port_priv *pp = ap->private_data; | |
2356 | int failed_links; | |
2357 | unsigned int old_map, new_map; | |
2358 | ||
2359 | /* | |
2360 | * Device error during FBS+NCQ operation: | |
2361 | * | |
2362 | * Set a port flag to prevent further I/O being enqueued. | |
2363 | * Leave the EDMA running to drain outstanding commands from this port. | |
2364 | * Perform the post-mortem/EH only when all responses are complete. | |
2365 | * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). | |
2366 | */ | |
2367 | if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { | |
2368 | pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; | |
2369 | pp->delayed_eh_pmp_map = 0; | |
2370 | } | |
2371 | old_map = pp->delayed_eh_pmp_map; | |
2372 | new_map = old_map | mv_get_err_pmp_map(ap); | |
2373 | ||
2374 | if (old_map != new_map) { | |
2375 | pp->delayed_eh_pmp_map = new_map; | |
2376 | mv_pmp_eh_prep(ap, new_map & ~old_map); | |
2377 | } | |
c46938cc | 2378 | failed_links = hweight16(new_map); |
4c299ca3 ML |
2379 | |
2380 | ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x " | |
2381 | "failed_links=%d nr_active_links=%d\n", | |
2382 | __func__, pp->delayed_eh_pmp_map, | |
2383 | ap->qc_active, failed_links, | |
2384 | ap->nr_active_links); | |
2385 | ||
06aaca3f | 2386 | if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { |
4c299ca3 ML |
2387 | mv_process_crpb_entries(ap, pp); |
2388 | mv_stop_edma(ap); | |
2389 | mv_eh_freeze(ap); | |
2390 | ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__); | |
2391 | return 1; /* handled */ | |
2392 | } | |
2393 | ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__); | |
2394 | return 1; /* handled */ | |
2395 | } | |
2396 | ||
2397 | static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) | |
2398 | { | |
2399 | /* | |
2400 | * Possible future enhancement: | |
2401 | * | |
2402 | * FBS+non-NCQ operation is not yet implemented. | |
2403 | * See related notes in mv_edma_cfg(). | |
2404 | * | |
2405 | * Device error during FBS+non-NCQ operation: | |
2406 | * | |
2407 | * We need to snapshot the shadow registers for each failed command. | |
2408 | * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). | |
2409 | */ | |
2410 | return 0; /* not handled */ | |
2411 | } | |
2412 | ||
2413 | static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) | |
2414 | { | |
2415 | struct mv_port_priv *pp = ap->private_data; | |
2416 | ||
2417 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) | |
2418 | return 0; /* EDMA was not active: not handled */ | |
2419 | if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) | |
2420 | return 0; /* FBS was not active: not handled */ | |
2421 | ||
2422 | if (!(edma_err_cause & EDMA_ERR_DEV)) | |
2423 | return 0; /* non DEV error: not handled */ | |
2424 | edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; | |
2425 | if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) | |
2426 | return 0; /* other problems: not handled */ | |
2427 | ||
2428 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { | |
2429 | /* | |
2430 | * EDMA should NOT have self-disabled for this case. | |
2431 | * If it did, then something is wrong elsewhere, | |
2432 | * and we cannot handle it here. | |
2433 | */ | |
2434 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { | |
2435 | ata_port_printk(ap, KERN_WARNING, | |
2436 | "%s: err_cause=0x%x pp_flags=0x%x\n", | |
2437 | __func__, edma_err_cause, pp->pp_flags); | |
2438 | return 0; /* not handled */ | |
2439 | } | |
2440 | return mv_handle_fbs_ncq_dev_err(ap); | |
2441 | } else { | |
2442 | /* | |
2443 | * EDMA should have self-disabled for this case. | |
2444 | * If it did not, then something is wrong elsewhere, | |
2445 | * and we cannot handle it here. | |
2446 | */ | |
2447 | if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { | |
2448 | ata_port_printk(ap, KERN_WARNING, | |
2449 | "%s: err_cause=0x%x pp_flags=0x%x\n", | |
2450 | __func__, edma_err_cause, pp->pp_flags); | |
2451 | return 0; /* not handled */ | |
2452 | } | |
2453 | return mv_handle_fbs_non_ncq_dev_err(ap); | |
2454 | } | |
2455 | return 0; /* not handled */ | |
2456 | } | |
2457 | ||
a9010329 | 2458 | static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) |
8f767f8a | 2459 | { |
8f767f8a | 2460 | struct ata_eh_info *ehi = &ap->link.eh_info; |
a9010329 | 2461 | char *when = "idle"; |
8f767f8a | 2462 | |
8f767f8a | 2463 | ata_ehi_clear_desc(ehi); |
a9010329 ML |
2464 | if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { |
2465 | when = "disabled"; | |
2466 | } else if (edma_was_enabled) { | |
2467 | when = "EDMA enabled"; | |
8f767f8a ML |
2468 | } else { |
2469 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
2470 | if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) | |
a9010329 | 2471 | when = "polling"; |
8f767f8a | 2472 | } |
a9010329 | 2473 | ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); |
8f767f8a ML |
2474 | ehi->err_mask |= AC_ERR_OTHER; |
2475 | ehi->action |= ATA_EH_RESET; | |
2476 | ata_port_freeze(ap); | |
2477 | } | |
2478 | ||
05b308e1 BR |
2479 | /** |
2480 | * mv_err_intr - Handle error interrupts on the port | |
2481 | * @ap: ATA channel to manipulate | |
2482 | * | |
8d07379d ML |
2483 | * Most cases require a full reset of the chip's state machine, |
2484 | * which also performs a COMRESET. | |
2485 | * Also, if the port disabled DMA, update our cached copy to match. | |
05b308e1 BR |
2486 | * |
2487 | * LOCKING: | |
2488 | * Inherited from caller. | |
2489 | */ | |
37b9046a | 2490 | static void mv_err_intr(struct ata_port *ap) |
31961943 BR |
2491 | { |
2492 | void __iomem *port_mmio = mv_ap_base(ap); | |
bdd4ddde | 2493 | u32 edma_err_cause, eh_freeze_mask, serr = 0; |
e4006077 | 2494 | u32 fis_cause = 0; |
bdd4ddde JG |
2495 | struct mv_port_priv *pp = ap->private_data; |
2496 | struct mv_host_priv *hpriv = ap->host->private_data; | |
bdd4ddde | 2497 | unsigned int action = 0, err_mask = 0; |
9af5c9c9 | 2498 | struct ata_eh_info *ehi = &ap->link.eh_info; |
37b9046a ML |
2499 | struct ata_queued_cmd *qc; |
2500 | int abort = 0; | |
20f733e7 | 2501 | |
8d07379d | 2502 | /* |
37b9046a | 2503 | * Read and clear the SError and err_cause bits. |
e4006077 ML |
2504 | * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear |
2505 | * the FIS_IRQ_CAUSE register before clearing edma_err_cause. | |
8d07379d | 2506 | */ |
37b9046a ML |
2507 | sata_scr_read(&ap->link, SCR_ERROR, &serr); |
2508 | sata_scr_write_flush(&ap->link, SCR_ERROR, serr); | |
2509 | ||
bdd4ddde | 2510 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
e4006077 ML |
2511 | if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { |
2512 | fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS); | |
2513 | writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS); | |
2514 | } | |
8d07379d | 2515 | writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); |
bdd4ddde | 2516 | |
4c299ca3 ML |
2517 | if (edma_err_cause & EDMA_ERR_DEV) { |
2518 | /* | |
2519 | * Device errors during FIS-based switching operation | |
2520 | * require special handling. | |
2521 | */ | |
2522 | if (mv_handle_dev_err(ap, edma_err_cause)) | |
2523 | return; | |
2524 | } | |
2525 | ||
37b9046a ML |
2526 | qc = mv_get_active_qc(ap); |
2527 | ata_ehi_clear_desc(ehi); | |
2528 | ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", | |
2529 | edma_err_cause, pp->pp_flags); | |
e4006077 | 2530 | |
c443c500 | 2531 | if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { |
e4006077 | 2532 | ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); |
c443c500 ML |
2533 | if (fis_cause & SATA_FIS_IRQ_AN) { |
2534 | u32 ec = edma_err_cause & | |
2535 | ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); | |
2536 | sata_async_notification(ap); | |
2537 | if (!ec) | |
2538 | return; /* Just an AN; no need for the nukes */ | |
2539 | ata_ehi_push_desc(ehi, "SDB notify"); | |
2540 | } | |
2541 | } | |
bdd4ddde | 2542 | /* |
352fab70 | 2543 | * All generations share these EDMA error cause bits: |
bdd4ddde | 2544 | */ |
37b9046a | 2545 | if (edma_err_cause & EDMA_ERR_DEV) { |
bdd4ddde | 2546 | err_mask |= AC_ERR_DEV; |
37b9046a ML |
2547 | action |= ATA_EH_RESET; |
2548 | ata_ehi_push_desc(ehi, "dev error"); | |
2549 | } | |
bdd4ddde | 2550 | if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
6c1153e0 | 2551 | EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | |
bdd4ddde JG |
2552 | EDMA_ERR_INTRL_PAR)) { |
2553 | err_mask |= AC_ERR_ATA_BUS; | |
cf480626 | 2554 | action |= ATA_EH_RESET; |
b64bbc39 | 2555 | ata_ehi_push_desc(ehi, "parity error"); |
bdd4ddde JG |
2556 | } |
2557 | if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { | |
2558 | ata_ehi_hotplugged(ehi); | |
2559 | ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? | |
b64bbc39 | 2560 | "dev disconnect" : "dev connect"); |
cf480626 | 2561 | action |= ATA_EH_RESET; |
bdd4ddde JG |
2562 | } |
2563 | ||
352fab70 ML |
2564 | /* |
2565 | * Gen-I has a different SELF_DIS bit, | |
2566 | * different FREEZE bits, and no SERR bit: | |
2567 | */ | |
ee9ccdf7 | 2568 | if (IS_GEN_I(hpriv)) { |
bdd4ddde | 2569 | eh_freeze_mask = EDMA_EH_FREEZE_5; |
bdd4ddde | 2570 | if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { |
bdd4ddde | 2571 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
b64bbc39 | 2572 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
bdd4ddde JG |
2573 | } |
2574 | } else { | |
2575 | eh_freeze_mask = EDMA_EH_FREEZE; | |
bdd4ddde | 2576 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { |
bdd4ddde | 2577 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
b64bbc39 | 2578 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
bdd4ddde | 2579 | } |
bdd4ddde | 2580 | if (edma_err_cause & EDMA_ERR_SERR) { |
8d07379d ML |
2581 | ata_ehi_push_desc(ehi, "SError=%08x", serr); |
2582 | err_mask |= AC_ERR_ATA_BUS; | |
cf480626 | 2583 | action |= ATA_EH_RESET; |
bdd4ddde | 2584 | } |
afb0edd9 | 2585 | } |
20f733e7 | 2586 | |
bdd4ddde JG |
2587 | if (!err_mask) { |
2588 | err_mask = AC_ERR_OTHER; | |
cf480626 | 2589 | action |= ATA_EH_RESET; |
bdd4ddde JG |
2590 | } |
2591 | ||
2592 | ehi->serror |= serr; | |
2593 | ehi->action |= action; | |
2594 | ||
2595 | if (qc) | |
2596 | qc->err_mask |= err_mask; | |
2597 | else | |
2598 | ehi->err_mask |= err_mask; | |
2599 | ||
37b9046a ML |
2600 | if (err_mask == AC_ERR_DEV) { |
2601 | /* | |
2602 | * Cannot do ata_port_freeze() here, | |
2603 | * because it would kill PIO access, | |
2604 | * which is needed for further diagnosis. | |
2605 | */ | |
2606 | mv_eh_freeze(ap); | |
2607 | abort = 1; | |
2608 | } else if (edma_err_cause & eh_freeze_mask) { | |
2609 | /* | |
2610 | * Note to self: ata_port_freeze() calls ata_port_abort() | |
2611 | */ | |
bdd4ddde | 2612 | ata_port_freeze(ap); |
37b9046a ML |
2613 | } else { |
2614 | abort = 1; | |
2615 | } | |
2616 | ||
2617 | if (abort) { | |
2618 | if (qc) | |
2619 | ata_link_abort(qc->dev->link); | |
2620 | else | |
2621 | ata_port_abort(ap); | |
2622 | } | |
bdd4ddde JG |
2623 | } |
2624 | ||
fcfb1f77 ML |
2625 | static void mv_process_crpb_response(struct ata_port *ap, |
2626 | struct mv_crpb *response, unsigned int tag, int ncq_enabled) | |
2627 | { | |
2628 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag); | |
2629 | ||
2630 | if (qc) { | |
2631 | u8 ata_status; | |
2632 | u16 edma_status = le16_to_cpu(response->flags); | |
2633 | /* | |
2634 | * edma_status from a response queue entry: | |
2635 | * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only). | |
2636 | * MSB is saved ATA status from command completion. | |
2637 | */ | |
2638 | if (!ncq_enabled) { | |
2639 | u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; | |
2640 | if (err_cause) { | |
2641 | /* | |
2642 | * Error will be seen/handled by mv_err_intr(). | |
2643 | * So do nothing at all here. | |
2644 | */ | |
2645 | return; | |
2646 | } | |
2647 | } | |
2648 | ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; | |
37b9046a ML |
2649 | if (!ac_err_mask(ata_status)) |
2650 | ata_qc_complete(qc); | |
2651 | /* else: leave it for mv_err_intr() */ | |
fcfb1f77 ML |
2652 | } else { |
2653 | ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n", | |
2654 | __func__, tag); | |
2655 | } | |
2656 | } | |
2657 | ||
2658 | static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) | |
bdd4ddde JG |
2659 | { |
2660 | void __iomem *port_mmio = mv_ap_base(ap); | |
2661 | struct mv_host_priv *hpriv = ap->host->private_data; | |
fcfb1f77 | 2662 | u32 in_index; |
bdd4ddde | 2663 | bool work_done = false; |
fcfb1f77 | 2664 | int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); |
bdd4ddde | 2665 | |
fcfb1f77 | 2666 | /* Get the hardware queue position index */ |
bdd4ddde JG |
2667 | in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) |
2668 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; | |
2669 | ||
fcfb1f77 ML |
2670 | /* Process new responses from since the last time we looked */ |
2671 | while (in_index != pp->resp_idx) { | |
6c1153e0 | 2672 | unsigned int tag; |
fcfb1f77 | 2673 | struct mv_crpb *response = &pp->crpb[pp->resp_idx]; |
bdd4ddde | 2674 | |
fcfb1f77 | 2675 | pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; |
bdd4ddde | 2676 | |
fcfb1f77 ML |
2677 | if (IS_GEN_I(hpriv)) { |
2678 | /* 50xx: no NCQ, only one command active at a time */ | |
9af5c9c9 | 2679 | tag = ap->link.active_tag; |
fcfb1f77 ML |
2680 | } else { |
2681 | /* Gen II/IIE: get command tag from CRPB entry */ | |
2682 | tag = le16_to_cpu(response->id) & 0x1f; | |
bdd4ddde | 2683 | } |
fcfb1f77 | 2684 | mv_process_crpb_response(ap, response, tag, ncq_enabled); |
bdd4ddde | 2685 | work_done = true; |
bdd4ddde JG |
2686 | } |
2687 | ||
352fab70 | 2688 | /* Update the software queue position index in hardware */ |
bdd4ddde JG |
2689 | if (work_done) |
2690 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | | |
fcfb1f77 | 2691 | (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), |
bdd4ddde | 2692 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
20f733e7 BR |
2693 | } |
2694 | ||
a9010329 ML |
2695 | static void mv_port_intr(struct ata_port *ap, u32 port_cause) |
2696 | { | |
2697 | struct mv_port_priv *pp; | |
2698 | int edma_was_enabled; | |
2699 | ||
2700 | if (!ap || (ap->flags & ATA_FLAG_DISABLED)) { | |
2701 | mv_unexpected_intr(ap, 0); | |
2702 | return; | |
2703 | } | |
2704 | /* | |
2705 | * Grab a snapshot of the EDMA_EN flag setting, | |
2706 | * so that we have a consistent view for this port, | |
2707 | * even if something we call of our routines changes it. | |
2708 | */ | |
2709 | pp = ap->private_data; | |
2710 | edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); | |
2711 | /* | |
2712 | * Process completed CRPB response(s) before other events. | |
2713 | */ | |
2714 | if (edma_was_enabled && (port_cause & DONE_IRQ)) { | |
2715 | mv_process_crpb_entries(ap, pp); | |
4c299ca3 ML |
2716 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) |
2717 | mv_handle_fbs_ncq_dev_err(ap); | |
a9010329 ML |
2718 | } |
2719 | /* | |
2720 | * Handle chip-reported errors, or continue on to handle PIO. | |
2721 | */ | |
2722 | if (unlikely(port_cause & ERR_IRQ)) { | |
2723 | mv_err_intr(ap); | |
2724 | } else if (!edma_was_enabled) { | |
2725 | struct ata_queued_cmd *qc = mv_get_active_qc(ap); | |
2726 | if (qc) | |
2727 | ata_sff_host_intr(ap, qc); | |
2728 | else | |
2729 | mv_unexpected_intr(ap, edma_was_enabled); | |
2730 | } | |
2731 | } | |
2732 | ||
05b308e1 BR |
2733 | /** |
2734 | * mv_host_intr - Handle all interrupts on the given host controller | |
cca3974e | 2735 | * @host: host specific structure |
7368f919 | 2736 | * @main_irq_cause: Main interrupt cause register for the chip. |
05b308e1 BR |
2737 | * |
2738 | * LOCKING: | |
2739 | * Inherited from caller. | |
2740 | */ | |
7368f919 | 2741 | static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) |
20f733e7 | 2742 | { |
f351b2d6 | 2743 | struct mv_host_priv *hpriv = host->private_data; |
eabd5eb1 | 2744 | void __iomem *mmio = hpriv->base, *hc_mmio; |
a3718c1f | 2745 | unsigned int handled = 0, port; |
20f733e7 | 2746 | |
2b748a0a ML |
2747 | /* If asserted, clear the "all ports" IRQ coalescing bit */ |
2748 | if (main_irq_cause & ALL_PORTS_COAL_DONE) | |
2749 | writel(~ALL_PORTS_COAL_IRQ, mmio + MV_IRQ_COAL_CAUSE); | |
2750 | ||
a3718c1f | 2751 | for (port = 0; port < hpriv->n_ports; port++) { |
cca3974e | 2752 | struct ata_port *ap = host->ports[port]; |
eabd5eb1 ML |
2753 | unsigned int p, shift, hardport, port_cause; |
2754 | ||
a3718c1f | 2755 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); |
a3718c1f | 2756 | /* |
eabd5eb1 ML |
2757 | * Each hc within the host has its own hc_irq_cause register, |
2758 | * where the interrupting ports bits get ack'd. | |
a3718c1f | 2759 | */ |
eabd5eb1 ML |
2760 | if (hardport == 0) { /* first port on this hc ? */ |
2761 | u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; | |
2762 | u32 port_mask, ack_irqs; | |
2763 | /* | |
2764 | * Skip this entire hc if nothing pending for any ports | |
2765 | */ | |
2766 | if (!hc_cause) { | |
2767 | port += MV_PORTS_PER_HC - 1; | |
2768 | continue; | |
2769 | } | |
2770 | /* | |
2771 | * We don't need/want to read the hc_irq_cause register, | |
2772 | * because doing so hurts performance, and | |
2773 | * main_irq_cause already gives us everything we need. | |
2774 | * | |
2775 | * But we do have to *write* to the hc_irq_cause to ack | |
2776 | * the ports that we are handling this time through. | |
2777 | * | |
2778 | * This requires that we create a bitmap for those | |
2779 | * ports which interrupted us, and use that bitmap | |
2780 | * to ack (only) those ports via hc_irq_cause. | |
2781 | */ | |
2782 | ack_irqs = 0; | |
2b748a0a ML |
2783 | if (hc_cause & PORTS_0_3_COAL_DONE) |
2784 | ack_irqs = HC_COAL_IRQ; | |
eabd5eb1 ML |
2785 | for (p = 0; p < MV_PORTS_PER_HC; ++p) { |
2786 | if ((port + p) >= hpriv->n_ports) | |
2787 | break; | |
2788 | port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); | |
2789 | if (hc_cause & port_mask) | |
2790 | ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; | |
2791 | } | |
a3718c1f | 2792 | hc_mmio = mv_hc_base_from_port(mmio, port); |
eabd5eb1 | 2793 | writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS); |
a3718c1f ML |
2794 | handled = 1; |
2795 | } | |
8f767f8a | 2796 | /* |
a9010329 | 2797 | * Handle interrupts signalled for this port: |
8f767f8a | 2798 | */ |
a9010329 ML |
2799 | port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); |
2800 | if (port_cause) | |
2801 | mv_port_intr(ap, port_cause); | |
20f733e7 | 2802 | } |
a3718c1f | 2803 | return handled; |
20f733e7 BR |
2804 | } |
2805 | ||
a3718c1f | 2806 | static int mv_pci_error(struct ata_host *host, void __iomem *mmio) |
bdd4ddde | 2807 | { |
02a121da | 2808 | struct mv_host_priv *hpriv = host->private_data; |
bdd4ddde JG |
2809 | struct ata_port *ap; |
2810 | struct ata_queued_cmd *qc; | |
2811 | struct ata_eh_info *ehi; | |
2812 | unsigned int i, err_mask, printed = 0; | |
2813 | u32 err_cause; | |
2814 | ||
02a121da | 2815 | err_cause = readl(mmio + hpriv->irq_cause_ofs); |
bdd4ddde JG |
2816 | |
2817 | dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", | |
2818 | err_cause); | |
2819 | ||
2820 | DPRINTK("All regs @ PCI error\n"); | |
2821 | mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev)); | |
2822 | ||
02a121da | 2823 | writelfl(0, mmio + hpriv->irq_cause_ofs); |
bdd4ddde JG |
2824 | |
2825 | for (i = 0; i < host->n_ports; i++) { | |
2826 | ap = host->ports[i]; | |
936fd732 | 2827 | if (!ata_link_offline(&ap->link)) { |
9af5c9c9 | 2828 | ehi = &ap->link.eh_info; |
bdd4ddde JG |
2829 | ata_ehi_clear_desc(ehi); |
2830 | if (!printed++) | |
2831 | ata_ehi_push_desc(ehi, | |
2832 | "PCI err cause 0x%08x", err_cause); | |
2833 | err_mask = AC_ERR_HOST_BUS; | |
cf480626 | 2834 | ehi->action = ATA_EH_RESET; |
9af5c9c9 | 2835 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
bdd4ddde JG |
2836 | if (qc) |
2837 | qc->err_mask |= err_mask; | |
2838 | else | |
2839 | ehi->err_mask |= err_mask; | |
2840 | ||
2841 | ata_port_freeze(ap); | |
2842 | } | |
2843 | } | |
a3718c1f | 2844 | return 1; /* handled */ |
bdd4ddde JG |
2845 | } |
2846 | ||
05b308e1 | 2847 | /** |
c5d3e45a | 2848 | * mv_interrupt - Main interrupt event handler |
05b308e1 BR |
2849 | * @irq: unused |
2850 | * @dev_instance: private data; in this case the host structure | |
05b308e1 BR |
2851 | * |
2852 | * Read the read only register to determine if any host | |
2853 | * controllers have pending interrupts. If so, call lower level | |
2854 | * routine to handle. Also check for PCI errors which are only | |
2855 | * reported here. | |
2856 | * | |
8b260248 | 2857 | * LOCKING: |
cca3974e | 2858 | * This routine holds the host lock while processing pending |
05b308e1 BR |
2859 | * interrupts. |
2860 | */ | |
7d12e780 | 2861 | static irqreturn_t mv_interrupt(int irq, void *dev_instance) |
20f733e7 | 2862 | { |
cca3974e | 2863 | struct ata_host *host = dev_instance; |
f351b2d6 | 2864 | struct mv_host_priv *hpriv = host->private_data; |
a3718c1f | 2865 | unsigned int handled = 0; |
6d3c30ef | 2866 | int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; |
96e2c487 | 2867 | u32 main_irq_cause, pending_irqs; |
20f733e7 | 2868 | |
646a4da5 | 2869 | spin_lock(&host->lock); |
6d3c30ef ML |
2870 | |
2871 | /* for MSI: block new interrupts while in here */ | |
2872 | if (using_msi) | |
2b748a0a | 2873 | mv_write_main_irq_mask(0, hpriv); |
6d3c30ef | 2874 | |
7368f919 | 2875 | main_irq_cause = readl(hpriv->main_irq_cause_addr); |
96e2c487 | 2876 | pending_irqs = main_irq_cause & hpriv->main_irq_mask; |
352fab70 ML |
2877 | /* |
2878 | * Deal with cases where we either have nothing pending, or have read | |
2879 | * a bogus register value which can indicate HW removal or PCI fault. | |
20f733e7 | 2880 | */ |
a44253d2 | 2881 | if (pending_irqs && main_irq_cause != 0xffffffffU) { |
1f398472 | 2882 | if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) |
a3718c1f ML |
2883 | handled = mv_pci_error(host, hpriv->base); |
2884 | else | |
a44253d2 | 2885 | handled = mv_host_intr(host, pending_irqs); |
bdd4ddde | 2886 | } |
6d3c30ef ML |
2887 | |
2888 | /* for MSI: unmask; interrupt cause bits will retrigger now */ | |
2889 | if (using_msi) | |
2b748a0a | 2890 | mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); |
6d3c30ef | 2891 | |
9d51af7b ML |
2892 | spin_unlock(&host->lock); |
2893 | ||
20f733e7 BR |
2894 | return IRQ_RETVAL(handled); |
2895 | } | |
2896 | ||
c9d39130 JG |
2897 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) |
2898 | { | |
2899 | unsigned int ofs; | |
2900 | ||
2901 | switch (sc_reg_in) { | |
2902 | case SCR_STATUS: | |
2903 | case SCR_ERROR: | |
2904 | case SCR_CONTROL: | |
2905 | ofs = sc_reg_in * sizeof(u32); | |
2906 | break; | |
2907 | default: | |
2908 | ofs = 0xffffffffU; | |
2909 | break; | |
2910 | } | |
2911 | return ofs; | |
2912 | } | |
2913 | ||
82ef04fb | 2914 | static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) |
c9d39130 | 2915 | { |
82ef04fb | 2916 | struct mv_host_priv *hpriv = link->ap->host->private_data; |
f351b2d6 | 2917 | void __iomem *mmio = hpriv->base; |
82ef04fb | 2918 | void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); |
c9d39130 JG |
2919 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
2920 | ||
da3dbb17 TH |
2921 | if (ofs != 0xffffffffU) { |
2922 | *val = readl(addr + ofs); | |
2923 | return 0; | |
2924 | } else | |
2925 | return -EINVAL; | |
c9d39130 JG |
2926 | } |
2927 | ||
82ef04fb | 2928 | static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) |
c9d39130 | 2929 | { |
82ef04fb | 2930 | struct mv_host_priv *hpriv = link->ap->host->private_data; |
f351b2d6 | 2931 | void __iomem *mmio = hpriv->base; |
82ef04fb | 2932 | void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); |
c9d39130 JG |
2933 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
2934 | ||
da3dbb17 | 2935 | if (ofs != 0xffffffffU) { |
0d5ff566 | 2936 | writelfl(val, addr + ofs); |
da3dbb17 TH |
2937 | return 0; |
2938 | } else | |
2939 | return -EINVAL; | |
c9d39130 JG |
2940 | } |
2941 | ||
7bb3c529 | 2942 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) |
522479fb | 2943 | { |
7bb3c529 | 2944 | struct pci_dev *pdev = to_pci_dev(host->dev); |
522479fb JG |
2945 | int early_5080; |
2946 | ||
44c10138 | 2947 | early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); |
522479fb JG |
2948 | |
2949 | if (!early_5080) { | |
2950 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
2951 | tmp |= (1 << 0); | |
2952 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
2953 | } | |
2954 | ||
7bb3c529 | 2955 | mv_reset_pci_bus(host, mmio); |
522479fb JG |
2956 | } |
2957 | ||
2958 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
2959 | { | |
8e7decdb | 2960 | writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS); |
522479fb JG |
2961 | } |
2962 | ||
47c2b677 | 2963 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
2964 | void __iomem *mmio) |
2965 | { | |
c9d39130 JG |
2966 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
2967 | u32 tmp; | |
2968 | ||
2969 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
2970 | ||
2971 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ | |
2972 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ | |
ba3fe8fb JG |
2973 | } |
2974 | ||
47c2b677 | 2975 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 2976 | { |
522479fb JG |
2977 | u32 tmp; |
2978 | ||
8e7decdb | 2979 | writel(0, mmio + MV_GPIO_PORT_CTL_OFS); |
522479fb JG |
2980 | |
2981 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ | |
2982 | ||
2983 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
2984 | tmp |= ~(1 << 0); | |
2985 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
ba3fe8fb JG |
2986 | } |
2987 | ||
2a47ce06 JG |
2988 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
2989 | unsigned int port) | |
bca1c4eb | 2990 | { |
c9d39130 JG |
2991 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
2992 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); | |
2993 | u32 tmp; | |
2994 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); | |
2995 | ||
2996 | if (fix_apm_sq) { | |
8e7decdb | 2997 | tmp = readl(phy_mmio + MV5_LTMODE_OFS); |
c9d39130 | 2998 | tmp |= (1 << 19); |
8e7decdb | 2999 | writel(tmp, phy_mmio + MV5_LTMODE_OFS); |
c9d39130 | 3000 | |
8e7decdb | 3001 | tmp = readl(phy_mmio + MV5_PHY_CTL_OFS); |
c9d39130 JG |
3002 | tmp &= ~0x3; |
3003 | tmp |= 0x1; | |
8e7decdb | 3004 | writel(tmp, phy_mmio + MV5_PHY_CTL_OFS); |
c9d39130 JG |
3005 | } |
3006 | ||
3007 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
3008 | tmp &= ~mask; | |
3009 | tmp |= hpriv->signal[port].pre; | |
3010 | tmp |= hpriv->signal[port].amps; | |
3011 | writel(tmp, phy_mmio + MV5_PHY_MODE); | |
bca1c4eb JG |
3012 | } |
3013 | ||
c9d39130 JG |
3014 | |
3015 | #undef ZERO | |
3016 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
3017 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3018 | unsigned int port) | |
3019 | { | |
3020 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3021 | ||
e12bef50 | 3022 | mv_reset_channel(hpriv, mmio, port); |
c9d39130 JG |
3023 | |
3024 | ZERO(0x028); /* command */ | |
3025 | writel(0x11f, port_mmio + EDMA_CFG_OFS); | |
3026 | ZERO(0x004); /* timer */ | |
3027 | ZERO(0x008); /* irq err cause */ | |
3028 | ZERO(0x00c); /* irq err mask */ | |
3029 | ZERO(0x010); /* rq bah */ | |
3030 | ZERO(0x014); /* rq inp */ | |
3031 | ZERO(0x018); /* rq outp */ | |
3032 | ZERO(0x01c); /* respq bah */ | |
3033 | ZERO(0x024); /* respq outp */ | |
3034 | ZERO(0x020); /* respq inp */ | |
3035 | ZERO(0x02c); /* test control */ | |
8e7decdb | 3036 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); |
c9d39130 JG |
3037 | } |
3038 | #undef ZERO | |
3039 | ||
3040 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
3041 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3042 | unsigned int hc) | |
47c2b677 | 3043 | { |
c9d39130 JG |
3044 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
3045 | u32 tmp; | |
3046 | ||
3047 | ZERO(0x00c); | |
3048 | ZERO(0x010); | |
3049 | ZERO(0x014); | |
3050 | ZERO(0x018); | |
3051 | ||
3052 | tmp = readl(hc_mmio + 0x20); | |
3053 | tmp &= 0x1c1c1c1c; | |
3054 | tmp |= 0x03030303; | |
3055 | writel(tmp, hc_mmio + 0x20); | |
3056 | } | |
3057 | #undef ZERO | |
3058 | ||
3059 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3060 | unsigned int n_hc) | |
3061 | { | |
3062 | unsigned int hc, port; | |
3063 | ||
3064 | for (hc = 0; hc < n_hc; hc++) { | |
3065 | for (port = 0; port < MV_PORTS_PER_HC; port++) | |
3066 | mv5_reset_hc_port(hpriv, mmio, | |
3067 | (hc * MV_PORTS_PER_HC) + port); | |
3068 | ||
3069 | mv5_reset_one_hc(hpriv, mmio, hc); | |
3070 | } | |
3071 | ||
3072 | return 0; | |
47c2b677 JG |
3073 | } |
3074 | ||
101ffae2 JG |
3075 | #undef ZERO |
3076 | #define ZERO(reg) writel(0, mmio + (reg)) | |
7bb3c529 | 3077 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) |
101ffae2 | 3078 | { |
02a121da | 3079 | struct mv_host_priv *hpriv = host->private_data; |
101ffae2 JG |
3080 | u32 tmp; |
3081 | ||
8e7decdb | 3082 | tmp = readl(mmio + MV_PCI_MODE_OFS); |
101ffae2 | 3083 | tmp &= 0xff00ffff; |
8e7decdb | 3084 | writel(tmp, mmio + MV_PCI_MODE_OFS); |
101ffae2 JG |
3085 | |
3086 | ZERO(MV_PCI_DISC_TIMER); | |
3087 | ZERO(MV_PCI_MSI_TRIGGER); | |
8e7decdb | 3088 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS); |
101ffae2 | 3089 | ZERO(MV_PCI_SERR_MASK); |
02a121da ML |
3090 | ZERO(hpriv->irq_cause_ofs); |
3091 | ZERO(hpriv->irq_mask_ofs); | |
101ffae2 JG |
3092 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
3093 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); | |
3094 | ZERO(MV_PCI_ERR_ATTRIBUTE); | |
3095 | ZERO(MV_PCI_ERR_COMMAND); | |
3096 | } | |
3097 | #undef ZERO | |
3098 | ||
3099 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
3100 | { | |
3101 | u32 tmp; | |
3102 | ||
3103 | mv5_reset_flash(hpriv, mmio); | |
3104 | ||
8e7decdb | 3105 | tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS); |
101ffae2 JG |
3106 | tmp &= 0x3; |
3107 | tmp |= (1 << 5) | (1 << 6); | |
8e7decdb | 3108 | writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS); |
101ffae2 JG |
3109 | } |
3110 | ||
3111 | /** | |
3112 | * mv6_reset_hc - Perform the 6xxx global soft reset | |
3113 | * @mmio: base address of the HBA | |
3114 | * | |
3115 | * This routine only applies to 6xxx parts. | |
3116 | * | |
3117 | * LOCKING: | |
3118 | * Inherited from caller. | |
3119 | */ | |
c9d39130 JG |
3120 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
3121 | unsigned int n_hc) | |
101ffae2 JG |
3122 | { |
3123 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; | |
3124 | int i, rc = 0; | |
3125 | u32 t; | |
3126 | ||
3127 | /* Following procedure defined in PCI "main command and status | |
3128 | * register" table. | |
3129 | */ | |
3130 | t = readl(reg); | |
3131 | writel(t | STOP_PCI_MASTER, reg); | |
3132 | ||
3133 | for (i = 0; i < 1000; i++) { | |
3134 | udelay(1); | |
3135 | t = readl(reg); | |
2dcb407e | 3136 | if (PCI_MASTER_EMPTY & t) |
101ffae2 | 3137 | break; |
101ffae2 JG |
3138 | } |
3139 | if (!(PCI_MASTER_EMPTY & t)) { | |
3140 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); | |
3141 | rc = 1; | |
3142 | goto done; | |
3143 | } | |
3144 | ||
3145 | /* set reset */ | |
3146 | i = 5; | |
3147 | do { | |
3148 | writel(t | GLOB_SFT_RST, reg); | |
3149 | t = readl(reg); | |
3150 | udelay(1); | |
3151 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); | |
3152 | ||
3153 | if (!(GLOB_SFT_RST & t)) { | |
3154 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); | |
3155 | rc = 1; | |
3156 | goto done; | |
3157 | } | |
3158 | ||
3159 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ | |
3160 | i = 5; | |
3161 | do { | |
3162 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); | |
3163 | t = readl(reg); | |
3164 | udelay(1); | |
3165 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); | |
3166 | ||
3167 | if (GLOB_SFT_RST & t) { | |
3168 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); | |
3169 | rc = 1; | |
3170 | } | |
3171 | done: | |
3172 | return rc; | |
3173 | } | |
3174 | ||
47c2b677 | 3175 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
3176 | void __iomem *mmio) |
3177 | { | |
3178 | void __iomem *port_mmio; | |
3179 | u32 tmp; | |
3180 | ||
8e7decdb | 3181 | tmp = readl(mmio + MV_RESET_CFG_OFS); |
ba3fe8fb | 3182 | if ((tmp & (1 << 0)) == 0) { |
47c2b677 | 3183 | hpriv->signal[idx].amps = 0x7 << 8; |
ba3fe8fb JG |
3184 | hpriv->signal[idx].pre = 0x1 << 5; |
3185 | return; | |
3186 | } | |
3187 | ||
3188 | port_mmio = mv_port_base(mmio, idx); | |
ba68460b | 3189 | tmp = readl(port_mmio + PHY_MODE2_OFS); |
ba3fe8fb JG |
3190 | |
3191 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
3192 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
3193 | } | |
3194 | ||
47c2b677 | 3195 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 3196 | { |
8e7decdb | 3197 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS); |
ba3fe8fb JG |
3198 | } |
3199 | ||
c9d39130 | 3200 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
2a47ce06 | 3201 | unsigned int port) |
bca1c4eb | 3202 | { |
c9d39130 JG |
3203 | void __iomem *port_mmio = mv_port_base(mmio, port); |
3204 | ||
bca1c4eb | 3205 | u32 hp_flags = hpriv->hp_flags; |
47c2b677 JG |
3206 | int fix_phy_mode2 = |
3207 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); | |
bca1c4eb | 3208 | int fix_phy_mode4 = |
47c2b677 | 3209 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
8c30a8b9 | 3210 | u32 m2, m3; |
47c2b677 JG |
3211 | |
3212 | if (fix_phy_mode2) { | |
ba68460b | 3213 | m2 = readl(port_mmio + PHY_MODE2_OFS); |
47c2b677 JG |
3214 | m2 &= ~(1 << 16); |
3215 | m2 |= (1 << 31); | |
ba68460b | 3216 | writel(m2, port_mmio + PHY_MODE2_OFS); |
47c2b677 JG |
3217 | |
3218 | udelay(200); | |
3219 | ||
ba68460b | 3220 | m2 = readl(port_mmio + PHY_MODE2_OFS); |
47c2b677 | 3221 | m2 &= ~((1 << 16) | (1 << 31)); |
ba68460b | 3222 | writel(m2, port_mmio + PHY_MODE2_OFS); |
47c2b677 JG |
3223 | |
3224 | udelay(200); | |
3225 | } | |
3226 | ||
8c30a8b9 | 3227 | /* |
ba68460b | 3228 | * Gen-II/IIe PHY_MODE3_OFS errata RM#2: |
8c30a8b9 ML |
3229 | * Achieves better receiver noise performance than the h/w default: |
3230 | */ | |
ba68460b | 3231 | m3 = readl(port_mmio + PHY_MODE3_OFS); |
8c30a8b9 | 3232 | m3 = (m3 & 0x1f) | (0x5555601 << 5); |
bca1c4eb | 3233 | |
0388a8c0 ML |
3234 | /* Guideline 88F5182 (GL# SATA-S11) */ |
3235 | if (IS_SOC(hpriv)) | |
3236 | m3 &= ~0x1c; | |
3237 | ||
bca1c4eb | 3238 | if (fix_phy_mode4) { |
ba68460b | 3239 | u32 m4 = readl(port_mmio + PHY_MODE4_OFS); |
ba069e37 ML |
3240 | /* |
3241 | * Enforce reserved-bit restrictions on GenIIe devices only. | |
3242 | * For earlier chipsets, force only the internal config field | |
3243 | * (workaround for errata FEr SATA#10 part 1). | |
3244 | */ | |
8c30a8b9 | 3245 | if (IS_GEN_IIE(hpriv)) |
ba069e37 ML |
3246 | m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; |
3247 | else | |
3248 | m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; | |
ba68460b | 3249 | writel(m4, port_mmio + PHY_MODE4_OFS); |
bca1c4eb | 3250 | } |
b406c7a6 ML |
3251 | /* |
3252 | * Workaround for 60x1-B2 errata SATA#13: | |
3253 | * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, | |
3254 | * so we must always rewrite PHY_MODE3 after PHY_MODE4. | |
ba68460b | 3255 | * Or ensure we use writelfl() when writing PHY_MODE4. |
b406c7a6 | 3256 | */ |
ba68460b | 3257 | writel(m3, port_mmio + PHY_MODE3_OFS); |
bca1c4eb JG |
3258 | |
3259 | /* Revert values of pre-emphasis and signal amps to the saved ones */ | |
ba68460b | 3260 | m2 = readl(port_mmio + PHY_MODE2_OFS); |
bca1c4eb JG |
3261 | |
3262 | m2 &= ~MV_M2_PREAMP_MASK; | |
2a47ce06 JG |
3263 | m2 |= hpriv->signal[port].amps; |
3264 | m2 |= hpriv->signal[port].pre; | |
47c2b677 | 3265 | m2 &= ~(1 << 16); |
bca1c4eb | 3266 | |
e4e7b892 JG |
3267 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
3268 | if (IS_GEN_IIE(hpriv)) { | |
3269 | m2 &= ~0xC30FF01F; | |
3270 | m2 |= 0x0000900F; | |
3271 | } | |
3272 | ||
ba68460b | 3273 | writel(m2, port_mmio + PHY_MODE2_OFS); |
bca1c4eb JG |
3274 | } |
3275 | ||
f351b2d6 SB |
3276 | /* TODO: use the generic LED interface to configure the SATA Presence */ |
3277 | /* & Acitivy LEDs on the board */ | |
3278 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, | |
3279 | void __iomem *mmio) | |
3280 | { | |
3281 | return; | |
3282 | } | |
3283 | ||
3284 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, | |
3285 | void __iomem *mmio) | |
3286 | { | |
3287 | void __iomem *port_mmio; | |
3288 | u32 tmp; | |
3289 | ||
3290 | port_mmio = mv_port_base(mmio, idx); | |
ba68460b | 3291 | tmp = readl(port_mmio + PHY_MODE2_OFS); |
f351b2d6 SB |
3292 | |
3293 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
3294 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
3295 | } | |
3296 | ||
3297 | #undef ZERO | |
3298 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
3299 | static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, | |
3300 | void __iomem *mmio, unsigned int port) | |
3301 | { | |
3302 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3303 | ||
e12bef50 | 3304 | mv_reset_channel(hpriv, mmio, port); |
f351b2d6 SB |
3305 | |
3306 | ZERO(0x028); /* command */ | |
3307 | writel(0x101f, port_mmio + EDMA_CFG_OFS); | |
3308 | ZERO(0x004); /* timer */ | |
3309 | ZERO(0x008); /* irq err cause */ | |
3310 | ZERO(0x00c); /* irq err mask */ | |
3311 | ZERO(0x010); /* rq bah */ | |
3312 | ZERO(0x014); /* rq inp */ | |
3313 | ZERO(0x018); /* rq outp */ | |
3314 | ZERO(0x01c); /* respq bah */ | |
3315 | ZERO(0x024); /* respq outp */ | |
3316 | ZERO(0x020); /* respq inp */ | |
3317 | ZERO(0x02c); /* test control */ | |
8e7decdb | 3318 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS); |
f351b2d6 SB |
3319 | } |
3320 | ||
3321 | #undef ZERO | |
3322 | ||
3323 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
3324 | static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, | |
3325 | void __iomem *mmio) | |
3326 | { | |
3327 | void __iomem *hc_mmio = mv_hc_base(mmio, 0); | |
3328 | ||
3329 | ZERO(0x00c); | |
3330 | ZERO(0x010); | |
3331 | ZERO(0x014); | |
3332 | ||
3333 | } | |
3334 | ||
3335 | #undef ZERO | |
3336 | ||
3337 | static int mv_soc_reset_hc(struct mv_host_priv *hpriv, | |
3338 | void __iomem *mmio, unsigned int n_hc) | |
3339 | { | |
3340 | unsigned int port; | |
3341 | ||
3342 | for (port = 0; port < hpriv->n_ports; port++) | |
3343 | mv_soc_reset_hc_port(hpriv, mmio, port); | |
3344 | ||
3345 | mv_soc_reset_one_hc(hpriv, mmio); | |
3346 | ||
3347 | return 0; | |
3348 | } | |
3349 | ||
3350 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, | |
3351 | void __iomem *mmio) | |
3352 | { | |
3353 | return; | |
3354 | } | |
3355 | ||
3356 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) | |
3357 | { | |
3358 | return; | |
3359 | } | |
3360 | ||
8e7decdb | 3361 | static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) |
b67a1064 | 3362 | { |
8e7decdb | 3363 | u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS); |
b67a1064 | 3364 | |
8e7decdb | 3365 | ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ |
b67a1064 | 3366 | if (want_gen2i) |
8e7decdb ML |
3367 | ifcfg |= (1 << 7); /* enable gen2i speed */ |
3368 | writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS); | |
b67a1064 ML |
3369 | } |
3370 | ||
e12bef50 | 3371 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
c9d39130 JG |
3372 | unsigned int port_no) |
3373 | { | |
3374 | void __iomem *port_mmio = mv_port_base(mmio, port_no); | |
3375 | ||
8e7decdb ML |
3376 | /* |
3377 | * The datasheet warns against setting EDMA_RESET when EDMA is active | |
3378 | * (but doesn't say what the problem might be). So we first try | |
3379 | * to disable the EDMA engine before doing the EDMA_RESET operation. | |
3380 | */ | |
0d8be5cb | 3381 | mv_stop_edma_engine(port_mmio); |
8e7decdb | 3382 | writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); |
c9d39130 | 3383 | |
b67a1064 | 3384 | if (!IS_GEN_I(hpriv)) { |
8e7decdb ML |
3385 | /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ |
3386 | mv_setup_ifcfg(port_mmio, 1); | |
c9d39130 | 3387 | } |
b67a1064 | 3388 | /* |
8e7decdb | 3389 | * Strobing EDMA_RESET here causes a hard reset of the SATA transport, |
b67a1064 ML |
3390 | * link, and physical layers. It resets all SATA interface registers |
3391 | * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev. | |
c9d39130 | 3392 | */ |
8e7decdb | 3393 | writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS); |
b67a1064 | 3394 | udelay(25); /* allow reset propagation */ |
c9d39130 JG |
3395 | writelfl(0, port_mmio + EDMA_CMD_OFS); |
3396 | ||
3397 | hpriv->ops->phy_errata(hpriv, mmio, port_no); | |
3398 | ||
ee9ccdf7 | 3399 | if (IS_GEN_I(hpriv)) |
c9d39130 JG |
3400 | mdelay(1); |
3401 | } | |
3402 | ||
e49856d8 | 3403 | static void mv_pmp_select(struct ata_port *ap, int pmp) |
20f733e7 | 3404 | { |
e49856d8 ML |
3405 | if (sata_pmp_supported(ap)) { |
3406 | void __iomem *port_mmio = mv_ap_base(ap); | |
3407 | u32 reg = readl(port_mmio + SATA_IFCTL_OFS); | |
3408 | int old = reg & 0xf; | |
22374677 | 3409 | |
e49856d8 ML |
3410 | if (old != pmp) { |
3411 | reg = (reg & ~0xf) | pmp; | |
3412 | writelfl(reg, port_mmio + SATA_IFCTL_OFS); | |
3413 | } | |
22374677 | 3414 | } |
20f733e7 BR |
3415 | } |
3416 | ||
e49856d8 ML |
3417 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, |
3418 | unsigned long deadline) | |
22374677 | 3419 | { |
e49856d8 ML |
3420 | mv_pmp_select(link->ap, sata_srst_pmp(link)); |
3421 | return sata_std_hardreset(link, class, deadline); | |
3422 | } | |
bdd4ddde | 3423 | |
e49856d8 ML |
3424 | static int mv_softreset(struct ata_link *link, unsigned int *class, |
3425 | unsigned long deadline) | |
3426 | { | |
3427 | mv_pmp_select(link->ap, sata_srst_pmp(link)); | |
3428 | return ata_sff_softreset(link, class, deadline); | |
22374677 JG |
3429 | } |
3430 | ||
cc0680a5 | 3431 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
bdd4ddde | 3432 | unsigned long deadline) |
31961943 | 3433 | { |
cc0680a5 | 3434 | struct ata_port *ap = link->ap; |
bdd4ddde | 3435 | struct mv_host_priv *hpriv = ap->host->private_data; |
b562468c | 3436 | struct mv_port_priv *pp = ap->private_data; |
f351b2d6 | 3437 | void __iomem *mmio = hpriv->base; |
0d8be5cb ML |
3438 | int rc, attempts = 0, extra = 0; |
3439 | u32 sstatus; | |
3440 | bool online; | |
31961943 | 3441 | |
e12bef50 | 3442 | mv_reset_channel(hpriv, mmio, ap->port_no); |
b562468c | 3443 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
d16ab3f6 ML |
3444 | pp->pp_flags &= |
3445 | ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); | |
bdd4ddde | 3446 | |
0d8be5cb ML |
3447 | /* Workaround for errata FEr SATA#10 (part 2) */ |
3448 | do { | |
17c5aab5 ML |
3449 | const unsigned long *timing = |
3450 | sata_ehc_deb_timing(&link->eh_context); | |
bdd4ddde | 3451 | |
17c5aab5 ML |
3452 | rc = sata_link_hardreset(link, timing, deadline + extra, |
3453 | &online, NULL); | |
9dcffd99 | 3454 | rc = online ? -EAGAIN : rc; |
17c5aab5 | 3455 | if (rc) |
0d8be5cb | 3456 | return rc; |
0d8be5cb ML |
3457 | sata_scr_read(link, SCR_STATUS, &sstatus); |
3458 | if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { | |
3459 | /* Force 1.5gb/s link speed and try again */ | |
8e7decdb | 3460 | mv_setup_ifcfg(mv_ap_base(ap), 0); |
0d8be5cb ML |
3461 | if (time_after(jiffies + HZ, deadline)) |
3462 | extra = HZ; /* only extend it once, max */ | |
3463 | } | |
3464 | } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); | |
08da1759 | 3465 | mv_save_cached_regs(ap); |
66e57a2c | 3466 | mv_edma_cfg(ap, 0, 0); |
bdd4ddde | 3467 | |
17c5aab5 | 3468 | return rc; |
bdd4ddde JG |
3469 | } |
3470 | ||
bdd4ddde JG |
3471 | static void mv_eh_freeze(struct ata_port *ap) |
3472 | { | |
1cfd19ae | 3473 | mv_stop_edma(ap); |
c4de573b | 3474 | mv_enable_port_irqs(ap, 0); |
bdd4ddde JG |
3475 | } |
3476 | ||
3477 | static void mv_eh_thaw(struct ata_port *ap) | |
3478 | { | |
f351b2d6 | 3479 | struct mv_host_priv *hpriv = ap->host->private_data; |
c4de573b ML |
3480 | unsigned int port = ap->port_no; |
3481 | unsigned int hardport = mv_hardport_from_port(port); | |
1cfd19ae | 3482 | void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); |
bdd4ddde | 3483 | void __iomem *port_mmio = mv_ap_base(ap); |
c4de573b | 3484 | u32 hc_irq_cause; |
bdd4ddde | 3485 | |
bdd4ddde JG |
3486 | /* clear EDMA errors on this port */ |
3487 | writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
3488 | ||
3489 | /* clear pending irq events */ | |
cae6edc3 | 3490 | hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); |
1cfd19ae | 3491 | writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
bdd4ddde | 3492 | |
88e675e1 | 3493 | mv_enable_port_irqs(ap, ERR_IRQ); |
31961943 BR |
3494 | } |
3495 | ||
05b308e1 BR |
3496 | /** |
3497 | * mv_port_init - Perform some early initialization on a single port. | |
3498 | * @port: libata data structure storing shadow register addresses | |
3499 | * @port_mmio: base address of the port | |
3500 | * | |
3501 | * Initialize shadow register mmio addresses, clear outstanding | |
3502 | * interrupts on the port, and unmask interrupts for the future | |
3503 | * start of the port. | |
3504 | * | |
3505 | * LOCKING: | |
3506 | * Inherited from caller. | |
3507 | */ | |
31961943 | 3508 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
20f733e7 | 3509 | { |
0d5ff566 | 3510 | void __iomem *shd_base = port_mmio + SHD_BLK_OFS; |
31961943 BR |
3511 | unsigned serr_ofs; |
3512 | ||
8b260248 | 3513 | /* PIO related setup |
31961943 BR |
3514 | */ |
3515 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); | |
8b260248 | 3516 | port->error_addr = |
31961943 BR |
3517 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
3518 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); | |
3519 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); | |
3520 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); | |
3521 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); | |
3522 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); | |
8b260248 | 3523 | port->status_addr = |
31961943 BR |
3524 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
3525 | /* special case: control/altstatus doesn't have ATA_REG_ address */ | |
3526 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; | |
3527 | ||
3528 | /* unused: */ | |
8d9db2d2 | 3529 | port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL; |
20f733e7 | 3530 | |
31961943 BR |
3531 | /* Clear any currently outstanding port interrupt conditions */ |
3532 | serr_ofs = mv_scr_offset(SCR_ERROR); | |
3533 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); | |
3534 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
3535 | ||
646a4da5 ML |
3536 | /* unmask all non-transient EDMA error interrupts */ |
3537 | writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS); | |
20f733e7 | 3538 | |
8b260248 | 3539 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
31961943 BR |
3540 | readl(port_mmio + EDMA_CFG_OFS), |
3541 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), | |
3542 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); | |
20f733e7 BR |
3543 | } |
3544 | ||
616d4a98 ML |
3545 | static unsigned int mv_in_pcix_mode(struct ata_host *host) |
3546 | { | |
3547 | struct mv_host_priv *hpriv = host->private_data; | |
3548 | void __iomem *mmio = hpriv->base; | |
3549 | u32 reg; | |
3550 | ||
1f398472 | 3551 | if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) |
616d4a98 ML |
3552 | return 0; /* not PCI-X capable */ |
3553 | reg = readl(mmio + MV_PCI_MODE_OFS); | |
3554 | if ((reg & MV_PCI_MODE_MASK) == 0) | |
3555 | return 0; /* conventional PCI mode */ | |
3556 | return 1; /* chip is in PCI-X mode */ | |
3557 | } | |
3558 | ||
3559 | static int mv_pci_cut_through_okay(struct ata_host *host) | |
3560 | { | |
3561 | struct mv_host_priv *hpriv = host->private_data; | |
3562 | void __iomem *mmio = hpriv->base; | |
3563 | u32 reg; | |
3564 | ||
3565 | if (!mv_in_pcix_mode(host)) { | |
3566 | reg = readl(mmio + PCI_COMMAND_OFS); | |
3567 | if (reg & PCI_COMMAND_MRDTRIG) | |
3568 | return 0; /* not okay */ | |
3569 | } | |
3570 | return 1; /* okay */ | |
3571 | } | |
3572 | ||
65ad7fef ML |
3573 | static void mv_60x1b2_errata_pci7(struct ata_host *host) |
3574 | { | |
3575 | struct mv_host_priv *hpriv = host->private_data; | |
3576 | void __iomem *mmio = hpriv->base; | |
3577 | ||
3578 | /* workaround for 60x1-B2 errata PCI#7 */ | |
3579 | if (mv_in_pcix_mode(host)) { | |
3580 | u32 reg = readl(mmio + PCI_COMMAND_OFS); | |
3581 | writelfl(reg & ~PCI_COMMAND_MWRCOM, mmio + PCI_COMMAND_OFS); | |
3582 | } | |
3583 | } | |
3584 | ||
4447d351 | 3585 | static int mv_chip_id(struct ata_host *host, unsigned int board_idx) |
bca1c4eb | 3586 | { |
4447d351 TH |
3587 | struct pci_dev *pdev = to_pci_dev(host->dev); |
3588 | struct mv_host_priv *hpriv = host->private_data; | |
bca1c4eb JG |
3589 | u32 hp_flags = hpriv->hp_flags; |
3590 | ||
5796d1c4 | 3591 | switch (board_idx) { |
47c2b677 JG |
3592 | case chip_5080: |
3593 | hpriv->ops = &mv5xxx_ops; | |
ee9ccdf7 | 3594 | hp_flags |= MV_HP_GEN_I; |
47c2b677 | 3595 | |
44c10138 | 3596 | switch (pdev->revision) { |
47c2b677 JG |
3597 | case 0x1: |
3598 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
3599 | break; | |
3600 | case 0x3: | |
3601 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3602 | break; | |
3603 | default: | |
3604 | dev_printk(KERN_WARNING, &pdev->dev, | |
3605 | "Applying 50XXB2 workarounds to unknown rev\n"); | |
3606 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3607 | break; | |
3608 | } | |
3609 | break; | |
3610 | ||
bca1c4eb JG |
3611 | case chip_504x: |
3612 | case chip_508x: | |
47c2b677 | 3613 | hpriv->ops = &mv5xxx_ops; |
ee9ccdf7 | 3614 | hp_flags |= MV_HP_GEN_I; |
bca1c4eb | 3615 | |
44c10138 | 3616 | switch (pdev->revision) { |
47c2b677 JG |
3617 | case 0x0: |
3618 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
3619 | break; | |
3620 | case 0x3: | |
3621 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3622 | break; | |
3623 | default: | |
3624 | dev_printk(KERN_WARNING, &pdev->dev, | |
3625 | "Applying B2 workarounds to unknown rev\n"); | |
3626 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3627 | break; | |
bca1c4eb JG |
3628 | } |
3629 | break; | |
3630 | ||
3631 | case chip_604x: | |
3632 | case chip_608x: | |
47c2b677 | 3633 | hpriv->ops = &mv6xxx_ops; |
ee9ccdf7 | 3634 | hp_flags |= MV_HP_GEN_II; |
47c2b677 | 3635 | |
44c10138 | 3636 | switch (pdev->revision) { |
47c2b677 | 3637 | case 0x7: |
65ad7fef | 3638 | mv_60x1b2_errata_pci7(host); |
47c2b677 JG |
3639 | hp_flags |= MV_HP_ERRATA_60X1B2; |
3640 | break; | |
3641 | case 0x9: | |
3642 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
bca1c4eb JG |
3643 | break; |
3644 | default: | |
3645 | dev_printk(KERN_WARNING, &pdev->dev, | |
47c2b677 JG |
3646 | "Applying B2 workarounds to unknown rev\n"); |
3647 | hp_flags |= MV_HP_ERRATA_60X1B2; | |
bca1c4eb JG |
3648 | break; |
3649 | } | |
3650 | break; | |
3651 | ||
e4e7b892 | 3652 | case chip_7042: |
616d4a98 | 3653 | hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; |
306b30f7 ML |
3654 | if (pdev->vendor == PCI_VENDOR_ID_TTI && |
3655 | (pdev->device == 0x2300 || pdev->device == 0x2310)) | |
3656 | { | |
4e520033 ML |
3657 | /* |
3658 | * Highpoint RocketRAID PCIe 23xx series cards: | |
3659 | * | |
3660 | * Unconfigured drives are treated as "Legacy" | |
3661 | * by the BIOS, and it overwrites sector 8 with | |
3662 | * a "Lgcy" metadata block prior to Linux boot. | |
3663 | * | |
3664 | * Configured drives (RAID or JBOD) leave sector 8 | |
3665 | * alone, but instead overwrite a high numbered | |
3666 | * sector for the RAID metadata. This sector can | |
3667 | * be determined exactly, by truncating the physical | |
3668 | * drive capacity to a nice even GB value. | |
3669 | * | |
3670 | * RAID metadata is at: (dev->n_sectors & ~0xfffff) | |
3671 | * | |
3672 | * Warn the user, lest they think we're just buggy. | |
3673 | */ | |
3674 | printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID" | |
3675 | " BIOS CORRUPTS DATA on all attached drives," | |
3676 | " regardless of if/how they are configured." | |
3677 | " BEWARE!\n"); | |
3678 | printk(KERN_WARNING DRV_NAME ": For data safety, do not" | |
3679 | " use sectors 8-9 on \"Legacy\" drives," | |
3680 | " and avoid the final two gigabytes on" | |
3681 | " all RocketRAID BIOS initialized drives.\n"); | |
306b30f7 | 3682 | } |
8e7decdb | 3683 | /* drop through */ |
e4e7b892 JG |
3684 | case chip_6042: |
3685 | hpriv->ops = &mv6xxx_ops; | |
e4e7b892 | 3686 | hp_flags |= MV_HP_GEN_IIE; |
616d4a98 ML |
3687 | if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) |
3688 | hp_flags |= MV_HP_CUT_THROUGH; | |
e4e7b892 | 3689 | |
44c10138 | 3690 | switch (pdev->revision) { |
5cf73bfb | 3691 | case 0x2: /* Rev.B0: the first/only public release */ |
e4e7b892 JG |
3692 | hp_flags |= MV_HP_ERRATA_60X1C0; |
3693 | break; | |
3694 | default: | |
3695 | dev_printk(KERN_WARNING, &pdev->dev, | |
3696 | "Applying 60X1C0 workarounds to unknown rev\n"); | |
3697 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
3698 | break; | |
3699 | } | |
3700 | break; | |
f351b2d6 SB |
3701 | case chip_soc: |
3702 | hpriv->ops = &mv_soc_ops; | |
eb3a55a9 SB |
3703 | hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | |
3704 | MV_HP_ERRATA_60X1C0; | |
f351b2d6 | 3705 | break; |
e4e7b892 | 3706 | |
bca1c4eb | 3707 | default: |
f351b2d6 | 3708 | dev_printk(KERN_ERR, host->dev, |
5796d1c4 | 3709 | "BUG: invalid board index %u\n", board_idx); |
bca1c4eb JG |
3710 | return 1; |
3711 | } | |
3712 | ||
3713 | hpriv->hp_flags = hp_flags; | |
02a121da ML |
3714 | if (hp_flags & MV_HP_PCIE) { |
3715 | hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS; | |
3716 | hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS; | |
3717 | hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; | |
3718 | } else { | |
3719 | hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS; | |
3720 | hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS; | |
3721 | hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; | |
3722 | } | |
bca1c4eb JG |
3723 | |
3724 | return 0; | |
3725 | } | |
3726 | ||
05b308e1 | 3727 | /** |
47c2b677 | 3728 | * mv_init_host - Perform some early initialization of the host. |
4447d351 TH |
3729 | * @host: ATA host to initialize |
3730 | * @board_idx: controller index | |
05b308e1 BR |
3731 | * |
3732 | * If possible, do an early global reset of the host. Then do | |
3733 | * our port init and clear/unmask all/relevant host interrupts. | |
3734 | * | |
3735 | * LOCKING: | |
3736 | * Inherited from caller. | |
3737 | */ | |
4447d351 | 3738 | static int mv_init_host(struct ata_host *host, unsigned int board_idx) |
20f733e7 BR |
3739 | { |
3740 | int rc = 0, n_hc, port, hc; | |
4447d351 | 3741 | struct mv_host_priv *hpriv = host->private_data; |
f351b2d6 | 3742 | void __iomem *mmio = hpriv->base; |
47c2b677 | 3743 | |
4447d351 | 3744 | rc = mv_chip_id(host, board_idx); |
bca1c4eb | 3745 | if (rc) |
352fab70 | 3746 | goto done; |
f351b2d6 | 3747 | |
1f398472 | 3748 | if (IS_SOC(hpriv)) { |
7368f919 ML |
3749 | hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; |
3750 | hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; | |
1f398472 ML |
3751 | } else { |
3752 | hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; | |
3753 | hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; | |
f351b2d6 | 3754 | } |
352fab70 | 3755 | |
5d0fb2e7 TR |
3756 | /* initialize shadow irq mask with register's value */ |
3757 | hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); | |
3758 | ||
352fab70 | 3759 | /* global interrupt mask: 0 == mask everything */ |
c4de573b | 3760 | mv_set_main_irq_mask(host, ~0, 0); |
bca1c4eb | 3761 | |
4447d351 | 3762 | n_hc = mv_get_hc_count(host->ports[0]->flags); |
bca1c4eb | 3763 | |
4447d351 | 3764 | for (port = 0; port < host->n_ports; port++) |
47c2b677 | 3765 | hpriv->ops->read_preamp(hpriv, port, mmio); |
20f733e7 | 3766 | |
c9d39130 | 3767 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
47c2b677 | 3768 | if (rc) |
20f733e7 | 3769 | goto done; |
20f733e7 | 3770 | |
522479fb | 3771 | hpriv->ops->reset_flash(hpriv, mmio); |
7bb3c529 | 3772 | hpriv->ops->reset_bus(host, mmio); |
47c2b677 | 3773 | hpriv->ops->enable_leds(hpriv, mmio); |
20f733e7 | 3774 | |
4447d351 | 3775 | for (port = 0; port < host->n_ports; port++) { |
cbcdd875 | 3776 | struct ata_port *ap = host->ports[port]; |
2a47ce06 | 3777 | void __iomem *port_mmio = mv_port_base(mmio, port); |
cbcdd875 TH |
3778 | |
3779 | mv_port_init(&ap->ioaddr, port_mmio); | |
3780 | ||
7bb3c529 | 3781 | #ifdef CONFIG_PCI |
1f398472 | 3782 | if (!IS_SOC(hpriv)) { |
f351b2d6 SB |
3783 | unsigned int offset = port_mmio - mmio; |
3784 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); | |
3785 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); | |
3786 | } | |
7bb3c529 | 3787 | #endif |
20f733e7 BR |
3788 | } |
3789 | ||
3790 | for (hc = 0; hc < n_hc; hc++) { | |
31961943 BR |
3791 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
3792 | ||
3793 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " | |
3794 | "(before clear)=0x%08x\n", hc, | |
3795 | readl(hc_mmio + HC_CFG_OFS), | |
3796 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); | |
3797 | ||
3798 | /* Clear any currently outstanding hc interrupt conditions */ | |
3799 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); | |
20f733e7 BR |
3800 | } |
3801 | ||
44c65d16 ML |
3802 | if (!IS_SOC(hpriv)) { |
3803 | /* Clear any currently outstanding host interrupt conditions */ | |
3804 | writelfl(0, mmio + hpriv->irq_cause_ofs); | |
31961943 | 3805 | |
44c65d16 ML |
3806 | /* and unmask interrupt generation for host regs */ |
3807 | writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs); | |
3808 | } | |
51de32d2 | 3809 | |
6be96ac1 ML |
3810 | /* |
3811 | * enable only global host interrupts for now. | |
3812 | * The per-port interrupts get done later as ports are set up. | |
3813 | */ | |
3814 | mv_set_main_irq_mask(host, 0, PCI_ERR); | |
2b748a0a ML |
3815 | mv_set_irq_coalescing(host, irq_coalescing_io_count, |
3816 | irq_coalescing_usecs); | |
f351b2d6 SB |
3817 | done: |
3818 | return rc; | |
3819 | } | |
fb621e2f | 3820 | |
fbf14e2f BB |
3821 | static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) |
3822 | { | |
3823 | hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, | |
3824 | MV_CRQB_Q_SZ, 0); | |
3825 | if (!hpriv->crqb_pool) | |
3826 | return -ENOMEM; | |
3827 | ||
3828 | hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, | |
3829 | MV_CRPB_Q_SZ, 0); | |
3830 | if (!hpriv->crpb_pool) | |
3831 | return -ENOMEM; | |
3832 | ||
3833 | hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, | |
3834 | MV_SG_TBL_SZ, 0); | |
3835 | if (!hpriv->sg_tbl_pool) | |
3836 | return -ENOMEM; | |
3837 | ||
3838 | return 0; | |
3839 | } | |
3840 | ||
15a32632 LB |
3841 | static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, |
3842 | struct mbus_dram_target_info *dram) | |
3843 | { | |
3844 | int i; | |
3845 | ||
3846 | for (i = 0; i < 4; i++) { | |
3847 | writel(0, hpriv->base + WINDOW_CTRL(i)); | |
3848 | writel(0, hpriv->base + WINDOW_BASE(i)); | |
3849 | } | |
3850 | ||
3851 | for (i = 0; i < dram->num_cs; i++) { | |
3852 | struct mbus_dram_window *cs = dram->cs + i; | |
3853 | ||
3854 | writel(((cs->size - 1) & 0xffff0000) | | |
3855 | (cs->mbus_attr << 8) | | |
3856 | (dram->mbus_dram_target_id << 4) | 1, | |
3857 | hpriv->base + WINDOW_CTRL(i)); | |
3858 | writel(cs->base, hpriv->base + WINDOW_BASE(i)); | |
3859 | } | |
3860 | } | |
3861 | ||
f351b2d6 SB |
3862 | /** |
3863 | * mv_platform_probe - handle a positive probe of an soc Marvell | |
3864 | * host | |
3865 | * @pdev: platform device found | |
3866 | * | |
3867 | * LOCKING: | |
3868 | * Inherited from caller. | |
3869 | */ | |
3870 | static int mv_platform_probe(struct platform_device *pdev) | |
3871 | { | |
3872 | static int printed_version; | |
3873 | const struct mv_sata_platform_data *mv_platform_data; | |
3874 | const struct ata_port_info *ppi[] = | |
3875 | { &mv_port_info[chip_soc], NULL }; | |
3876 | struct ata_host *host; | |
3877 | struct mv_host_priv *hpriv; | |
3878 | struct resource *res; | |
3879 | int n_ports, rc; | |
20f733e7 | 3880 | |
f351b2d6 SB |
3881 | if (!printed_version++) |
3882 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
bca1c4eb | 3883 | |
f351b2d6 SB |
3884 | /* |
3885 | * Simple resource validation .. | |
3886 | */ | |
3887 | if (unlikely(pdev->num_resources != 2)) { | |
3888 | dev_err(&pdev->dev, "invalid number of resources\n"); | |
3889 | return -EINVAL; | |
3890 | } | |
3891 | ||
3892 | /* | |
3893 | * Get the register base first | |
3894 | */ | |
3895 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
3896 | if (res == NULL) | |
3897 | return -EINVAL; | |
3898 | ||
3899 | /* allocate host */ | |
3900 | mv_platform_data = pdev->dev.platform_data; | |
3901 | n_ports = mv_platform_data->n_ports; | |
3902 | ||
3903 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
3904 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
3905 | ||
3906 | if (!host || !hpriv) | |
3907 | return -ENOMEM; | |
3908 | host->private_data = hpriv; | |
3909 | hpriv->n_ports = n_ports; | |
3910 | ||
3911 | host->iomap = NULL; | |
f1cb0ea1 SB |
3912 | hpriv->base = devm_ioremap(&pdev->dev, res->start, |
3913 | res->end - res->start + 1); | |
f351b2d6 SB |
3914 | hpriv->base -= MV_SATAHC0_REG_BASE; |
3915 | ||
15a32632 LB |
3916 | /* |
3917 | * (Re-)program MBUS remapping windows if we are asked to. | |
3918 | */ | |
3919 | if (mv_platform_data->dram != NULL) | |
3920 | mv_conf_mbus_windows(hpriv, mv_platform_data->dram); | |
3921 | ||
fbf14e2f BB |
3922 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
3923 | if (rc) | |
3924 | return rc; | |
3925 | ||
f351b2d6 SB |
3926 | /* initialize adapter */ |
3927 | rc = mv_init_host(host, chip_soc); | |
3928 | if (rc) | |
3929 | return rc; | |
3930 | ||
3931 | dev_printk(KERN_INFO, &pdev->dev, | |
3932 | "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH, | |
3933 | host->n_ports); | |
3934 | ||
3935 | return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt, | |
3936 | IRQF_SHARED, &mv6_sht); | |
3937 | } | |
3938 | ||
3939 | /* | |
3940 | * | |
3941 | * mv_platform_remove - unplug a platform interface | |
3942 | * @pdev: platform device | |
3943 | * | |
3944 | * A platform bus SATA device has been unplugged. Perform the needed | |
3945 | * cleanup. Also called on module unload for any active devices. | |
3946 | */ | |
3947 | static int __devexit mv_platform_remove(struct platform_device *pdev) | |
3948 | { | |
3949 | struct device *dev = &pdev->dev; | |
3950 | struct ata_host *host = dev_get_drvdata(dev); | |
f351b2d6 SB |
3951 | |
3952 | ata_host_detach(host); | |
f351b2d6 | 3953 | return 0; |
20f733e7 BR |
3954 | } |
3955 | ||
f351b2d6 SB |
3956 | static struct platform_driver mv_platform_driver = { |
3957 | .probe = mv_platform_probe, | |
3958 | .remove = __devexit_p(mv_platform_remove), | |
3959 | .driver = { | |
3960 | .name = DRV_NAME, | |
3961 | .owner = THIS_MODULE, | |
3962 | }, | |
3963 | }; | |
3964 | ||
3965 | ||
7bb3c529 | 3966 | #ifdef CONFIG_PCI |
f351b2d6 SB |
3967 | static int mv_pci_init_one(struct pci_dev *pdev, |
3968 | const struct pci_device_id *ent); | |
3969 | ||
7bb3c529 SB |
3970 | |
3971 | static struct pci_driver mv_pci_driver = { | |
3972 | .name = DRV_NAME, | |
3973 | .id_table = mv_pci_tbl, | |
f351b2d6 | 3974 | .probe = mv_pci_init_one, |
7bb3c529 SB |
3975 | .remove = ata_pci_remove_one, |
3976 | }; | |
3977 | ||
7bb3c529 SB |
3978 | /* move to PCI layer or libata core? */ |
3979 | static int pci_go_64(struct pci_dev *pdev) | |
3980 | { | |
3981 | int rc; | |
3982 | ||
3983 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
3984 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3985 | if (rc) { | |
3986 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
3987 | if (rc) { | |
3988 | dev_printk(KERN_ERR, &pdev->dev, | |
3989 | "64-bit DMA enable failed\n"); | |
3990 | return rc; | |
3991 | } | |
3992 | } | |
3993 | } else { | |
3994 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
3995 | if (rc) { | |
3996 | dev_printk(KERN_ERR, &pdev->dev, | |
3997 | "32-bit DMA enable failed\n"); | |
3998 | return rc; | |
3999 | } | |
4000 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
4001 | if (rc) { | |
4002 | dev_printk(KERN_ERR, &pdev->dev, | |
4003 | "32-bit consistent DMA enable failed\n"); | |
4004 | return rc; | |
4005 | } | |
4006 | } | |
4007 | ||
4008 | return rc; | |
4009 | } | |
4010 | ||
05b308e1 BR |
4011 | /** |
4012 | * mv_print_info - Dump key info to kernel log for perusal. | |
4447d351 | 4013 | * @host: ATA host to print info about |
05b308e1 BR |
4014 | * |
4015 | * FIXME: complete this. | |
4016 | * | |
4017 | * LOCKING: | |
4018 | * Inherited from caller. | |
4019 | */ | |
4447d351 | 4020 | static void mv_print_info(struct ata_host *host) |
31961943 | 4021 | { |
4447d351 TH |
4022 | struct pci_dev *pdev = to_pci_dev(host->dev); |
4023 | struct mv_host_priv *hpriv = host->private_data; | |
44c10138 | 4024 | u8 scc; |
c1e4fe71 | 4025 | const char *scc_s, *gen; |
31961943 BR |
4026 | |
4027 | /* Use this to determine the HW stepping of the chip so we know | |
4028 | * what errata to workaround | |
4029 | */ | |
31961943 BR |
4030 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); |
4031 | if (scc == 0) | |
4032 | scc_s = "SCSI"; | |
4033 | else if (scc == 0x01) | |
4034 | scc_s = "RAID"; | |
4035 | else | |
c1e4fe71 JG |
4036 | scc_s = "?"; |
4037 | ||
4038 | if (IS_GEN_I(hpriv)) | |
4039 | gen = "I"; | |
4040 | else if (IS_GEN_II(hpriv)) | |
4041 | gen = "II"; | |
4042 | else if (IS_GEN_IIE(hpriv)) | |
4043 | gen = "IIE"; | |
4044 | else | |
4045 | gen = "?"; | |
31961943 | 4046 | |
a9524a76 | 4047 | dev_printk(KERN_INFO, &pdev->dev, |
c1e4fe71 JG |
4048 | "Gen-%s %u slots %u ports %s mode IRQ via %s\n", |
4049 | gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, | |
31961943 BR |
4050 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
4051 | } | |
4052 | ||
05b308e1 | 4053 | /** |
f351b2d6 | 4054 | * mv_pci_init_one - handle a positive probe of a PCI Marvell host |
05b308e1 BR |
4055 | * @pdev: PCI device found |
4056 | * @ent: PCI device ID entry for the matched host | |
4057 | * | |
4058 | * LOCKING: | |
4059 | * Inherited from caller. | |
4060 | */ | |
f351b2d6 SB |
4061 | static int mv_pci_init_one(struct pci_dev *pdev, |
4062 | const struct pci_device_id *ent) | |
20f733e7 | 4063 | { |
2dcb407e | 4064 | static int printed_version; |
20f733e7 | 4065 | unsigned int board_idx = (unsigned int)ent->driver_data; |
4447d351 TH |
4066 | const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; |
4067 | struct ata_host *host; | |
4068 | struct mv_host_priv *hpriv; | |
4069 | int n_ports, rc; | |
20f733e7 | 4070 | |
a9524a76 JG |
4071 | if (!printed_version++) |
4072 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
20f733e7 | 4073 | |
4447d351 TH |
4074 | /* allocate host */ |
4075 | n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; | |
4076 | ||
4077 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4078 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
4079 | if (!host || !hpriv) | |
4080 | return -ENOMEM; | |
4081 | host->private_data = hpriv; | |
f351b2d6 | 4082 | hpriv->n_ports = n_ports; |
4447d351 TH |
4083 | |
4084 | /* acquire resources */ | |
24dc5f33 TH |
4085 | rc = pcim_enable_device(pdev); |
4086 | if (rc) | |
20f733e7 | 4087 | return rc; |
20f733e7 | 4088 | |
0d5ff566 TH |
4089 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
4090 | if (rc == -EBUSY) | |
24dc5f33 | 4091 | pcim_pin_device(pdev); |
0d5ff566 | 4092 | if (rc) |
24dc5f33 | 4093 | return rc; |
4447d351 | 4094 | host->iomap = pcim_iomap_table(pdev); |
f351b2d6 | 4095 | hpriv->base = host->iomap[MV_PRIMARY_BAR]; |
20f733e7 | 4096 | |
d88184fb JG |
4097 | rc = pci_go_64(pdev); |
4098 | if (rc) | |
4099 | return rc; | |
4100 | ||
da2fa9ba ML |
4101 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
4102 | if (rc) | |
4103 | return rc; | |
4104 | ||
20f733e7 | 4105 | /* initialize adapter */ |
4447d351 | 4106 | rc = mv_init_host(host, board_idx); |
24dc5f33 TH |
4107 | if (rc) |
4108 | return rc; | |
20f733e7 | 4109 | |
6d3c30ef ML |
4110 | /* Enable message-switched interrupts, if requested */ |
4111 | if (msi && pci_enable_msi(pdev) == 0) | |
4112 | hpriv->hp_flags |= MV_HP_FLAG_MSI; | |
20f733e7 | 4113 | |
31961943 | 4114 | mv_dump_pci_cfg(pdev, 0x68); |
4447d351 | 4115 | mv_print_info(host); |
20f733e7 | 4116 | |
4447d351 | 4117 | pci_set_master(pdev); |
ea8b4db9 | 4118 | pci_try_set_mwi(pdev); |
4447d351 | 4119 | return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, |
c5d3e45a | 4120 | IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); |
20f733e7 | 4121 | } |
7bb3c529 | 4122 | #endif |
20f733e7 | 4123 | |
f351b2d6 SB |
4124 | static int mv_platform_probe(struct platform_device *pdev); |
4125 | static int __devexit mv_platform_remove(struct platform_device *pdev); | |
4126 | ||
20f733e7 BR |
4127 | static int __init mv_init(void) |
4128 | { | |
7bb3c529 SB |
4129 | int rc = -ENODEV; |
4130 | #ifdef CONFIG_PCI | |
4131 | rc = pci_register_driver(&mv_pci_driver); | |
f351b2d6 SB |
4132 | if (rc < 0) |
4133 | return rc; | |
4134 | #endif | |
4135 | rc = platform_driver_register(&mv_platform_driver); | |
4136 | ||
4137 | #ifdef CONFIG_PCI | |
4138 | if (rc < 0) | |
4139 | pci_unregister_driver(&mv_pci_driver); | |
7bb3c529 SB |
4140 | #endif |
4141 | return rc; | |
20f733e7 BR |
4142 | } |
4143 | ||
4144 | static void __exit mv_exit(void) | |
4145 | { | |
7bb3c529 | 4146 | #ifdef CONFIG_PCI |
20f733e7 | 4147 | pci_unregister_driver(&mv_pci_driver); |
7bb3c529 | 4148 | #endif |
f351b2d6 | 4149 | platform_driver_unregister(&mv_platform_driver); |
20f733e7 BR |
4150 | } |
4151 | ||
4152 | MODULE_AUTHOR("Brett Russ"); | |
4153 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); | |
4154 | MODULE_LICENSE("GPL"); | |
4155 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); | |
4156 | MODULE_VERSION(DRV_VERSION); | |
17c5aab5 | 4157 | MODULE_ALIAS("platform:" DRV_NAME); |
20f733e7 BR |
4158 | |
4159 | module_init(mv_init); | |
4160 | module_exit(mv_exit); |