[net-next-2.6.git] / drivers / ata / pata_sl82c105.c

/*
 * pata_sl82c105.c 	- SL82C105 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *
 * Based in part on linux/drivers/ide/pci/sl82c105.c
 * 		SL82C105/Winbond 553 IDE driver
 *
 * and in part on the documentation and errata sheet
 *
 *
 * Note: The controller like many controllers has shared timings for
 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
 * in the dma_stop function. Thus we actually don't need a set_dmamode
 * method as the PIO method is always called and will set the right PIO
 * timing parameters.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sl82c105"
#define DRV_VERSION "0.3.3"

enum {
	/*
	 * SL82C105 PCI config register 0x40 bits.
	 */
	CTRL_IDE_IRQB	=	(1 << 30),
	CTRL_IDE_IRQA   =	(1 << 28),
	CTRL_LEGIRQ     =	(1 << 11),
	CTRL_P1F16      =	(1 << 5),
	CTRL_P1EN       =	(1 << 4),
	CTRL_P0F16      =	(1 << 1),
	CTRL_P0EN       =	(1 << 0)
};

/**
 *	sl82c105_pre_reset		-	probe begin
 *	@link: ATA link
 *	@deadline: deadline jiffies for the operation
 *
 *	Set up cable type and use generic probe init
 */

static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
{
	static const struct pci_bits sl82c105_enable_bits[] = {
		{ 0x40, 1, 0x01, 0x01 },
		{ 0x40, 1, 0x10, 0x10 }
	};
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);

	if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
		return -ENOENT;
	return ata_sff_prereset(link, deadline);
}


/**
 *	sl82c105_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static u16 pio_timing[5] = {
		0x50D, 0x407, 0x304, 0x242, 0x240
	};
	u16 dummy;
	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);

	pci_write_config_word(pdev, timing, pio_timing[pio]);
	/* Can we lose this oddity of the old driver */
	pci_read_config_word(pdev, timing, &dummy);
}

/**
 *	sl82c105_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	sl82c105_configure_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static u16 dma_timing[3] = {
		0x707, 0x201, 0x200
	};
	u16 dummy;
	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
	int dma = adev->dma_mode - XFER_MW_DMA_0;

	pci_write_config_word(pdev, timing, dma_timing[dma]);
	/* Can we lose this oddity of the old driver */
	pci_read_config_word(pdev, timing, &dummy);
}

/**
 *	sl82c105_reset_engine	-	Reset the DMA engine
 *	@ap: ATA interface
 *
 *	The sl82c105 has some serious problems with the DMA engine
 *	when transfers don't run as expected or ATAPI is used. The
 *	recommended fix is to reset the engine each use using a chip
 *	test register.
 */

static void sl82c105_reset_engine(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 val;

	pci_read_config_word(pdev, 0x7E, &val);
	pci_write_config_word(pdev, 0x7E, val | 4);
	pci_write_config_word(pdev, 0x7E, val & ~4);
}

/**
 *	sl82c105_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	Reset the DMA engine each use as recommended by the errata
 *	document.
 *
 *	FIXME: if we switch clock at BMDMA start/end we might get better
 *	PIO performance on DMA capable devices.
 */

static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	udelay(100);
	sl82c105_reset_engine(ap);
	udelay(100);

	/* Set the clocks for DMA */
	sl82c105_configure_dmamode(ap, qc->dev);
	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	sl82c105_bmdma_end		-	DMA engine stop
 *	@qc: ATA command
 *
 *	Reset the DMA engine each use as recommended by the errata
 *	document.
 *
 *	This function is also called to turn off DMA when a timeout occurs
 *	during DMA operation. In both cases we need to reset the engine,
 *	so no actual eng_timeout handler is required.
 *
 *	We assume bmdma_stop is always called if bmdma_start as called. If
 *	not then we may need to wrap qc_issue.
 */

static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	ata_bmdma_stop(qc);
	sl82c105_reset_engine(ap);
	udelay(100);

	/* This will redo the initial setup of the DMA device to matching
	   PIO timings */
	sl82c105_set_piomode(ap, qc->dev);
}

/**
 *	sl82c105_qc_defer	-	implement serialization
 *	@qc: command
 *
 *	We must issue one command per host not per channel because
 *	of the reset bug.
 *
 *	Q: is the scsi host lock sufficient ?
 */

static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
{
	struct ata_host *host = qc->ap->host;
	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	int rc;

	/* First apply the usual rules */
	rc = ata_std_qc_defer(qc);
	if (rc != 0)
		return rc;

	/* Now apply serialization rules. Only allow a command if the
	   other channel state machine is idle */
	if (alt && alt->qc_active)
		return	ATA_DEFER_PORT;
	return 0;
}

static struct scsi_host_template sl82c105_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations sl82c105_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.qc_defer	= sl82c105_qc_defer,
	.bmdma_start 	= sl82c105_bmdma_start,
	.bmdma_stop	= sl82c105_bmdma_stop,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= sl82c105_set_piomode,
	.prereset	= sl82c105_pre_reset,
};

/**
 *	sl82c105_bridge_revision	-	find bridge version
 *	@pdev: PCI device for the ATA function
 *
 *	Locates the PCI bridge associated with the ATA function and
 *	providing it is a Winbond 553 reports the revision. If it cannot
 *	find a revision or the right device it returns -1
 */

static int sl82c105_bridge_revision(struct pci_dev *pdev)
{
	struct pci_dev *bridge;

	/*
	 * The bridge should be part of the same device, but function 0.
	 */
	bridge = pci_get_slot(pdev->bus,
			       PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
	if (!bridge)
		return -1;

	/*
	 * Make sure it is a Winbond 553 and is an ISA bridge.
	 */
	if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
	    bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
	    bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	    	pci_dev_put(bridge);
		return -1;
	}
	/*
	 * We need to find function 0's revision, not function 1
	 */
	pci_dev_put(bridge);
	return bridge->revision;
}


static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_dma = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.port_ops = &sl82c105_port_ops
	};
	static const struct ata_port_info info_early = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.port_ops = &sl82c105_port_ops
	};
	/* for now use only the first port */
	const struct ata_port_info *ppi[] = { &info_early,
					       NULL };
	u32 val;
	int rev;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	rev = sl82c105_bridge_revision(dev);

	if (rev == -1)
		dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
	else if (rev <= 5)
		dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
	else
		ppi[0] = &info_dma;

	pci_read_config_dword(dev, 0x40, &val);
	val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
	pci_write_config_dword(dev, 0x40, val);

	return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
}

static const struct pci_device_id sl82c105[] = {
	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },

	{ },
};

static struct pci_driver sl82c105_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sl82c105,
	.probe 		= sl82c105_init_one,
	.remove		= ata_pci_remove_one
};

static int __init sl82c105_init(void)
{
	return pci_register_driver(&sl82c105_pci_driver);
}

static void __exit sl82c105_exit(void)
{
	pci_unregister_driver(&sl82c105_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Sl82c105");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sl82c105);
MODULE_VERSION(DRV_VERSION);

module_init(sl82c105_init);
module_exit(sl82c105_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sl82c105.c - SL82C105 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
669a5db4 JG	4	*
	5	* Based in part on linux/drivers/ide/pci/sl82c105.c
	6	* SL82C105/Winbond 553 IDE driver
	7	*
	8	* and in part on the documentation and errata sheet
16728da9 AC	9	*
	10	*
	11	* Note: The controller like many controllers has shared timings for
	12	* PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
	13	* in the dma_stop function. Thus we actually don't need a set_dmamode
	14	* method as the PIO method is always called and will set the right PIO
	15	* timing parameters.
669a5db4	16	*/
85cd7251	17
669a5db4 JG	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/pci.h>
	21	#include <linux/init.h>
	22	#include <linux/blkdev.h>
	23	#include <linux/delay.h>
	24	#include <scsi/scsi_host.h>
	25	#include <linux/libata.h>
	26
	27	#define DRV_NAME "pata_sl82c105"
92ba5d02	28	#define DRV_VERSION "0.3.3"
669a5db4 JG	29
	30	enum {
	31	/*
	32	* SL82C105 PCI config register 0x40 bits.
	33	*/
	34	CTRL_IDE_IRQB = (1 << 30),
	35	CTRL_IDE_IRQA = (1 << 28),
	36	CTRL_LEGIRQ = (1 << 11),
	37	CTRL_P1F16 = (1 << 5),
	38	CTRL_P1EN = (1 << 4),
	39	CTRL_P0F16 = (1 << 1),
	40	CTRL_P0EN = (1 << 0)
	41	};
	42
	43	/**
	44	* sl82c105_pre_reset - probe begin
cc0680a5	45	* @link: ATA link
d4b2bab4	46	* @deadline: deadline jiffies for the operation
669a5db4 JG	47	*
	48	* Set up cable type and use generic probe init
	49	*/
85cd7251	50
cc0680a5	51	static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4 JG	52	{
	53	static const struct pci_bits sl82c105_enable_bits[] = {
	54	{ 0x40, 1, 0x01, 0x01 },
	55	{ 0x40, 1, 0x10, 0x10 }
	56	};
cc0680a5	57	struct ata_port *ap = link->ap;
669a5db4 JG	58	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
669a5db4 JG	59
c961922b AC	60	if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
c961922b AC	61	return -ENOENT;
9363c382	62	return ata_sff_prereset(link, deadline);
669a5db4 JG	63	}
	64
	65
669a5db4 JG	66	/**
	67	* sl82c105_configure_piomode - set chip PIO timing
	68	* @ap: ATA interface
	69	* @adev: ATA device
	70	* @pio: PIO mode
	71	*
	72	* Called to do the PIO mode setup. Our timing registers are shared
	73	* so a configure_dmamode call will undo any work we do here and vice
	74	* versa
	75	*/
85cd7251	76
669a5db4 JG	77	static void sl82c105_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
	78	{
	79	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	80	static u16 pio_timing[5] = {
	81	0x50D, 0x407, 0x304, 0x242, 0x240
	82	};
	83	u16 dummy;
	84	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
85cd7251	85
669a5db4 JG	86	pci_write_config_word(pdev, timing, pio_timing[pio]);
	87	/* Can we lose this oddity of the old driver */
	88	pci_read_config_word(pdev, timing, &dummy);
	89	}
	90
	91	/**
	92	* sl82c105_set_piomode - set initial PIO mode data
	93	* @ap: ATA interface
	94	* @adev: ATA device
	95	*
	96	* Called to do the PIO mode setup. Our timing registers are shared
	97	* but we want to set the PIO timing by default.
	98	*/
85cd7251	99
669a5db4 JG	100	static void sl82c105_set_piomode(struct ata_port ap, struct ata_device adev)
	101	{
	102	sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
	103	}
	104
	105	/**
	106	* sl82c105_configure_dmamode - set DMA mode in chip
	107	* @ap: ATA interface
	108	* @adev: ATA device
	109	*
	110	* Load DMA cycle times into the chip ready for a DMA transfer
	111	* to occur.
	112	*/
85cd7251	113
669a5db4 JG	114	static void sl82c105_configure_dmamode(struct ata_port ap, struct ata_device adev)
	115	{
	116	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	117	static u16 dma_timing[3] = {
	118	0x707, 0x201, 0x200
	119	};
	120	u16 dummy;
	121	int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
	122	int dma = adev->dma_mode - XFER_MW_DMA_0;
85cd7251	123
669a5db4 JG	124	pci_write_config_word(pdev, timing, dma_timing[dma]);
	125	/* Can we lose this oddity of the old driver */
	126	pci_read_config_word(pdev, timing, &dummy);
	127	}
	128
669a5db4 JG	129	/**
	130	* sl82c105_reset_engine - Reset the DMA engine
	131	* @ap: ATA interface
	132	*
	133	* The sl82c105 has some serious problems with the DMA engine
85cd7251	134	* when transfers don't run as expected or ATAPI is used. The
669a5db4 JG	135	* recommended fix is to reset the engine each use using a chip
	136	* test register.
	137	*/
85cd7251	138
669a5db4 JG	139	static void sl82c105_reset_engine(struct ata_port *ap)
	140	{
	141	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	142	u16 val;
85cd7251	143
669a5db4 JG	144	pci_read_config_word(pdev, 0x7E, &val);
	145	pci_write_config_word(pdev, 0x7E, val \| 4);
	146	pci_write_config_word(pdev, 0x7E, val & ~4);
	147	}
	148
	149	/**
	150	* sl82c105_bmdma_start - DMA engine begin
	151	* @qc: ATA command
	152	*
	153	* Reset the DMA engine each use as recommended by the errata
85cd7251	154	* document.
669a5db4 JG	155	*
	156	* FIXME: if we switch clock at BMDMA start/end we might get better
	157	* PIO performance on DMA capable devices.
	158	*/
85cd7251	159
669a5db4 JG	160	static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
	161	{
	162	struct ata_port *ap = qc->ap;
	163
8361cd79	164	udelay(100);
669a5db4	165	sl82c105_reset_engine(ap);
8361cd79	166	udelay(100);
85cd7251	167
669a5db4 JG	168	/* Set the clocks for DMA */
669a5db4 JG	169	sl82c105_configure_dmamode(ap, qc->dev);
85cd7251	170	/* Activate DMA */
669a5db4 JG	171	ata_bmdma_start(qc);
	172	}
	173
	174	/**
	175	* sl82c105_bmdma_end - DMA engine stop
	176	* @qc: ATA command
	177	*
	178	* Reset the DMA engine each use as recommended by the errata
	179	* document.
	180	*
	181	* This function is also called to turn off DMA when a timeout occurs
	182	* during DMA operation. In both cases we need to reset the engine,
	183	* so no actual eng_timeout handler is required.
	184	*
	185	* We assume bmdma_stop is always called if bmdma_start as called. If
	186	* not then we may need to wrap qc_issue.
	187	*/
85cd7251	188
669a5db4 JG	189	static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
	190	{
	191	struct ata_port *ap = qc->ap;
	192
	193	ata_bmdma_stop(qc);
	194	sl82c105_reset_engine(ap);
8361cd79	195	udelay(100);
85cd7251	196
669a5db4 JG	197	/* This will redo the initial setup of the DMA device to matching
669a5db4 JG	198	PIO timings */
16728da9	199	sl82c105_set_piomode(ap, qc->dev);
669a5db4 JG	200	}
669a5db4 JG	201
92ba5d02 AC	202	/**
	203	* sl82c105_qc_defer - implement serialization
	204	* @qc: command
	205	*
	206	* We must issue one command per host not per channel because
	207	* of the reset bug.
	208	*
	209	* Q: is the scsi host lock sufficient ?
	210	*/
	211
	212	static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
	213	{
	214	struct ata_host *host = qc->ap->host;
	215	struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
	216	int rc;
	217
c85665ff	218	/* First apply the usual rules */
92ba5d02 AC	219	rc = ata_std_qc_defer(qc);
	220	if (rc != 0)
	221	return rc;
	222
	223	/* Now apply serialization rules. Only allow a command if the
	224	other channel state machine is idle */
	225	if (alt && alt->qc_active)
	226	return ATA_DEFER_PORT;
	227	return 0;
	228	}
	229
669a5db4	230	static struct scsi_host_template sl82c105_sht = {
68d1d07b	231	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	232	};
	233
	234	static struct ata_port_operations sl82c105_port_ops = {
029cfd6b TH	235	.inherits = &ata_bmdma_port_ops,
029cfd6b TH	236	.qc_defer = sl82c105_qc_defer,
669a5db4 JG	237	.bmdma_start = sl82c105_bmdma_start,
669a5db4 JG	238	.bmdma_stop = sl82c105_bmdma_stop,
029cfd6b TH	239	.cable_detect = ata_cable_40wire,
029cfd6b TH	240	.set_piomode = sl82c105_set_piomode,
a1efdaba	241	.prereset = sl82c105_pre_reset,
85cd7251	242	};
669a5db4 JG	243
	244	/**
	245	* sl82c105_bridge_revision - find bridge version
	246	* @pdev: PCI device for the ATA function
	247	*
	248	* Locates the PCI bridge associated with the ATA function and
	249	* providing it is a Winbond 553 reports the revision. If it cannot
	250	* find a revision or the right device it returns -1
	251	*/
85cd7251	252
669a5db4 JG	253	static int sl82c105_bridge_revision(struct pci_dev *pdev)
	254	{
	255	struct pci_dev *bridge;
669a5db4 JG	256
	257	/*
	258	* The bridge should be part of the same device, but function 0.
	259	*/
	260	bridge = pci_get_slot(pdev->bus,
	261	PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
	262	if (!bridge)
	263	return -1;
	264
	265	/*
	266	* Make sure it is a Winbond 553 and is an ISA bridge.
	267	*/
	268	if (bridge->vendor != PCI_VENDOR_ID_WINBOND \|\|
	269	bridge->device != PCI_DEVICE_ID_WINBOND_83C553 \|\|
	270	bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
	271	pci_dev_put(bridge);
	272	return -1;
	273	}
	274	/*
	275	* We need to find function 0's revision, not function 1
	276	*/
669a5db4	277	pci_dev_put(bridge);
44c10138	278	return bridge->revision;
669a5db4 JG	279	}
669a5db4 JG	280
85cd7251	281
669a5db4 JG	282	static int sl82c105_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	283	{
1626aeb8	284	static const struct ata_port_info info_dma = {
1d2808fd	285	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	286	.pio_mask = ATA_PIO4,
14bdef98 EIB	287	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	288	.port_ops = &sl82c105_port_ops
669a5db4 JG	289	};
1626aeb8	290	static const struct ata_port_info info_early = {
1d2808fd	291	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98	292	.pio_mask = ATA_PIO4,
669a5db4 JG	293	.port_ops = &sl82c105_port_ops
669a5db4 JG	294	};
1626aeb8 TH	295	/* for now use only the first port */
1626aeb8 TH	296	const struct ata_port_info *ppi[] = { &info_early,
92ba5d02	297	NULL };
669a5db4 JG	298	u32 val;
669a5db4 JG	299	int rev;
f08048e9 TH	300	int rc;
	301
	302	rc = pcim_enable_device(dev);
	303	if (rc)
	304	return rc;
669a5db4 JG	305
669a5db4 JG	306	rev = sl82c105_bridge_revision(dev);
85cd7251	307
669a5db4 JG	308	if (rev == -1)
	309	dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
	310	else if (rev <= 5)
	311	dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
1626aeb8 TH	312	else
1626aeb8 TH	313	ppi[0] = &info_dma;
85cd7251	314
669a5db4 JG	315	pci_read_config_dword(dev, 0x40, &val);
	316	val \|= CTRL_P0EN \| CTRL_P0F16 \| CTRL_P1F16;
	317	pci_write_config_dword(dev, 0x40, val);
	318
1c5afdf7	319	return ata_pci_bmdma_init_one(dev, ppi, &sl82c105_sht, NULL, 0);
669a5db4 JG	320	}
669a5db4 JG	321
2d2744fc JG	322	static const struct pci_device_id sl82c105[] = {
	323	{ PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
	324
	325	{ },
669a5db4 JG	326	};
	327
	328	static struct pci_driver sl82c105_pci_driver = {
	329	.name = DRV_NAME,
	330	.id_table = sl82c105,
	331	.probe = sl82c105_init_one,
	332	.remove = ata_pci_remove_one
	333	};
	334
	335	static int __init sl82c105_init(void)
	336	{
	337	return pci_register_driver(&sl82c105_pci_driver);
	338	}
	339
669a5db4 JG	340	static void __exit sl82c105_exit(void)
	341	{
	342	pci_unregister_driver(&sl82c105_pci_driver);
	343	}
	344
669a5db4 JG	345	MODULE_AUTHOR("Alan Cox");
	346	MODULE_DESCRIPTION("low-level driver for Sl82c105");
	347	MODULE_LICENSE("GPL");
	348	MODULE_DEVICE_TABLE(pci, sl82c105);
	349	MODULE_VERSION(DRV_VERSION);
	350
	351	module_init(sl82c105_init);
	352	module_exit(sl82c105_exit);