[net-next-2.6.git] / drivers / ata / pata_mpiix.c

/*
 * pata_mpiix.c 	- Intel MPIIX PATA for new ATA layer
 *			  (C) 2005-2006 Red Hat Inc
 *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * The MPIIX is different enough to the PIIX4 and friends that we give it
 * a separate driver. The old ide/pci code handles this by just not tuning
 * MPIIX at all.
 *
 * The MPIIX also differs in another important way from the majority of PIIX
 * devices. The chip is a bridge (pardon the pun) between the old world of
 * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
 * IDE controller is not decoded in PCI space and the chip does not claim to
 * be IDE class PCI. This requires slightly non-standard probe logic compared
 * with PCI IDE and also that we do not disable the device when our driver is
 * unloaded (as it has many other functions).
 *
 * The driver conciously keeps this logic internally to avoid pushing quirky
 * PATA history into the clean libata layer.
 *
 * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
 * hard disk present this driver will not detect it. This is not a bug. In this
 * configuration the secondary port of the MPIIX is disabled and the addresses
 * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
 * to operate.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_mpiix"
#define DRV_VERSION "0.7.7"

enum {
	IDETIM = 0x6C,		/* IDE control register */
	IORDY = (1 << 1),
	PPE = (1 << 2),
	FTIM = (1 << 0),
	ENABLED = (1 << 15),
	SECONDARY = (1 << 14)
};

static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };

	if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
		return -ENOENT;

	return ata_sff_prereset(link, deadline);
}

/**
 *	mpiix_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. The MPIIX allows us to program the
 *	IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
 *	prefetching or IORDY are used.
 *
 *	This would get very ugly because we can only program timing for one
 *	device at a time, the other gets PIO0. Fortunately libata calls
 *	our qc_issue command before a command is issued so we can flip the
 *	timings back and forth to reduce the pain.
 */

static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	int control = 0;
	int pio = adev->pio_mode - XFER_PIO_0;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 idetim;
	static const	 /* ISP  RTC */
	u8 timings[][2]	= { { 0, 0 },
			    { 0, 0 },
			    { 1, 0 },
			    { 2, 1 },
			    { 2, 3 }, };

	pci_read_config_word(pdev, IDETIM, &idetim);

	/* Mask the IORDY/TIME/PPE for this device */
	if (adev->class == ATA_DEV_ATA)
		control |= PPE;		/* Enable prefetch/posting for disk */
	if (ata_pio_need_iordy(adev))
		control |= IORDY;
	if (pio > 1)
		control |= FTIM;	/* This drive is on the fast timing bank */

	/* Mask out timing and clear both TIME bank selects */
	idetim &= 0xCCEE;
	idetim &= ~(0x07  << (4 * adev->devno));
	idetim |= control << (4 * adev->devno);

	idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
	pci_write_config_word(pdev, IDETIM, idetim);

	/* We use ap->private_data as a pointer to the device currently
	   loaded for timing */
	ap->private_data = adev;
}

/**
 *	mpiix_qc_issue		-	command issue
 *	@qc: command pending
 *
 *	Called when the libata layer is about to issue a command. We wrap
 *	this interface so that we can load the correct ATA timings if
 *	necessary. Our logic also clears TIME0/TIME1 for the other device so
 *	that, even if we get this wrong, cycles to the other device will
 *	be made PIO0.
 */

static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;

	/* If modes have been configured and the channel data is not loaded
	   then load it. We have to check if pio_mode is set as the core code
	   does not set adev->pio_mode to XFER_PIO_0 while probing as would be
	   logical */

	if (adev->pio_mode && adev != ap->private_data)
		mpiix_set_piomode(ap, adev);

	return ata_sff_qc_issue(qc);
}

static struct scsi_host_template mpiix_sht = {
	ATA_PIO_SHT(DRV_NAME),
};

static struct ata_port_operations mpiix_port_ops = {
	.inherits	= &ata_sff_port_ops,
	.qc_issue	= mpiix_qc_issue,
	.cable_detect	= ata_cable_40wire,
	.set_piomode	= mpiix_set_piomode,
	.prereset	= mpiix_pre_reset,
	.sff_data_xfer	= ata_sff_data_xfer32,
};

static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	/* Single threaded by the PCI probe logic */
	static int printed_version;
	struct ata_host *host;
	struct ata_port *ap;
	void __iomem *cmd_addr, *ctl_addr;
	u16 idetim;
	int cmd, ctl, irq;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");

	host = ata_host_alloc(&dev->dev, 1);
	if (!host)
		return -ENOMEM;
	ap = host->ports[0];

	/* MPIIX has many functions which can be turned on or off according
	   to other devices present. Make sure IDE is enabled before we try
	   and use it */

	pci_read_config_word(dev, IDETIM, &idetim);
	if (!(idetim & ENABLED))
		return -ENODEV;

	/* See if it's primary or secondary channel... */
	if (!(idetim & SECONDARY)) {
		cmd = 0x1F0;
		ctl = 0x3F6;
		irq = 14;
	} else {
		cmd = 0x170;
		ctl = 0x376;
		irq = 15;
	}

	cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
	ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
	if (!cmd_addr || !ctl_addr)
		return -ENOMEM;

	ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);

	/* We do our own plumbing to avoid leaking special cases for whacko
	   ancient hardware into the core code. There are two issues to
	   worry about.  #1 The chip is a bridge so if in legacy mode and
	   without BARs set fools the setup.  #2 If you pci_disable_device
	   the MPIIX your box goes castors up */

	ap->ops = &mpiix_port_ops;
	ap->pio_mask = ATA_PIO4;
	ap->flags |= ATA_FLAG_SLAVE_POSS;

	ap->ioaddr.cmd_addr = cmd_addr;
	ap->ioaddr.ctl_addr = ctl_addr;
	ap->ioaddr.altstatus_addr = ctl_addr;

	/* Let libata fill in the port details */
	ata_sff_std_ports(&ap->ioaddr);

	/* activate host */
	return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED,
				 &mpiix_sht);
}

static const struct pci_device_id mpiix[] = {
	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },

	{ },
};

static struct pci_driver mpiix_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= mpiix,
	.probe 		= mpiix_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

static int __init mpiix_init(void)
{
	return pci_register_driver(&mpiix_pci_driver);
}

static void __exit mpiix_exit(void)
{
	pci_unregister_driver(&mpiix_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, mpiix);
MODULE_VERSION(DRV_VERSION);

module_init(mpiix_init);
module_exit(mpiix_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_mpiix.c - Intel MPIIX PATA for new ATA layer
	3	* (C) 2005-2006 Red Hat Inc
ab771630	4	* Alan Cox <alan@lxorguk.ukuu.org.uk>
669a5db4 JG	5	*
	6	* The MPIIX is different enough to the PIIX4 and friends that we give it
	7	* a separate driver. The old ide/pci code handles this by just not tuning
	8	* MPIIX at all.
	9	*
	10	* The MPIIX also differs in another important way from the majority of PIIX
	11	* devices. The chip is a bridge (pardon the pun) between the old world of
	12	* ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
	13	* IDE controller is not decoded in PCI space and the chip does not claim to
	14	* be IDE class PCI. This requires slightly non-standard probe logic compared
	15	* with PCI IDE and also that we do not disable the device when our driver is
	16	* unloaded (as it has many other functions).
	17	*
	18	* The driver conciously keeps this logic internally to avoid pushing quirky
	19	* PATA history into the clean libata layer.
	20	*
c961922b	21	* Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
669a5db4 JG	22	* hard disk present this driver will not detect it. This is not a bug. In this
	23	* configuration the secondary port of the MPIIX is disabled and the addresses
	24	* are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
	25	* to operate.
	26	*/
	27
	28	#include <linux/kernel.h>
	29	#include <linux/module.h>
	30	#include <linux/pci.h>
	31	#include <linux/init.h>
	32	#include <linux/blkdev.h>
	33	#include <linux/delay.h>
	34	#include <scsi/scsi_host.h>
	35	#include <linux/libata.h>
	36
	37	#define DRV_NAME "pata_mpiix"
871af121	38	#define DRV_VERSION "0.7.7"
669a5db4 JG	39
	40	enum {
	41	IDETIM = 0x6C, /* IDE control register */
	42	IORDY = (1 << 1),
	43	PPE = (1 << 2),
	44	FTIM = (1 << 0),
	45	ENABLED = (1 << 15),
	46	SECONDARY = (1 << 14)
	47	};
	48
cc0680a5	49	static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
669a5db4	50	{
cc0680a5	51	struct ata_port *ap = link->ap;
669a5db4	52	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
92ae7849	53	static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
669a5db4	54
92ae7849	55	if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
c961922b	56	return -ENOENT;
d4b2bab4	57
9363c382	58	return ata_sff_prereset(link, deadline);
669a5db4 JG	59	}
669a5db4 JG	60
669a5db4 JG	61	/**
	62	* mpiix_set_piomode - set initial PIO mode data
	63	* @ap: ATA interface
	64	* @adev: ATA device
	65	*
	66	* Called to do the PIO mode setup. The MPIIX allows us to program the
7b4f1a13 SS	67	* IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
7b4f1a13 SS	68	* prefetching or IORDY are used.
669a5db4 JG	69	*
	70	* This would get very ugly because we can only program timing for one
	71	* device at a time, the other gets PIO0. Fortunately libata calls
9363c382 TH	72	* our qc_issue command before a command is issued so we can flip the
9363c382 TH	73	* timings back and forth to reduce the pain.
669a5db4 JG	74	*/
	75
	76	static void mpiix_set_piomode(struct ata_port ap, struct ata_device adev)
	77	{
	78	int control = 0;
	79	int pio = adev->pio_mode - XFER_PIO_0;
	80	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	81	u16 idetim;
	82	static const /* ISP RTC */
	83	u8 timings[][2] = { { 0, 0 },
	84	{ 0, 0 },
	85	{ 1, 0 },
	86	{ 2, 1 },
	87	{ 2, 3 }, };
	88
	89	pci_read_config_word(pdev, IDETIM, &idetim);
7b4f1a13 SS	90
7b4f1a13 SS	91	/* Mask the IORDY/TIME/PPE for this device */
669a5db4	92	if (adev->class == ATA_DEV_ATA)
7b4f1a13	93	control \|= PPE; /* Enable prefetch/posting for disk */
669a5db4	94	if (ata_pio_need_iordy(adev))
7b4f1a13 SS	95	control \|= IORDY;
7b4f1a13 SS	96	if (pio > 1)
669a5db4 JG	97	control \|= FTIM; /* This drive is on the fast timing bank */
	98
	99	/* Mask out timing and clear both TIME bank selects */
	100	idetim &= 0xCCEE;
7b4f1a13 SS	101	idetim &= ~(0x07 << (4 * adev->devno));
7b4f1a13 SS	102	idetim \|= control << (4 * adev->devno);
669a5db4 JG	103
	104	idetim \|= (timings[pio][0] << 12) \| (timings[pio][1] << 8);
	105	pci_write_config_word(pdev, IDETIM, idetim);
	106
	107	/* We use ap->private_data as a pointer to the device currently
	108	loaded for timing */
	109	ap->private_data = adev;
	110	}
	111
	112	/**
9363c382	113	* mpiix_qc_issue - command issue
669a5db4 JG	114	* @qc: command pending
	115	*
	116	* Called when the libata layer is about to issue a command. We wrap
	117	* this interface so that we can load the correct ATA timings if
3a4fa0a2	118	* necessary. Our logic also clears TIME0/TIME1 for the other device so
669a5db4 JG	119	* that, even if we get this wrong, cycles to the other device will
	120	* be made PIO0.
	121	*/
	122
9363c382	123	static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
669a5db4 JG	124	{
	125	struct ata_port *ap = qc->ap;
	126	struct ata_device *adev = qc->dev;
	127
	128	/* If modes have been configured and the channel data is not loaded
	129	then load it. We have to check if pio_mode is set as the core code
	130	does not set adev->pio_mode to XFER_PIO_0 while probing as would be
	131	logical */
	132
	133	if (adev->pio_mode && adev != ap->private_data)
	134	mpiix_set_piomode(ap, adev);
	135
9363c382	136	return ata_sff_qc_issue(qc);
669a5db4 JG	137	}
	138
	139	static struct scsi_host_template mpiix_sht = {
68d1d07b	140	ATA_PIO_SHT(DRV_NAME),
669a5db4 JG	141	};
	142
	143	static struct ata_port_operations mpiix_port_ops = {
029cfd6b	144	.inherits = &ata_sff_port_ops,
9363c382	145	.qc_issue = mpiix_qc_issue,
029cfd6b	146	.cable_detect = ata_cable_40wire,
669a5db4	147	.set_piomode = mpiix_set_piomode,
a1efdaba	148	.prereset = mpiix_pre_reset,
871af121	149	.sff_data_xfer = ata_sff_data_xfer32,
669a5db4 JG	150	};
	151
	152	static int mpiix_init_one(struct pci_dev dev, const struct pci_device_id id)
	153	{
	154	/* Single threaded by the PCI probe logic */
669a5db4	155	static int printed_version;
5d728824 TH	156	struct ata_host *host;
5d728824 TH	157	struct ata_port *ap;
0d5ff566	158	void __iomem cmd_addr, ctl_addr;
669a5db4	159	u16 idetim;
cbcdd875	160	int cmd, ctl, irq;
669a5db4 JG	161
	162	if (!printed_version++)
	163	dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
	164
5d728824 TH	165	host = ata_host_alloc(&dev->dev, 1);
	166	if (!host)
	167	return -ENOMEM;
cbcdd875	168	ap = host->ports[0];
5d728824	169
669a5db4 JG	170	/* MPIIX has many functions which can be turned on or off according
	171	to other devices present. Make sure IDE is enabled before we try
	172	and use it */
	173
	174	pci_read_config_word(dev, IDETIM, &idetim);
	175	if (!(idetim & ENABLED))
	176	return -ENODEV;
	177
92ae7849	178	/* See if it's primary or secondary channel... */
0d5ff566	179	if (!(idetim & SECONDARY)) {
cbcdd875 TH	180	cmd = 0x1F0;
cbcdd875 TH	181	ctl = 0x3F6;
0d5ff566	182	irq = 14;
0d5ff566	183	} else {
cbcdd875 TH	184	cmd = 0x170;
cbcdd875 TH	185	ctl = 0x376;
0d5ff566	186	irq = 15;
0d5ff566 TH	187	}
0d5ff566 TH	188
cbcdd875 TH	189	cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
cbcdd875 TH	190	ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
0d5ff566 TH	191	if (!cmd_addr \|\| !ctl_addr)
	192	return -ENOMEM;
	193
cbcdd875 TH	194	ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
cbcdd875 TH	195
669a5db4 JG	196	/* We do our own plumbing to avoid leaking special cases for whacko
	197	ancient hardware into the core code. There are two issues to
	198	worry about. #1 The chip is a bridge so if in legacy mode and
	199	without BARs set fools the setup. #2 If you pci_disable_device
	200	the MPIIX your box goes castors up */
	201
5d728824	202	ap->ops = &mpiix_port_ops;
14bdef98	203	ap->pio_mask = ATA_PIO4;
5d728824	204	ap->flags \|= ATA_FLAG_SLAVE_POSS;
92ae7849	205
5d728824 TH	206	ap->ioaddr.cmd_addr = cmd_addr;
	207	ap->ioaddr.ctl_addr = ctl_addr;
	208	ap->ioaddr.altstatus_addr = ctl_addr;
669a5db4 JG	209
669a5db4 JG	210	/* Let libata fill in the port details */
9363c382	211	ata_sff_std_ports(&ap->ioaddr);
669a5db4	212
5d728824	213	/* activate host */
9363c382	214	return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED,
5d728824	215	&mpiix_sht);
669a5db4 JG	216	}
669a5db4 JG	217
669a5db4	218	static const struct pci_device_id mpiix[] = {
2d2744fc JG	219	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
	220
	221	{ },
669a5db4 JG	222	};
	223
	224	static struct pci_driver mpiix_pci_driver = {
	225	.name = DRV_NAME,
	226	.id_table = mpiix,
	227	.probe = mpiix_init_one,
24dc5f33	228	.remove = ata_pci_remove_one,
438ac6d5	229	#ifdef CONFIG_PM
30ced0f0 AC	230	.suspend = ata_pci_device_suspend,
30ced0f0 AC	231	.resume = ata_pci_device_resume,
438ac6d5	232	#endif
669a5db4 JG	233	};
	234
	235	static int __init mpiix_init(void)
	236	{
	237	return pci_register_driver(&mpiix_pci_driver);
	238	}
	239
669a5db4 JG	240	static void __exit mpiix_exit(void)
	241	{
	242	pci_unregister_driver(&mpiix_pci_driver);
	243	}
	244
669a5db4 JG	245	MODULE_AUTHOR("Alan Cox");
	246	MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
	247	MODULE_LICENSE("GPL");
	248	MODULE_DEVICE_TABLE(pci, mpiix);
	249	MODULE_VERSION(DRV_VERSION);
	250
	251	module_init(mpiix_init);
	252	module_exit(mpiix_exit);