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669a5db4 JG |
1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. | |
3 | * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * An ATA driver for the legacy ATA ports. | |
20 | * | |
21 | * Data Sources: | |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com | |
23 | * HT6560 series: | |
24 | * Promise 20230/20620: | |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html | |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html | |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html | |
28 | * | |
29 | * Unsupported but docs exist: | |
30 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 | |
669a5db4 JG |
31 | * |
32 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found | |
33 | * on PC class systems. There are three hybrid devices that are exceptions | |
34 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and | |
35 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". | |
36 | * | |
37 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ | |
b8325487 | 38 | * opti82c465mv/promise 20230c/20630/winbond83759A |
669a5db4 JG |
39 | * |
40 | * Use the autospeed and pio_mask options with: | |
41 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. | |
42 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with | |
43 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, | |
44 | * Winbond W83759A, Promise PDC20230-B | |
45 | * | |
46 | * For now use autospeed and pio_mask as above with the W83759A. This may | |
47 | * change. | |
48 | * | |
669a5db4 JG |
49 | */ |
50 | ||
51 | #include <linux/kernel.h> | |
52 | #include <linux/module.h> | |
53 | #include <linux/pci.h> | |
54 | #include <linux/init.h> | |
55 | #include <linux/blkdev.h> | |
56 | #include <linux/delay.h> | |
57 | #include <scsi/scsi_host.h> | |
58 | #include <linux/ata.h> | |
59 | #include <linux/libata.h> | |
60 | #include <linux/platform_device.h> | |
61 | ||
62 | #define DRV_NAME "pata_legacy" | |
b8325487 | 63 | #define DRV_VERSION "0.6.5" |
669a5db4 JG |
64 | |
65 | #define NR_HOST 6 | |
66 | ||
defc9cd8 AC |
67 | static int all; |
68 | module_param(all, int, 0444); | |
69 | MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)"); | |
669a5db4 JG |
70 | |
71 | struct legacy_data { | |
72 | unsigned long timing; | |
73 | u8 clock[2]; | |
74 | u8 last; | |
75 | int fast; | |
76 | struct platform_device *platform_dev; | |
77 | ||
78 | }; | |
79 | ||
defc9cd8 AC |
80 | enum controller { |
81 | BIOS = 0, | |
82 | SNOOP = 1, | |
83 | PDC20230 = 2, | |
84 | HT6560A = 3, | |
85 | HT6560B = 4, | |
86 | OPTI611A = 5, | |
87 | OPTI46X = 6, | |
88 | QDI6500 = 7, | |
89 | QDI6580 = 8, | |
90 | QDI6580DP = 9, /* Dual channel mode is different */ | |
b8325487 | 91 | W83759A = 10, |
defc9cd8 AC |
92 | |
93 | UNKNOWN = -1 | |
94 | }; | |
95 | ||
96 | ||
97 | struct legacy_probe { | |
98 | unsigned char *name; | |
99 | unsigned long port; | |
100 | unsigned int irq; | |
101 | unsigned int slot; | |
102 | enum controller type; | |
103 | unsigned long private; | |
104 | }; | |
105 | ||
106 | struct legacy_controller { | |
107 | const char *name; | |
108 | struct ata_port_operations *ops; | |
109 | unsigned int pio_mask; | |
110 | unsigned int flags; | |
b8325487 AC |
111 | int (*setup)(struct platform_device *, struct legacy_probe *probe, |
112 | struct legacy_data *data); | |
defc9cd8 AC |
113 | }; |
114 | ||
115 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; | |
116 | ||
117 | static struct legacy_probe probe_list[NR_HOST]; | |
669a5db4 JG |
118 | static struct legacy_data legacy_data[NR_HOST]; |
119 | static struct ata_host *legacy_host[NR_HOST]; | |
120 | static int nr_legacy_host; | |
121 | ||
122 | ||
defc9cd8 AC |
123 | static int probe_all; /* Set to check all ISA port ranges */ |
124 | static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */ | |
125 | static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */ | |
126 | static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */ | |
127 | static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */ | |
128 | static int qdi; /* Set to probe QDI controllers */ | |
b8325487 | 129 | static int winbond; /* Set to probe Winbond controllers, |
8397248d | 130 | give I/O port if non standard */ |
defc9cd8 AC |
131 | static int autospeed; /* Chip present which snoops speed changes */ |
132 | static int pio_mask = 0x1F; /* PIO range for autospeed devices */ | |
f834e49f | 133 | static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
669a5db4 | 134 | |
defc9cd8 AC |
135 | /** |
136 | * legacy_probe_add - Add interface to probe list | |
137 | * @port: Controller port | |
138 | * @irq: IRQ number | |
139 | * @type: Controller type | |
140 | * @private: Controller specific info | |
141 | * | |
142 | * Add an entry into the probe list for ATA controllers. This is used | |
143 | * to add the default ISA slots and then to build up the table | |
144 | * further according to other ISA/VLB/Weird device scans | |
145 | * | |
146 | * An I/O port list is used to keep ordering stable and sane, as we | |
147 | * don't have any good way to talk about ordering otherwise | |
148 | */ | |
149 | ||
150 | static int legacy_probe_add(unsigned long port, unsigned int irq, | |
151 | enum controller type, unsigned long private) | |
152 | { | |
153 | struct legacy_probe *lp = &probe_list[0]; | |
154 | int i; | |
155 | struct legacy_probe *free = NULL; | |
156 | ||
157 | for (i = 0; i < NR_HOST; i++) { | |
158 | if (lp->port == 0 && free == NULL) | |
159 | free = lp; | |
160 | /* Matching port, or the correct slot for ordering */ | |
161 | if (lp->port == port || legacy_port[i] == port) { | |
162 | free = lp; | |
163 | break; | |
164 | } | |
165 | lp++; | |
166 | } | |
167 | if (free == NULL) { | |
168 | printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); | |
169 | return -1; | |
170 | } | |
171 | /* Fill in the entry for later probing */ | |
172 | free->port = port; | |
173 | free->irq = irq; | |
174 | free->type = type; | |
175 | free->private = private; | |
176 | return 0; | |
177 | } | |
178 | ||
179 | ||
669a5db4 JG |
180 | /** |
181 | * legacy_set_mode - mode setting | |
0260731f | 182 | * @link: IDE link |
b229a7b0 | 183 | * @unused: Device that failed when error is returned |
669a5db4 JG |
184 | * |
185 | * Use a non standard set_mode function. We don't want to be tuned. | |
186 | * | |
187 | * The BIOS configured everything. Our job is not to fiddle. Just use | |
188 | * whatever PIO the hardware is using and leave it at that. When we | |
189 | * get some kind of nice user driven API for control then we can | |
190 | * expand on this as per hdparm in the base kernel. | |
191 | */ | |
192 | ||
0260731f | 193 | static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) |
669a5db4 | 194 | { |
f58229f8 | 195 | struct ata_device *dev; |
669a5db4 | 196 | |
0260731f | 197 | ata_link_for_each_dev(dev, link) { |
669a5db4 | 198 | if (ata_dev_enabled(dev)) { |
defc9cd8 AC |
199 | ata_dev_printk(dev, KERN_INFO, |
200 | "configured for PIO\n"); | |
669a5db4 JG |
201 | dev->pio_mode = XFER_PIO_0; |
202 | dev->xfer_mode = XFER_PIO_0; | |
203 | dev->xfer_shift = ATA_SHIFT_PIO; | |
204 | dev->flags |= ATA_DFLAG_PIO; | |
205 | } | |
206 | } | |
b229a7b0 | 207 | return 0; |
669a5db4 JG |
208 | } |
209 | ||
210 | static struct scsi_host_template legacy_sht = { | |
68d1d07b | 211 | ATA_PIO_SHT(DRV_NAME), |
669a5db4 JG |
212 | }; |
213 | ||
214 | /* | |
215 | * These ops are used if the user indicates the hardware | |
216 | * snoops the commands to decide on the mode and handles the | |
217 | * mode selection "magically" itself. Several legacy controllers | |
218 | * do this. The mode range can be set if it is not 0x1F by setting | |
219 | * pio_mask as well. | |
220 | */ | |
221 | ||
222 | static struct ata_port_operations simple_port_ops = { | |
669a5db4 JG |
223 | .tf_load = ata_tf_load, |
224 | .tf_read = ata_tf_read, | |
225 | .check_status = ata_check_status, | |
226 | .exec_command = ata_exec_command, | |
227 | .dev_select = ata_std_dev_select, | |
228 | ||
229 | .freeze = ata_bmdma_freeze, | |
230 | .thaw = ata_bmdma_thaw, | |
231 | .error_handler = ata_bmdma_error_handler, | |
232 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a73984a0 | 233 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
234 | |
235 | .qc_prep = ata_qc_prep, | |
236 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 237 | |
0d5ff566 | 238 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
239 | |
240 | .irq_handler = ata_interrupt, | |
358f9a77 | 241 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 242 | .irq_on = ata_irq_on, |
669a5db4 | 243 | |
defc9cd8 | 244 | .port_start = ata_sff_port_start, |
669a5db4 JG |
245 | }; |
246 | ||
247 | static struct ata_port_operations legacy_port_ops = { | |
248 | .set_mode = legacy_set_mode, | |
249 | ||
669a5db4 JG |
250 | .tf_load = ata_tf_load, |
251 | .tf_read = ata_tf_read, | |
252 | .check_status = ata_check_status, | |
253 | .exec_command = ata_exec_command, | |
254 | .dev_select = ata_std_dev_select, | |
a73984a0 | 255 | .cable_detect = ata_cable_40wire, |
669a5db4 | 256 | |
bf7551c4 JG |
257 | .freeze = ata_bmdma_freeze, |
258 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 259 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 260 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
261 | |
262 | .qc_prep = ata_qc_prep, | |
263 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 264 | |
0d5ff566 | 265 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
266 | |
267 | .irq_handler = ata_interrupt, | |
358f9a77 | 268 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 269 | .irq_on = ata_irq_on, |
669a5db4 | 270 | |
defc9cd8 | 271 | .port_start = ata_sff_port_start, |
669a5db4 JG |
272 | }; |
273 | ||
274 | /* | |
275 | * Promise 20230C and 20620 support | |
276 | * | |
defc9cd8 AC |
277 | * This controller supports PIO0 to PIO2. We set PIO timings |
278 | * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA | |
279 | * support is weird being DMA to controller and PIO'd to the host | |
280 | * and not supported. | |
669a5db4 JG |
281 | */ |
282 | ||
283 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
284 | { | |
285 | int tries = 5; | |
286 | int pio = adev->pio_mode - XFER_PIO_0; | |
287 | u8 rt; | |
288 | unsigned long flags; | |
85cd7251 | 289 | |
669a5db4 | 290 | /* Safe as UP only. Force I/Os to occur together */ |
85cd7251 | 291 | |
669a5db4 | 292 | local_irq_save(flags); |
85cd7251 | 293 | |
669a5db4 | 294 | /* Unlock the control interface */ |
defc9cd8 | 295 | do { |
669a5db4 JG |
296 | inb(0x1F5); |
297 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
298 | inb(0x1F2); | |
299 | inb(0x3F6); | |
300 | inb(0x3F6); | |
301 | inb(0x1F2); | |
302 | inb(0x1F2); | |
303 | } | |
defc9cd8 | 304 | while ((inb(0x1F2) & 0x80) && --tries); |
669a5db4 JG |
305 | |
306 | local_irq_restore(flags); | |
85cd7251 | 307 | |
669a5db4 JG |
308 | outb(inb(0x1F4) & 0x07, 0x1F4); |
309 | ||
310 | rt = inb(0x1F3); | |
311 | rt &= 0x07 << (3 * adev->devno); | |
312 | if (pio) | |
313 | rt |= (1 + 3 * pio) << (3 * adev->devno); | |
314 | ||
315 | udelay(100); | |
316 | outb(inb(0x1F2) | 0x01, 0x1F2); | |
317 | udelay(100); | |
318 | inb(0x1F5); | |
319 | ||
320 | } | |
321 | ||
55dba312 | 322 | static unsigned int pdc_data_xfer_vlb(struct ata_device *dev, |
defc9cd8 | 323 | unsigned char *buf, unsigned int buflen, int rw) |
669a5db4 | 324 | { |
c294f1b3 | 325 | if (ata_id_has_dword_io(dev->id)) { |
55dba312 TH |
326 | struct ata_port *ap = dev->link->ap; |
327 | int slop = buflen & 3; | |
328 | unsigned long flags; | |
329 | ||
669a5db4 JG |
330 | local_irq_save(flags); |
331 | ||
332 | /* Perform the 32bit I/O synchronization sequence */ | |
0d5ff566 TH |
333 | ioread8(ap->ioaddr.nsect_addr); |
334 | ioread8(ap->ioaddr.nsect_addr); | |
335 | ioread8(ap->ioaddr.nsect_addr); | |
669a5db4 JG |
336 | |
337 | /* Now the data */ | |
55dba312 | 338 | if (rw == READ) |
0d5ff566 | 339 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
55dba312 TH |
340 | else |
341 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 JG |
342 | |
343 | if (unlikely(slop)) { | |
55dba312 TH |
344 | u32 pad; |
345 | if (rw == READ) { | |
b50e56d8 | 346 | pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); |
669a5db4 | 347 | memcpy(buf + buflen - slop, &pad, slop); |
55dba312 TH |
348 | } else { |
349 | memcpy(&pad, buf + buflen - slop, slop); | |
350 | iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); | |
669a5db4 | 351 | } |
55dba312 | 352 | buflen += 4 - slop; |
669a5db4 JG |
353 | } |
354 | local_irq_restore(flags); | |
55dba312 TH |
355 | } else |
356 | buflen = ata_data_xfer_noirq(dev, buf, buflen, rw); | |
357 | ||
358 | return buflen; | |
669a5db4 JG |
359 | } |
360 | ||
361 | static struct ata_port_operations pdc20230_port_ops = { | |
362 | .set_piomode = pdc20230_set_piomode, | |
363 | ||
669a5db4 JG |
364 | .tf_load = ata_tf_load, |
365 | .tf_read = ata_tf_read, | |
366 | .check_status = ata_check_status, | |
367 | .exec_command = ata_exec_command, | |
368 | .dev_select = ata_std_dev_select, | |
369 | ||
bf7551c4 JG |
370 | .freeze = ata_bmdma_freeze, |
371 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 372 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 373 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 374 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
375 | |
376 | .qc_prep = ata_qc_prep, | |
377 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 378 | |
669a5db4 JG |
379 | .data_xfer = pdc_data_xfer_vlb, |
380 | ||
381 | .irq_handler = ata_interrupt, | |
358f9a77 | 382 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 383 | .irq_on = ata_irq_on, |
669a5db4 | 384 | |
defc9cd8 | 385 | .port_start = ata_sff_port_start, |
669a5db4 JG |
386 | }; |
387 | ||
388 | /* | |
389 | * Holtek 6560A support | |
390 | * | |
defc9cd8 AC |
391 | * This controller supports PIO0 to PIO2 (no IORDY even though higher |
392 | * timings can be loaded). | |
669a5db4 JG |
393 | */ |
394 | ||
395 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
396 | { | |
397 | u8 active, recover; | |
398 | struct ata_timing t; | |
399 | ||
400 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
401 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
402 | ||
403 | active = FIT(t.active, 2, 15); | |
404 | recover = FIT(t.recover, 4, 15); | |
405 | ||
406 | inb(0x3E6); | |
407 | inb(0x3E6); | |
408 | inb(0x3E6); | |
409 | inb(0x3E6); | |
410 | ||
0d5ff566 TH |
411 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
412 | ioread8(ap->ioaddr.status_addr); | |
669a5db4 JG |
413 | } |
414 | ||
415 | static struct ata_port_operations ht6560a_port_ops = { | |
416 | .set_piomode = ht6560a_set_piomode, | |
417 | ||
669a5db4 JG |
418 | .tf_load = ata_tf_load, |
419 | .tf_read = ata_tf_read, | |
420 | .check_status = ata_check_status, | |
421 | .exec_command = ata_exec_command, | |
422 | .dev_select = ata_std_dev_select, | |
423 | ||
bf7551c4 JG |
424 | .freeze = ata_bmdma_freeze, |
425 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 426 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 427 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 428 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
429 | |
430 | .qc_prep = ata_qc_prep, | |
431 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 432 | |
0d5ff566 | 433 | .data_xfer = ata_data_xfer, /* Check vlb/noirq */ |
669a5db4 JG |
434 | |
435 | .irq_handler = ata_interrupt, | |
358f9a77 | 436 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 437 | .irq_on = ata_irq_on, |
669a5db4 | 438 | |
defc9cd8 | 439 | .port_start = ata_sff_port_start, |
669a5db4 JG |
440 | }; |
441 | ||
442 | /* | |
443 | * Holtek 6560B support | |
444 | * | |
defc9cd8 AC |
445 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO |
446 | * setting unless we see an ATAPI device in which case we force it off. | |
669a5db4 JG |
447 | * |
448 | * FIXME: need to implement 2nd channel support. | |
449 | */ | |
450 | ||
451 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
452 | { | |
453 | u8 active, recover; | |
454 | struct ata_timing t; | |
455 | ||
456 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
457 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
458 | ||
459 | active = FIT(t.active, 2, 15); | |
460 | recover = FIT(t.recover, 2, 16); | |
461 | recover &= 0x15; | |
462 | ||
463 | inb(0x3E6); | |
464 | inb(0x3E6); | |
465 | inb(0x3E6); | |
466 | inb(0x3E6); | |
467 | ||
0d5ff566 | 468 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
669a5db4 JG |
469 | |
470 | if (adev->class != ATA_DEV_ATA) { | |
471 | u8 rconf = inb(0x3E6); | |
472 | if (rconf & 0x24) { | |
defc9cd8 | 473 | rconf &= ~0x24; |
669a5db4 JG |
474 | outb(rconf, 0x3E6); |
475 | } | |
476 | } | |
0d5ff566 | 477 | ioread8(ap->ioaddr.status_addr); |
669a5db4 JG |
478 | } |
479 | ||
480 | static struct ata_port_operations ht6560b_port_ops = { | |
481 | .set_piomode = ht6560b_set_piomode, | |
482 | ||
669a5db4 JG |
483 | .tf_load = ata_tf_load, |
484 | .tf_read = ata_tf_read, | |
485 | .check_status = ata_check_status, | |
486 | .exec_command = ata_exec_command, | |
487 | .dev_select = ata_std_dev_select, | |
488 | ||
bf7551c4 JG |
489 | .freeze = ata_bmdma_freeze, |
490 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 491 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 492 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 493 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
494 | |
495 | .qc_prep = ata_qc_prep, | |
496 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 497 | |
defc9cd8 | 498 | .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */ |
669a5db4 JG |
499 | |
500 | .irq_handler = ata_interrupt, | |
358f9a77 | 501 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 502 | .irq_on = ata_irq_on, |
669a5db4 | 503 | |
defc9cd8 | 504 | .port_start = ata_sff_port_start, |
669a5db4 JG |
505 | }; |
506 | ||
507 | /* | |
508 | * Opti core chipset helpers | |
509 | */ | |
85cd7251 | 510 | |
669a5db4 JG |
511 | /** |
512 | * opti_syscfg - read OPTI chipset configuration | |
513 | * @reg: Configuration register to read | |
514 | * | |
515 | * Returns the value of an OPTI system board configuration register. | |
516 | */ | |
517 | ||
518 | static u8 opti_syscfg(u8 reg) | |
519 | { | |
520 | unsigned long flags; | |
521 | u8 r; | |
85cd7251 | 522 | |
669a5db4 JG |
523 | /* Uniprocessor chipset and must force cycles adjancent */ |
524 | local_irq_save(flags); | |
525 | outb(reg, 0x22); | |
526 | r = inb(0x24); | |
527 | local_irq_restore(flags); | |
528 | return r; | |
529 | } | |
530 | ||
531 | /* | |
532 | * Opti 82C611A | |
533 | * | |
534 | * This controller supports PIO0 to PIO3. | |
535 | */ | |
536 | ||
defc9cd8 AC |
537 | static void opti82c611a_set_piomode(struct ata_port *ap, |
538 | struct ata_device *adev) | |
669a5db4 JG |
539 | { |
540 | u8 active, recover, setup; | |
541 | struct ata_timing t; | |
542 | struct ata_device *pair = ata_dev_pair(adev); | |
543 | int clock; | |
544 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
545 | u8 rc; | |
546 | ||
547 | /* Enter configuration mode */ | |
0d5ff566 TH |
548 | ioread16(ap->ioaddr.error_addr); |
549 | ioread16(ap->ioaddr.error_addr); | |
550 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
551 | |
552 | /* Read VLB clock strapping */ | |
0d5ff566 | 553 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
669a5db4 JG |
554 | |
555 | /* Get the timing data in cycles */ | |
556 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
557 | ||
558 | /* Setup timing is shared */ | |
559 | if (pair) { | |
560 | struct ata_timing tp; | |
561 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
562 | ||
563 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
564 | } | |
565 | ||
566 | active = FIT(t.active, 2, 17) - 2; | |
567 | recover = FIT(t.recover, 1, 16) - 1; | |
568 | setup = FIT(t.setup, 1, 4) - 1; | |
569 | ||
570 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 571 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
572 | rc &= 0x7F; |
573 | rc |= (adev->devno << 7); | |
0d5ff566 | 574 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
575 | |
576 | /* Write the timings */ | |
0d5ff566 | 577 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
578 | |
579 | /* Select the right bank for read timings, also | |
580 | load the shared timings for address */ | |
0d5ff566 | 581 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
582 | rc &= 0xC0; |
583 | rc |= adev->devno; /* Index select */ | |
584 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 585 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
586 | |
587 | /* Load the read timings */ | |
0d5ff566 | 588 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
589 | |
590 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 591 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
592 | rc &= 0x73; |
593 | rc |= 0x84; | |
0d5ff566 | 594 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
595 | |
596 | /* Exit command mode */ | |
0d5ff566 | 597 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
598 | } |
599 | ||
600 | ||
601 | static struct ata_port_operations opti82c611a_port_ops = { | |
602 | .set_piomode = opti82c611a_set_piomode, | |
603 | ||
669a5db4 JG |
604 | .tf_load = ata_tf_load, |
605 | .tf_read = ata_tf_read, | |
606 | .check_status = ata_check_status, | |
607 | .exec_command = ata_exec_command, | |
608 | .dev_select = ata_std_dev_select, | |
609 | ||
bf7551c4 JG |
610 | .freeze = ata_bmdma_freeze, |
611 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 612 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 613 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 614 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
615 | |
616 | .qc_prep = ata_qc_prep, | |
617 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 618 | |
0d5ff566 | 619 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
620 | |
621 | .irq_handler = ata_interrupt, | |
358f9a77 | 622 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 623 | .irq_on = ata_irq_on, |
669a5db4 | 624 | |
defc9cd8 | 625 | .port_start = ata_sff_port_start, |
669a5db4 JG |
626 | }; |
627 | ||
628 | /* | |
629 | * Opti 82C465MV | |
630 | * | |
631 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB | |
632 | * version is dual channel but doesn't have a lot of unique registers. | |
633 | */ | |
634 | ||
635 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
636 | { | |
637 | u8 active, recover, setup; | |
638 | struct ata_timing t; | |
639 | struct ata_device *pair = ata_dev_pair(adev); | |
640 | int clock; | |
641 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
642 | u8 rc; | |
643 | u8 sysclk; | |
644 | ||
645 | /* Get the clock */ | |
646 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | |
647 | ||
648 | /* Enter configuration mode */ | |
0d5ff566 TH |
649 | ioread16(ap->ioaddr.error_addr); |
650 | ioread16(ap->ioaddr.error_addr); | |
651 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
652 | |
653 | /* Read VLB clock strapping */ | |
654 | clock = 1000000000 / khz[sysclk]; | |
655 | ||
656 | /* Get the timing data in cycles */ | |
657 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
658 | ||
659 | /* Setup timing is shared */ | |
660 | if (pair) { | |
661 | struct ata_timing tp; | |
662 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
663 | ||
664 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
665 | } | |
666 | ||
667 | active = FIT(t.active, 2, 17) - 2; | |
668 | recover = FIT(t.recover, 1, 16) - 1; | |
669 | setup = FIT(t.setup, 1, 4) - 1; | |
670 | ||
671 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 672 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
673 | rc &= 0x7F; |
674 | rc |= (adev->devno << 7); | |
0d5ff566 | 675 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
676 | |
677 | /* Write the timings */ | |
0d5ff566 | 678 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
679 | |
680 | /* Select the right bank for read timings, also | |
681 | load the shared timings for address */ | |
0d5ff566 | 682 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
683 | rc &= 0xC0; |
684 | rc |= adev->devno; /* Index select */ | |
685 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 686 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
687 | |
688 | /* Load the read timings */ | |
0d5ff566 | 689 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
690 | |
691 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 692 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
693 | rc &= 0x73; |
694 | rc |= 0x84; | |
0d5ff566 | 695 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
696 | |
697 | /* Exit command mode */ | |
0d5ff566 | 698 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
699 | |
700 | /* We need to know this for quad device on the MVB */ | |
701 | ap->host->private_data = ap; | |
702 | } | |
703 | ||
704 | /** | |
705 | * opt82c465mv_qc_issue_prot - command issue | |
706 | * @qc: command pending | |
707 | * | |
708 | * Called when the libata layer is about to issue a command. We wrap | |
709 | * this interface so that we can load the correct ATA timings. The | |
710 | * MVB has a single set of timing registers and these are shared | |
711 | * across channels. As there are two registers we really ought to | |
712 | * track the last two used values as a sort of register window. For | |
713 | * now we just reload on a channel switch. On the single channel | |
714 | * setup this condition never fires so we do nothing extra. | |
715 | * | |
716 | * FIXME: dual channel needs ->serialize support | |
717 | */ | |
718 | ||
719 | static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) | |
720 | { | |
721 | struct ata_port *ap = qc->ap; | |
722 | struct ata_device *adev = qc->dev; | |
723 | ||
724 | /* If timings are set and for the wrong channel (2nd test is | |
725 | due to a libata shortcoming and will eventually go I hope) */ | |
726 | if (ap->host->private_data != ap->host | |
727 | && ap->host->private_data != NULL) | |
728 | opti82c46x_set_piomode(ap, adev); | |
729 | ||
730 | return ata_qc_issue_prot(qc); | |
731 | } | |
732 | ||
733 | static struct ata_port_operations opti82c46x_port_ops = { | |
734 | .set_piomode = opti82c46x_set_piomode, | |
735 | ||
669a5db4 JG |
736 | .tf_load = ata_tf_load, |
737 | .tf_read = ata_tf_read, | |
738 | .check_status = ata_check_status, | |
739 | .exec_command = ata_exec_command, | |
740 | .dev_select = ata_std_dev_select, | |
741 | ||
bf7551c4 JG |
742 | .freeze = ata_bmdma_freeze, |
743 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 744 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 745 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
a73984a0 | 746 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
747 | |
748 | .qc_prep = ata_qc_prep, | |
749 | .qc_issue = opti82c46x_qc_issue_prot, | |
bda30288 | 750 | |
0d5ff566 | 751 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
752 | |
753 | .irq_handler = ata_interrupt, | |
358f9a77 | 754 | .irq_clear = ata_noop_irq_clear, |
246ce3b6 | 755 | .irq_on = ata_irq_on, |
669a5db4 | 756 | |
defc9cd8 | 757 | .port_start = ata_sff_port_start, |
669a5db4 JG |
758 | }; |
759 | ||
defc9cd8 AC |
760 | static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev) |
761 | { | |
762 | struct ata_timing t; | |
cb616dd5 | 763 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
764 | int active, recovery; |
765 | u8 timing; | |
766 | ||
767 | /* Get the timing data in cycles */ | |
768 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
769 | ||
cb616dd5 | 770 | if (ld_qdi->fast) { |
defc9cd8 AC |
771 | active = 8 - FIT(t.active, 1, 8); |
772 | recovery = 18 - FIT(t.recover, 3, 18); | |
773 | } else { | |
774 | active = 9 - FIT(t.active, 2, 9); | |
775 | recovery = 15 - FIT(t.recover, 0, 15); | |
776 | } | |
777 | timing = (recovery << 4) | active | 0x08; | |
778 | ||
cb616dd5 | 779 | ld_qdi->clock[adev->devno] = timing; |
defc9cd8 | 780 | |
cb616dd5 | 781 | outb(timing, ld_qdi->timing); |
defc9cd8 | 782 | } |
669a5db4 JG |
783 | |
784 | /** | |
defc9cd8 AC |
785 | * qdi6580dp_set_piomode - PIO setup for dual channel |
786 | * @ap: Port | |
787 | * @adev: Device | |
669a5db4 JG |
788 | * @irq: interrupt line |
789 | * | |
defc9cd8 AC |
790 | * In dual channel mode the 6580 has one clock per channel and we have |
791 | * to software clockswitch in qc_issue_prot. | |
669a5db4 JG |
792 | */ |
793 | ||
defc9cd8 | 794 | static void qdi6580dp_set_piomode(struct ata_port *ap, struct ata_device *adev) |
669a5db4 | 795 | { |
defc9cd8 | 796 | struct ata_timing t; |
cb616dd5 | 797 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
798 | int active, recovery; |
799 | u8 timing; | |
669a5db4 | 800 | |
defc9cd8 AC |
801 | /* Get the timing data in cycles */ |
802 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
803 | ||
cb616dd5 | 804 | if (ld_qdi->fast) { |
defc9cd8 AC |
805 | active = 8 - FIT(t.active, 1, 8); |
806 | recovery = 18 - FIT(t.recover, 3, 18); | |
807 | } else { | |
808 | active = 9 - FIT(t.active, 2, 9); | |
809 | recovery = 15 - FIT(t.recover, 0, 15); | |
810 | } | |
811 | timing = (recovery << 4) | active | 0x08; | |
24dc5f33 | 812 | |
cb616dd5 | 813 | ld_qdi->clock[adev->devno] = timing; |
669a5db4 | 814 | |
cb616dd5 | 815 | outb(timing, ld_qdi->timing + 2 * ap->port_no); |
defc9cd8 AC |
816 | /* Clear the FIFO */ |
817 | if (adev->class != ATA_DEV_ATA) | |
cb616dd5 | 818 | outb(0x5F, ld_qdi->timing + 3); |
defc9cd8 | 819 | } |
0d5ff566 | 820 | |
defc9cd8 AC |
821 | /** |
822 | * qdi6580_set_piomode - PIO setup for single channel | |
823 | * @ap: Port | |
824 | * @adev: Device | |
825 | * | |
826 | * In single channel mode the 6580 has one clock per device and we can | |
827 | * avoid the requirement to clock switch. We also have to load the timing | |
828 | * into the right clock according to whether we are master or slave. | |
829 | */ | |
830 | ||
831 | static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
832 | { | |
833 | struct ata_timing t; | |
cb616dd5 | 834 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 AC |
835 | int active, recovery; |
836 | u8 timing; | |
837 | ||
838 | /* Get the timing data in cycles */ | |
839 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
840 | ||
cb616dd5 | 841 | if (ld_qdi->fast) { |
defc9cd8 AC |
842 | active = 8 - FIT(t.active, 1, 8); |
843 | recovery = 18 - FIT(t.recover, 3, 18); | |
844 | } else { | |
845 | active = 9 - FIT(t.active, 2, 9); | |
846 | recovery = 15 - FIT(t.recover, 0, 15); | |
669a5db4 | 847 | } |
defc9cd8 | 848 | timing = (recovery << 4) | active | 0x08; |
cb616dd5 HH |
849 | ld_qdi->clock[adev->devno] = timing; |
850 | outb(timing, ld_qdi->timing + 2 * adev->devno); | |
defc9cd8 AC |
851 | /* Clear the FIFO */ |
852 | if (adev->class != ATA_DEV_ATA) | |
cb616dd5 | 853 | outb(0x5F, ld_qdi->timing + 3); |
defc9cd8 AC |
854 | } |
855 | ||
856 | /** | |
857 | * qdi_qc_issue_prot - command issue | |
858 | * @qc: command pending | |
859 | * | |
860 | * Called when the libata layer is about to issue a command. We wrap | |
861 | * this interface so that we can load the correct ATA timings. | |
862 | */ | |
863 | ||
864 | static unsigned int qdi_qc_issue_prot(struct ata_queued_cmd *qc) | |
865 | { | |
866 | struct ata_port *ap = qc->ap; | |
867 | struct ata_device *adev = qc->dev; | |
cb616dd5 | 868 | struct legacy_data *ld_qdi = ap->host->private_data; |
defc9cd8 | 869 | |
cb616dd5 | 870 | if (ld_qdi->clock[adev->devno] != ld_qdi->last) { |
defc9cd8 | 871 | if (adev->pio_mode) { |
cb616dd5 HH |
872 | ld_qdi->last = ld_qdi->clock[adev->devno]; |
873 | outb(ld_qdi->clock[adev->devno], ld_qdi->timing + | |
defc9cd8 AC |
874 | 2 * ap->port_no); |
875 | } | |
669a5db4 | 876 | } |
defc9cd8 AC |
877 | return ata_qc_issue_prot(qc); |
878 | } | |
669a5db4 | 879 | |
b8325487 | 880 | static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf, |
defc9cd8 AC |
881 | unsigned int buflen, int rw) |
882 | { | |
883 | struct ata_port *ap = adev->link->ap; | |
884 | int slop = buflen & 3; | |
669a5db4 | 885 | |
defc9cd8 AC |
886 | if (ata_id_has_dword_io(adev->id)) { |
887 | if (rw == WRITE) | |
888 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
889 | else | |
890 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); | |
669a5db4 | 891 | |
defc9cd8 AC |
892 | if (unlikely(slop)) { |
893 | u32 pad; | |
894 | if (rw == WRITE) { | |
895 | memcpy(&pad, buf + buflen - slop, slop); | |
896 | pad = le32_to_cpu(pad); | |
897 | iowrite32(pad, ap->ioaddr.data_addr); | |
898 | } else { | |
899 | pad = ioread32(ap->ioaddr.data_addr); | |
900 | pad = cpu_to_le32(pad); | |
901 | memcpy(buf + buflen - slop, &pad, slop); | |
902 | } | |
903 | } | |
904 | return (buflen + 3) & ~3; | |
905 | } else | |
906 | return ata_data_xfer(adev, buf, buflen, rw); | |
907 | } | |
908 | ||
b8325487 AC |
909 | static int qdi_port(struct platform_device *dev, |
910 | struct legacy_probe *lp, struct legacy_data *ld) | |
911 | { | |
912 | if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) | |
913 | return -EBUSY; | |
914 | ld->timing = lp->private; | |
915 | return 0; | |
916 | } | |
917 | ||
defc9cd8 AC |
918 | static struct ata_port_operations qdi6500_port_ops = { |
919 | .set_piomode = qdi6500_set_piomode, | |
920 | ||
921 | .tf_load = ata_tf_load, | |
922 | .tf_read = ata_tf_read, | |
923 | .check_status = ata_check_status, | |
924 | .exec_command = ata_exec_command, | |
925 | .dev_select = ata_std_dev_select, | |
926 | ||
927 | .freeze = ata_bmdma_freeze, | |
928 | .thaw = ata_bmdma_thaw, | |
929 | .error_handler = ata_bmdma_error_handler, | |
930 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
931 | .cable_detect = ata_cable_40wire, | |
932 | ||
933 | .qc_prep = ata_qc_prep, | |
934 | .qc_issue = qdi_qc_issue_prot, | |
935 | ||
b8325487 | 936 | .data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
937 | |
938 | .irq_handler = ata_interrupt, | |
358f9a77 | 939 | .irq_clear = ata_noop_irq_clear, |
defc9cd8 AC |
940 | .irq_on = ata_irq_on, |
941 | ||
942 | .port_start = ata_sff_port_start, | |
943 | }; | |
944 | ||
945 | static struct ata_port_operations qdi6580_port_ops = { | |
946 | .set_piomode = qdi6580_set_piomode, | |
947 | ||
948 | .tf_load = ata_tf_load, | |
949 | .tf_read = ata_tf_read, | |
950 | .check_status = ata_check_status, | |
951 | .exec_command = ata_exec_command, | |
952 | .dev_select = ata_std_dev_select, | |
953 | ||
954 | .freeze = ata_bmdma_freeze, | |
955 | .thaw = ata_bmdma_thaw, | |
956 | .error_handler = ata_bmdma_error_handler, | |
957 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
958 | .cable_detect = ata_cable_40wire, | |
959 | ||
960 | .qc_prep = ata_qc_prep, | |
961 | .qc_issue = ata_qc_issue_prot, | |
962 | ||
b8325487 | 963 | .data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
964 | |
965 | .irq_handler = ata_interrupt, | |
358f9a77 | 966 | .irq_clear = ata_noop_irq_clear, |
defc9cd8 AC |
967 | .irq_on = ata_irq_on, |
968 | ||
969 | .port_start = ata_sff_port_start, | |
970 | }; | |
971 | ||
972 | static struct ata_port_operations qdi6580dp_port_ops = { | |
973 | .set_piomode = qdi6580dp_set_piomode, | |
974 | ||
975 | .tf_load = ata_tf_load, | |
976 | .tf_read = ata_tf_read, | |
977 | .check_status = ata_check_status, | |
978 | .exec_command = ata_exec_command, | |
979 | .dev_select = ata_std_dev_select, | |
980 | ||
981 | .freeze = ata_bmdma_freeze, | |
982 | .thaw = ata_bmdma_thaw, | |
983 | .error_handler = ata_bmdma_error_handler, | |
984 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
985 | .cable_detect = ata_cable_40wire, | |
986 | ||
987 | .qc_prep = ata_qc_prep, | |
988 | .qc_issue = qdi_qc_issue_prot, | |
989 | ||
b8325487 | 990 | .data_xfer = vlb32_data_xfer, |
defc9cd8 AC |
991 | |
992 | .irq_handler = ata_interrupt, | |
358f9a77 | 993 | .irq_clear = ata_noop_irq_clear, |
defc9cd8 AC |
994 | .irq_on = ata_irq_on, |
995 | ||
996 | .port_start = ata_sff_port_start, | |
997 | }; | |
998 | ||
b8325487 AC |
999 | static DEFINE_SPINLOCK(winbond_lock); |
1000 | ||
1001 | static void winbond_writecfg(unsigned long port, u8 reg, u8 val) | |
1002 | { | |
1003 | unsigned long flags; | |
1004 | spin_lock_irqsave(&winbond_lock, flags); | |
1005 | outb(reg, port + 0x01); | |
1006 | outb(val, port + 0x02); | |
1007 | spin_unlock_irqrestore(&winbond_lock, flags); | |
1008 | } | |
1009 | ||
1010 | static u8 winbond_readcfg(unsigned long port, u8 reg) | |
1011 | { | |
1012 | u8 val; | |
1013 | ||
1014 | unsigned long flags; | |
1015 | spin_lock_irqsave(&winbond_lock, flags); | |
1016 | outb(reg, port + 0x01); | |
1017 | val = inb(port + 0x02); | |
1018 | spin_unlock_irqrestore(&winbond_lock, flags); | |
1019 | ||
1020 | return val; | |
1021 | } | |
1022 | ||
1023 | static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
1024 | { | |
1025 | struct ata_timing t; | |
cb616dd5 | 1026 | struct legacy_data *ld_winbond = ap->host->private_data; |
b8325487 AC |
1027 | int active, recovery; |
1028 | u8 reg; | |
1029 | int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); | |
1030 | ||
cb616dd5 | 1031 | reg = winbond_readcfg(ld_winbond->timing, 0x81); |
b8325487 AC |
1032 | |
1033 | /* Get the timing data in cycles */ | |
1034 | if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ | |
1035 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
1036 | else | |
1037 | ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); | |
1038 | ||
1039 | active = (FIT(t.active, 3, 17) - 1) & 0x0F; | |
1040 | recovery = (FIT(t.recover, 1, 15) + 1) & 0x0F; | |
1041 | timing = (active << 4) | recovery; | |
cb616dd5 | 1042 | winbond_writecfg(ld_winbond->timing, timing, reg); |
b8325487 AC |
1043 | |
1044 | /* Load the setup timing */ | |
1045 | ||
1046 | reg = 0x35; | |
1047 | if (adev->class != ATA_DEV_ATA) | |
1048 | reg |= 0x08; /* FIFO off */ | |
1049 | if (!ata_pio_need_iordy(adev)) | |
1050 | reg |= 0x02; /* IORDY off */ | |
1051 | reg |= (FIT(t.setup, 0, 3) << 6); | |
cb616dd5 | 1052 | winbond_writecfg(ld_winbond->timing, timing + 1, reg); |
b8325487 AC |
1053 | } |
1054 | ||
1055 | static int winbond_port(struct platform_device *dev, | |
1056 | struct legacy_probe *lp, struct legacy_data *ld) | |
1057 | { | |
1058 | if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) | |
1059 | return -EBUSY; | |
1060 | ld->timing = lp->private; | |
1061 | return 0; | |
1062 | } | |
1063 | ||
1064 | static struct ata_port_operations winbond_port_ops = { | |
1065 | .set_piomode = winbond_set_piomode, | |
1066 | ||
1067 | .tf_load = ata_tf_load, | |
1068 | .tf_read = ata_tf_read, | |
1069 | .check_status = ata_check_status, | |
1070 | .exec_command = ata_exec_command, | |
1071 | .dev_select = ata_std_dev_select, | |
1072 | ||
1073 | .freeze = ata_bmdma_freeze, | |
1074 | .thaw = ata_bmdma_thaw, | |
1075 | .error_handler = ata_bmdma_error_handler, | |
1076 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1077 | .cable_detect = ata_cable_40wire, | |
1078 | ||
1079 | .qc_prep = ata_qc_prep, | |
1080 | .qc_issue = ata_qc_issue_prot, | |
1081 | ||
1082 | .data_xfer = vlb32_data_xfer, | |
1083 | ||
358f9a77 | 1084 | .irq_clear = ata_noop_irq_clear, |
b8325487 AC |
1085 | .irq_on = ata_irq_on, |
1086 | ||
1087 | .port_start = ata_sff_port_start, | |
1088 | }; | |
1089 | ||
defc9cd8 AC |
1090 | static struct legacy_controller controllers[] = { |
1091 | {"BIOS", &legacy_port_ops, 0x1F, | |
1092 | ATA_FLAG_NO_IORDY, NULL }, | |
1093 | {"Snooping", &simple_port_ops, 0x1F, | |
1094 | 0 , NULL }, | |
1095 | {"PDC20230", &pdc20230_port_ops, 0x7, | |
1096 | ATA_FLAG_NO_IORDY, NULL }, | |
1097 | {"HT6560A", &ht6560a_port_ops, 0x07, | |
1098 | ATA_FLAG_NO_IORDY, NULL }, | |
1099 | {"HT6560B", &ht6560b_port_ops, 0x1F, | |
1100 | ATA_FLAG_NO_IORDY, NULL }, | |
1101 | {"OPTI82C611A", &opti82c611a_port_ops, 0x0F, | |
1102 | 0 , NULL }, | |
1103 | {"OPTI82C46X", &opti82c46x_port_ops, 0x0F, | |
1104 | 0 , NULL }, | |
1105 | {"QDI6500", &qdi6500_port_ops, 0x07, | |
b8325487 | 1106 | ATA_FLAG_NO_IORDY, qdi_port }, |
defc9cd8 | 1107 | {"QDI6580", &qdi6580_port_ops, 0x1F, |
b8325487 | 1108 | 0 , qdi_port }, |
defc9cd8 | 1109 | {"QDI6580DP", &qdi6580dp_port_ops, 0x1F, |
b8325487 AC |
1110 | 0 , qdi_port }, |
1111 | {"W83759A", &winbond_port_ops, 0x1F, | |
1112 | 0 , winbond_port } | |
defc9cd8 AC |
1113 | }; |
1114 | ||
1115 | /** | |
1116 | * probe_chip_type - Discover controller | |
1117 | * @probe: Probe entry to check | |
1118 | * | |
1119 | * Probe an ATA port and identify the type of controller. We don't | |
1120 | * check if the controller appears to be driveless at this point. | |
1121 | */ | |
1122 | ||
b8325487 | 1123 | static __init int probe_chip_type(struct legacy_probe *probe) |
defc9cd8 AC |
1124 | { |
1125 | int mask = 1 << probe->slot; | |
1126 | ||
b8325487 AC |
1127 | if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { |
1128 | u8 reg = winbond_readcfg(winbond, 0x81); | |
1129 | reg |= 0x80; /* jumpered mode off */ | |
1130 | winbond_writecfg(winbond, 0x81, reg); | |
1131 | reg = winbond_readcfg(winbond, 0x83); | |
1132 | reg |= 0xF0; /* local control */ | |
1133 | winbond_writecfg(winbond, 0x83, reg); | |
1134 | reg = winbond_readcfg(winbond, 0x85); | |
1135 | reg |= 0xF0; /* programmable timing */ | |
1136 | winbond_writecfg(winbond, 0x85, reg); | |
1137 | ||
1138 | reg = winbond_readcfg(winbond, 0x81); | |
1139 | ||
1140 | if (reg & mask) | |
1141 | return W83759A; | |
1142 | } | |
defc9cd8 AC |
1143 | if (probe->port == 0x1F0) { |
1144 | unsigned long flags; | |
1145 | local_irq_save(flags); | |
669a5db4 | 1146 | /* Probes */ |
669a5db4 | 1147 | outb(inb(0x1F2) | 0x80, 0x1F2); |
defc9cd8 | 1148 | inb(0x1F5); |
669a5db4 JG |
1149 | inb(0x1F2); |
1150 | inb(0x3F6); | |
1151 | inb(0x3F6); | |
1152 | inb(0x1F2); | |
1153 | inb(0x1F2); | |
1154 | ||
1155 | if ((inb(0x1F2) & 0x80) == 0) { | |
1156 | /* PDC20230c or 20630 ? */ | |
defc9cd8 AC |
1157 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" |
1158 | " detected.\n"); | |
669a5db4 JG |
1159 | udelay(100); |
1160 | inb(0x1F5); | |
defc9cd8 AC |
1161 | local_irq_restore(flags); |
1162 | return PDC20230; | |
669a5db4 JG |
1163 | } else { |
1164 | outb(0x55, 0x1F2); | |
1165 | inb(0x1F2); | |
1166 | inb(0x1F2); | |
defc9cd8 AC |
1167 | if (inb(0x1F2) == 0x00) |
1168 | printk(KERN_INFO "PDC20230-B VLB ATA " | |
1169 | "controller detected.\n"); | |
1170 | local_irq_restore(flags); | |
1171 | return BIOS; | |
669a5db4 JG |
1172 | } |
1173 | local_irq_restore(flags); | |
1174 | } | |
1175 | ||
defc9cd8 AC |
1176 | if (ht6560a & mask) |
1177 | return HT6560A; | |
1178 | if (ht6560b & mask) | |
1179 | return HT6560B; | |
1180 | if (opti82c611a & mask) | |
1181 | return OPTI611A; | |
1182 | if (opti82c46x & mask) | |
1183 | return OPTI46X; | |
1184 | if (autospeed & mask) | |
1185 | return SNOOP; | |
1186 | return BIOS; | |
1187 | } | |
1188 | ||
1189 | ||
1190 | /** | |
1191 | * legacy_init_one - attach a legacy interface | |
1192 | * @pl: probe record | |
1193 | * | |
1194 | * Register an ISA bus IDE interface. Such interfaces are PIO and we | |
1195 | * assume do not support IRQ sharing. | |
1196 | */ | |
1197 | ||
1198 | static __init int legacy_init_one(struct legacy_probe *probe) | |
1199 | { | |
1200 | struct legacy_controller *controller = &controllers[probe->type]; | |
1201 | int pio_modes = controller->pio_mask; | |
1202 | unsigned long io = probe->port; | |
1203 | u32 mask = (1 << probe->slot); | |
1204 | struct ata_port_operations *ops = controller->ops; | |
1205 | struct legacy_data *ld = &legacy_data[probe->slot]; | |
1206 | struct ata_host *host = NULL; | |
1207 | struct ata_port *ap; | |
1208 | struct platform_device *pdev; | |
1209 | struct ata_device *dev; | |
1210 | void __iomem *io_addr, *ctrl_addr; | |
1211 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; | |
1212 | int ret; | |
1213 | ||
1214 | iordy |= controller->flags; | |
1215 | ||
1216 | pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); | |
1217 | if (IS_ERR(pdev)) | |
1218 | return PTR_ERR(pdev); | |
669a5db4 | 1219 | |
defc9cd8 AC |
1220 | ret = -EBUSY; |
1221 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || | |
1222 | devm_request_region(&pdev->dev, io + 0x0206, 1, | |
1223 | "pata_legacy") == NULL) | |
1224 | goto fail; | |
f834e49f | 1225 | |
5d728824 | 1226 | ret = -ENOMEM; |
defc9cd8 AC |
1227 | io_addr = devm_ioport_map(&pdev->dev, io, 8); |
1228 | ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); | |
1229 | if (!io_addr || !ctrl_addr) | |
1230 | goto fail; | |
1231 | if (controller->setup) | |
b8325487 | 1232 | if (controller->setup(pdev, probe, ld) < 0) |
defc9cd8 | 1233 | goto fail; |
5d728824 TH |
1234 | host = ata_host_alloc(&pdev->dev, 1); |
1235 | if (!host) | |
1236 | goto fail; | |
1237 | ap = host->ports[0]; | |
1238 | ||
1239 | ap->ops = ops; | |
1240 | ap->pio_mask = pio_modes; | |
1241 | ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; | |
1242 | ap->ioaddr.cmd_addr = io_addr; | |
1243 | ap->ioaddr.altstatus_addr = ctrl_addr; | |
1244 | ap->ioaddr.ctl_addr = ctrl_addr; | |
1245 | ata_std_ports(&ap->ioaddr); | |
b8325487 | 1246 | ap->host->private_data = ld; |
5d728824 | 1247 | |
defc9cd8 | 1248 | ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); |
cbcdd875 | 1249 | |
defc9cd8 AC |
1250 | ret = ata_host_activate(host, probe->irq, ata_interrupt, 0, |
1251 | &legacy_sht); | |
5d728824 | 1252 | if (ret) |
669a5db4 | 1253 | goto fail; |
669a5db4 | 1254 | ld->platform_dev = pdev; |
669a5db4 | 1255 | |
defc9cd8 AC |
1256 | /* Nothing found means we drop the port as its probably not there */ |
1257 | ||
1258 | ret = -ENODEV; | |
1259 | ata_link_for_each_dev(dev, &ap->link) { | |
1260 | if (!ata_dev_absent(dev)) { | |
1261 | legacy_host[probe->slot] = host; | |
1262 | ld->platform_dev = pdev; | |
1263 | return 0; | |
1264 | } | |
1265 | } | |
669a5db4 JG |
1266 | fail: |
1267 | platform_device_unregister(pdev); | |
669a5db4 JG |
1268 | return ret; |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * legacy_check_special_cases - ATA special cases | |
1273 | * @p: PCI device to check | |
1274 | * @master: set this if we find an ATA master | |
1275 | * @master: set this if we find an ATA secondary | |
1276 | * | |
defc9cd8 AC |
1277 | * A small number of vendors implemented early PCI ATA interfaces |
1278 | * on bridge logic without the ATA interface being PCI visible. | |
1279 | * Where we have a matching PCI driver we must skip the relevant | |
1280 | * device here. If we don't know about it then the legacy driver | |
1281 | * is the right driver anyway. | |
669a5db4 JG |
1282 | */ |
1283 | ||
b8325487 | 1284 | static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, |
defc9cd8 | 1285 | int *secondary) |
669a5db4 JG |
1286 | { |
1287 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ | |
1288 | if (p->vendor == 0x1078 && p->device == 0x0000) { | |
1289 | *primary = *secondary = 1; | |
1290 | return; | |
1291 | } | |
1292 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ | |
1293 | if (p->vendor == 0x1078 && p->device == 0x0002) { | |
1294 | *primary = *secondary = 1; | |
1295 | return; | |
1296 | } | |
1297 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ | |
1298 | if (p->vendor == 0x8086 && p->device == 0x1234) { | |
1299 | u16 r; | |
1300 | pci_read_config_word(p, 0x6C, &r); | |
defc9cd8 AC |
1301 | if (r & 0x8000) { |
1302 | /* ATA port enabled */ | |
669a5db4 JG |
1303 | if (r & 0x4000) |
1304 | *secondary = 1; | |
1305 | else | |
1306 | *primary = 1; | |
1307 | } | |
1308 | return; | |
1309 | } | |
1310 | } | |
1311 | ||
defc9cd8 AC |
1312 | static __init void probe_opti_vlb(void) |
1313 | { | |
1314 | /* If an OPTI 82C46X is present find out where the channels are */ | |
1315 | static const char *optis[4] = { | |
1316 | "3/463MV", "5MV", | |
1317 | "5MVA", "5MVB" | |
1318 | }; | |
1319 | u8 chans = 1; | |
1320 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; | |
1321 | ||
1322 | opti82c46x = 3; /* Assume master and slave first */ | |
1323 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", | |
1324 | optis[ctrl]); | |
1325 | if (ctrl == 3) | |
1326 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; | |
1327 | ctrl = opti_syscfg(0xAC); | |
1328 | /* Check enabled and this port is the 465MV port. On the | |
1329 | MVB we may have two channels */ | |
1330 | if (ctrl & 8) { | |
1331 | if (chans == 2) { | |
1332 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1333 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1334 | } | |
1335 | if (ctrl & 4) | |
1336 | legacy_probe_add(0x170, 15, OPTI46X, 0); | |
1337 | else | |
1338 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1339 | } else | |
1340 | legacy_probe_add(0x1F0, 14, OPTI46X, 0); | |
1341 | } | |
1342 | ||
1343 | static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) | |
1344 | { | |
1345 | static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; | |
1346 | /* Check card type */ | |
1347 | if ((r & 0xF0) == 0xC0) { | |
1348 | /* QD6500: single channel */ | |
b8325487 | 1349 | if (r & 8) |
defc9cd8 | 1350 | /* Disabled ? */ |
defc9cd8 | 1351 | return; |
defc9cd8 AC |
1352 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), |
1353 | QDI6500, port); | |
1354 | } | |
1355 | if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { | |
1356 | /* QD6580: dual channel */ | |
1357 | if (!request_region(port + 2 , 2, "pata_qdi")) { | |
1358 | release_region(port, 2); | |
1359 | return; | |
1360 | } | |
1361 | res = inb(port + 3); | |
1362 | /* Single channel mode ? */ | |
1363 | if (res & 1) | |
1364 | legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), | |
1365 | QDI6580, port); | |
1366 | else { /* Dual channel mode */ | |
1367 | legacy_probe_add(0x1F0, 14, QDI6580DP, port); | |
1368 | /* port + 0x02, r & 0x04 */ | |
1369 | legacy_probe_add(0x170, 15, QDI6580DP, port + 2); | |
1370 | } | |
b8325487 | 1371 | release_region(port + 2, 2); |
defc9cd8 AC |
1372 | } |
1373 | } | |
1374 | ||
1375 | static __init void probe_qdi_vlb(void) | |
1376 | { | |
1377 | unsigned long flags; | |
1378 | static const unsigned long qd_port[2] = { 0x30, 0xB0 }; | |
1379 | int i; | |
1380 | ||
1381 | /* | |
1382 | * Check each possible QD65xx base address | |
1383 | */ | |
1384 | ||
1385 | for (i = 0; i < 2; i++) { | |
1386 | unsigned long port = qd_port[i]; | |
1387 | u8 r, res; | |
1388 | ||
1389 | ||
1390 | if (request_region(port, 2, "pata_qdi")) { | |
1391 | /* Check for a card */ | |
1392 | local_irq_save(flags); | |
1393 | /* I have no h/w that needs this delay but it | |
1394 | is present in the historic code */ | |
1395 | r = inb(port); | |
1396 | udelay(1); | |
1397 | outb(0x19, port); | |
1398 | udelay(1); | |
1399 | res = inb(port); | |
1400 | udelay(1); | |
1401 | outb(r, port); | |
1402 | udelay(1); | |
1403 | local_irq_restore(flags); | |
1404 | ||
1405 | /* Fail */ | |
1406 | if (res == 0x19) { | |
1407 | release_region(port, 2); | |
1408 | continue; | |
1409 | } | |
1410 | /* Passes the presence test */ | |
1411 | r = inb(port + 1); | |
1412 | udelay(1); | |
1413 | /* Check port agrees with port set */ | |
b8325487 AC |
1414 | if ((r & 2) >> 1 == i) |
1415 | qdi65_identify_port(r, res, port); | |
1416 | release_region(port, 2); | |
defc9cd8 AC |
1417 | } |
1418 | } | |
1419 | } | |
669a5db4 JG |
1420 | |
1421 | /** | |
1422 | * legacy_init - attach legacy interfaces | |
1423 | * | |
1424 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. | |
1425 | * Right now we do not scan the ide0 and ide1 address but should do so | |
1426 | * for non PCI systems or systems with no PCI IDE legacy mode devices. | |
1427 | * If you fix that note there are special cases to consider like VLB | |
1428 | * drivers and CS5510/20. | |
1429 | */ | |
1430 | ||
1431 | static __init int legacy_init(void) | |
1432 | { | |
1433 | int i; | |
1434 | int ct = 0; | |
1435 | int primary = 0; | |
1436 | int secondary = 0; | |
defc9cd8 AC |
1437 | int pci_present = 0; |
1438 | struct legacy_probe *pl = &probe_list[0]; | |
1439 | int slot = 0; | |
669a5db4 JG |
1440 | |
1441 | struct pci_dev *p = NULL; | |
1442 | ||
1443 | for_each_pci_dev(p) { | |
1444 | int r; | |
defc9cd8 AC |
1445 | /* Check for any overlap of the system ATA mappings. Native |
1446 | mode controllers stuck on these addresses or some devices | |
1447 | in 'raid' mode won't be found by the storage class test */ | |
669a5db4 JG |
1448 | for (r = 0; r < 6; r++) { |
1449 | if (pci_resource_start(p, r) == 0x1f0) | |
1450 | primary = 1; | |
1451 | if (pci_resource_start(p, r) == 0x170) | |
1452 | secondary = 1; | |
1453 | } | |
1454 | /* Check for special cases */ | |
1455 | legacy_check_special_cases(p, &primary, &secondary); | |
1456 | ||
defc9cd8 AC |
1457 | /* If PCI bus is present then don't probe for tertiary |
1458 | legacy ports */ | |
1459 | pci_present = 1; | |
669a5db4 JG |
1460 | } |
1461 | ||
b8325487 AC |
1462 | if (winbond == 1) |
1463 | winbond = 0x130; /* Default port, alt is 1B0 */ | |
1464 | ||
defc9cd8 AC |
1465 | if (primary == 0 || all) |
1466 | legacy_probe_add(0x1F0, 14, UNKNOWN, 0); | |
1467 | if (secondary == 0 || all) | |
1468 | legacy_probe_add(0x170, 15, UNKNOWN, 0); | |
1469 | ||
1470 | if (probe_all || !pci_present) { | |
1471 | /* ISA/VLB extra ports */ | |
1472 | legacy_probe_add(0x1E8, 11, UNKNOWN, 0); | |
1473 | legacy_probe_add(0x168, 10, UNKNOWN, 0); | |
1474 | legacy_probe_add(0x1E0, 8, UNKNOWN, 0); | |
1475 | legacy_probe_add(0x160, 12, UNKNOWN, 0); | |
669a5db4 JG |
1476 | } |
1477 | ||
defc9cd8 AC |
1478 | if (opti82c46x) |
1479 | probe_opti_vlb(); | |
1480 | if (qdi) | |
1481 | probe_qdi_vlb(); | |
1482 | ||
defc9cd8 AC |
1483 | for (i = 0; i < NR_HOST; i++, pl++) { |
1484 | if (pl->port == 0) | |
669a5db4 | 1485 | continue; |
defc9cd8 AC |
1486 | if (pl->type == UNKNOWN) |
1487 | pl->type = probe_chip_type(pl); | |
1488 | pl->slot = slot++; | |
1489 | if (legacy_init_one(pl) == 0) | |
669a5db4 JG |
1490 | ct++; |
1491 | } | |
1492 | if (ct != 0) | |
1493 | return 0; | |
1494 | return -ENODEV; | |
1495 | } | |
1496 | ||
1497 | static __exit void legacy_exit(void) | |
1498 | { | |
1499 | int i; | |
1500 | ||
1501 | for (i = 0; i < nr_legacy_host; i++) { | |
1502 | struct legacy_data *ld = &legacy_data[i]; | |
24dc5f33 | 1503 | ata_host_detach(legacy_host[i]); |
669a5db4 | 1504 | platform_device_unregister(ld->platform_dev); |
669a5db4 JG |
1505 | } |
1506 | } | |
1507 | ||
1508 | MODULE_AUTHOR("Alan Cox"); | |
1509 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); | |
1510 | MODULE_LICENSE("GPL"); | |
1511 | MODULE_VERSION(DRV_VERSION); | |
1512 | ||
1513 | module_param(probe_all, int, 0); | |
1514 | module_param(autospeed, int, 0); | |
1515 | module_param(ht6560a, int, 0); | |
1516 | module_param(ht6560b, int, 0); | |
1517 | module_param(opti82c611a, int, 0); | |
1518 | module_param(opti82c46x, int, 0); | |
defc9cd8 | 1519 | module_param(qdi, int, 0); |
669a5db4 | 1520 | module_param(pio_mask, int, 0); |
f834e49f | 1521 | module_param(iordy_mask, int, 0); |
669a5db4 JG |
1522 | |
1523 | module_init(legacy_init); | |
1524 | module_exit(legacy_exit); |