[net-next-2.6.git] / drivers / ata / pata_cmd64x.c

/*
 * pata_cmd64x.c 	- CMD64x PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
 *			  (C) 2009-2010 Bartlomiej Zolnierkiewicz
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 *
 * TODO
 *	Testing work
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.5"

/*
 * CMD64x specific registers definition.
 */

enum {
	CFR 		= 0x50,
		CFR_INTR_CH0  = 0x02,
	CNTRL 		= 0x51,
		CNTRL_DIS_RA0 = 0x40,
		CNTRL_DIS_RA1 = 0x80,
		CNTRL_ENA_2ND = 0x08,
	CMDTIM 		= 0x52,
	ARTTIM0 	= 0x53,
	DRWTIM0 	= 0x54,
	ARTTIM1 	= 0x55,
	DRWTIM1 	= 0x56,
	ARTTIM23 	= 0x57,
		ARTTIM23_DIS_RA2  = 0x04,
		ARTTIM23_DIS_RA3  = 0x08,
		ARTTIM23_INTR_CH1 = 0x10,
	ARTTIM2 	= 0x57,
	ARTTIM3 	= 0x57,
	DRWTIM23	= 0x58,
	DRWTIM2 	= 0x58,
	BRST 		= 0x59,
	DRWTIM3 	= 0x5b,
	BMIDECR0	= 0x70,
	MRDMODE		= 0x71,
		MRDMODE_INTR_CH0 = 0x04,
		MRDMODE_INTR_CH1 = 0x08,
		MRDMODE_BLK_CH0  = 0x10,
		MRDMODE_BLK_CH1	 = 0x20,
	BMIDESR0	= 0x72,
	UDIDETCR0	= 0x73,
	DTPR0		= 0x74,
	BMIDECR1	= 0x78,
	BMIDECSR	= 0x79,
	BMIDESR1	= 0x7A,
	UDIDETCR1	= 0x7B,
	DTPR1		= 0x7C
};

static int cmd648_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 r;

	/* Check cable detect bits */
	pci_read_config_byte(pdev, BMIDECSR, &r);
	if (r & (1 << ap->port_no))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	cmd64x_set_piomode	-	set PIO and MWDMA timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@mode: mode
 *
 *	Called to do the PIO and MWDMA mode setup.
 */

static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_timing t;
	const unsigned long T = 1000000 / 33;
	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };

	u8 reg;

	/* Port layout is not logical so use a table */
	const u8 arttim_port[2][2] = {
		{ ARTTIM0, ARTTIM1 },
		{ ARTTIM23, ARTTIM23 }
	};
	const u8 drwtim_port[2][2] = {
		{ DRWTIM0, DRWTIM1 },
		{ DRWTIM2, DRWTIM3 }
	};

	int arttim = arttim_port[ap->port_no][adev->devno];
	int drwtim = drwtim_port[ap->port_no][adev->devno];

	/* ata_timing_compute is smart and will produce timings for MWDMA
	   that don't violate the drives PIO capabilities. */
	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
		return;
	}
	if (ap->port_no) {
		/* Slave has shared address setup */
		struct ata_device *pair = ata_dev_pair(adev);

		if (pair) {
			struct ata_timing tp;

			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
			if (pair->dma_mode) {
				ata_timing_compute(pair, pair->dma_mode,
						&tp, T, 0);
				ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
			}
		}
	}

	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
		t.active, t.recover, t.setup);
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)
		t.active = 16;

	/* Now convert the clocks into values we can actually stuff into
	   the chip */

	if (t.recover == 16)
		t.recover = 0;
	else if (t.recover > 1)
		t.recover--;
	else
		t.recover = 15;

	if (t.setup > 4)
		t.setup = 0xC0;
	else
		t.setup = setup_data[t.setup];

	t.active &= 0x0F;	/* 0 = 16 */

	/* Load setup timing */
	pci_read_config_byte(pdev, arttim, &reg);
	reg &= 0x3F;
	reg |= t.setup;
	pci_write_config_byte(pdev, arttim, reg);

	/* Load active/recovery */
	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}

/**
 *	cmd64x_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Used when configuring the devices ot set the PIO timings. All the
 *	actual work is done by the PIO/MWDMA setting helper
 */

static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	cmd64x_set_timing(ap, adev, adev->pio_mode);
}

/**
 *	cmd64x_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup.
 */

static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 udma_data[] = {
		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 regU, regD;

	int pciU = UDIDETCR0 + 8 * ap->port_no;
	int pciD = BMIDESR0 + 8 * ap->port_no;
	int shift = 2 * adev->devno;

	pci_read_config_byte(pdev, pciD, &regD);
	pci_read_config_byte(pdev, pciU, &regU);

	/* DMA bits off */
	regD &= ~(0x20 << adev->devno);
	/* DMA control bits */
	regU &= ~(0x30 << shift);
	/* DMA timing bits */
	regU &= ~(0x05 << adev->devno);

	if (adev->dma_mode >= XFER_UDMA_0) {
		/* Merge the timing value */
		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
		/* Merge the control bits */
		regU |= 1 << adev->devno; /* UDMA on */
		if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
			regU |= 4 << adev->devno;
	} else {
		regU &= ~ (1 << adev->devno);	/* UDMA off */
		cmd64x_set_timing(ap, adev, adev->dma_mode);
	}

	regD |= 0x20 << adev->devno;

	pci_write_config_byte(pdev, pciU, regU);
	pci_write_config_byte(pdev, pciD, regD);
}

/**
 *	cmd648_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed.
 */

static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 dma_intr;
	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	int dma_reg = ap->port_no ? ARTTIM2 : CFR;

	ata_bmdma_stop(qc);

	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}

/**
 *	cmd646r1_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	Stub for now while investigating the r1 quirk in the old driver.
 */

static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
	ata_bmdma_stop(qc);
}

static struct scsi_host_template cmd64x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static const struct ata_port_operations cmd64x_base_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
};

static struct ata_port_operations cmd64x_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd646r1_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd646r1_bmdma_stop,
	.cable_detect	= ata_cable_40wire,
};

static struct ata_port_operations cmd648_port_ops = {
	.inherits	= &cmd64x_base_ops,
	.bmdma_stop	= cmd648_bmdma_stop,
	.cable_detect	= cmd648_cable_detect,
};

static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info cmd_info[6] = {
		{	/* CMD 643 - no UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with broken UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with working UDMA */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 rev 1  */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.port_ops = &cmd646r1_port_ops
		},
		{	/* CMD 648 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &cmd648_port_ops
		},
		{	/* CMD 649 */
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &cmd648_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
	u8 mrdmode;
	int rc;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	if (id->driver_data == 0)	/* 643 */
		ata_pci_bmdma_clear_simplex(pdev);

	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
		/* Does UDMA work ? */
		if (pdev->revision > 4)
			ppi[0] = &cmd_info[2];
		/* Early rev with other problems ? */
		else if (pdev->revision == 1)
			ppi[0] = &cmd_info[3];
	}

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);

	/* Force PIO 0 here.. */

	/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif

	return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL);
}

#ifdef CONFIG_PM
static int cmd64x_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = dev_get_drvdata(&pdev->dev);
	u8 mrdmode;
	int rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id cmd64x[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },

	{ },
};

static struct pci_driver cmd64x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cmd64x,
	.probe 		= cmd64x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cmd64x_reinit_one,
#endif
};

static int __init cmd64x_init(void)
{
	return pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);

module_init(cmd64x_init);
module_exit(cmd64x_exit);
Commit	Line	Data
669a5db4	1	/*
fb9f8905	2	* pata_cmd64x.c - CMD64x PATA for new ATA layer
669a5db4	3	* (C) 2005 Red Hat Inc
ab771630	4	* Alan Cox <alan@lxorguk.ukuu.org.uk>
a2bd6220	5	* (C) 2009-2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	6	*
	7	* Based upon
	8	* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
	9	*
	10	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
	11	* Note, this driver is not used at all on other systems because
	12	* there the "BIOS" has done all of the following already.
	13	* Due to massive hardware bugs, UltraDMA is only supported
	14	* on the 646U2 and not on the 646U.
	15	*
	16	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	17	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	18	*
	19	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
	20	*
	21	* TODO
	22	* Testing work
	23	*/
85cd7251	24
669a5db4 JG	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
	27	#include <linux/pci.h>
	28	#include <linux/init.h>
	29	#include <linux/blkdev.h>
	30	#include <linux/delay.h>
	31	#include <scsi/scsi_host.h>
	32	#include <linux/libata.h>
	33
	34	#define DRV_NAME "pata_cmd64x"
06393afd	35	#define DRV_VERSION "0.2.5"
669a5db4 JG	36
	37	/*
	38	* CMD64x specific registers definition.
	39	*/
85cd7251	40
669a5db4 JG	41	enum {
	42	CFR = 0x50,
	43	CFR_INTR_CH0 = 0x02,
	44	CNTRL = 0x51,
	45	CNTRL_DIS_RA0 = 0x40,
	46	CNTRL_DIS_RA1 = 0x80,
	47	CNTRL_ENA_2ND = 0x08,
	48	CMDTIM = 0x52,
	49	ARTTIM0 = 0x53,
	50	DRWTIM0 = 0x54,
	51	ARTTIM1 = 0x55,
	52	DRWTIM1 = 0x56,
	53	ARTTIM23 = 0x57,
	54	ARTTIM23_DIS_RA2 = 0x04,
	55	ARTTIM23_DIS_RA3 = 0x08,
	56	ARTTIM23_INTR_CH1 = 0x10,
	57	ARTTIM2 = 0x57,
	58	ARTTIM3 = 0x57,
	59	DRWTIM23 = 0x58,
	60	DRWTIM2 = 0x58,
	61	BRST = 0x59,
	62	DRWTIM3 = 0x5b,
	63	BMIDECR0 = 0x70,
	64	MRDMODE = 0x71,
	65	MRDMODE_INTR_CH0 = 0x04,
	66	MRDMODE_INTR_CH1 = 0x08,
	67	MRDMODE_BLK_CH0 = 0x10,
	68	MRDMODE_BLK_CH1 = 0x20,
	69	BMIDESR0 = 0x72,
	70	UDIDETCR0 = 0x73,
	71	DTPR0 = 0x74,
	72	BMIDECR1 = 0x78,
	73	BMIDECSR = 0x79,
	74	BMIDESR1 = 0x7A,
	75	UDIDETCR1 = 0x7B,
	76	DTPR1 = 0x7C
	77	};
	78
a73984a0	79	static int cmd648_cable_detect(struct ata_port *ap)
669a5db4 JG	80	{
	81	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	82	u8 r;
	83
	84	/* Check cable detect bits */
	85	pci_read_config_byte(pdev, BMIDECSR, &r);
	86	if (r & (1 << ap->port_no))
a73984a0 JG	87	return ATA_CBL_PATA80;
a73984a0 JG	88	return ATA_CBL_PATA40;
669a5db4 JG	89	}
	90
	91	/**
05d1efff	92	* cmd64x_set_piomode - set PIO and MWDMA timing
669a5db4 JG	93	* @ap: ATA interface
669a5db4 JG	94	* @adev: ATA device
05d1efff	95	* @mode: mode
669a5db4	96	*
05d1efff	97	* Called to do the PIO and MWDMA mode setup.
669a5db4	98	*/
85cd7251	99
05d1efff	100	static void cmd64x_set_timing(struct ata_port ap, struct ata_device adev, u8 mode)
669a5db4 JG	101	{
	102	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	103	struct ata_timing t;
	104	const unsigned long T = 1000000 / 33;
	105	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
85cd7251	106
669a5db4	107	u8 reg;
85cd7251	108
669a5db4	109	/* Port layout is not logical so use a table */
85cd7251	110	const u8 arttim_port[2][2] = {
669a5db4 JG	111	{ ARTTIM0, ARTTIM1 },
	112	{ ARTTIM23, ARTTIM23 }
	113	};
	114	const u8 drwtim_port[2][2] = {
	115	{ DRWTIM0, DRWTIM1 },
	116	{ DRWTIM2, DRWTIM3 }
	117	};
85cd7251	118
669a5db4 JG	119	int arttim = arttim_port[ap->port_no][adev->devno];
669a5db4 JG	120	int drwtim = drwtim_port[ap->port_no][adev->devno];
85cd7251	121
05d1efff AC	122	/* ata_timing_compute is smart and will produce timings for MWDMA
	123	that don't violate the drives PIO capabilities. */
	124	if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
669a5db4 JG	125	printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
	126	return;
	127	}
	128	if (ap->port_no) {
	129	/* Slave has shared address setup */
	130	struct ata_device *pair = ata_dev_pair(adev);
85cd7251	131
669a5db4 JG	132	if (pair) {
669a5db4 JG	133	struct ata_timing tp;
d62f5576	134
669a5db4 JG	135	ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
669a5db4 JG	136	ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
d62f5576 BZ	137	if (pair->dma_mode) {
	138	ata_timing_compute(pair, pair->dma_mode,
	139	&tp, T, 0);
	140	ata_timing_merge(&tp, &t, &t, ATA_TIMING_SETUP);
	141	}
669a5db4 JG	142	}
669a5db4 JG	143	}
85cd7251	144
669a5db4 JG	145	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
	146	t.active, t.recover, t.setup);
	147	if (t.recover > 16) {
	148	t.active += t.recover - 16;
	149	t.recover = 16;
	150	}
	151	if (t.active > 16)
	152	t.active = 16;
85cd7251	153
669a5db4 JG	154	/* Now convert the clocks into values we can actually stuff into
669a5db4 JG	155	the chip */
85cd7251	156
a2bd6220 BZ	157	if (t.recover == 16)
	158	t.recover = 0;
	159	else if (t.recover > 1)
669a5db4 JG	160	t.recover--;
	161	else
	162	t.recover = 15;
85cd7251	163
669a5db4 JG	164	if (t.setup > 4)
	165	t.setup = 0xC0;
	166	else
	167	t.setup = setup_data[t.setup];
85cd7251	168
669a5db4	169	t.active &= 0x0F; /* 0 = 16 */
85cd7251	170
669a5db4 JG	171	/* Load setup timing */
	172	pci_read_config_byte(pdev, arttim, &reg);
	173	reg &= 0x3F;
	174	reg \|= t.setup;
	175	pci_write_config_byte(pdev, arttim, reg);
85cd7251	176
669a5db4	177	/* Load active/recovery */
85cd7251	178	pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);
669a5db4 JG	179	}
669a5db4 JG	180
05d1efff AC	181	/**
	182	* cmd64x_set_piomode - set initial PIO mode data
	183	* @ap: ATA interface
	184	* @adev: ATA device
	185	*
	186	* Used when configuring the devices ot set the PIO timings. All the
	187	* actual work is done by the PIO/MWDMA setting helper
	188	*/
	189
	190	static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)
	191	{
	192	cmd64x_set_timing(ap, adev, adev->pio_mode);
	193	}
	194
669a5db4 JG	195	/**
	196	* cmd64x_set_dmamode - set initial DMA mode data
	197	* @ap: ATA interface
	198	* @adev: ATA device
	199	*
	200	* Called to do the DMA mode setup.
	201	*/
85cd7251	202
669a5db4 JG	203	static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)
	204	{
	205	static const u8 udma_data[] = {
6a40da02	206	0x30, 0x20, 0x10, 0x20, 0x10, 0x00
669a5db4	207	};
85cd7251	208
669a5db4 JG	209	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	210	u8 regU, regD;
	211
	212	int pciU = UDIDETCR0 + 8 * ap->port_no;
	213	int pciD = BMIDESR0 + 8 * ap->port_no;
	214	int shift = 2 * adev->devno;
85cd7251	215
669a5db4 JG	216	pci_read_config_byte(pdev, pciD, &regD);
	217	pci_read_config_byte(pdev, pciU, &regU);
	218
6a40da02 AC	219	/* DMA bits off */
	220	regD &= ~(0x20 << adev->devno);
	221	/* DMA control bits */
	222	regU &= ~(0x30 << shift);
	223	/* DMA timing bits */
	224	regU &= ~(0x05 << adev->devno);
85cd7251	225
6a40da02	226	if (adev->dma_mode >= XFER_UDMA_0) {
24b7ce98	227	/* Merge the timing value */
669a5db4	228	regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
6a40da02 AC	229	/* Merge the control bits */
6a40da02 AC	230	regU \|= 1 << adev->devno; /* UDMA on */
509426bd	231	if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
6a40da02	232	regU \|= 4 << adev->devno;
05d1efff AC	233	} else {
	234	regU &= ~ (1 << adev->devno); /* UDMA off */
	235	cmd64x_set_timing(ap, adev, adev->dma_mode);
	236	}
669a5db4 JG	237
	238	regD \|= 0x20 << adev->devno;
	239
	240	pci_write_config_byte(pdev, pciU, regU);
	241	pci_write_config_byte(pdev, pciD, regD);
	242	}
	243
	244	/**
	245	* cmd648_dma_stop - DMA stop callback
	246	* @qc: Command in progress
	247	*
	248	* DMA has completed.
	249	*/
	250
	251	static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
	252	{
	253	struct ata_port *ap = qc->ap;
	254	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	255	u8 dma_intr;
6a40da02 AC	256	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
6a40da02 AC	257	int dma_reg = ap->port_no ? ARTTIM2 : CFR;
85cd7251	258
669a5db4	259	ata_bmdma_stop(qc);
85cd7251	260
669a5db4 JG	261	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	262	pci_write_config_byte(pdev, dma_reg, dma_intr \| dma_mask);
	263	}
85cd7251	264
669a5db4	265	/**
06393afd	266	* cmd646r1_dma_stop - DMA stop callback
669a5db4 JG	267	* @qc: Command in progress
669a5db4 JG	268	*
06393afd	269	* Stub for now while investigating the r1 quirk in the old driver.
669a5db4 JG	270	*/
669a5db4 JG	271
06393afd	272	static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
669a5db4 JG	273	{
	274	ata_bmdma_stop(qc);
	275	}
85cd7251	276
669a5db4	277	static struct scsi_host_template cmd64x_sht = {
68d1d07b	278	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	279	};
669a5db4 JG	280
029cfd6b TH	281	static const struct ata_port_operations cmd64x_base_ops = {
029cfd6b TH	282	.inherits = &ata_bmdma_port_ops,
669a5db4 JG	283	.set_piomode = cmd64x_set_piomode,
669a5db4 JG	284	.set_dmamode = cmd64x_set_dmamode,
85cd7251	285	};
669a5db4	286
029cfd6b TH	287	static struct ata_port_operations cmd64x_port_ops = {
029cfd6b TH	288	.inherits = &cmd64x_base_ops,
a73984a0	289	.cable_detect = ata_cable_40wire,
029cfd6b	290	};
669a5db4	291
029cfd6b TH	292	static struct ata_port_operations cmd646r1_port_ops = {
029cfd6b TH	293	.inherits = &cmd64x_base_ops,
06393afd	294	.bmdma_stop = cmd646r1_bmdma_stop,
029cfd6b	295	.cable_detect = ata_cable_40wire,
85cd7251	296	};
669a5db4 JG	297
669a5db4 JG	298	static struct ata_port_operations cmd648_port_ops = {
029cfd6b	299	.inherits = &cmd64x_base_ops,
669a5db4	300	.bmdma_stop = cmd648_bmdma_stop,
029cfd6b	301	.cable_detect = cmd648_cable_detect,
85cd7251 JG	302	};
85cd7251 JG	303
669a5db4 JG	304	static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4 JG	305	{
1626aeb8	306	static const struct ata_port_info cmd_info[6] = {
669a5db4	307	{ /* CMD 643 - no UDMA */
1d2808fd	308	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	309	.pio_mask = ATA_PIO4,
14bdef98 EIB	310	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	311	.port_ops = &cmd64x_port_ops
	312	},
	313	{ /* CMD 646 with broken UDMA */
1d2808fd	314	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	315	.pio_mask = ATA_PIO4,
14bdef98 EIB	316	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	317	.port_ops = &cmd64x_port_ops
	318	},
	319	{ /* CMD 646 with working UDMA */
1d2808fd	320	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	321	.pio_mask = ATA_PIO4,
14bdef98 EIB	322	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	323	.udma_mask = ATA_UDMA2,
669a5db4 JG	324	.port_ops = &cmd64x_port_ops
	325	},
	326	{ /* CMD 646 rev 1 */
1d2808fd	327	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	328	.pio_mask = ATA_PIO4,
14bdef98 EIB	329	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	330	.port_ops = &cmd646r1_port_ops
	331	},
	332	{ /* CMD 648 */
1d2808fd	333	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	334	.pio_mask = ATA_PIO4,
14bdef98 EIB	335	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	336	.udma_mask = ATA_UDMA4,
669a5db4 JG	337	.port_ops = &cmd648_port_ops
	338	},
	339	{ /* CMD 649 */
1d2808fd	340	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	341	.pio_mask = ATA_PIO4,
14bdef98 EIB	342	.mwdma_mask = ATA_MWDMA2,
dbf0c89c	343	.udma_mask = ATA_UDMA5,
669a5db4 JG	344	.port_ops = &cmd648_port_ops
	345	}
	346	};
1626aeb8	347	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
669a5db4	348	u8 mrdmode;
f08048e9 TH	349	int rc;
	350
	351	rc = pcim_enable_device(pdev);
	352	if (rc)
	353	return rc;
85cd7251	354
669a5db4	355	if (id->driver_data == 0) /* 643 */
9363c382	356	ata_pci_bmdma_clear_simplex(pdev);
85cd7251	357
669a5db4 JG	358	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
669a5db4 JG	359	/* Does UDMA work ? */
89d3b360	360	if (pdev->revision > 4)
1626aeb8	361	ppi[0] = &cmd_info[2];
669a5db4	362	/* Early rev with other problems ? */
89d3b360	363	else if (pdev->revision == 1)
1626aeb8	364	ppi[0] = &cmd_info[3];
669a5db4 JG	365	}
	366
	367	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	368	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	369	mrdmode &= ~ 0x30; /* IRQ set up */
	370	mrdmode \|= 0x02; /* Memory read line enable */
	371	pci_write_config_byte(pdev, MRDMODE, mrdmode);
85cd7251	372
06393afd JG	373	/* Force PIO 0 here.. */
06393afd JG	374
669a5db4 JG	375	/* PPC specific fixup copied from old driver */
	376	#ifdef CONFIG_PPC
	377	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	378	#endif
85cd7251	379
06393afd	380	return ata_pci_sff_init_one(pdev, ppi, &cmd64x_sht, NULL);
669a5db4 JG	381	}
669a5db4 JG	382
438ac6d5	383	#ifdef CONFIG_PM
7f72a379 AC	384	static int cmd64x_reinit_one(struct pci_dev *pdev)
7f72a379 AC	385	{
f08048e9	386	struct ata_host *host = dev_get_drvdata(&pdev->dev);
7f72a379	387	u8 mrdmode;
f08048e9 TH	388	int rc;
	389
	390	rc = ata_pci_device_do_resume(pdev);
	391	if (rc)
	392	return rc;
	393
7f72a379 AC	394	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	395	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	396	mrdmode &= ~ 0x30; /* IRQ set up */
	397	mrdmode \|= 0x02; /* Memory read line enable */
	398	pci_write_config_byte(pdev, MRDMODE, mrdmode);
	399	#ifdef CONFIG_PPC
	400	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	401	#endif
f08048e9 TH	402	ata_host_resume(host);
f08048e9 TH	403	return 0;
7f72a379	404	}
438ac6d5	405	#endif
7f72a379	406
2d2744fc JG	407	static const struct pci_device_id cmd64x[] = {
	408	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	409	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	410	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	411	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
	412
	413	{ },
669a5db4 JG	414	};
	415
	416	static struct pci_driver cmd64x_pci_driver = {
2d2744fc	417	.name = DRV_NAME,
669a5db4 JG	418	.id_table = cmd64x,
669a5db4 JG	419	.probe = cmd64x_init_one,
7f72a379	420	.remove = ata_pci_remove_one,
438ac6d5	421	#ifdef CONFIG_PM
7f72a379 AC	422	.suspend = ata_pci_device_suspend,
7f72a379 AC	423	.resume = cmd64x_reinit_one,
438ac6d5	424	#endif
669a5db4 JG	425	};
	426
	427	static int __init cmd64x_init(void)
	428	{
	429	return pci_register_driver(&cmd64x_pci_driver);
	430	}
	431
669a5db4 JG	432	static void __exit cmd64x_exit(void)
	433	{
	434	pci_unregister_driver(&cmd64x_pci_driver);
	435	}
	436
669a5db4 JG	437	MODULE_AUTHOR("Alan Cox");
	438	MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
	439	MODULE_LICENSE("GPL");
	440	MODULE_DEVICE_TABLE(pci, cmd64x);
	441	MODULE_VERSION(DRV_VERSION);
	442
	443	module_init(cmd64x_init);
	444	module_exit(cmd64x_exit);