[net-next-2.6.git] / drivers / ata / pata_cmd64x.c

/*
 * pata_cmd64x.c 	- CMD64x PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@redhat.com>
 *
 * Based upon
 * linux/drivers/ide/pci/cmd64x.c		Version 1.30	Sept 10, 2002
 *
 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
 *           Note, this driver is not used at all on other systems because
 *           there the "BIOS" has done all of the following already.
 *           Due to massive hardware bugs, UltraDMA is only supported
 *           on the 646U2 and not on the 646U.
 *
 * Copyright (C) 1998		Eddie C. Dost  (ecd@skynet.be)
 * Copyright (C) 1998		David S. Miller (davem@redhat.com)
 *
 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
 *
 * TODO
 *	Testing work
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_cmd64x"
#define DRV_VERSION "0.2.3"

/*
 * CMD64x specific registers definition.
 */

enum {
	CFR 		= 0x50,
		CFR_INTR_CH0  = 0x02,
	CNTRL 		= 0x51,
		CNTRL_DIS_RA0 = 0x40,
		CNTRL_DIS_RA1 = 0x80,
		CNTRL_ENA_2ND = 0x08,
	CMDTIM 		= 0x52,
	ARTTIM0 	= 0x53,
	DRWTIM0 	= 0x54,
	ARTTIM1 	= 0x55,
	DRWTIM1 	= 0x56,
	ARTTIM23 	= 0x57,
		ARTTIM23_DIS_RA2  = 0x04,
		ARTTIM23_DIS_RA3  = 0x08,
		ARTTIM23_INTR_CH1 = 0x10,
	ARTTIM2 	= 0x57,
	ARTTIM3 	= 0x57,
	DRWTIM23	= 0x58,
	DRWTIM2 	= 0x58,
	BRST 		= 0x59,
	DRWTIM3 	= 0x5b,
	BMIDECR0	= 0x70,
	MRDMODE		= 0x71,
		MRDMODE_INTR_CH0 = 0x04,
		MRDMODE_INTR_CH1 = 0x08,
		MRDMODE_BLK_CH0  = 0x10,
		MRDMODE_BLK_CH1	 = 0x20,
	BMIDESR0	= 0x72,
	UDIDETCR0	= 0x73,
	DTPR0		= 0x74,
	BMIDECR1	= 0x78,
	BMIDECSR	= 0x79,
	BMIDESR1	= 0x7A,
	UDIDETCR1	= 0x7B,
	DTPR1		= 0x7C
};

static int cmd648_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 r;

	/* Check cable detect bits */
	pci_read_config_byte(pdev, BMIDECSR, &r);
	if (r & (1 << ap->port_no))
		return ATA_CBL_PATA80;
	return ATA_CBL_PATA40;
}

/**
 *	cmd64x_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup.
 */

static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	struct ata_timing t;
	const unsigned long T = 1000000 / 33;
	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };

	u8 reg;

	/* Port layout is not logical so use a table */
	const u8 arttim_port[2][2] = {
		{ ARTTIM0, ARTTIM1 },
		{ ARTTIM23, ARTTIM23 }
	};
	const u8 drwtim_port[2][2] = {
		{ DRWTIM0, DRWTIM1 },
		{ DRWTIM2, DRWTIM3 }
	};

	int arttim = arttim_port[ap->port_no][adev->devno];
	int drwtim = drwtim_port[ap->port_no][adev->devno];


	if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
		printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
		return;
	}
	if (ap->port_no) {
		/* Slave has shared address setup */
		struct ata_device *pair = ata_dev_pair(adev);

		if (pair) {
			struct ata_timing tp;
			ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
			ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
		}
	}

	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
		t.active, t.recover, t.setup);
	if (t.recover > 16) {
		t.active += t.recover - 16;
		t.recover = 16;
	}
	if (t.active > 16)
		t.active = 16;

	/* Now convert the clocks into values we can actually stuff into
	   the chip */

	if (t.recover > 1)
		t.recover--;
	else
		t.recover = 15;

	if (t.setup > 4)
		t.setup = 0xC0;
	else
		t.setup = setup_data[t.setup];

	t.active &= 0x0F;	/* 0 = 16 */

	/* Load setup timing */
	pci_read_config_byte(pdev, arttim, &reg);
	reg &= 0x3F;
	reg |= t.setup;
	pci_write_config_byte(pdev, arttim, reg);

	/* Load active/recovery */
	pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
}

/**
 *	cmd64x_set_dmamode	-	set initial DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the DMA mode setup.
 */

static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 udma_data[] = {
		0x30, 0x20, 0x10, 0x20, 0x10, 0x00
	};
	static const u8 mwdma_data[] = {
		0x30, 0x20, 0x10
	};

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 regU, regD;

	int pciU = UDIDETCR0 + 8 * ap->port_no;
	int pciD = BMIDESR0 + 8 * ap->port_no;
	int shift = 2 * adev->devno;

	pci_read_config_byte(pdev, pciD, &regD);
	pci_read_config_byte(pdev, pciU, &regU);

	/* DMA bits off */
	regD &= ~(0x20 << adev->devno);
	/* DMA control bits */
	regU &= ~(0x30 << shift);
	/* DMA timing bits */
	regU &= ~(0x05 << adev->devno);

	if (adev->dma_mode >= XFER_UDMA_0) {
		/* Merge thge timing value */
		regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
		/* Merge the control bits */
		regU |= 1 << adev->devno; /* UDMA on */
		if (adev->dma_mode > 2)	/* 15nS timing */
			regU |= 4 << adev->devno;
	} else
		regD |= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;

	regD |= 0x20 << adev->devno;

	pci_write_config_byte(pdev, pciU, regU);
	pci_write_config_byte(pdev, pciD, regD);
}

/**
 *	cmd648_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	DMA has completed.
 */

static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 dma_intr;
	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
	int dma_reg = ap->port_no ? ARTTIM2 : CFR;

	ata_bmdma_stop(qc);

	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}

/**
 *	cmd646r1_dma_stop	-	DMA stop callback
 *	@qc: Command in progress
 *
 *	Stub for now while investigating the r1 quirk in the old driver.
 */

static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
{
	ata_bmdma_stop(qc);
}

static struct scsi_host_template cmd64x_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations cmd64x_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct ata_port_operations cmd646r1_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= cmd646r1_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static struct ata_port_operations cmd648_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= cmd64x_set_piomode,
	.set_dmamode	= cmd64x_set_dmamode,
	.mode_filter	= ata_pci_default_filter,
	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= cmd648_cable_detect,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= cmd648_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	u32 class_rev;

	static const struct ata_port_info cmd_info[6] = {
		{	/* CMD 643 - no UDMA */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with broken UDMA */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 with working UDMA */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA1,
			.port_ops = &cmd64x_port_ops
		},
		{	/* CMD 646 rev 1  */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.port_ops = &cmd646r1_port_ops
		},
		{	/* CMD 648 */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA2,
			.port_ops = &cmd648_port_ops
		},
		{	/* CMD 649 */
			.sht = &cmd64x_sht,
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = 0x1f,
			.mwdma_mask = 0x07,
			.udma_mask = ATA_UDMA3,
			.port_ops = &cmd648_port_ops
		}
	};
	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
	u8 mrdmode;

	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
	class_rev &= 0xFF;

	if (id->driver_data == 0)	/* 643 */
		ata_pci_clear_simplex(pdev);

	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
		/* Does UDMA work ? */
		if (class_rev > 4)
			ppi[0] = &cmd_info[2];
		/* Early rev with other problems ? */
		else if (class_rev == 1)
			ppi[0] = &cmd_info[3];
	}

	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);

	/* Force PIO 0 here.. */

	/* PPC specific fixup copied from old driver */
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif

	return ata_pci_init_one(pdev, ppi);
}

#ifdef CONFIG_PM
static int cmd64x_reinit_one(struct pci_dev *pdev)
{
	u8 mrdmode;
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	mrdmode &= ~ 0x30;	/* IRQ set up */
	mrdmode |= 0x02;	/* Memory read line enable */
	pci_write_config_byte(pdev, MRDMODE, mrdmode);
#ifdef CONFIG_PPC
	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
#endif
	return ata_pci_device_resume(pdev);
}
#endif

static const struct pci_device_id cmd64x[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },

	{ },
};

static struct pci_driver cmd64x_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= cmd64x,
	.probe 		= cmd64x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= cmd64x_reinit_one,
#endif
};

static int __init cmd64x_init(void)
{
	return pci_register_driver(&cmd64x_pci_driver);
}

static void __exit cmd64x_exit(void)
{
	pci_unregister_driver(&cmd64x_pci_driver);
}

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, cmd64x);
MODULE_VERSION(DRV_VERSION);

module_init(cmd64x_init);
module_exit(cmd64x_exit);
Commit	Line	Data
669a5db4	1	/*
fb9f8905	2	* pata_cmd64x.c - CMD64x PATA for new ATA layer
669a5db4 JG	3	* (C) 2005 Red Hat Inc
	4	* Alan Cox <alan@redhat.com>
	5	*
	6	* Based upon
	7	* linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
	8	*
	9	* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
	10	* Note, this driver is not used at all on other systems because
	11	* there the "BIOS" has done all of the following already.
	12	* Due to massive hardware bugs, UltraDMA is only supported
	13	* on the 646U2 and not on the 646U.
	14	*
	15	* Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
	16	* Copyright (C) 1998 David S. Miller (davem@redhat.com)
	17	*
	18	* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
	19	*
	20	* TODO
	21	* Testing work
	22	*/
85cd7251	23
669a5db4 JG	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/pci.h>
	27	#include <linux/init.h>
	28	#include <linux/blkdev.h>
	29	#include <linux/delay.h>
	30	#include <scsi/scsi_host.h>
	31	#include <linux/libata.h>
	32
	33	#define DRV_NAME "pata_cmd64x"
8bc3fc47	34	#define DRV_VERSION "0.2.3"
669a5db4 JG	35
	36	/*
	37	* CMD64x specific registers definition.
	38	*/
85cd7251	39
669a5db4 JG	40	enum {
	41	CFR = 0x50,
	42	CFR_INTR_CH0 = 0x02,
	43	CNTRL = 0x51,
	44	CNTRL_DIS_RA0 = 0x40,
	45	CNTRL_DIS_RA1 = 0x80,
	46	CNTRL_ENA_2ND = 0x08,
	47	CMDTIM = 0x52,
	48	ARTTIM0 = 0x53,
	49	DRWTIM0 = 0x54,
	50	ARTTIM1 = 0x55,
	51	DRWTIM1 = 0x56,
	52	ARTTIM23 = 0x57,
	53	ARTTIM23_DIS_RA2 = 0x04,
	54	ARTTIM23_DIS_RA3 = 0x08,
	55	ARTTIM23_INTR_CH1 = 0x10,
	56	ARTTIM2 = 0x57,
	57	ARTTIM3 = 0x57,
	58	DRWTIM23 = 0x58,
	59	DRWTIM2 = 0x58,
	60	BRST = 0x59,
	61	DRWTIM3 = 0x5b,
	62	BMIDECR0 = 0x70,
	63	MRDMODE = 0x71,
	64	MRDMODE_INTR_CH0 = 0x04,
	65	MRDMODE_INTR_CH1 = 0x08,
	66	MRDMODE_BLK_CH0 = 0x10,
	67	MRDMODE_BLK_CH1 = 0x20,
	68	BMIDESR0 = 0x72,
	69	UDIDETCR0 = 0x73,
	70	DTPR0 = 0x74,
	71	BMIDECR1 = 0x78,
	72	BMIDECSR = 0x79,
	73	BMIDESR1 = 0x7A,
	74	UDIDETCR1 = 0x7B,
	75	DTPR1 = 0x7C
	76	};
	77
a73984a0	78	static int cmd648_cable_detect(struct ata_port *ap)
669a5db4 JG	79	{
	80	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	81	u8 r;
	82
	83	/* Check cable detect bits */
	84	pci_read_config_byte(pdev, BMIDECSR, &r);
	85	if (r & (1 << ap->port_no))
a73984a0 JG	86	return ATA_CBL_PATA80;
a73984a0 JG	87	return ATA_CBL_PATA40;
669a5db4 JG	88	}
	89
	90	/**
	91	* cmd64x_set_piomode - set initial PIO mode data
	92	* @ap: ATA interface
	93	* @adev: ATA device
	94	*
	95	* Called to do the PIO mode setup.
	96	*/
85cd7251	97
669a5db4 JG	98	static void cmd64x_set_piomode(struct ata_port ap, struct ata_device adev)
	99	{
	100	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	101	struct ata_timing t;
	102	const unsigned long T = 1000000 / 33;
	103	const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
85cd7251	104
669a5db4	105	u8 reg;
85cd7251	106
669a5db4	107	/* Port layout is not logical so use a table */
85cd7251	108	const u8 arttim_port[2][2] = {
669a5db4 JG	109	{ ARTTIM0, ARTTIM1 },
	110	{ ARTTIM23, ARTTIM23 }
	111	};
	112	const u8 drwtim_port[2][2] = {
	113	{ DRWTIM0, DRWTIM1 },
	114	{ DRWTIM2, DRWTIM3 }
	115	};
85cd7251	116
669a5db4 JG	117	int arttim = arttim_port[ap->port_no][adev->devno];
669a5db4 JG	118	int drwtim = drwtim_port[ap->port_no][adev->devno];
85cd7251 JG	119
85cd7251 JG	120
669a5db4 JG	121	if (ata_timing_compute(adev, adev->pio_mode, &t, T, 0) < 0) {
	122	printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
	123	return;
	124	}
	125	if (ap->port_no) {
	126	/* Slave has shared address setup */
	127	struct ata_device *pair = ata_dev_pair(adev);
85cd7251	128
669a5db4 JG	129	if (pair) {
	130	struct ata_timing tp;
	131	ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
	132	ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
	133	}
	134	}
85cd7251	135
669a5db4 JG	136	printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
	137	t.active, t.recover, t.setup);
	138	if (t.recover > 16) {
	139	t.active += t.recover - 16;
	140	t.recover = 16;
	141	}
	142	if (t.active > 16)
	143	t.active = 16;
85cd7251	144
669a5db4 JG	145	/* Now convert the clocks into values we can actually stuff into
669a5db4 JG	146	the chip */
85cd7251	147
669a5db4 JG	148	if (t.recover > 1)
	149	t.recover--;
	150	else
	151	t.recover = 15;
85cd7251	152
669a5db4 JG	153	if (t.setup > 4)
	154	t.setup = 0xC0;
	155	else
	156	t.setup = setup_data[t.setup];
85cd7251	157
669a5db4	158	t.active &= 0x0F; /* 0 = 16 */
85cd7251	159
669a5db4 JG	160	/* Load setup timing */
	161	pci_read_config_byte(pdev, arttim, &reg);
	162	reg &= 0x3F;
	163	reg \|= t.setup;
	164	pci_write_config_byte(pdev, arttim, reg);
85cd7251	165
669a5db4	166	/* Load active/recovery */
85cd7251	167	pci_write_config_byte(pdev, drwtim, (t.active << 4) \| t.recover);
669a5db4 JG	168	}
	169
	170	/**
	171	* cmd64x_set_dmamode - set initial DMA mode data
	172	* @ap: ATA interface
	173	* @adev: ATA device
	174	*
	175	* Called to do the DMA mode setup.
	176	*/
85cd7251	177
669a5db4 JG	178	static void cmd64x_set_dmamode(struct ata_port ap, struct ata_device adev)
	179	{
	180	static const u8 udma_data[] = {
6a40da02	181	0x30, 0x20, 0x10, 0x20, 0x10, 0x00
669a5db4	182	};
85cd7251	183	static const u8 mwdma_data[] = {
669a5db4 JG	184	0x30, 0x20, 0x10
669a5db4 JG	185	};
85cd7251	186
669a5db4 JG	187	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	188	u8 regU, regD;
	189
	190	int pciU = UDIDETCR0 + 8 * ap->port_no;
	191	int pciD = BMIDESR0 + 8 * ap->port_no;
	192	int shift = 2 * adev->devno;
85cd7251	193
669a5db4 JG	194	pci_read_config_byte(pdev, pciD, &regD);
	195	pci_read_config_byte(pdev, pciU, &regU);
	196
6a40da02 AC	197	/* DMA bits off */
	198	regD &= ~(0x20 << adev->devno);
	199	/* DMA control bits */
	200	regU &= ~(0x30 << shift);
	201	/* DMA timing bits */
	202	regU &= ~(0x05 << adev->devno);
85cd7251	203
6a40da02 AC	204	if (adev->dma_mode >= XFER_UDMA_0) {
6a40da02 AC	205	/* Merge thge timing value */
669a5db4	206	regU \|= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
6a40da02 AC	207	/* Merge the control bits */
	208	regU \|= 1 << adev->devno; /* UDMA on */
	209	if (adev->dma_mode > 2) /* 15nS timing */
	210	regU \|= 4 << adev->devno;
	211	} else
669a5db4 JG	212	regD \|= mwdma_data[adev->dma_mode - XFER_MW_DMA_0] << shift;
	213
	214	regD \|= 0x20 << adev->devno;
	215
	216	pci_write_config_byte(pdev, pciU, regU);
	217	pci_write_config_byte(pdev, pciD, regD);
	218	}
	219
	220	/**
	221	* cmd648_dma_stop - DMA stop callback
	222	* @qc: Command in progress
	223	*
	224	* DMA has completed.
	225	*/
	226
	227	static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
	228	{
	229	struct ata_port *ap = qc->ap;
	230	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	231	u8 dma_intr;
6a40da02 AC	232	int dma_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
6a40da02 AC	233	int dma_reg = ap->port_no ? ARTTIM2 : CFR;
85cd7251	234
669a5db4	235	ata_bmdma_stop(qc);
85cd7251	236
669a5db4 JG	237	pci_read_config_byte(pdev, dma_reg, &dma_intr);
	238	pci_write_config_byte(pdev, dma_reg, dma_intr \| dma_mask);
	239	}
85cd7251	240
669a5db4 JG	241	/**
	242	* cmd646r1_dma_stop - DMA stop callback
	243	* @qc: Command in progress
	244	*
	245	* Stub for now while investigating the r1 quirk in the old driver.
	246	*/
	247
	248	static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
	249	{
	250	ata_bmdma_stop(qc);
	251	}
85cd7251	252
669a5db4 JG	253	static struct scsi_host_template cmd64x_sht = {
	254	.module = THIS_MODULE,
	255	.name = DRV_NAME,
	256	.ioctl = ata_scsi_ioctl,
	257	.queuecommand = ata_scsi_queuecmd,
	258	.can_queue = ATA_DEF_QUEUE,
	259	.this_id = ATA_SHT_THIS_ID,
	260	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	261	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	262	.emulated = ATA_SHT_EMULATED,
	263	.use_clustering = ATA_SHT_USE_CLUSTERING,
	264	.proc_name = DRV_NAME,
	265	.dma_boundary = ATA_DMA_BOUNDARY,
	266	.slave_configure = ata_scsi_slave_config,
afdfe899	267	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	268	.bios_param = ata_std_bios_param,
	269	};
	270
	271	static struct ata_port_operations cmd64x_port_ops = {
	272	.port_disable = ata_port_disable,
	273	.set_piomode = cmd64x_set_piomode,
	274	.set_dmamode = cmd64x_set_dmamode,
	275	.mode_filter = ata_pci_default_filter,
	276	.tf_load = ata_tf_load,
	277	.tf_read = ata_tf_read,
	278	.check_status = ata_check_status,
	279	.exec_command = ata_exec_command,
	280	.dev_select = ata_std_dev_select,
	281
	282	.freeze = ata_bmdma_freeze,
	283	.thaw = ata_bmdma_thaw,
a73984a0	284	.error_handler = ata_bmdma_error_handler,
669a5db4	285	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	286	.cable_detect = ata_cable_40wire,
669a5db4 JG	287
	288	.bmdma_setup = ata_bmdma_setup,
	289	.bmdma_start = ata_bmdma_start,
	290	.bmdma_stop = ata_bmdma_stop,
	291	.bmdma_status = ata_bmdma_status,
	292
	293	.qc_prep = ata_qc_prep,
	294	.qc_issue = ata_qc_issue_prot,
bda30288	295
0d5ff566	296	.data_xfer = ata_data_xfer,
669a5db4 JG	297
	298	.irq_handler = ata_interrupt,
	299	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	300	.irq_on = ata_irq_on,
246ce3b6 AI	301	.irq_ack = ata_irq_ack,
85cd7251	302
669a5db4	303	.port_start = ata_port_start,
85cd7251	304	};
669a5db4 JG	305
	306	static struct ata_port_operations cmd646r1_port_ops = {
	307	.port_disable = ata_port_disable,
	308	.set_piomode = cmd64x_set_piomode,
	309	.set_dmamode = cmd64x_set_dmamode,
	310	.mode_filter = ata_pci_default_filter,
	311	.tf_load = ata_tf_load,
	312	.tf_read = ata_tf_read,
	313	.check_status = ata_check_status,
	314	.exec_command = ata_exec_command,
	315	.dev_select = ata_std_dev_select,
	316
	317	.freeze = ata_bmdma_freeze,
	318	.thaw = ata_bmdma_thaw,
a73984a0	319	.error_handler = ata_bmdma_error_handler,
669a5db4	320	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	321	.cable_detect = ata_cable_40wire,
669a5db4 JG	322
	323	.bmdma_setup = ata_bmdma_setup,
	324	.bmdma_start = ata_bmdma_start,
	325	.bmdma_stop = cmd646r1_bmdma_stop,
	326	.bmdma_status = ata_bmdma_status,
	327
	328	.qc_prep = ata_qc_prep,
	329	.qc_issue = ata_qc_issue_prot,
bda30288	330
0d5ff566	331	.data_xfer = ata_data_xfer,
669a5db4 JG	332
	333	.irq_handler = ata_interrupt,
	334	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	335	.irq_on = ata_irq_on,
246ce3b6 AI	336	.irq_ack = ata_irq_ack,
85cd7251	337
669a5db4	338	.port_start = ata_port_start,
85cd7251	339	};
669a5db4 JG	340
	341	static struct ata_port_operations cmd648_port_ops = {
	342	.port_disable = ata_port_disable,
	343	.set_piomode = cmd64x_set_piomode,
	344	.set_dmamode = cmd64x_set_dmamode,
	345	.mode_filter = ata_pci_default_filter,
	346	.tf_load = ata_tf_load,
	347	.tf_read = ata_tf_read,
	348	.check_status = ata_check_status,
	349	.exec_command = ata_exec_command,
	350	.dev_select = ata_std_dev_select,
	351
	352	.freeze = ata_bmdma_freeze,
	353	.thaw = ata_bmdma_thaw,
a73984a0	354	.error_handler = ata_bmdma_error_handler,
669a5db4	355	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	356	.cable_detect = cmd648_cable_detect,
669a5db4 JG	357
	358	.bmdma_setup = ata_bmdma_setup,
	359	.bmdma_start = ata_bmdma_start,
	360	.bmdma_stop = cmd648_bmdma_stop,
	361	.bmdma_status = ata_bmdma_status,
	362
	363	.qc_prep = ata_qc_prep,
	364	.qc_issue = ata_qc_issue_prot,
bda30288	365
0d5ff566	366	.data_xfer = ata_data_xfer,
669a5db4 JG	367
	368	.irq_handler = ata_interrupt,
	369	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	370	.irq_on = ata_irq_on,
246ce3b6 AI	371	.irq_ack = ata_irq_ack,
85cd7251	372
669a5db4	373	.port_start = ata_port_start,
85cd7251 JG	374	};
85cd7251 JG	375
669a5db4 JG	376	static int cmd64x_init_one(struct pci_dev pdev, const struct pci_device_id id)
	377	{
	378	u32 class_rev;
85cd7251	379
1626aeb8	380	static const struct ata_port_info cmd_info[6] = {
669a5db4 JG	381	{ /* CMD 643 - no UDMA */
669a5db4 JG	382	.sht = &cmd64x_sht,
1d2808fd	383	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	384	.pio_mask = 0x1f,
	385	.mwdma_mask = 0x07,
	386	.port_ops = &cmd64x_port_ops
	387	},
	388	{ /* CMD 646 with broken UDMA */
	389	.sht = &cmd64x_sht,
1d2808fd	390	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	391	.pio_mask = 0x1f,
	392	.mwdma_mask = 0x07,
	393	.port_ops = &cmd64x_port_ops
	394	},
	395	{ /* CMD 646 with working UDMA */
	396	.sht = &cmd64x_sht,
1d2808fd	397	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	398	.pio_mask = 0x1f,
	399	.mwdma_mask = 0x07,
	400	.udma_mask = ATA_UDMA1,
	401	.port_ops = &cmd64x_port_ops
	402	},
	403	{ /* CMD 646 rev 1 */
	404	.sht = &cmd64x_sht,
1d2808fd	405	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	406	.pio_mask = 0x1f,
	407	.mwdma_mask = 0x07,
	408	.port_ops = &cmd646r1_port_ops
	409	},
	410	{ /* CMD 648 */
	411	.sht = &cmd64x_sht,
1d2808fd	412	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	413	.pio_mask = 0x1f,
	414	.mwdma_mask = 0x07,
	415	.udma_mask = ATA_UDMA2,
	416	.port_ops = &cmd648_port_ops
	417	},
	418	{ /* CMD 649 */
	419	.sht = &cmd64x_sht,
1d2808fd	420	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4 JG	421	.pio_mask = 0x1f,
	422	.mwdma_mask = 0x07,
	423	.udma_mask = ATA_UDMA3,
	424	.port_ops = &cmd648_port_ops
	425	}
	426	};
1626aeb8	427	const struct ata_port_info *ppi[] = { &cmd_info[id->driver_data], NULL };
669a5db4	428	u8 mrdmode;
85cd7251	429
669a5db4 JG	430	pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
669a5db4 JG	431	class_rev &= 0xFF;
85cd7251	432
669a5db4 JG	433	if (id->driver_data == 0) /* 643 */
669a5db4 JG	434	ata_pci_clear_simplex(pdev);
85cd7251	435
669a5db4 JG	436	if (pdev->device == PCI_DEVICE_ID_CMD_646) {
	437	/* Does UDMA work ? */
	438	if (class_rev > 4)
1626aeb8	439	ppi[0] = &cmd_info[2];
669a5db4 JG	440	/* Early rev with other problems ? */
669a5db4 JG	441	else if (class_rev == 1)
1626aeb8	442	ppi[0] = &cmd_info[3];
669a5db4 JG	443	}
	444
	445	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	446	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	447	mrdmode &= ~ 0x30; /* IRQ set up */
	448	mrdmode \|= 0x02; /* Memory read line enable */
	449	pci_write_config_byte(pdev, MRDMODE, mrdmode);
85cd7251	450
669a5db4	451	/* Force PIO 0 here.. */
85cd7251	452
669a5db4 JG	453	/* PPC specific fixup copied from old driver */
	454	#ifdef CONFIG_PPC
	455	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	456	#endif
85cd7251	457
1626aeb8	458	return ata_pci_init_one(pdev, ppi);
669a5db4 JG	459	}
669a5db4 JG	460
438ac6d5	461	#ifdef CONFIG_PM
7f72a379 AC	462	static int cmd64x_reinit_one(struct pci_dev *pdev)
	463	{
	464	u8 mrdmode;
	465	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
	466	pci_read_config_byte(pdev, MRDMODE, &mrdmode);
	467	mrdmode &= ~ 0x30; /* IRQ set up */
	468	mrdmode \|= 0x02; /* Memory read line enable */
	469	pci_write_config_byte(pdev, MRDMODE, mrdmode);
	470	#ifdef CONFIG_PPC
	471	pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
	472	#endif
	473	return ata_pci_device_resume(pdev);
	474	}
438ac6d5	475	#endif
7f72a379	476
2d2744fc JG	477	static const struct pci_device_id cmd64x[] = {
	478	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
	479	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
	480	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 4 },
	481	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 5 },
	482
	483	{ },
669a5db4 JG	484	};
	485
	486	static struct pci_driver cmd64x_pci_driver = {
2d2744fc	487	.name = DRV_NAME,
669a5db4 JG	488	.id_table = cmd64x,
669a5db4 JG	489	.probe = cmd64x_init_one,
7f72a379	490	.remove = ata_pci_remove_one,
438ac6d5	491	#ifdef CONFIG_PM
7f72a379 AC	492	.suspend = ata_pci_device_suspend,
7f72a379 AC	493	.resume = cmd64x_reinit_one,
438ac6d5	494	#endif
669a5db4 JG	495	};
	496
	497	static int __init cmd64x_init(void)
	498	{
	499	return pci_register_driver(&cmd64x_pci_driver);
	500	}
	501
669a5db4 JG	502	static void __exit cmd64x_exit(void)
	503	{
	504	pci_unregister_driver(&cmd64x_pci_driver);
	505	}
	506
669a5db4 JG	507	MODULE_AUTHOR("Alan Cox");
	508	MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
	509	MODULE_LICENSE("GPL");
	510	MODULE_DEVICE_TABLE(pci, cmd64x);
	511	MODULE_VERSION(DRV_VERSION);
	512
	513	module_init(cmd64x_init);
	514	module_exit(cmd64x_exit);