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[PATCH] libata: convert @post_reset to @flags in ata_dev_read_id()
[net-next-2.6.git] / drivers / ata / libata-core.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
1da177e4
LT		 35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/list.h>
40#include <linux/mm.h>
41#include <linux/highmem.h>
42#include <linux/spinlock.h>
43#include <linux/blkdev.h>
44#include <linux/delay.h>
45#include <linux/timer.h>
46#include <linux/interrupt.h>
47#include <linux/completion.h>
48#include <linux/suspend.h>
49#include <linux/workqueue.h>
67846b30 50#include <linux/jiffies.h>
378f058c 51#include <linux/scatterlist.h>
1da177e4 52#include <scsi/scsi.h>
193515d5 53#include <scsi/scsi_cmnd.h>
1da177e4
LT		 54#include <scsi/scsi_host.h>
55#include <linux/libata.h>
56#include <asm/io.h>
57#include <asm/semaphore.h>
58#include <asm/byteorder.h>
59
60#include "libata.h"
61
d7bb4cc7 62/* debounce timing parameters in msecs { interval, duration, timeout } */
e9c83914
TH		 63const unsigned long sata_deb_timing_normal[] = { 5, 100, 2000 };
64const unsigned long sata_deb_timing_hotplug[] = { 25, 500, 2000 };
65const unsigned long sata_deb_timing_long[] = { 100, 2000, 5000 };
d7bb4cc7 66
3373efd8
TH		 67static unsigned int ata_dev_init_params(struct ata_device *dev,
68 u16 heads, u16 sectors);
69static unsigned int ata_dev_set_xfermode(struct ata_device *dev);
70static void ata_dev_xfermask(struct ata_device *dev);
1da177e4
LT		 71
72static unsigned int ata_unique_id = 1;
73static struct workqueue_struct *ata_wq;
74
453b07ac
TH		 75struct workqueue_struct *ata_aux_wq;
76
418dc1f5 77int atapi_enabled = 1;
1623c81e
JG		 78module_param(atapi_enabled, int, 0444);
79MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
80
95de719a
AL		 81int atapi_dmadir = 0;
82module_param(atapi_dmadir, int, 0444);
83MODULE_PARM_DESC(atapi_dmadir, "Enable ATAPI DMADIR bridge support (0=off, 1=on)");
84
c3c013a2
JG		 85int libata_fua = 0;
86module_param_named(fua, libata_fua, int, 0444);
87MODULE_PARM_DESC(fua, "FUA support (0=off, 1=on)");
88
a8601e5f
AM		 89static int ata_probe_timeout = ATA_TMOUT_INTERNAL / HZ;
90module_param(ata_probe_timeout, int, 0444);
91MODULE_PARM_DESC(ata_probe_timeout, "Set ATA probing timeout (seconds)");
92
1da177e4
LT		 93MODULE_AUTHOR("Jeff Garzik");
94MODULE_DESCRIPTION("Library module for ATA devices");
95MODULE_LICENSE("GPL");
96MODULE_VERSION(DRV_VERSION);
97
0baab86b 98
1da177e4
LT		 99/**
100 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
101 * @tf: Taskfile to convert
102 * @fis: Buffer into which data will output
103 * @pmp: Port multiplier port
104 *
105 * Converts a standard ATA taskfile to a Serial ATA
106 * FIS structure (Register - Host to Device).
107 *
108 * LOCKING:
109 * Inherited from caller.
110 */
111
057ace5e 112void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 113{
114 fis[0] = 0x27; /* Register - Host to Device FIS */
115 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
116 bit 7 indicates Command FIS */
117 fis[2] = tf->command;
118 fis[3] = tf->feature;
119
120 fis[4] = tf->lbal;
121 fis[5] = tf->lbam;
122 fis[6] = tf->lbah;
123 fis[7] = tf->device;
124
125 fis[8] = tf->hob_lbal;
126 fis[9] = tf->hob_lbam;
127 fis[10] = tf->hob_lbah;
128 fis[11] = tf->hob_feature;
129
130 fis[12] = tf->nsect;
131 fis[13] = tf->hob_nsect;
132 fis[14] = 0;
133 fis[15] = tf->ctl;
134
135 fis[16] = 0;
136 fis[17] = 0;
137 fis[18] = 0;
138 fis[19] = 0;
139}
140
141/**
142 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
143 * @fis: Buffer from which data will be input
144 * @tf: Taskfile to output
145 *
e12a1be6 146 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 147 *
148 * LOCKING:
149 * Inherited from caller.
150 */
151
057ace5e 152void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 153{
154 tf->command = fis[2]; /* status */
155 tf->feature = fis[3]; /* error */
156
157 tf->lbal = fis[4];
158 tf->lbam = fis[5];
159 tf->lbah = fis[6];
160 tf->device = fis[7];
161
162 tf->hob_lbal = fis[8];
163 tf->hob_lbam = fis[9];
164 tf->hob_lbah = fis[10];
165
166 tf->nsect = fis[12];
167 tf->hob_nsect = fis[13];
168}
169
8cbd6df1
AL		 170static const u8 ata_rw_cmds[] = {
171 /* pio multi */
172 ATA_CMD_READ_MULTI,
173 ATA_CMD_WRITE_MULTI,
174 ATA_CMD_READ_MULTI_EXT,
175 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 176 0,
177 0,
178 0,
179 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 180 /* pio */
181 ATA_CMD_PIO_READ,
182 ATA_CMD_PIO_WRITE,
183 ATA_CMD_PIO_READ_EXT,
184 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 185 0,
186 0,
187 0,
188 0,
8cbd6df1
AL		 189 /* dma */
190 ATA_CMD_READ,
191 ATA_CMD_WRITE,
192 ATA_CMD_READ_EXT,
9a3dccc4
TH		 193 ATA_CMD_WRITE_EXT,
194 0,
195 0,
196 0,
197 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 198};
1da177e4
LT		 199
200/**
8cbd6df1
AL		 201 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
202 * @qc: command to examine and configure
1da177e4 203 *
2e9edbf8 204 * Examine the device configuration and tf->flags to calculate
8cbd6df1 205 * the proper read/write commands and protocol to use.
1da177e4
LT		 206 *
207 * LOCKING:
208 * caller.
209 */
9a3dccc4 210int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 211{
8cbd6df1
AL		 212 struct ata_taskfile *tf = &qc->tf;
213 struct ata_device *dev = qc->dev;
9a3dccc4 214 u8 cmd;
1da177e4 215
9a3dccc4 216 int index, fua, lba48, write;
2e9edbf8 217
9a3dccc4 218 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 219 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
220 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 221
8cbd6df1
AL		 222 if (dev->flags & ATA_DFLAG_PIO) {
223 tf->protocol = ATA_PROT_PIO;
9a3dccc4 224 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 225 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
226 /* Unable to use DMA due to host limitation */
227 tf->protocol = ATA_PROT_PIO;
0565c26d 228 index = dev->multi_count ? 0 : 8;
8cbd6df1
AL		 229 } else {
230 tf->protocol = ATA_PROT_DMA;
9a3dccc4 231 index = 16;
8cbd6df1 232 }
1da177e4 233
9a3dccc4
TH		 234 cmd = ata_rw_cmds[index + fua + lba48 + write];
235 if (cmd) {
236 tf->command = cmd;
237 return 0;
238 }
239 return -1;
1da177e4
LT		 240}
241
cb95d562
TH		 242/**
243 * ata_pack_xfermask - Pack pio, mwdma and udma masks into xfer_mask
244 * @pio_mask: pio_mask
245 * @mwdma_mask: mwdma_mask
246 * @udma_mask: udma_mask
247 *
248 * Pack @pio_mask, @mwdma_mask and @udma_mask into a single
249 * unsigned int xfer_mask.
250 *
251 * LOCKING:
252 * None.
253 *
254 * RETURNS:
255 * Packed xfer_mask.
256 */
257static unsigned int ata_pack_xfermask(unsigned int pio_mask,
258 unsigned int mwdma_mask,
259 unsigned int udma_mask)
260{
261 return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
262 ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
263 ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
264}
265
c0489e4e
TH		 266/**
267 * ata_unpack_xfermask - Unpack xfer_mask into pio, mwdma and udma masks
268 * @xfer_mask: xfer_mask to unpack
269 * @pio_mask: resulting pio_mask
270 * @mwdma_mask: resulting mwdma_mask
271 * @udma_mask: resulting udma_mask
272 *
273 * Unpack @xfer_mask into @pio_mask, @mwdma_mask and @udma_mask.
274 * Any NULL distination masks will be ignored.
275 */
276static void ata_unpack_xfermask(unsigned int xfer_mask,
277 unsigned int *pio_mask,
278 unsigned int *mwdma_mask,
279 unsigned int *udma_mask)
280{
281 if (pio_mask)
282 *pio_mask = (xfer_mask & ATA_MASK_PIO) >> ATA_SHIFT_PIO;
283 if (mwdma_mask)
284 *mwdma_mask = (xfer_mask & ATA_MASK_MWDMA) >> ATA_SHIFT_MWDMA;
285 if (udma_mask)
286 *udma_mask = (xfer_mask & ATA_MASK_UDMA) >> ATA_SHIFT_UDMA;
287}
288
cb95d562 289static const struct ata_xfer_ent {
be9a50c8 290 int shift, bits;
cb95d562
TH		 291 u8 base;
292} ata_xfer_tbl[] = {
293 { ATA_SHIFT_PIO, ATA_BITS_PIO, XFER_PIO_0 },
294 { ATA_SHIFT_MWDMA, ATA_BITS_MWDMA, XFER_MW_DMA_0 },
295 { ATA_SHIFT_UDMA, ATA_BITS_UDMA, XFER_UDMA_0 },
296 { -1, },
297};
298
299/**
300 * ata_xfer_mask2mode - Find matching XFER_* for the given xfer_mask
301 * @xfer_mask: xfer_mask of interest
302 *
303 * Return matching XFER_* value for @xfer_mask. Only the highest
304 * bit of @xfer_mask is considered.
305 *
306 * LOCKING:
307 * None.
308 *
309 * RETURNS:
310 * Matching XFER_* value, 0 if no match found.
311 */
312static u8 ata_xfer_mask2mode(unsigned int xfer_mask)
313{
314 int highbit = fls(xfer_mask) - 1;
315 const struct ata_xfer_ent *ent;
316
317 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
318 if (highbit >= ent->shift && highbit < ent->shift + ent->bits)
319 return ent->base + highbit - ent->shift;
320 return 0;
321}
322
323/**
324 * ata_xfer_mode2mask - Find matching xfer_mask for XFER_*
325 * @xfer_mode: XFER_* of interest
326 *
327 * Return matching xfer_mask for @xfer_mode.
328 *
329 * LOCKING:
330 * None.
331 *
332 * RETURNS:
333 * Matching xfer_mask, 0 if no match found.
334 */
335static unsigned int ata_xfer_mode2mask(u8 xfer_mode)
336{
337 const struct ata_xfer_ent *ent;
338
339 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
340 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
341 return 1 << (ent->shift + xfer_mode - ent->base);
342 return 0;
343}
344
345/**
346 * ata_xfer_mode2shift - Find matching xfer_shift for XFER_*
347 * @xfer_mode: XFER_* of interest
348 *
349 * Return matching xfer_shift for @xfer_mode.
350 *
351 * LOCKING:
352 * None.
353 *
354 * RETURNS:
355 * Matching xfer_shift, -1 if no match found.
356 */
357static int ata_xfer_mode2shift(unsigned int xfer_mode)
358{
359 const struct ata_xfer_ent *ent;
360
361 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
362 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
363 return ent->shift;
364 return -1;
365}
366
1da177e4 367/**
1da7b0d0
TH		 368 * ata_mode_string - convert xfer_mask to string
369 * @xfer_mask: mask of bits supported; only highest bit counts.
1da177e4
LT		 370 *
371 * Determine string which represents the highest speed
1da7b0d0 372 * (highest bit in @modemask).
1da177e4
LT		 373 *
374 * LOCKING:
375 * None.
376 *
377 * RETURNS:
378 * Constant C string representing highest speed listed in
1da7b0d0 379 * @mode_mask, or the constant C string "<n/a>".
1da177e4 380 */
1da7b0d0 381static const char *ata_mode_string(unsigned int xfer_mask)
1da177e4 382{
75f554bc
TH		 383 static const char * const xfer_mode_str[] = {
384 "PIO0",
385 "PIO1",
386 "PIO2",
387 "PIO3",
388 "PIO4",
b352e57d
AC		 389 "PIO5",
390 "PIO6",
75f554bc
TH		 391 "MWDMA0",
392 "MWDMA1",
393 "MWDMA2",
b352e57d
AC		 394 "MWDMA3",
395 "MWDMA4",
75f554bc
TH		 396 "UDMA/16",
397 "UDMA/25",
398 "UDMA/33",
399 "UDMA/44",
400 "UDMA/66",
401 "UDMA/100",
402 "UDMA/133",
403 "UDMA7",
404 };
1da7b0d0 405 int highbit;
1da177e4 406
1da7b0d0
TH		 407 highbit = fls(xfer_mask) - 1;
408 if (highbit >= 0 && highbit < ARRAY_SIZE(xfer_mode_str))
409 return xfer_mode_str[highbit];
1da177e4 410 return "<n/a>";
1da177e4
LT		 411}
412
4c360c81
TH		 413static const char *sata_spd_string(unsigned int spd)
414{
415 static const char * const spd_str[] = {
416 "1.5 Gbps",
417 "3.0 Gbps",
418 };
419
420 if (spd == 0 || (spd - 1) >= ARRAY_SIZE(spd_str))
421 return "<unknown>";
422 return spd_str[spd - 1];
423}
424
3373efd8 425void ata_dev_disable(struct ata_device *dev)
0b8efb0a 426{
0dd4b21f 427 if (ata_dev_enabled(dev) && ata_msg_drv(dev->ap)) {
f15a1daf 428 ata_dev_printk(dev, KERN_WARNING, "disabled\n");
0b8efb0a
TH		 429 dev->class++;
430 }
431}
432
1da177e4
LT		 433/**
434 * ata_pio_devchk - PATA device presence detection
435 * @ap: ATA channel to examine
436 * @device: Device to examine (starting at zero)
437 *
438 * This technique was originally described in
439 * Hale Landis's ATADRVR (www.ata-atapi.com), and
440 * later found its way into the ATA/ATAPI spec.
441 *
442 * Write a pattern to the ATA shadow registers,
443 * and if a device is present, it will respond by
444 * correctly storing and echoing back the
445 * ATA shadow register contents.
446 *
447 * LOCKING:
448 * caller.
449 */
450
451static unsigned int ata_pio_devchk(struct ata_port *ap,
452 unsigned int device)
453{
454 struct ata_ioports *ioaddr = &ap->ioaddr;
455 u8 nsect, lbal;
456
457 ap->ops->dev_select(ap, device);
458
459 outb(0x55, ioaddr->nsect_addr);
460 outb(0xaa, ioaddr->lbal_addr);
461
462 outb(0xaa, ioaddr->nsect_addr);
463 outb(0x55, ioaddr->lbal_addr);
464
465 outb(0x55, ioaddr->nsect_addr);
466 outb(0xaa, ioaddr->lbal_addr);
467
468 nsect = inb(ioaddr->nsect_addr);
469 lbal = inb(ioaddr->lbal_addr);
470
471 if ((nsect == 0x55) && (lbal == 0xaa))
472 return 1; /* we found a device */
473
474 return 0; /* nothing found */
475}
476
477/**
478 * ata_mmio_devchk - PATA device presence detection
479 * @ap: ATA channel to examine
480 * @device: Device to examine (starting at zero)
481 *
482 * This technique was originally described in
483 * Hale Landis's ATADRVR (www.ata-atapi.com), and
484 * later found its way into the ATA/ATAPI spec.
485 *
486 * Write a pattern to the ATA shadow registers,
487 * and if a device is present, it will respond by
488 * correctly storing and echoing back the
489 * ATA shadow register contents.
490 *
491 * LOCKING:
492 * caller.
493 */
494
495static unsigned int ata_mmio_devchk(struct ata_port *ap,
496 unsigned int device)
497{
498 struct ata_ioports *ioaddr = &ap->ioaddr;
499 u8 nsect, lbal;
500
501 ap->ops->dev_select(ap, device);
502
503 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
504 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
505
506 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
507 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
508
509 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
510 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
511
512 nsect = readb((void __iomem *) ioaddr->nsect_addr);
513 lbal = readb((void __iomem *) ioaddr->lbal_addr);
514
515 if ((nsect == 0x55) && (lbal == 0xaa))
516 return 1; /* we found a device */
517
518 return 0; /* nothing found */
519}
520
521/**
522 * ata_devchk - PATA device presence detection
523 * @ap: ATA channel to examine
524 * @device: Device to examine (starting at zero)
525 *
526 * Dispatch ATA device presence detection, depending
527 * on whether we are using PIO or MMIO to talk to the
528 * ATA shadow registers.
529 *
530 * LOCKING:
531 * caller.
532 */
533
534static unsigned int ata_devchk(struct ata_port *ap,
535 unsigned int device)
536{
537 if (ap->flags & ATA_FLAG_MMIO)
538 return ata_mmio_devchk(ap, device);
539 return ata_pio_devchk(ap, device);
540}
541
542/**
543 * ata_dev_classify - determine device type based on ATA-spec signature
544 * @tf: ATA taskfile register set for device to be identified
545 *
546 * Determine from taskfile register contents whether a device is
547 * ATA or ATAPI, as per "Signature and persistence" section
548 * of ATA/PI spec (volume 1, sect 5.14).
549 *
550 * LOCKING:
551 * None.
552 *
553 * RETURNS:
554 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
555 * the event of failure.
556 */
557
057ace5e 558unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 559{
560 /* Apple's open source Darwin code hints that some devices only
561 * put a proper signature into the LBA mid/high registers,
562 * So, we only check those. It's sufficient for uniqueness.
563 */
564
565 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
566 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
567 DPRINTK("found ATA device by sig\n");
568 return ATA_DEV_ATA;
569 }
570
571 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
572 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
573 DPRINTK("found ATAPI device by sig\n");
574 return ATA_DEV_ATAPI;
575 }
576
577 DPRINTK("unknown device\n");
578 return ATA_DEV_UNKNOWN;
579}
580
581/**
582 * ata_dev_try_classify - Parse returned ATA device signature
583 * @ap: ATA channel to examine
584 * @device: Device to examine (starting at zero)
b4dc7623 585 * @r_err: Value of error register on completion
1da177e4
LT		 586 *
587 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
588 * an ATA/ATAPI-defined set of values is placed in the ATA
589 * shadow registers, indicating the results of device detection
590 * and diagnostics.
591 *
592 * Select the ATA device, and read the values from the ATA shadow
593 * registers. Then parse according to the Error register value,
594 * and the spec-defined values examined by ata_dev_classify().
595 *
596 * LOCKING:
597 * caller.
b4dc7623
TH		 598 *
599 * RETURNS:
600 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 601 */
602
b4dc7623
TH		 603static unsigned int
604ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 605{
1da177e4
LT		 606 struct ata_taskfile tf;
607 unsigned int class;
608 u8 err;
609
610 ap->ops->dev_select(ap, device);
611
612 memset(&tf, 0, sizeof(tf));
613
1da177e4 614 ap->ops->tf_read(ap, &tf);
0169e284 615 err = tf.feature;
b4dc7623
TH		 616 if (r_err)
617 *r_err = err;
1da177e4 618
93590859
AC		 619 /* see if device passed diags: if master then continue and warn later */
620 if (err == 0 && device == 0)
621 /* diagnostic fail : do nothing _YET_ */
622 ap->device[device].horkage |= ATA_HORKAGE_DIAGNOSTIC;
623 else if (err == 1)
1da177e4
LT		 624 /* do nothing */ ;
625 else if ((device == 0) && (err == 0x81))
626 /* do nothing */ ;
627 else
b4dc7623 628 return ATA_DEV_NONE;
1da177e4 629
b4dc7623 630 /* determine if device is ATA or ATAPI */
1da177e4 631 class = ata_dev_classify(&tf);
b4dc7623 632
1da177e4 633 if (class == ATA_DEV_UNKNOWN)
b4dc7623 634 return ATA_DEV_NONE;
1da177e4 635 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 636 return ATA_DEV_NONE;
637 return class;
1da177e4
LT		 638}
639
640/**
6a62a04d 641 * ata_id_string - Convert IDENTIFY DEVICE page into string
1da177e4
LT		 642 * @id: IDENTIFY DEVICE results we will examine
643 * @s: string into which data is output
644 * @ofs: offset into identify device page
645 * @len: length of string to return. must be an even number.
646 *
647 * The strings in the IDENTIFY DEVICE page are broken up into
648 * 16-bit chunks. Run through the string, and output each
649 * 8-bit chunk linearly, regardless of platform.
650 *
651 * LOCKING:
652 * caller.
653 */
654
6a62a04d
TH		 655void ata_id_string(const u16 *id, unsigned char *s,
656 unsigned int ofs, unsigned int len)
1da177e4
LT		 657{
658 unsigned int c;
659
660 while (len > 0) {
661 c = id[ofs] >> 8;
662 *s = c;
663 s++;
664
665 c = id[ofs] & 0xff;
666 *s = c;
667 s++;
668
669 ofs++;
670 len -= 2;
671 }
672}
673
0e949ff3 674/**
6a62a04d 675 * ata_id_c_string - Convert IDENTIFY DEVICE page into C string
0e949ff3
TH		 676 * @id: IDENTIFY DEVICE results we will examine
677 * @s: string into which data is output
678 * @ofs: offset into identify device page
679 * @len: length of string to return. must be an odd number.
680 *
6a62a04d 681 * This function is identical to ata_id_string except that it
0e949ff3
TH		 682 * trims trailing spaces and terminates the resulting string with
683 * null. @len must be actual maximum length (even number) + 1.
684 *
685 * LOCKING:
686 * caller.
687 */
6a62a04d
TH		 688void ata_id_c_string(const u16 *id, unsigned char *s,
689 unsigned int ofs, unsigned int len)
0e949ff3
TH		 690{
691 unsigned char *p;
692
693 WARN_ON(!(len & 1));
694
6a62a04d 695 ata_id_string(id, s, ofs, len - 1);
0e949ff3
TH		 696
697 p = s + strnlen(s, len - 1);
698 while (p > s && p[-1] == ' ')
699 p--;
700 *p = '\0';
701}
0baab86b 702
2940740b
TH		 703static u64 ata_id_n_sectors(const u16 *id)
704{
705 if (ata_id_has_lba(id)) {
706 if (ata_id_has_lba48(id))
707 return ata_id_u64(id, 100);
708 else
709 return ata_id_u32(id, 60);
710 } else {
711 if (ata_id_current_chs_valid(id))
712 return ata_id_u32(id, 57);
713 else
714 return id[1] * id[3] * id[6];
715 }
716}
717
0baab86b
EF		 718/**
719 * ata_noop_dev_select - Select device 0/1 on ATA bus
720 * @ap: ATA channel to manipulate
721 * @device: ATA device (numbered from zero) to select
722 *
723 * This function performs no actual function.
724 *
725 * May be used as the dev_select() entry in ata_port_operations.
726 *
727 * LOCKING:
728 * caller.
729 */
1da177e4
LT		 730void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
731{
732}
733
0baab86b 734
1da177e4
LT		 735/**
736 * ata_std_dev_select - Select device 0/1 on ATA bus
737 * @ap: ATA channel to manipulate
738 * @device: ATA device (numbered from zero) to select
739 *
740 * Use the method defined in the ATA specification to
741 * make either device 0, or device 1, active on the
0baab86b
EF		 742 * ATA channel. Works with both PIO and MMIO.
743 *
744 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 745 *
746 * LOCKING:
747 * caller.
748 */
749
750void ata_std_dev_select (struct ata_port *ap, unsigned int device)
751{
752 u8 tmp;
753
754 if (device == 0)
755 tmp = ATA_DEVICE_OBS;
756 else
757 tmp = ATA_DEVICE_OBS | ATA_DEV1;
758
759 if (ap->flags & ATA_FLAG_MMIO) {
760 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
761 } else {
762 outb(tmp, ap->ioaddr.device_addr);
763 }
764 ata_pause(ap); /* needed; also flushes, for mmio */
765}
766
767/**
768 * ata_dev_select - Select device 0/1 on ATA bus
769 * @ap: ATA channel to manipulate
770 * @device: ATA device (numbered from zero) to select
771 * @wait: non-zero to wait for Status register BSY bit to clear
772 * @can_sleep: non-zero if context allows sleeping
773 *
774 * Use the method defined in the ATA specification to
775 * make either device 0, or device 1, active on the
776 * ATA channel.
777 *
778 * This is a high-level version of ata_std_dev_select(),
779 * which additionally provides the services of inserting
780 * the proper pauses and status polling, where needed.
781 *
782 * LOCKING:
783 * caller.
784 */
785
786void ata_dev_select(struct ata_port *ap, unsigned int device,
787 unsigned int wait, unsigned int can_sleep)
788{
88574551 789 if (ata_msg_probe(ap))
0dd4b21f 790 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, ata%u: "
88574551 791 "device %u, wait %u\n", ap->id, device, wait);
1da177e4
LT		 792
793 if (wait)
794 ata_wait_idle(ap);
795
796 ap->ops->dev_select(ap, device);
797
798 if (wait) {
799 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
800 msleep(150);
801 ata_wait_idle(ap);
802 }
803}
804
805/**
806 * ata_dump_id - IDENTIFY DEVICE info debugging output
0bd3300a 807 * @id: IDENTIFY DEVICE page to dump
1da177e4 808 *
0bd3300a
TH		 809 * Dump selected 16-bit words from the given IDENTIFY DEVICE
810 * page.
1da177e4
LT		 811 *
812 * LOCKING:
813 * caller.
814 */
815
0bd3300a 816static inline void ata_dump_id(const u16 *id)
1da177e4
LT		 817{
818 DPRINTK("49==0x%04x "
819 "53==0x%04x "
820 "63==0x%04x "
821 "64==0x%04x "
822 "75==0x%04x \n",
0bd3300a
TH		 823 id[49],
824 id[53],
825 id[63],
826 id[64],
827 id[75]);
1da177e4
LT		 828 DPRINTK("80==0x%04x "
829 "81==0x%04x "
830 "82==0x%04x "
831 "83==0x%04x "
832 "84==0x%04x \n",
0bd3300a
TH		 833 id[80],
834 id[81],
835 id[82],
836 id[83],
837 id[84]);
1da177e4
LT		 838 DPRINTK("88==0x%04x "
839 "93==0x%04x\n",
0bd3300a
TH		 840 id[88],
841 id[93]);
1da177e4
LT		 842}
843
cb95d562
TH		 844/**
845 * ata_id_xfermask - Compute xfermask from the given IDENTIFY data
846 * @id: IDENTIFY data to compute xfer mask from
847 *
848 * Compute the xfermask for this device. This is not as trivial
849 * as it seems if we must consider early devices correctly.
850 *
851 * FIXME: pre IDE drive timing (do we care ?).
852 *
853 * LOCKING:
854 * None.
855 *
856 * RETURNS:
857 * Computed xfermask
858 */
859static unsigned int ata_id_xfermask(const u16 *id)
860{
861 unsigned int pio_mask, mwdma_mask, udma_mask;
862
863 /* Usual case. Word 53 indicates word 64 is valid */
864 if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
865 pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
866 pio_mask <<= 3;
867 pio_mask |= 0x7;
868 } else {
869 /* If word 64 isn't valid then Word 51 high byte holds
870 * the PIO timing number for the maximum. Turn it into
871 * a mask.
872 */
46767aeb
AC		 873 u8 mode = id[ATA_ID_OLD_PIO_MODES] & 0xFF;
874 if (mode < 5) /* Valid PIO range */
875 pio_mask = (2 << mode) - 1;
876 else
877 pio_mask = 1;
cb95d562
TH		 878
879 /* But wait.. there's more. Design your standards by
880 * committee and you too can get a free iordy field to
881 * process. However its the speeds not the modes that
882 * are supported... Note drivers using the timing API
883 * will get this right anyway
884 */
885 }
886
887 mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
fb21f0d0 888
b352e57d
AC		 889 if (ata_id_is_cfa(id)) {
890 /*
891 * Process compact flash extended modes
892 */
893 int pio = id[163] & 0x7;
894 int dma = (id[163] >> 3) & 7;
895
896 if (pio)
897 pio_mask |= (1 << 5);
898 if (pio > 1)
899 pio_mask |= (1 << 6);
900 if (dma)
901 mwdma_mask |= (1 << 3);
902 if (dma > 1)
903 mwdma_mask |= (1 << 4);
904 }
905
fb21f0d0
TH		 906 udma_mask = 0;
907 if (id[ATA_ID_FIELD_VALID] & (1 << 2))
908 udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
cb95d562
TH		 909
910 return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
911}
912
86e45b6b
TH		 913/**
914 * ata_port_queue_task - Queue port_task
915 * @ap: The ata_port to queue port_task for
e2a7f77a
RD		 916 * @fn: workqueue function to be scheduled
917 * @data: data value to pass to workqueue function
918 * @delay: delay time for workqueue function
86e45b6b
TH		 919 *
920 * Schedule @fn(@data) for execution after @delay jiffies using
921 * port_task. There is one port_task per port and it's the
922 * user(low level driver)'s responsibility to make sure that only
923 * one task is active at any given time.
924 *
925 * libata core layer takes care of synchronization between
926 * port_task and EH. ata_port_queue_task() may be ignored for EH
927 * synchronization.
928 *
929 * LOCKING:
930 * Inherited from caller.
931 */
932void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *), void *data,
933 unsigned long delay)
934{
935 int rc;
936
b51e9e5d 937 if (ap->pflags & ATA_PFLAG_FLUSH_PORT_TASK)
86e45b6b
TH		 938 return;
939
940 PREPARE_WORK(&ap->port_task, fn, data);
941
942 if (!delay)
943 rc = queue_work(ata_wq, &ap->port_task);
944 else
945 rc = queue_delayed_work(ata_wq, &ap->port_task, delay);
946
947 /* rc == 0 means that another user is using port task */
948 WARN_ON(rc == 0);
949}
950
951/**
952 * ata_port_flush_task - Flush port_task
953 * @ap: The ata_port to flush port_task for
954 *
955 * After this function completes, port_task is guranteed not to
956 * be running or scheduled.
957 *
958 * LOCKING:
959 * Kernel thread context (may sleep)
960 */
961void ata_port_flush_task(struct ata_port *ap)
962{
963 unsigned long flags;
964
965 DPRINTK("ENTER\n");
966
ba6a1308 967 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 968 ap->pflags |= ATA_PFLAG_FLUSH_PORT_TASK;
ba6a1308 969 spin_unlock_irqrestore(ap->lock, flags);
86e45b6b
TH		 970
971 DPRINTK("flush #1\n");
972 flush_workqueue(ata_wq);
973
974 /*
975 * At this point, if a task is running, it's guaranteed to see
976 * the FLUSH flag; thus, it will never queue pio tasks again.
977 * Cancel and flush.
978 */
979 if (!cancel_delayed_work(&ap->port_task)) {
0dd4b21f 980 if (ata_msg_ctl(ap))
88574551
TH		 981 ata_port_printk(ap, KERN_DEBUG, "%s: flush #2\n",
982 __FUNCTION__);
86e45b6b
TH		 983 flush_workqueue(ata_wq);
984 }
985
ba6a1308 986 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 987 ap->pflags &= ~ATA_PFLAG_FLUSH_PORT_TASK;
ba6a1308 988 spin_unlock_irqrestore(ap->lock, flags);
86e45b6b 989
0dd4b21f
BP		 990 if (ata_msg_ctl(ap))
991 ata_port_printk(ap, KERN_DEBUG, "%s: EXIT\n", __FUNCTION__);
86e45b6b
TH		 992}
993
77853bf2 994void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 995{
77853bf2 996 struct completion *waiting = qc->private_data;
a2a7a662 997
a2a7a662 998 complete(waiting);
a2a7a662
TH		 999}
1000
1001/**
1002 * ata_exec_internal - execute libata internal command
a2a7a662
TH		 1003 * @dev: Device to which the command is sent
1004 * @tf: Taskfile registers for the command and the result
d69cf37d 1005 * @cdb: CDB for packet command
a2a7a662
TH		 1006 * @dma_dir: Data tranfer direction of the command
1007 * @buf: Data buffer of the command
1008 * @buflen: Length of data buffer
1009 *
1010 * Executes libata internal command with timeout. @tf contains
1011 * command on entry and result on return. Timeout and error
1012 * conditions are reported via return value. No recovery action
1013 * is taken after a command times out. It's caller's duty to
1014 * clean up after timeout.
1015 *
1016 * LOCKING:
1017 * None. Should be called with kernel context, might sleep.
551e8889
TH		 1018 *
1019 * RETURNS:
1020 * Zero on success, AC_ERR_* mask on failure
a2a7a662 1021 */
3373efd8 1022unsigned ata_exec_internal(struct ata_device *dev,
1ad8e7f9
TH		 1023 struct ata_taskfile *tf, const u8 *cdb,
1024 int dma_dir, void *buf, unsigned int buflen)
a2a7a662 1025{
3373efd8 1026 struct ata_port *ap = dev->ap;
a2a7a662
TH		 1027 u8 command = tf->command;
1028 struct ata_queued_cmd *qc;
2ab7db1f 1029 unsigned int tag, preempted_tag;
dedaf2b0 1030 u32 preempted_sactive, preempted_qc_active;
60be6b9a 1031 DECLARE_COMPLETION_ONSTACK(wait);
a2a7a662 1032 unsigned long flags;
77853bf2 1033 unsigned int err_mask;
d95a717f 1034 int rc;
a2a7a662 1035
ba6a1308 1036 spin_lock_irqsave(ap->lock, flags);
a2a7a662 1037
e3180499 1038 /* no internal command while frozen */
b51e9e5d 1039 if (ap->pflags & ATA_PFLAG_FROZEN) {
ba6a1308 1040 spin_unlock_irqrestore(ap->lock, flags);
e3180499
TH		 1041 return AC_ERR_SYSTEM;
1042 }
1043
2ab7db1f 1044 /* initialize internal qc */
a2a7a662 1045
2ab7db1f
TH		 1046 /* XXX: Tag 0 is used for drivers with legacy EH as some
1047 * drivers choke if any other tag is given. This breaks
1048 * ata_tag_internal() test for those drivers. Don't use new
1049 * EH stuff without converting to it.
1050 */
1051 if (ap->ops->error_handler)
1052 tag = ATA_TAG_INTERNAL;
1053 else
1054 tag = 0;
1055
6cec4a39 1056 if (test_and_set_bit(tag, &ap->qc_allocated))
2ab7db1f 1057 BUG();
f69499f4 1058 qc = __ata_qc_from_tag(ap, tag);
2ab7db1f
TH		 1059
1060 qc->tag = tag;
1061 qc->scsicmd = NULL;
1062 qc->ap = ap;
1063 qc->dev = dev;
1064 ata_qc_reinit(qc);
1065
1066 preempted_tag = ap->active_tag;
dedaf2b0
TH		 1067 preempted_sactive = ap->sactive;
1068 preempted_qc_active = ap->qc_active;
2ab7db1f 1069 ap->active_tag = ATA_TAG_POISON;
dedaf2b0
TH		 1070 ap->sactive = 0;
1071 ap->qc_active = 0;
2ab7db1f
TH		 1072
1073 /* prepare & issue qc */
a2a7a662 1074 qc->tf = *tf;
d69cf37d
TH		 1075 if (cdb)
1076 memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
e61e0672 1077 qc->flags |= ATA_QCFLAG_RESULT_TF;
a2a7a662
TH		 1078 qc->dma_dir = dma_dir;
1079 if (dma_dir != DMA_NONE) {
1080 ata_sg_init_one(qc, buf, buflen);
1081 qc->nsect = buflen / ATA_SECT_SIZE;
1082 }
1083
77853bf2 1084 qc->private_data = &wait;
a2a7a662
TH		 1085 qc->complete_fn = ata_qc_complete_internal;
1086
8e0e694a 1087 ata_qc_issue(qc);
a2a7a662 1088
ba6a1308 1089 spin_unlock_irqrestore(ap->lock, flags);
a2a7a662 1090
a8601e5f 1091 rc = wait_for_completion_timeout(&wait, ata_probe_timeout);
d95a717f
TH		 1092
1093 ata_port_flush_task(ap);
41ade50c 1094
d95a717f 1095 if (!rc) {
ba6a1308 1096 spin_lock_irqsave(ap->lock, flags);
a2a7a662
TH		 1097
1098 /* We're racing with irq here. If we lose, the
1099 * following test prevents us from completing the qc
d95a717f
TH		 1100 * twice. If we win, the port is frozen and will be
1101 * cleaned up by ->post_internal_cmd().
a2a7a662 1102 */
77853bf2 1103 if (qc->flags & ATA_QCFLAG_ACTIVE) {
d95a717f
TH		 1104 qc->err_mask |= AC_ERR_TIMEOUT;
1105
1106 if (ap->ops->error_handler)
1107 ata_port_freeze(ap);
1108 else
1109 ata_qc_complete(qc);
f15a1daf 1110
0dd4b21f
BP		 1111 if (ata_msg_warn(ap))
1112 ata_dev_printk(dev, KERN_WARNING,
88574551 1113 "qc timeout (cmd 0x%x)\n", command);
a2a7a662
TH		 1114 }
1115
ba6a1308 1116 spin_unlock_irqrestore(ap->lock, flags);
a2a7a662
TH		 1117 }
1118
d95a717f
TH		 1119 /* do post_internal_cmd */
1120 if (ap->ops->post_internal_cmd)
1121 ap->ops->post_internal_cmd(qc);
1122
1123 if (qc->flags & ATA_QCFLAG_FAILED && !qc->err_mask) {
0dd4b21f 1124 if (ata_msg_warn(ap))
88574551 1125 ata_dev_printk(dev, KERN_WARNING,
0dd4b21f 1126 "zero err_mask for failed "
88574551 1127 "internal command, assuming AC_ERR_OTHER\n");
d95a717f
TH		 1128 qc->err_mask |= AC_ERR_OTHER;
1129 }
1130
15869303 1131 /* finish up */
ba6a1308 1132 spin_lock_irqsave(ap->lock, flags);
15869303 1133
e61e0672 1134 *tf = qc->result_tf;
77853bf2
TH		 1135 err_mask = qc->err_mask;
1136
1137 ata_qc_free(qc);
2ab7db1f 1138 ap->active_tag = preempted_tag;
dedaf2b0
TH		 1139 ap->sactive = preempted_sactive;
1140 ap->qc_active = preempted_qc_active;
77853bf2 1141
1f7dd3e9
TH		 1142 /* XXX - Some LLDDs (sata_mv) disable port on command failure.
1143 * Until those drivers are fixed, we detect the condition
1144 * here, fail the command with AC_ERR_SYSTEM and reenable the
1145 * port.
1146 *
1147 * Note that this doesn't change any behavior as internal
1148 * command failure results in disabling the device in the
1149 * higher layer for LLDDs without new reset/EH callbacks.
1150 *
1151 * Kill the following code as soon as those drivers are fixed.
1152 */
198e0fed 1153 if (ap->flags & ATA_FLAG_DISABLED) {
1f7dd3e9
TH		 1154 err_mask |= AC_ERR_SYSTEM;
1155 ata_port_probe(ap);
1156 }
1157
ba6a1308 1158 spin_unlock_irqrestore(ap->lock, flags);
15869303 1159
77853bf2 1160 return err_mask;
a2a7a662
TH		 1161}
1162
977e6b9f
TH		 1163/**
1164 * ata_do_simple_cmd - execute simple internal command
1165 * @dev: Device to which the command is sent
1166 * @cmd: Opcode to execute
1167 *
1168 * Execute a 'simple' command, that only consists of the opcode
1169 * 'cmd' itself, without filling any other registers
1170 *
1171 * LOCKING:
1172 * Kernel thread context (may sleep).
1173 *
1174 * RETURNS:
1175 * Zero on success, AC_ERR_* mask on failure
e58eb583 1176 */
77b08fb5 1177unsigned int ata_do_simple_cmd(struct ata_device *dev, u8 cmd)
e58eb583
TH		 1178{
1179 struct ata_taskfile tf;
e58eb583
TH		 1180
1181 ata_tf_init(dev, &tf);
1182
1183 tf.command = cmd;
1184 tf.flags |= ATA_TFLAG_DEVICE;
1185 tf.protocol = ATA_PROT_NODATA;
1186
977e6b9f 1187 return ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
e58eb583
TH		 1188}
1189
1bc4ccff
AC		 1190/**
1191 * ata_pio_need_iordy - check if iordy needed
1192 * @adev: ATA device
1193 *
1194 * Check if the current speed of the device requires IORDY. Used
1195 * by various controllers for chip configuration.
1196 */
1197
1198unsigned int ata_pio_need_iordy(const struct ata_device *adev)
1199{
1200 int pio;
1201 int speed = adev->pio_mode - XFER_PIO_0;
1202
1203 if (speed < 2)
1204 return 0;
1205 if (speed > 2)
1206 return 1;
2e9edbf8 1207
1bc4ccff
AC		 1208 /* If we have no drive specific rule, then PIO 2 is non IORDY */
1209
1210 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
1211 pio = adev->id[ATA_ID_EIDE_PIO];
1212 /* Is the speed faster than the drive allows non IORDY ? */
1213 if (pio) {
1214 /* This is cycle times not frequency - watch the logic! */
1215 if (pio > 240) /* PIO2 is 240nS per cycle */
1216 return 1;
1217 return 0;
1218 }
1219 }
1220 return 0;
1221}
1222
1da177e4 1223/**
49016aca 1224 * ata_dev_read_id - Read ID data from the specified device
49016aca
TH		 1225 * @dev: target device
1226 * @p_class: pointer to class of the target device (may be changed)
bff04647 1227 * @flags: ATA_READID_* flags
fe635c7e 1228 * @id: buffer to read IDENTIFY data into
1da177e4 1229 *
49016aca
TH		 1230 * Read ID data from the specified device. ATA_CMD_ID_ATA is
1231 * performed on ATA devices and ATA_CMD_ID_ATAPI on ATAPI
aec5c3c1
TH		 1232 * devices. This function also issues ATA_CMD_INIT_DEV_PARAMS
1233 * for pre-ATA4 drives.
1da177e4
LT		 1234 *
1235 * LOCKING:
49016aca
TH		 1236 * Kernel thread context (may sleep)
1237 *
1238 * RETURNS:
1239 * 0 on success, -errno otherwise.
1da177e4 1240 */
a9beec95 1241int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class,
bff04647 1242 unsigned int flags, u16 *id)
1da177e4 1243{
3373efd8 1244 struct ata_port *ap = dev->ap;
49016aca 1245 unsigned int class = *p_class;
a0123703 1246 struct ata_taskfile tf;
49016aca
TH		 1247 unsigned int err_mask = 0;
1248 const char *reason;
1249 int rc;
1da177e4 1250
0dd4b21f 1251 if (ata_msg_ctl(ap))
88574551
TH		 1252 ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER, host %u, dev %u\n",
1253 __FUNCTION__, ap->id, dev->devno);
1da177e4 1254
49016aca 1255 ata_dev_select(ap, dev->devno, 1, 1); /* select device 0/1 */
1da177e4 1256
49016aca 1257 retry:
3373efd8 1258 ata_tf_init(dev, &tf);
a0123703 1259
49016aca
TH		 1260 switch (class) {
1261 case ATA_DEV_ATA:
a0123703 1262 tf.command = ATA_CMD_ID_ATA;
49016aca
TH		 1263 break;
1264 case ATA_DEV_ATAPI:
a0123703 1265 tf.command = ATA_CMD_ID_ATAPI;
49016aca
TH		 1266 break;
1267 default:
1268 rc = -ENODEV;
1269 reason = "unsupported class";
1270 goto err_out;
1da177e4
LT		 1271 }
1272
a0123703 1273 tf.protocol = ATA_PROT_PIO;
1da177e4 1274
3373efd8 1275 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_FROM_DEVICE,
49016aca 1276 id, sizeof(id[0]) * ATA_ID_WORDS);
a0123703 1277 if (err_mask) {
49016aca
TH		 1278 rc = -EIO;
1279 reason = "I/O error";
1da177e4
LT		 1280 goto err_out;
1281 }
1282
49016aca 1283 swap_buf_le16(id, ATA_ID_WORDS);
1da177e4 1284
49016aca 1285 /* sanity check */
a4f5749b
TH		 1286 rc = -EINVAL;
1287 reason = "device reports illegal type";
1288
1289 if (class == ATA_DEV_ATA) {
1290 if (!ata_id_is_ata(id) && !ata_id_is_cfa(id))
1291 goto err_out;
1292 } else {
1293 if (ata_id_is_ata(id))
1294 goto err_out;
49016aca
TH		 1295 }
1296
bff04647 1297 if ((flags & ATA_READID_POSTRESET) && class == ATA_DEV_ATA) {
49016aca
TH		 1298 /*
1299 * The exact sequence expected by certain pre-ATA4 drives is:
1300 * SRST RESET
1301 * IDENTIFY
1302 * INITIALIZE DEVICE PARAMETERS
1303 * anything else..
1304 * Some drives were very specific about that exact sequence.
1305 */
1306 if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
3373efd8 1307 err_mask = ata_dev_init_params(dev, id[3], id[6]);
49016aca
TH		 1308 if (err_mask) {
1309 rc = -EIO;
1310 reason = "INIT_DEV_PARAMS failed";
1311 goto err_out;
1312 }
1313
1314 /* current CHS translation info (id[53-58]) might be
1315 * changed. reread the identify device info.
1316 */
bff04647 1317 flags &= ~ATA_READID_POSTRESET;
49016aca
TH		 1318 goto retry;
1319 }
1320 }
1321
1322 *p_class = class;
fe635c7e 1323
49016aca
TH		 1324 return 0;
1325
1326 err_out:
88574551 1327 if (ata_msg_warn(ap))
0dd4b21f 1328 ata_dev_printk(dev, KERN_WARNING, "failed to IDENTIFY "
88574551 1329 "(%s, err_mask=0x%x)\n", reason, err_mask);
49016aca
TH		 1330 return rc;
1331}
1332
3373efd8 1333static inline u8 ata_dev_knobble(struct ata_device *dev)
4b2f3ede 1334{
3373efd8 1335 return ((dev->ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
4b2f3ede
TH		 1336}
1337
a6e6ce8e
TH		 1338static void ata_dev_config_ncq(struct ata_device *dev,
1339 char *desc, size_t desc_sz)
1340{
1341 struct ata_port *ap = dev->ap;
1342 int hdepth = 0, ddepth = ata_id_queue_depth(dev->id);
1343
1344 if (!ata_id_has_ncq(dev->id)) {
1345 desc[0] = '\0';
1346 return;
1347 }
6919a0a6
AC		 1348 if (ata_device_blacklisted(dev) & ATA_HORKAGE_NONCQ) {
1349 snprintf(desc, desc_sz, "NCQ (not used)");
1350 return;
1351 }
a6e6ce8e 1352 if (ap->flags & ATA_FLAG_NCQ) {
cca3974e 1353 hdepth = min(ap->scsi_host->can_queue, ATA_MAX_QUEUE - 1);
a6e6ce8e
TH		 1354 dev->flags |= ATA_DFLAG_NCQ;
1355 }
1356
1357 if (hdepth >= ddepth)
1358 snprintf(desc, desc_sz, "NCQ (depth %d)", ddepth);
1359 else
1360 snprintf(desc, desc_sz, "NCQ (depth %d/%d)", hdepth, ddepth);
1361}
1362
e6d902a3
BK		 1363static void ata_set_port_max_cmd_len(struct ata_port *ap)
1364{
1365 int i;
1366
cca3974e
JG		 1367 if (ap->scsi_host) {
1368 unsigned int len = 0;
1369
e6d902a3 1370 for (i = 0; i < ATA_MAX_DEVICES; i++)
cca3974e
JG		 1371 len = max(len, ap->device[i].cdb_len);
1372
1373 ap->scsi_host->max_cmd_len = len;
e6d902a3
BK		 1374 }
1375}
1376
49016aca 1377/**
ffeae418 1378 * ata_dev_configure - Configure the specified ATA/ATAPI device
ffeae418
TH		 1379 * @dev: Target device to configure
1380 *
1381 * Configure @dev according to @dev->id. Generic and low-level
1382 * driver specific fixups are also applied.
49016aca
TH		 1383 *
1384 * LOCKING:
ffeae418
TH		 1385 * Kernel thread context (may sleep)
1386 *
1387 * RETURNS:
1388 * 0 on success, -errno otherwise
49016aca 1389 */
efdaedc4 1390int ata_dev_configure(struct ata_device *dev)
49016aca 1391{
3373efd8 1392 struct ata_port *ap = dev->ap;
efdaedc4 1393 int print_info = ap->eh_context.i.flags & ATA_EHI_PRINTINFO;
1148c3a7 1394 const u16 *id = dev->id;
ff8854b2 1395 unsigned int xfer_mask;
b352e57d 1396 char revbuf[7]; /* XYZ-99\0 */
e6d902a3 1397 int rc;
49016aca 1398
0dd4b21f 1399 if (!ata_dev_enabled(dev) && ata_msg_info(ap)) {
88574551
TH		 1400 ata_dev_printk(dev, KERN_INFO,
1401 "%s: ENTER/EXIT (host %u, dev %u) -- nodev\n",
1402 __FUNCTION__, ap->id, dev->devno);
ffeae418 1403 return 0;
49016aca
TH		 1404 }
1405
0dd4b21f 1406 if (ata_msg_probe(ap))
88574551
TH		 1407 ata_dev_printk(dev, KERN_DEBUG, "%s: ENTER, host %u, dev %u\n",
1408 __FUNCTION__, ap->id, dev->devno);
1da177e4 1409
c39f5ebe 1410 /* print device capabilities */
0dd4b21f 1411 if (ata_msg_probe(ap))
88574551
TH		 1412 ata_dev_printk(dev, KERN_DEBUG,
1413 "%s: cfg 49:%04x 82:%04x 83:%04x 84:%04x "
1414 "85:%04x 86:%04x 87:%04x 88:%04x\n",
0dd4b21f 1415 __FUNCTION__,
f15a1daf
TH		 1416 id[49], id[82], id[83], id[84],
1417 id[85], id[86], id[87], id[88]);
c39f5ebe 1418
208a9933 1419 /* initialize to-be-configured parameters */
ea1dd4e1 1420 dev->flags &= ~ATA_DFLAG_CFG_MASK;
208a9933
TH		 1421 dev->max_sectors = 0;
1422 dev->cdb_len = 0;
1423 dev->n_sectors = 0;
1424 dev->cylinders = 0;
1425 dev->heads = 0;
1426 dev->sectors = 0;
1427
1da177e4
LT		 1428 /*
1429 * common ATA, ATAPI feature tests
1430 */
1431
ff8854b2 1432 /* find max transfer mode; for printk only */
1148c3a7 1433 xfer_mask = ata_id_xfermask(id);
1da177e4 1434
0dd4b21f
BP		 1435 if (ata_msg_probe(ap))
1436 ata_dump_id(id);
1da177e4
LT		 1437
1438 /* ATA-specific feature tests */
1439 if (dev->class == ATA_DEV_ATA) {
b352e57d
AC		 1440 if (ata_id_is_cfa(id)) {
1441 if (id[162] & 1) /* CPRM may make this media unusable */
1442 ata_dev_printk(dev, KERN_WARNING, "ata%u: device %u supports DRM functions and may not be fully accessable.\n",
1443 ap->id, dev->devno);
1444 snprintf(revbuf, 7, "CFA");
1445 }
1446 else
1447 snprintf(revbuf, 7, "ATA-%d", ata_id_major_version(id));
1448
1148c3a7 1449 dev->n_sectors = ata_id_n_sectors(id);
2940740b 1450
1148c3a7 1451 if (ata_id_has_lba(id)) {
4c2d721a 1452 const char *lba_desc;
a6e6ce8e 1453 char ncq_desc[20];
8bf62ece 1454
4c2d721a
TH		 1455 lba_desc = "LBA";
1456 dev->flags |= ATA_DFLAG_LBA;
1148c3a7 1457 if (ata_id_has_lba48(id)) {
8bf62ece 1458 dev->flags |= ATA_DFLAG_LBA48;
4c2d721a 1459 lba_desc = "LBA48";
6fc49adb
TH		 1460
1461 if (dev->n_sectors >= (1UL << 28) &&
1462 ata_id_has_flush_ext(id))
1463 dev->flags |= ATA_DFLAG_FLUSH_EXT;
4c2d721a 1464 }
8bf62ece 1465
a6e6ce8e
TH		 1466 /* config NCQ */
1467 ata_dev_config_ncq(dev, ncq_desc, sizeof(ncq_desc));
1468
8bf62ece 1469 /* print device info to dmesg */
5afc8142 1470 if (ata_msg_drv(ap) && print_info)
b352e57d 1471 ata_dev_printk(dev, KERN_INFO, "%s, "
a6e6ce8e 1472 "max %s, %Lu sectors: %s %s\n",
b352e57d 1473 revbuf,
f15a1daf
TH		 1474 ata_mode_string(xfer_mask),
1475 (unsigned long long)dev->n_sectors,
a6e6ce8e 1476 lba_desc, ncq_desc);
ffeae418 1477 } else {
8bf62ece
AL		 1478 /* CHS */
1479
1480 /* Default translation */
1148c3a7
TH		 1481 dev->cylinders = id[1];
1482 dev->heads = id[3];
1483 dev->sectors = id[6];
8bf62ece 1484
1148c3a7 1485 if (ata_id_current_chs_valid(id)) {
8bf62ece 1486 /* Current CHS translation is valid. */
1148c3a7
TH		 1487 dev->cylinders = id[54];
1488 dev->heads = id[55];
1489 dev->sectors = id[56];
8bf62ece
AL		 1490 }
1491
1492 /* print device info to dmesg */
5afc8142 1493 if (ata_msg_drv(ap) && print_info)
b352e57d 1494 ata_dev_printk(dev, KERN_INFO, "%s, "
f15a1daf 1495 "max %s, %Lu sectors: CHS %u/%u/%u\n",
b352e57d 1496 revbuf,
f15a1daf
TH		 1497 ata_mode_string(xfer_mask),
1498 (unsigned long long)dev->n_sectors,
88574551
TH		 1499 dev->cylinders, dev->heads,
1500 dev->sectors);
1da177e4
LT		 1501 }
1502
07f6f7d0
AL		 1503 if (dev->id[59] & 0x100) {
1504 dev->multi_count = dev->id[59] & 0xff;
5afc8142 1505 if (ata_msg_drv(ap) && print_info)
88574551
TH		 1506 ata_dev_printk(dev, KERN_INFO,
1507 "ata%u: dev %u multi count %u\n",
1508 ap->id, dev->devno, dev->multi_count);
07f6f7d0
AL		 1509 }
1510
6e7846e9 1511 dev->cdb_len = 16;
1da177e4
LT		 1512 }
1513
1514 /* ATAPI-specific feature tests */
2c13b7ce 1515 else if (dev->class == ATA_DEV_ATAPI) {
08a556db
AL		 1516 char *cdb_intr_string = "";
1517
1148c3a7 1518 rc = atapi_cdb_len(id);
1da177e4 1519 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
0dd4b21f 1520 if (ata_msg_warn(ap))
88574551
TH		 1521 ata_dev_printk(dev, KERN_WARNING,
1522 "unsupported CDB len\n");
ffeae418 1523 rc = -EINVAL;
1da177e4
LT		 1524 goto err_out_nosup;
1525 }
6e7846e9 1526 dev->cdb_len = (unsigned int) rc;
1da177e4 1527
08a556db 1528 if (ata_id_cdb_intr(dev->id)) {
312f7da2 1529 dev->flags |= ATA_DFLAG_CDB_INTR;
08a556db
AL		 1530 cdb_intr_string = ", CDB intr";
1531 }
312f7da2 1532
1da177e4 1533 /* print device info to dmesg */
5afc8142 1534 if (ata_msg_drv(ap) && print_info)
12436c30
TH		 1535 ata_dev_printk(dev, KERN_INFO, "ATAPI, max %s%s\n",
1536 ata_mode_string(xfer_mask),
1537 cdb_intr_string);
1da177e4
LT		 1538 }
1539
914ed354
TH		 1540 /* determine max_sectors */
1541 dev->max_sectors = ATA_MAX_SECTORS;
1542 if (dev->flags & ATA_DFLAG_LBA48)
1543 dev->max_sectors = ATA_MAX_SECTORS_LBA48;
1544
93590859
AC		 1545 if (dev->horkage & ATA_HORKAGE_DIAGNOSTIC) {
1546 /* Let the user know. We don't want to disallow opens for
1547 rescue purposes, or in case the vendor is just a blithering
1548 idiot */
1549 if (print_info) {
1550 ata_dev_printk(dev, KERN_WARNING,
1551"Drive reports diagnostics failure. This may indicate a drive\n");
1552 ata_dev_printk(dev, KERN_WARNING,
1553"fault or invalid emulation. Contact drive vendor for information.\n");
1554 }
1555 }
1556
e6d902a3 1557 ata_set_port_max_cmd_len(ap);
6e7846e9 1558
4b2f3ede 1559 /* limit bridge transfers to udma5, 200 sectors */
3373efd8 1560 if (ata_dev_knobble(dev)) {
5afc8142 1561 if (ata_msg_drv(ap) && print_info)
f15a1daf
TH		 1562 ata_dev_printk(dev, KERN_INFO,
1563 "applying bridge limits\n");
5a529139 1564 dev->udma_mask &= ATA_UDMA5;
4b2f3ede
TH		 1565 dev->max_sectors = ATA_MAX_SECTORS;
1566 }
1567
1568 if (ap->ops->dev_config)
1569 ap->ops->dev_config(ap, dev);
1570
0dd4b21f
BP		 1571 if (ata_msg_probe(ap))
1572 ata_dev_printk(dev, KERN_DEBUG, "%s: EXIT, drv_stat = 0x%x\n",
1573 __FUNCTION__, ata_chk_status(ap));
ffeae418 1574 return 0;
1da177e4
LT		 1575
1576err_out_nosup:
0dd4b21f 1577 if (ata_msg_probe(ap))
88574551
TH		 1578 ata_dev_printk(dev, KERN_DEBUG,
1579 "%s: EXIT, err\n", __FUNCTION__);
ffeae418 1580 return rc;
1da177e4
LT		 1581}
1582
1583/**
1584 * ata_bus_probe - Reset and probe ATA bus
1585 * @ap: Bus to probe
1586 *
0cba632b
JG		 1587 * Master ATA bus probing function. Initiates a hardware-dependent
1588 * bus reset, then attempts to identify any devices found on
1589 * the bus.
1590 *
1da177e4 1591 * LOCKING:
0cba632b 1592 * PCI/etc. bus probe sem.
1da177e4
LT		 1593 *
1594 * RETURNS:
96072e69 1595 * Zero on success, negative errno otherwise.
1da177e4
LT		 1596 */
1597
80289167 1598int ata_bus_probe(struct ata_port *ap)
1da177e4 1599{
28ca5c57 1600 unsigned int classes[ATA_MAX_DEVICES];
14d2bac1
TH		 1601 int tries[ATA_MAX_DEVICES];
1602 int i, rc, down_xfermask;
e82cbdb9 1603 struct ata_device *dev;
1da177e4 1604
28ca5c57 1605 ata_port_probe(ap);
c19ba8af 1606
14d2bac1
TH		 1607 for (i = 0; i < ATA_MAX_DEVICES; i++)
1608 tries[i] = ATA_PROBE_MAX_TRIES;
1609
1610 retry:
1611 down_xfermask = 0;
1612
2044470c 1613 /* reset and determine device classes */
52783c5d 1614 ap->ops->phy_reset(ap);
2061a47a 1615
52783c5d
TH		 1616 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1617 dev = &ap->device[i];
c19ba8af 1618
52783c5d
TH		 1619 if (!(ap->flags & ATA_FLAG_DISABLED) &&
1620 dev->class != ATA_DEV_UNKNOWN)
1621 classes[dev->devno] = dev->class;
1622 else
1623 classes[dev->devno] = ATA_DEV_NONE;
2044470c 1624
52783c5d 1625 dev->class = ATA_DEV_UNKNOWN;
28ca5c57 1626 }
1da177e4 1627
52783c5d 1628 ata_port_probe(ap);
2044470c 1629
b6079ca4
AC		 1630 /* after the reset the device state is PIO 0 and the controller
1631 state is undefined. Record the mode */
1632
1633 for (i = 0; i < ATA_MAX_DEVICES; i++)
1634 ap->device[i].pio_mode = XFER_PIO_0;
1635
28ca5c57 1636 /* read IDENTIFY page and configure devices */
1da177e4 1637 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e82cbdb9 1638 dev = &ap->device[i];
28ca5c57 1639
ec573755
TH		 1640 if (tries[i])
1641 dev->class = classes[i];
ffeae418 1642
14d2bac1 1643 if (!ata_dev_enabled(dev))
ffeae418 1644 continue;
ffeae418 1645
bff04647
TH		 1646 rc = ata_dev_read_id(dev, &dev->class, ATA_READID_POSTRESET,
1647 dev->id);
14d2bac1
TH		 1648 if (rc)
1649 goto fail;
1650
efdaedc4
TH		 1651 ap->eh_context.i.flags |= ATA_EHI_PRINTINFO;
1652 rc = ata_dev_configure(dev);
1653 ap->eh_context.i.flags &= ~ATA_EHI_PRINTINFO;
14d2bac1
TH		 1654 if (rc)
1655 goto fail;
1da177e4
LT		 1656 }
1657
e82cbdb9 1658 /* configure transfer mode */
3adcebb2 1659 rc = ata_set_mode(ap, &dev);
51713d35
TH		 1660 if (rc) {
1661 down_xfermask = 1;
1662 goto fail;
e82cbdb9 1663 }
1da177e4 1664
e82cbdb9
TH		 1665 for (i = 0; i < ATA_MAX_DEVICES; i++)
1666 if (ata_dev_enabled(&ap->device[i]))
1667 return 0;
1da177e4 1668
e82cbdb9
TH		 1669 /* no device present, disable port */
1670 ata_port_disable(ap);
1da177e4 1671 ap->ops->port_disable(ap);
96072e69 1672 return -ENODEV;
14d2bac1
TH		 1673
1674 fail:
1675 switch (rc) {
1676 case -EINVAL:
1677 case -ENODEV:
1678 tries[dev->devno] = 0;
1679 break;
1680 case -EIO:
3c567b7d 1681 sata_down_spd_limit(ap);
14d2bac1
TH		 1682 /* fall through */
1683 default:
1684 tries[dev->devno]--;
1685 if (down_xfermask &&
3373efd8 1686 ata_down_xfermask_limit(dev, tries[dev->devno] == 1))
14d2bac1
TH		 1687 tries[dev->devno] = 0;
1688 }
1689
ec573755 1690 if (!tries[dev->devno]) {
3373efd8
TH		 1691 ata_down_xfermask_limit(dev, 1);
1692 ata_dev_disable(dev);
ec573755
TH		 1693 }
1694
14d2bac1 1695 goto retry;
1da177e4
LT		 1696}
1697
1698/**
0cba632b
JG		 1699 * ata_port_probe - Mark port as enabled
1700 * @ap: Port for which we indicate enablement
1da177e4 1701 *
0cba632b
JG		 1702 * Modify @ap data structure such that the system
1703 * thinks that the entire port is enabled.
1704 *
cca3974e 1705 * LOCKING: host lock, or some other form of
0cba632b 1706 * serialization.
1da177e4
LT		 1707 */
1708
1709void ata_port_probe(struct ata_port *ap)
1710{
198e0fed 1711 ap->flags &= ~ATA_FLAG_DISABLED;
1da177e4
LT		 1712}
1713
3be680b7
TH		 1714/**
1715 * sata_print_link_status - Print SATA link status
1716 * @ap: SATA port to printk link status about
1717 *
1718 * This function prints link speed and status of a SATA link.
1719 *
1720 * LOCKING:
1721 * None.
1722 */
1723static void sata_print_link_status(struct ata_port *ap)
1724{
6d5f9732 1725 u32 sstatus, scontrol, tmp;
3be680b7 1726
81952c54 1727 if (sata_scr_read(ap, SCR_STATUS, &sstatus))
3be680b7 1728 return;
81952c54 1729 sata_scr_read(ap, SCR_CONTROL, &scontrol);
3be680b7 1730
81952c54 1731 if (ata_port_online(ap)) {
3be680b7 1732 tmp = (sstatus >> 4) & 0xf;
f15a1daf
TH		 1733 ata_port_printk(ap, KERN_INFO,
1734 "SATA link up %s (SStatus %X SControl %X)\n",
1735 sata_spd_string(tmp), sstatus, scontrol);
3be680b7 1736 } else {
f15a1daf
TH		 1737 ata_port_printk(ap, KERN_INFO,
1738 "SATA link down (SStatus %X SControl %X)\n",
1739 sstatus, scontrol);
3be680b7
TH		 1740 }
1741}
1742
1da177e4 1743/**
780a87f7
JG		 1744 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1745 * @ap: SATA port associated with target SATA PHY.
1da177e4 1746 *
780a87f7
JG		 1747 * This function issues commands to standard SATA Sxxx
1748 * PHY registers, to wake up the phy (and device), and
1749 * clear any reset condition.
1da177e4
LT		 1750 *
1751 * LOCKING:
0cba632b 1752 * PCI/etc. bus probe sem.
1da177e4
LT		 1753 *
1754 */
1755void __sata_phy_reset(struct ata_port *ap)
1756{
1757 u32 sstatus;
1758 unsigned long timeout = jiffies + (HZ * 5);
1759
1760 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e 1761 /* issue phy wake/reset */
81952c54 1762 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1763 /* Couldn't find anything in SATA I/II specs, but
1764 * AHCI-1.1 10.4.2 says at least 1 ms. */
1765 mdelay(1);
1da177e4 1766 }
81952c54
TH		 1767 /* phy wake/clear reset */
1768 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1da177e4
LT		 1769
1770 /* wait for phy to become ready, if necessary */
1771 do {
1772 msleep(200);
81952c54 1773 sata_scr_read(ap, SCR_STATUS, &sstatus);
1da177e4
LT		 1774 if ((sstatus & 0xf) != 1)
1775 break;
1776 } while (time_before(jiffies, timeout));
1777
3be680b7
TH		 1778 /* print link status */
1779 sata_print_link_status(ap);
656563e3 1780
3be680b7 1781 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 1782 if (!ata_port_offline(ap))
1da177e4 1783 ata_port_probe(ap);
3be680b7 1784 else
1da177e4 1785 ata_port_disable(ap);
1da177e4 1786
198e0fed 1787 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1788 return;
1789
1790 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1791 ata_port_disable(ap);
1792 return;
1793 }
1794
1795 ap->cbl = ATA_CBL_SATA;
1796}
1797
1798/**
780a87f7
JG		 1799 * sata_phy_reset - Reset SATA bus.
1800 * @ap: SATA port associated with target SATA PHY.
1da177e4 1801 *
780a87f7
JG		 1802 * This function resets the SATA bus, and then probes
1803 * the bus for devices.
1da177e4
LT		 1804 *
1805 * LOCKING:
0cba632b 1806 * PCI/etc. bus probe sem.
1da177e4
LT		 1807 *
1808 */
1809void sata_phy_reset(struct ata_port *ap)
1810{
1811 __sata_phy_reset(ap);
198e0fed 1812 if (ap->flags & ATA_FLAG_DISABLED)
1da177e4
LT		 1813 return;
1814 ata_bus_reset(ap);
1815}
1816
ebdfca6e
AC		 1817/**
1818 * ata_dev_pair - return other device on cable
ebdfca6e
AC		 1819 * @adev: device
1820 *
1821 * Obtain the other device on the same cable, or if none is
1822 * present NULL is returned
1823 */
2e9edbf8 1824
3373efd8 1825struct ata_device *ata_dev_pair(struct ata_device *adev)
ebdfca6e 1826{
3373efd8 1827 struct ata_port *ap = adev->ap;
ebdfca6e 1828 struct ata_device *pair = &ap->device[1 - adev->devno];
e1211e3f 1829 if (!ata_dev_enabled(pair))
ebdfca6e
AC		 1830 return NULL;
1831 return pair;
1832}
1833
1da177e4 1834/**
780a87f7
JG		 1835 * ata_port_disable - Disable port.
1836 * @ap: Port to be disabled.
1da177e4 1837 *
780a87f7
JG		 1838 * Modify @ap data structure such that the system
1839 * thinks that the entire port is disabled, and should
1840 * never attempt to probe or communicate with devices
1841 * on this port.
1842 *
cca3974e 1843 * LOCKING: host lock, or some other form of
780a87f7 1844 * serialization.
1da177e4
LT		 1845 */
1846
1847void ata_port_disable(struct ata_port *ap)
1848{
1849 ap->device[0].class = ATA_DEV_NONE;
1850 ap->device[1].class = ATA_DEV_NONE;
198e0fed 1851 ap->flags |= ATA_FLAG_DISABLED;
1da177e4
LT		 1852}
1853
1c3fae4d 1854/**
3c567b7d 1855 * sata_down_spd_limit - adjust SATA spd limit downward
1c3fae4d
TH		 1856 * @ap: Port to adjust SATA spd limit for
1857 *
1858 * Adjust SATA spd limit of @ap downward. Note that this
1859 * function only adjusts the limit. The change must be applied
3c567b7d 1860 * using sata_set_spd().
1c3fae4d
TH		 1861 *
1862 * LOCKING:
1863 * Inherited from caller.
1864 *
1865 * RETURNS:
1866 * 0 on success, negative errno on failure
1867 */
3c567b7d 1868int sata_down_spd_limit(struct ata_port *ap)
1c3fae4d 1869{
81952c54
TH		 1870 u32 sstatus, spd, mask;
1871 int rc, highbit;
1c3fae4d 1872
81952c54
TH		 1873 rc = sata_scr_read(ap, SCR_STATUS, &sstatus);
1874 if (rc)
1875 return rc;
1c3fae4d
TH		 1876
1877 mask = ap->sata_spd_limit;
1878 if (mask <= 1)
1879 return -EINVAL;
1880 highbit = fls(mask) - 1;
1881 mask &= ~(1 << highbit);
1882
81952c54 1883 spd = (sstatus >> 4) & 0xf;
1c3fae4d
TH		 1884 if (spd <= 1)
1885 return -EINVAL;
1886 spd--;
1887 mask &= (1 << spd) - 1;
1888 if (!mask)
1889 return -EINVAL;
1890
1891 ap->sata_spd_limit = mask;
1892
f15a1daf
TH		 1893 ata_port_printk(ap, KERN_WARNING, "limiting SATA link speed to %s\n",
1894 sata_spd_string(fls(mask)));
1c3fae4d
TH		 1895
1896 return 0;
1897}
1898
3c567b7d 1899static int __sata_set_spd_needed(struct ata_port *ap, u32 *scontrol)
1c3fae4d
TH		 1900{
1901 u32 spd, limit;
1902
1903 if (ap->sata_spd_limit == UINT_MAX)
1904 limit = 0;
1905 else
1906 limit = fls(ap->sata_spd_limit);
1907
1908 spd = (*scontrol >> 4) & 0xf;
1909 *scontrol = (*scontrol & ~0xf0) | ((limit & 0xf) << 4);
1910
1911 return spd != limit;
1912}
1913
1914/**
3c567b7d 1915 * sata_set_spd_needed - is SATA spd configuration needed
1c3fae4d
TH		 1916 * @ap: Port in question
1917 *
1918 * Test whether the spd limit in SControl matches
1919 * @ap->sata_spd_limit. This function is used to determine
1920 * whether hardreset is necessary to apply SATA spd
1921 * configuration.
1922 *
1923 * LOCKING:
1924 * Inherited from caller.
1925 *
1926 * RETURNS:
1927 * 1 if SATA spd configuration is needed, 0 otherwise.
1928 */
3c567b7d 1929int sata_set_spd_needed(struct ata_port *ap)
1c3fae4d
TH		 1930{
1931 u32 scontrol;
1932
81952c54 1933 if (sata_scr_read(ap, SCR_CONTROL, &scontrol))
1c3fae4d
TH		 1934 return 0;
1935
3c567b7d 1936 return __sata_set_spd_needed(ap, &scontrol);
1c3fae4d
TH		 1937}
1938
1939/**
3c567b7d 1940 * sata_set_spd - set SATA spd according to spd limit
1c3fae4d
TH		 1941 * @ap: Port to set SATA spd for
1942 *
1943 * Set SATA spd of @ap according to sata_spd_limit.
1944 *
1945 * LOCKING:
1946 * Inherited from caller.
1947 *
1948 * RETURNS:
1949 * 0 if spd doesn't need to be changed, 1 if spd has been
81952c54 1950 * changed. Negative errno if SCR registers are inaccessible.
1c3fae4d 1951 */
3c567b7d 1952int sata_set_spd(struct ata_port *ap)
1c3fae4d
TH		 1953{
1954 u32 scontrol;
81952c54 1955 int rc;
1c3fae4d 1956
81952c54
TH		 1957 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
1958 return rc;
1c3fae4d 1959
3c567b7d 1960 if (!__sata_set_spd_needed(ap, &scontrol))
1c3fae4d
TH		 1961 return 0;
1962
81952c54
TH		 1963 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
1964 return rc;
1965
1c3fae4d
TH		 1966 return 1;
1967}
1968
452503f9
AC		 1969/*
1970 * This mode timing computation functionality is ported over from
1971 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1972 */
1973/*
b352e57d 1974 * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
452503f9 1975 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
b352e57d
AC		 1976 * for UDMA6, which is currently supported only by Maxtor drives.
1977 *
1978 * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
452503f9
AC		 1979 */
1980
1981static const struct ata_timing ata_timing[] = {
1982
1983 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1984 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1985 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1986 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1987
b352e57d
AC		 1988 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 },
1989 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 },
452503f9
AC		 1990 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1991 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1992 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1993
1994/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
2e9edbf8 1995
452503f9
AC		 1996 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1997 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1998 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
2e9edbf8 1999
452503f9
AC		 2000 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
2001 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
2002 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
2003
b352e57d
AC		 2004 { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 },
2005 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 },
452503f9
AC		 2006 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
2007 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
2008
2009 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
2010 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
2011 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
2012
2013/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
2014
2015 { 0xFF }
2016};
2017
2018#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
2019#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
2020
2021static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
2022{
2023 q->setup = EZ(t->setup * 1000, T);
2024 q->act8b = EZ(t->act8b * 1000, T);
2025 q->rec8b = EZ(t->rec8b * 1000, T);
2026 q->cyc8b = EZ(t->cyc8b * 1000, T);
2027 q->active = EZ(t->active * 1000, T);
2028 q->recover = EZ(t->recover * 1000, T);
2029 q->cycle = EZ(t->cycle * 1000, T);
2030 q->udma = EZ(t->udma * 1000, UT);
2031}
2032
2033void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
2034 struct ata_timing *m, unsigned int what)
2035{
2036 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
2037 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
2038 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
2039 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
2040 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
2041 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
2042 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
2043 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
2044}
2045
2046static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
2047{
2048 const struct ata_timing *t;
2049
2050 for (t = ata_timing; t->mode != speed; t++)
91190758 2051 if (t->mode == 0xFF)
452503f9 2052 return NULL;
2e9edbf8 2053 return t;
452503f9
AC		 2054}
2055
2056int ata_timing_compute(struct ata_device *adev, unsigned short speed,
2057 struct ata_timing *t, int T, int UT)
2058{
2059 const struct ata_timing *s;
2060 struct ata_timing p;
2061
2062 /*
2e9edbf8 2063 * Find the mode.
75b1f2f8 2064 */
452503f9
AC		 2065
2066 if (!(s = ata_timing_find_mode(speed)))
2067 return -EINVAL;
2068
75b1f2f8
AL		 2069 memcpy(t, s, sizeof(*s));
2070
452503f9
AC		 2071 /*
2072 * If the drive is an EIDE drive, it can tell us it needs extended
2073 * PIO/MW_DMA cycle timing.
2074 */
2075
2076 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
2077 memset(&p, 0, sizeof(p));
2078 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
2079 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
2080 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
2081 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
2082 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
2083 }
2084 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
2085 }
2086
2087 /*
2088 * Convert the timing to bus clock counts.
2089 */
2090
75b1f2f8 2091 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 2092
2093 /*
c893a3ae
RD		 2094 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
2095 * S.M.A.R.T * and some other commands. We have to ensure that the
2096 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 2097 */
2098
2099 if (speed > XFER_PIO_4) {
2100 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
2101 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
2102 }
2103
2104 /*
c893a3ae 2105 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 2106 */
2107
2108 if (t->act8b + t->rec8b < t->cyc8b) {
2109 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
2110 t->rec8b = t->cyc8b - t->act8b;
2111 }
2112
2113 if (t->active + t->recover < t->cycle) {
2114 t->active += (t->cycle - (t->active + t->recover)) / 2;
2115 t->recover = t->cycle - t->active;
2116 }
2117
2118 return 0;
2119}
2120
cf176e1a
TH		 2121/**
2122 * ata_down_xfermask_limit - adjust dev xfer masks downward
cf176e1a
TH		 2123 * @dev: Device to adjust xfer masks
2124 * @force_pio0: Force PIO0
2125 *
2126 * Adjust xfer masks of @dev downward. Note that this function
2127 * does not apply the change. Invoking ata_set_mode() afterwards
2128 * will apply the limit.
2129 *
2130 * LOCKING:
2131 * Inherited from caller.
2132 *
2133 * RETURNS:
2134 * 0 on success, negative errno on failure
2135 */
3373efd8 2136int ata_down_xfermask_limit(struct ata_device *dev, int force_pio0)
cf176e1a
TH		 2137{
2138 unsigned long xfer_mask;
2139 int highbit;
2140
2141 xfer_mask = ata_pack_xfermask(dev->pio_mask, dev->mwdma_mask,
2142 dev->udma_mask);
2143
2144 if (!xfer_mask)
2145 goto fail;
2146 /* don't gear down to MWDMA from UDMA, go directly to PIO */
2147 if (xfer_mask & ATA_MASK_UDMA)
2148 xfer_mask &= ~ATA_MASK_MWDMA;
2149
2150 highbit = fls(xfer_mask) - 1;
2151 xfer_mask &= ~(1 << highbit);
2152 if (force_pio0)
2153 xfer_mask &= 1 << ATA_SHIFT_PIO;
2154 if (!xfer_mask)
2155 goto fail;
2156
2157 ata_unpack_xfermask(xfer_mask, &dev->pio_mask, &dev->mwdma_mask,
2158 &dev->udma_mask);
2159
f15a1daf
TH		 2160 ata_dev_printk(dev, KERN_WARNING, "limiting speed to %s\n",
2161 ata_mode_string(xfer_mask));
cf176e1a
TH		 2162
2163 return 0;
2164
2165 fail:
2166 return -EINVAL;
2167}
2168
3373efd8 2169static int ata_dev_set_mode(struct ata_device *dev)
1da177e4 2170{
baa1e78a 2171 struct ata_eh_context *ehc = &dev->ap->eh_context;
83206a29
TH		 2172 unsigned int err_mask;
2173 int rc;
1da177e4 2174
e8384607 2175 dev->flags &= ~ATA_DFLAG_PIO;
1da177e4
LT		 2176 if (dev->xfer_shift == ATA_SHIFT_PIO)
2177 dev->flags |= ATA_DFLAG_PIO;
2178
3373efd8 2179 err_mask = ata_dev_set_xfermode(dev);
83206a29 2180 if (err_mask) {
f15a1daf
TH		 2181 ata_dev_printk(dev, KERN_ERR, "failed to set xfermode "
2182 "(err_mask=0x%x)\n", err_mask);
83206a29
TH		 2183 return -EIO;
2184 }
1da177e4 2185
baa1e78a 2186 ehc->i.flags |= ATA_EHI_POST_SETMODE;
3373efd8 2187 rc = ata_dev_revalidate(dev, 0);
baa1e78a 2188 ehc->i.flags &= ~ATA_EHI_POST_SETMODE;
5eb45c02 2189 if (rc)
83206a29 2190 return rc;
48a8a14f 2191
23e71c3d
TH		 2192 DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
2193 dev->xfer_shift, (int)dev->xfer_mode);
1da177e4 2194
f15a1daf
TH		 2195 ata_dev_printk(dev, KERN_INFO, "configured for %s\n",
2196 ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)));
83206a29 2197 return 0;
1da177e4
LT		 2198}
2199
1da177e4
LT		 2200/**
2201 * ata_set_mode - Program timings and issue SET FEATURES - XFER
2202 * @ap: port on which timings will be programmed
e82cbdb9 2203 * @r_failed_dev: out paramter for failed device
1da177e4 2204 *
e82cbdb9
TH		 2205 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.). If
2206 * ata_set_mode() fails, pointer to the failing device is
2207 * returned in @r_failed_dev.
780a87f7 2208 *
1da177e4 2209 * LOCKING:
0cba632b 2210 * PCI/etc. bus probe sem.
e82cbdb9
TH		 2211 *
2212 * RETURNS:
2213 * 0 on success, negative errno otherwise
1da177e4 2214 */
1ad8e7f9 2215int ata_set_mode(struct ata_port *ap, struct ata_device **r_failed_dev)
1da177e4 2216{
e8e0619f 2217 struct ata_device *dev;
e82cbdb9 2218 int i, rc = 0, used_dma = 0, found = 0;
1da177e4 2219
3adcebb2
TH		 2220 /* has private set_mode? */
2221 if (ap->ops->set_mode) {
2222 /* FIXME: make ->set_mode handle no device case and
2223 * return error code and failing device on failure.
2224 */
2225 for (i = 0; i < ATA_MAX_DEVICES; i++) {
02670bf3 2226 if (ata_dev_ready(&ap->device[i])) {
3adcebb2
TH		 2227 ap->ops->set_mode(ap);
2228 break;
2229 }
2230 }
2231 return 0;
2232 }
2233
a6d5a51c
TH		 2234 /* step 1: calculate xfer_mask */
2235 for (i = 0; i < ATA_MAX_DEVICES; i++) {
acf356b1 2236 unsigned int pio_mask, dma_mask;
a6d5a51c 2237
e8e0619f
TH		 2238 dev = &ap->device[i];
2239
e1211e3f 2240 if (!ata_dev_enabled(dev))
a6d5a51c
TH		 2241 continue;
2242
3373efd8 2243 ata_dev_xfermask(dev);
1da177e4 2244
acf356b1
TH		 2245 pio_mask = ata_pack_xfermask(dev->pio_mask, 0, 0);
2246 dma_mask = ata_pack_xfermask(0, dev->mwdma_mask, dev->udma_mask);
2247 dev->pio_mode = ata_xfer_mask2mode(pio_mask);
2248 dev->dma_mode = ata_xfer_mask2mode(dma_mask);
5444a6f4 2249
4f65977d 2250 found = 1;
5444a6f4
AC		 2251 if (dev->dma_mode)
2252 used_dma = 1;
a6d5a51c 2253 }
4f65977d 2254 if (!found)
e82cbdb9 2255 goto out;
a6d5a51c
TH		 2256
2257 /* step 2: always set host PIO timings */
e8e0619f
TH		 2258 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2259 dev = &ap->device[i];
2260 if (!ata_dev_enabled(dev))
2261 continue;
2262
2263 if (!dev->pio_mode) {
f15a1daf 2264 ata_dev_printk(dev, KERN_WARNING, "no PIO support\n");
e8e0619f 2265 rc = -EINVAL;
e82cbdb9 2266 goto out;
e8e0619f
TH		 2267 }
2268
2269 dev->xfer_mode = dev->pio_mode;
2270 dev->xfer_shift = ATA_SHIFT_PIO;
2271 if (ap->ops->set_piomode)
2272 ap->ops->set_piomode(ap, dev);
2273 }
1da177e4 2274
a6d5a51c 2275 /* step 3: set host DMA timings */
e8e0619f
TH		 2276 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2277 dev = &ap->device[i];
2278
2279 if (!ata_dev_enabled(dev) || !dev->dma_mode)
2280 continue;
2281
2282 dev->xfer_mode = dev->dma_mode;
2283 dev->xfer_shift = ata_xfer_mode2shift(dev->dma_mode);
2284 if (ap->ops->set_dmamode)
2285 ap->ops->set_dmamode(ap, dev);
2286 }
1da177e4
LT		 2287
2288 /* step 4: update devices' xfer mode */
83206a29 2289 for (i = 0; i < ATA_MAX_DEVICES; i++) {
e8e0619f 2290 dev = &ap->device[i];
1da177e4 2291
02670bf3
TH		 2292 /* don't udpate suspended devices' xfer mode */
2293 if (!ata_dev_ready(dev))
83206a29
TH		 2294 continue;
2295
3373efd8 2296 rc = ata_dev_set_mode(dev);
5bbc53f4 2297 if (rc)
e82cbdb9 2298 goto out;
83206a29 2299 }
1da177e4 2300
e8e0619f
TH		 2301 /* Record simplex status. If we selected DMA then the other
2302 * host channels are not permitted to do so.
5444a6f4 2303 */
cca3974e
JG		 2304 if (used_dma && (ap->host->flags & ATA_HOST_SIMPLEX))
2305 ap->host->simplex_claimed = 1;
5444a6f4 2306
e8e0619f 2307 /* step5: chip specific finalisation */
1da177e4
LT		 2308 if (ap->ops->post_set_mode)
2309 ap->ops->post_set_mode(ap);
2310
e82cbdb9
TH		 2311 out:
2312 if (rc)
2313 *r_failed_dev = dev;
2314 return rc;
1da177e4
LT		 2315}
2316
1fdffbce
JG		 2317/**
2318 * ata_tf_to_host - issue ATA taskfile to host controller
2319 * @ap: port to which command is being issued
2320 * @tf: ATA taskfile register set
2321 *
2322 * Issues ATA taskfile register set to ATA host controller,
2323 * with proper synchronization with interrupt handler and
2324 * other threads.
2325 *
2326 * LOCKING:
cca3974e 2327 * spin_lock_irqsave(host lock)
1fdffbce
JG		 2328 */
2329
2330static inline void ata_tf_to_host(struct ata_port *ap,
2331 const struct ata_taskfile *tf)
2332{
2333 ap->ops->tf_load(ap, tf);
2334 ap->ops->exec_command(ap, tf);
2335}
2336
1da177e4
LT		 2337/**
2338 * ata_busy_sleep - sleep until BSY clears, or timeout
2339 * @ap: port containing status register to be polled
2340 * @tmout_pat: impatience timeout
2341 * @tmout: overall timeout
2342 *
780a87f7
JG		 2343 * Sleep until ATA Status register bit BSY clears,
2344 * or a timeout occurs.
2345 *
d1adc1bb
TH		 2346 * LOCKING:
2347 * Kernel thread context (may sleep).
2348 *
2349 * RETURNS:
2350 * 0 on success, -errno otherwise.
1da177e4 2351 */
d1adc1bb
TH		 2352int ata_busy_sleep(struct ata_port *ap,
2353 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 2354{
2355 unsigned long timer_start, timeout;
2356 u8 status;
2357
2358 status = ata_busy_wait(ap, ATA_BUSY, 300);
2359 timer_start = jiffies;
2360 timeout = timer_start + tmout_pat;
d1adc1bb
TH		 2361 while (status != 0xff && (status & ATA_BUSY) &&
2362 time_before(jiffies, timeout)) {
1da177e4
LT		 2363 msleep(50);
2364 status = ata_busy_wait(ap, ATA_BUSY, 3);
2365 }
2366
d1adc1bb 2367 if (status != 0xff && (status & ATA_BUSY))
f15a1daf 2368 ata_port_printk(ap, KERN_WARNING,
35aa7a43
JG		 2369 "port is slow to respond, please be patient "
2370 "(Status 0x%x)\n", status);
1da177e4
LT		 2371
2372 timeout = timer_start + tmout;
d1adc1bb
TH		 2373 while (status != 0xff && (status & ATA_BUSY) &&
2374 time_before(jiffies, timeout)) {
1da177e4
LT		 2375 msleep(50);
2376 status = ata_chk_status(ap);
2377 }
2378
d1adc1bb
TH		 2379 if (status == 0xff)
2380 return -ENODEV;
2381
1da177e4 2382 if (status & ATA_BUSY) {
f15a1daf 2383 ata_port_printk(ap, KERN_ERR, "port failed to respond "
35aa7a43
JG		 2384 "(%lu secs, Status 0x%x)\n",
2385 tmout / HZ, status);
d1adc1bb 2386 return -EBUSY;
1da177e4
LT		 2387 }
2388
2389 return 0;
2390}
2391
2392static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
2393{
2394 struct ata_ioports *ioaddr = &ap->ioaddr;
2395 unsigned int dev0 = devmask & (1 << 0);
2396 unsigned int dev1 = devmask & (1 << 1);
2397 unsigned long timeout;
2398
2399 /* if device 0 was found in ata_devchk, wait for its
2400 * BSY bit to clear
2401 */
2402 if (dev0)
2403 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2404
2405 /* if device 1 was found in ata_devchk, wait for
2406 * register access, then wait for BSY to clear
2407 */
2408 timeout = jiffies + ATA_TMOUT_BOOT;
2409 while (dev1) {
2410 u8 nsect, lbal;
2411
2412 ap->ops->dev_select(ap, 1);
2413 if (ap->flags & ATA_FLAG_MMIO) {
2414 nsect = readb((void __iomem *) ioaddr->nsect_addr);
2415 lbal = readb((void __iomem *) ioaddr->lbal_addr);
2416 } else {
2417 nsect = inb(ioaddr->nsect_addr);
2418 lbal = inb(ioaddr->lbal_addr);
2419 }
2420 if ((nsect == 1) && (lbal == 1))
2421 break;
2422 if (time_after(jiffies, timeout)) {
2423 dev1 = 0;
2424 break;
2425 }
2426 msleep(50); /* give drive a breather */
2427 }
2428 if (dev1)
2429 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2430
2431 /* is all this really necessary? */
2432 ap->ops->dev_select(ap, 0);
2433 if (dev1)
2434 ap->ops->dev_select(ap, 1);
2435 if (dev0)
2436 ap->ops->dev_select(ap, 0);
2437}
2438
1da177e4
LT		 2439static unsigned int ata_bus_softreset(struct ata_port *ap,
2440 unsigned int devmask)
2441{
2442 struct ata_ioports *ioaddr = &ap->ioaddr;
2443
2444 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
2445
2446 /* software reset. causes dev0 to be selected */
2447 if (ap->flags & ATA_FLAG_MMIO) {
2448 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2449 udelay(20); /* FIXME: flush */
2450 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
2451 udelay(20); /* FIXME: flush */
2452 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2453 } else {
2454 outb(ap->ctl, ioaddr->ctl_addr);
2455 udelay(10);
2456 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2457 udelay(10);
2458 outb(ap->ctl, ioaddr->ctl_addr);
2459 }
2460
2461 /* spec mandates ">= 2ms" before checking status.
2462 * We wait 150ms, because that was the magic delay used for
2463 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
2464 * between when the ATA command register is written, and then
2465 * status is checked. Because waiting for "a while" before
2466 * checking status is fine, post SRST, we perform this magic
2467 * delay here as well.
09c7ad79
AC		 2468 *
2469 * Old drivers/ide uses the 2mS rule and then waits for ready
1da177e4
LT		 2470 */
2471 msleep(150);
2472
2e9edbf8 2473 /* Before we perform post reset processing we want to see if
298a41ca
TH		 2474 * the bus shows 0xFF because the odd clown forgets the D7
2475 * pulldown resistor.
2476 */
d1adc1bb
TH		 2477 if (ata_check_status(ap) == 0xFF)
2478 return 0;
09c7ad79 2479
1da177e4
LT		 2480 ata_bus_post_reset(ap, devmask);
2481
2482 return 0;
2483}
2484
2485/**
2486 * ata_bus_reset - reset host port and associated ATA channel
2487 * @ap: port to reset
2488 *
2489 * This is typically the first time we actually start issuing
2490 * commands to the ATA channel. We wait for BSY to clear, then
2491 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2492 * result. Determine what devices, if any, are on the channel
2493 * by looking at the device 0/1 error register. Look at the signature
2494 * stored in each device's taskfile registers, to determine if
2495 * the device is ATA or ATAPI.
2496 *
2497 * LOCKING:
0cba632b 2498 * PCI/etc. bus probe sem.
cca3974e 2499 * Obtains host lock.
1da177e4
LT		 2500 *
2501 * SIDE EFFECTS:
198e0fed 2502 * Sets ATA_FLAG_DISABLED if bus reset fails.
1da177e4
LT		 2503 */
2504
2505void ata_bus_reset(struct ata_port *ap)
2506{
2507 struct ata_ioports *ioaddr = &ap->ioaddr;
2508 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2509 u8 err;
aec5c3c1 2510 unsigned int dev0, dev1 = 0, devmask = 0;
1da177e4
LT		 2511
2512 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2513
2514 /* determine if device 0/1 are present */
2515 if (ap->flags & ATA_FLAG_SATA_RESET)
2516 dev0 = 1;
2517 else {
2518 dev0 = ata_devchk(ap, 0);
2519 if (slave_possible)
2520 dev1 = ata_devchk(ap, 1);
2521 }
2522
2523 if (dev0)
2524 devmask |= (1 << 0);
2525 if (dev1)
2526 devmask |= (1 << 1);
2527
2528 /* select device 0 again */
2529 ap->ops->dev_select(ap, 0);
2530
2531 /* issue bus reset */
2532 if (ap->flags & ATA_FLAG_SRST)
aec5c3c1
TH		 2533 if (ata_bus_softreset(ap, devmask))
2534 goto err_out;
1da177e4
LT		 2535
2536 /*
2537 * determine by signature whether we have ATA or ATAPI devices
2538 */
b4dc7623 2539 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 2540 if ((slave_possible) && (err != 0x81))
b4dc7623 2541 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 2542
2543 /* re-enable interrupts */
2544 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2545 ata_irq_on(ap);
2546
2547 /* is double-select really necessary? */
2548 if (ap->device[1].class != ATA_DEV_NONE)
2549 ap->ops->dev_select(ap, 1);
2550 if (ap->device[0].class != ATA_DEV_NONE)
2551 ap->ops->dev_select(ap, 0);
2552
2553 /* if no devices were detected, disable this port */
2554 if ((ap->device[0].class == ATA_DEV_NONE) &&
2555 (ap->device[1].class == ATA_DEV_NONE))
2556 goto err_out;
2557
2558 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2559 /* set up device control for ATA_FLAG_SATA_RESET */
2560 if (ap->flags & ATA_FLAG_MMIO)
2561 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2562 else
2563 outb(ap->ctl, ioaddr->ctl_addr);
2564 }
2565
2566 DPRINTK("EXIT\n");
2567 return;
2568
2569err_out:
f15a1daf 2570 ata_port_printk(ap, KERN_ERR, "disabling port\n");
1da177e4
LT		 2571 ap->ops->port_disable(ap);
2572
2573 DPRINTK("EXIT\n");
2574}
2575
d7bb4cc7
TH		 2576/**
2577 * sata_phy_debounce - debounce SATA phy status
2578 * @ap: ATA port to debounce SATA phy status for
2579 * @params: timing parameters { interval, duratinon, timeout } in msec
2580 *
2581 * Make sure SStatus of @ap reaches stable state, determined by
2582 * holding the same value where DET is not 1 for @duration polled
2583 * every @interval, before @timeout. Timeout constraints the
2584 * beginning of the stable state. Because, after hot unplugging,
2585 * DET gets stuck at 1 on some controllers, this functions waits
2586 * until timeout then returns 0 if DET is stable at 1.
2587 *
2588 * LOCKING:
2589 * Kernel thread context (may sleep)
2590 *
2591 * RETURNS:
2592 * 0 on success, -errno on failure.
2593 */
2594int sata_phy_debounce(struct ata_port *ap, const unsigned long *params)
7a7921e8 2595{
d7bb4cc7
TH		 2596 unsigned long interval_msec = params[0];
2597 unsigned long duration = params[1] * HZ / 1000;
2598 unsigned long timeout = jiffies + params[2] * HZ / 1000;
2599 unsigned long last_jiffies;
2600 u32 last, cur;
2601 int rc;
2602
2603 if ((rc = sata_scr_read(ap, SCR_STATUS, &cur)))
2604 return rc;
2605 cur &= 0xf;
2606
2607 last = cur;
2608 last_jiffies = jiffies;
2609
2610 while (1) {
2611 msleep(interval_msec);
2612 if ((rc = sata_scr_read(ap, SCR_STATUS, &cur)))
2613 return rc;
2614 cur &= 0xf;
2615
2616 /* DET stable? */
2617 if (cur == last) {
2618 if (cur == 1 && time_before(jiffies, timeout))
2619 continue;
2620 if (time_after(jiffies, last_jiffies + duration))
2621 return 0;
2622 continue;
2623 }
2624
2625 /* unstable, start over */
2626 last = cur;
2627 last_jiffies = jiffies;
2628
2629 /* check timeout */
2630 if (time_after(jiffies, timeout))
2631 return -EBUSY;
2632 }
2633}
2634
2635/**
2636 * sata_phy_resume - resume SATA phy
2637 * @ap: ATA port to resume SATA phy for
2638 * @params: timing parameters { interval, duratinon, timeout } in msec
2639 *
2640 * Resume SATA phy of @ap and debounce it.
2641 *
2642 * LOCKING:
2643 * Kernel thread context (may sleep)
2644 *
2645 * RETURNS:
2646 * 0 on success, -errno on failure.
2647 */
2648int sata_phy_resume(struct ata_port *ap, const unsigned long *params)
2649{
2650 u32 scontrol;
81952c54
TH		 2651 int rc;
2652
2653 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
2654 return rc;
7a7921e8 2655
852ee16a 2656 scontrol = (scontrol & 0x0f0) | 0x300;
81952c54
TH		 2657
2658 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
2659 return rc;
7a7921e8 2660
d7bb4cc7
TH		 2661 /* Some PHYs react badly if SStatus is pounded immediately
2662 * after resuming. Delay 200ms before debouncing.
2663 */
2664 msleep(200);
7a7921e8 2665
d7bb4cc7 2666 return sata_phy_debounce(ap, params);
7a7921e8
TH		 2667}
2668
f5914a46
TH		 2669static void ata_wait_spinup(struct ata_port *ap)
2670{
2671 struct ata_eh_context *ehc = &ap->eh_context;
2672 unsigned long end, secs;
2673 int rc;
2674
2675 /* first, debounce phy if SATA */
2676 if (ap->cbl == ATA_CBL_SATA) {
e9c83914 2677 rc = sata_phy_debounce(ap, sata_deb_timing_hotplug);
f5914a46
TH		 2678
2679 /* if debounced successfully and offline, no need to wait */
2680 if ((rc == 0 || rc == -EOPNOTSUPP) && ata_port_offline(ap))
2681 return;
2682 }
2683
2684 /* okay, let's give the drive time to spin up */
2685 end = ehc->i.hotplug_timestamp + ATA_SPINUP_WAIT * HZ / 1000;
2686 secs = ((end - jiffies) + HZ - 1) / HZ;
2687
2688 if (time_after(jiffies, end))
2689 return;
2690
2691 if (secs > 5)
2692 ata_port_printk(ap, KERN_INFO, "waiting for device to spin up "
2693 "(%lu secs)\n", secs);
2694
2695 schedule_timeout_uninterruptible(end - jiffies);
2696}
2697
2698/**
2699 * ata_std_prereset - prepare for reset
2700 * @ap: ATA port to be reset
2701 *
2702 * @ap is about to be reset. Initialize it.
2703 *
2704 * LOCKING:
2705 * Kernel thread context (may sleep)
2706 *
2707 * RETURNS:
2708 * 0 on success, -errno otherwise.
2709 */
2710int ata_std_prereset(struct ata_port *ap)
2711{
2712 struct ata_eh_context *ehc = &ap->eh_context;
e9c83914 2713 const unsigned long *timing = sata_ehc_deb_timing(ehc);
f5914a46
TH		 2714 int rc;
2715
28324304
TH		 2716 /* handle link resume & hotplug spinup */
2717 if ((ehc->i.flags & ATA_EHI_RESUME_LINK) &&
2718 (ap->flags & ATA_FLAG_HRST_TO_RESUME))
2719 ehc->i.action |= ATA_EH_HARDRESET;
2720
2721 if ((ehc->i.flags & ATA_EHI_HOTPLUGGED) &&
2722 (ap->flags & ATA_FLAG_SKIP_D2H_BSY))
2723 ata_wait_spinup(ap);
f5914a46
TH		 2724
2725 /* if we're about to do hardreset, nothing more to do */
2726 if (ehc->i.action & ATA_EH_HARDRESET)
2727 return 0;
2728
2729 /* if SATA, resume phy */
2730 if (ap->cbl == ATA_CBL_SATA) {
f5914a46
TH		 2731 rc = sata_phy_resume(ap, timing);
2732 if (rc && rc != -EOPNOTSUPP) {
2733 /* phy resume failed */
2734 ata_port_printk(ap, KERN_WARNING, "failed to resume "
2735 "link for reset (errno=%d)\n", rc);
2736 return rc;
2737 }
2738 }
2739
2740 /* Wait for !BSY if the controller can wait for the first D2H
2741 * Reg FIS and we don't know that no device is attached.
2742 */
2743 if (!(ap->flags & ATA_FLAG_SKIP_D2H_BSY) && !ata_port_offline(ap))
2744 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2745
2746 return 0;
2747}
2748
c2bd5804
TH		 2749/**
2750 * ata_std_softreset - reset host port via ATA SRST
2751 * @ap: port to reset
c2bd5804
TH		 2752 * @classes: resulting classes of attached devices
2753 *
52783c5d 2754 * Reset host port using ATA SRST.
c2bd5804
TH		 2755 *
2756 * LOCKING:
2757 * Kernel thread context (may sleep)
2758 *
2759 * RETURNS:
2760 * 0 on success, -errno otherwise.
2761 */
2bf2cb26 2762int ata_std_softreset(struct ata_port *ap, unsigned int *classes)
c2bd5804
TH		 2763{
2764 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2765 unsigned int devmask = 0, err_mask;
2766 u8 err;
2767
2768 DPRINTK("ENTER\n");
2769
81952c54 2770 if (ata_port_offline(ap)) {
3a39746a
TH		 2771 classes[0] = ATA_DEV_NONE;
2772 goto out;
2773 }
2774
c2bd5804
TH		 2775 /* determine if device 0/1 are present */
2776 if (ata_devchk(ap, 0))
2777 devmask |= (1 << 0);
2778 if (slave_possible && ata_devchk(ap, 1))
2779 devmask |= (1 << 1);
2780
c2bd5804
TH		 2781 /* select device 0 again */
2782 ap->ops->dev_select(ap, 0);
2783
2784 /* issue bus reset */
2785 DPRINTK("about to softreset, devmask=%x\n", devmask);
2786 err_mask = ata_bus_softreset(ap, devmask);
2787 if (err_mask) {
f15a1daf
TH		 2788 ata_port_printk(ap, KERN_ERR, "SRST failed (err_mask=0x%x)\n",
2789 err_mask);
c2bd5804
TH		 2790 return -EIO;
2791 }
2792
2793 /* determine by signature whether we have ATA or ATAPI devices */
2794 classes[0] = ata_dev_try_classify(ap, 0, &err);
2795 if (slave_possible && err != 0x81)
2796 classes[1] = ata_dev_try_classify(ap, 1, &err);
2797
3a39746a 2798 out:
c2bd5804
TH		 2799 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2800 return 0;
2801}
2802
2803/**
b6103f6d 2804 * sata_port_hardreset - reset port via SATA phy reset
c2bd5804 2805 * @ap: port to reset
b6103f6d 2806 * @timing: timing parameters { interval, duratinon, timeout } in msec
c2bd5804
TH		 2807 *
2808 * SATA phy-reset host port using DET bits of SControl register.
c2bd5804
TH		 2809 *
2810 * LOCKING:
2811 * Kernel thread context (may sleep)
2812 *
2813 * RETURNS:
2814 * 0 on success, -errno otherwise.
2815 */
b6103f6d 2816int sata_port_hardreset(struct ata_port *ap, const unsigned long *timing)
c2bd5804 2817{
852ee16a 2818 u32 scontrol;
81952c54 2819 int rc;
852ee16a 2820
c2bd5804
TH		 2821 DPRINTK("ENTER\n");
2822
3c567b7d 2823 if (sata_set_spd_needed(ap)) {
1c3fae4d
TH		 2824 /* SATA spec says nothing about how to reconfigure
2825 * spd. To be on the safe side, turn off phy during
2826 * reconfiguration. This works for at least ICH7 AHCI
2827 * and Sil3124.
2828 */
81952c54 2829 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
b6103f6d 2830 goto out;
81952c54 2831
a34b6fc0 2832 scontrol = (scontrol & 0x0f0) | 0x304;
81952c54
TH		 2833
2834 if ((rc = sata_scr_write(ap, SCR_CONTROL, scontrol)))
b6103f6d 2835 goto out;
1c3fae4d 2836
3c567b7d 2837 sata_set_spd(ap);
1c3fae4d
TH		 2838 }
2839
2840 /* issue phy wake/reset */
81952c54 2841 if ((rc = sata_scr_read(ap, SCR_CONTROL, &scontrol)))
b6103f6d 2842 goto out;
81952c54 2843
852ee16a 2844 scontrol = (scontrol & 0x0f0) | 0x301;
81952c54
TH		 2845
2846 if ((rc = sata_scr_write_flush(ap, SCR_CONTROL, scontrol)))
b6103f6d 2847 goto out;
c2bd5804 2848
1c3fae4d 2849 /* Couldn't find anything in SATA I/II specs, but AHCI-1.1
c2bd5804
TH		 2850 * 10.4.2 says at least 1 ms.
2851 */
2852 msleep(1);
2853
1c3fae4d 2854 /* bring phy back */
b6103f6d
TH		 2855 rc = sata_phy_resume(ap, timing);
2856 out:
2857 DPRINTK("EXIT, rc=%d\n", rc);
2858 return rc;
2859}
2860
2861/**
2862 * sata_std_hardreset - reset host port via SATA phy reset
2863 * @ap: port to reset
2864 * @class: resulting class of attached device
2865 *
2866 * SATA phy-reset host port using DET bits of SControl register,
2867 * wait for !BSY and classify the attached device.
2868 *
2869 * LOCKING:
2870 * Kernel thread context (may sleep)
2871 *
2872 * RETURNS:
2873 * 0 on success, -errno otherwise.
2874 */
2875int sata_std_hardreset(struct ata_port *ap, unsigned int *class)
2876{
2877 const unsigned long *timing = sata_ehc_deb_timing(&ap->eh_context);
2878 int rc;
2879
2880 DPRINTK("ENTER\n");
2881
2882 /* do hardreset */
2883 rc = sata_port_hardreset(ap, timing);
2884 if (rc) {
2885 ata_port_printk(ap, KERN_ERR,
2886 "COMRESET failed (errno=%d)\n", rc);
2887 return rc;
2888 }
c2bd5804 2889
c2bd5804 2890 /* TODO: phy layer with polling, timeouts, etc. */
81952c54 2891 if (ata_port_offline(ap)) {
c2bd5804
TH		 2892 *class = ATA_DEV_NONE;
2893 DPRINTK("EXIT, link offline\n");
2894 return 0;
2895 }
2896
2897 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
f15a1daf
TH		 2898 ata_port_printk(ap, KERN_ERR,
2899 "COMRESET failed (device not ready)\n");
c2bd5804
TH		 2900 return -EIO;
2901 }
2902
3a39746a
TH		 2903 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2904
c2bd5804
TH		 2905 *class = ata_dev_try_classify(ap, 0, NULL);
2906
2907 DPRINTK("EXIT, class=%u\n", *class);
2908 return 0;
2909}
2910
2911/**
2912 * ata_std_postreset - standard postreset callback
2913 * @ap: the target ata_port
2914 * @classes: classes of attached devices
2915 *
2916 * This function is invoked after a successful reset. Note that
2917 * the device might have been reset more than once using
2918 * different reset methods before postreset is invoked.
c2bd5804 2919 *
c2bd5804
TH		 2920 * LOCKING:
2921 * Kernel thread context (may sleep)
2922 */
2923void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2924{
dc2b3515
TH		 2925 u32 serror;
2926
c2bd5804
TH		 2927 DPRINTK("ENTER\n");
2928
c2bd5804 2929 /* print link status */
81952c54 2930 sata_print_link_status(ap);
c2bd5804 2931
dc2b3515
TH		 2932 /* clear SError */
2933 if (sata_scr_read(ap, SCR_ERROR, &serror) == 0)
2934 sata_scr_write(ap, SCR_ERROR, serror);
2935
3a39746a 2936 /* re-enable interrupts */
e3180499
TH		 2937 if (!ap->ops->error_handler) {
2938 /* FIXME: hack. create a hook instead */
2939 if (ap->ioaddr.ctl_addr)
2940 ata_irq_on(ap);
2941 }
c2bd5804
TH		 2942
2943 /* is double-select really necessary? */
2944 if (classes[0] != ATA_DEV_NONE)
2945 ap->ops->dev_select(ap, 1);
2946 if (classes[1] != ATA_DEV_NONE)
2947 ap->ops->dev_select(ap, 0);
2948
3a39746a
TH		 2949 /* bail out if no device is present */
2950 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2951 DPRINTK("EXIT, no device\n");
2952 return;
2953 }
2954
2955 /* set up device control */
2956 if (ap->ioaddr.ctl_addr) {
2957 if (ap->flags & ATA_FLAG_MMIO)
2958 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2959 else
2960 outb(ap->ctl, ap->ioaddr.ctl_addr);
2961 }
c2bd5804
TH		 2962
2963 DPRINTK("EXIT\n");
2964}
2965
623a3128
TH		 2966/**
2967 * ata_dev_same_device - Determine whether new ID matches configured device
623a3128
TH		 2968 * @dev: device to compare against
2969 * @new_class: class of the new device
2970 * @new_id: IDENTIFY page of the new device
2971 *
2972 * Compare @new_class and @new_id against @dev and determine
2973 * whether @dev is the device indicated by @new_class and
2974 * @new_id.
2975 *
2976 * LOCKING:
2977 * None.
2978 *
2979 * RETURNS:
2980 * 1 if @dev matches @new_class and @new_id, 0 otherwise.
2981 */
3373efd8
TH		 2982static int ata_dev_same_device(struct ata_device *dev, unsigned int new_class,
2983 const u16 *new_id)
623a3128
TH		 2984{
2985 const u16 *old_id = dev->id;
2986 unsigned char model[2][41], serial[2][21];
2987 u64 new_n_sectors;
2988
2989 if (dev->class != new_class) {
f15a1daf
TH		 2990 ata_dev_printk(dev, KERN_INFO, "class mismatch %d != %d\n",
2991 dev->class, new_class);
623a3128
TH		 2992 return 0;
2993 }
2994
2995 ata_id_c_string(old_id, model[0], ATA_ID_PROD_OFS, sizeof(model[0]));
2996 ata_id_c_string(new_id, model[1], ATA_ID_PROD_OFS, sizeof(model[1]));
2997 ata_id_c_string(old_id, serial[0], ATA_ID_SERNO_OFS, sizeof(serial[0]));
2998 ata_id_c_string(new_id, serial[1], ATA_ID_SERNO_OFS, sizeof(serial[1]));
2999 new_n_sectors = ata_id_n_sectors(new_id);
3000
3001 if (strcmp(model[0], model[1])) {
f15a1daf
TH		 3002 ata_dev_printk(dev, KERN_INFO, "model number mismatch "
3003 "'%s' != '%s'\n", model[0], model[1]);
623a3128
TH		 3004 return 0;
3005 }
3006
3007 if (strcmp(serial[0], serial[1])) {
f15a1daf
TH		 3008 ata_dev_printk(dev, KERN_INFO, "serial number mismatch "
3009 "'%s' != '%s'\n", serial[0], serial[1]);
623a3128
TH		 3010 return 0;
3011 }
3012
3013 if (dev->class == ATA_DEV_ATA && dev->n_sectors != new_n_sectors) {
f15a1daf
TH		 3014 ata_dev_printk(dev, KERN_INFO, "n_sectors mismatch "
3015 "%llu != %llu\n",
3016 (unsigned long long)dev->n_sectors,
3017 (unsigned long long)new_n_sectors);
623a3128
TH		 3018 return 0;
3019 }
3020
3021 return 1;
3022}
3023
3024/**
3025 * ata_dev_revalidate - Revalidate ATA device
623a3128 3026 * @dev: device to revalidate
bff04647 3027 * @readid_flags: read ID flags
623a3128
TH		 3028 *
3029 * Re-read IDENTIFY page and make sure @dev is still attached to
3030 * the port.
3031 *
3032 * LOCKING:
3033 * Kernel thread context (may sleep)
3034 *
3035 * RETURNS:
3036 * 0 on success, negative errno otherwise
3037 */
bff04647 3038int ata_dev_revalidate(struct ata_device *dev, unsigned int readid_flags)
623a3128 3039{
5eb45c02 3040 unsigned int class = dev->class;
f15a1daf 3041 u16 *id = (void *)dev->ap->sector_buf;
623a3128
TH		 3042 int rc;
3043
5eb45c02
TH		 3044 if (!ata_dev_enabled(dev)) {
3045 rc = -ENODEV;
3046 goto fail;
3047 }
623a3128 3048
fe635c7e 3049 /* read ID data */
bff04647 3050 rc = ata_dev_read_id(dev, &class, readid_flags, id);
623a3128
TH		 3051 if (rc)
3052 goto fail;
3053
3054 /* is the device still there? */
3373efd8 3055 if (!ata_dev_same_device(dev, class, id)) {
623a3128
TH		 3056 rc = -ENODEV;
3057 goto fail;
3058 }
3059
fe635c7e 3060 memcpy(dev->id, id, sizeof(id[0]) * ATA_ID_WORDS);
623a3128
TH		 3061
3062 /* configure device according to the new ID */
efdaedc4 3063 rc = ata_dev_configure(dev);
5eb45c02
TH		 3064 if (rc == 0)
3065 return 0;
623a3128
TH		 3066
3067 fail:
f15a1daf 3068 ata_dev_printk(dev, KERN_ERR, "revalidation failed (errno=%d)\n", rc);
623a3128
TH		 3069 return rc;
3070}
3071
6919a0a6
AC		 3072struct ata_blacklist_entry {
3073 const char *model_num;
3074 const char *model_rev;
3075 unsigned long horkage;
3076};
3077
3078static const struct ata_blacklist_entry ata_device_blacklist [] = {
3079 /* Devices with DMA related problems under Linux */
3080 { "WDC AC11000H", NULL, ATA_HORKAGE_NODMA },
3081 { "WDC AC22100H", NULL, ATA_HORKAGE_NODMA },
3082 { "WDC AC32500H", NULL, ATA_HORKAGE_NODMA },
3083 { "WDC AC33100H", NULL, ATA_HORKAGE_NODMA },
3084 { "WDC AC31600H", NULL, ATA_HORKAGE_NODMA },
3085 { "WDC AC32100H", "24.09P07", ATA_HORKAGE_NODMA },
3086 { "WDC AC23200L", "21.10N21", ATA_HORKAGE_NODMA },
3087 { "Compaq CRD-8241B", NULL, ATA_HORKAGE_NODMA },
3088 { "CRD-8400B", NULL, ATA_HORKAGE_NODMA },
3089 { "CRD-8480B", NULL, ATA_HORKAGE_NODMA },
3090 { "CRD-8482B", NULL, ATA_HORKAGE_NODMA },
3091 { "CRD-84", NULL, ATA_HORKAGE_NODMA },
3092 { "SanDisk SDP3B", NULL, ATA_HORKAGE_NODMA },
3093 { "SanDisk SDP3B-64", NULL, ATA_HORKAGE_NODMA },
3094 { "SANYO CD-ROM CRD", NULL, ATA_HORKAGE_NODMA },
3095 { "HITACHI CDR-8", NULL, ATA_HORKAGE_NODMA },
3096 { "HITACHI CDR-8335", NULL, ATA_HORKAGE_NODMA },
3097 { "HITACHI CDR-8435", NULL, ATA_HORKAGE_NODMA },
3098 { "Toshiba CD-ROM XM-6202B", NULL, ATA_HORKAGE_NODMA },
3099 { "TOSHIBA CD-ROM XM-1702BC", NULL, ATA_HORKAGE_NODMA },
3100 { "CD-532E-A", NULL, ATA_HORKAGE_NODMA },
3101 { "E-IDE CD-ROM CR-840",NULL, ATA_HORKAGE_NODMA },
3102 { "CD-ROM Drive/F5A", NULL, ATA_HORKAGE_NODMA },
3103 { "WPI CDD-820", NULL, ATA_HORKAGE_NODMA },
3104 { "SAMSUNG CD-ROM SC-148C", NULL, ATA_HORKAGE_NODMA },
3105 { "SAMSUNG CD-ROM SC", NULL, ATA_HORKAGE_NODMA },
3106 { "SanDisk SDP3B-64", NULL, ATA_HORKAGE_NODMA },
3107 { "ATAPI CD-ROM DRIVE 40X MAXIMUM",NULL,ATA_HORKAGE_NODMA },
3108 { "_NEC DV5800A", NULL, ATA_HORKAGE_NODMA },
3109 { "SAMSUNG CD-ROM SN-124","N001", ATA_HORKAGE_NODMA },
3110
3111 /* Devices we expect to fail diagnostics */
3112
3113 /* Devices where NCQ should be avoided */
3114 /* NCQ is slow */
3115 { "WDC WD740ADFD-00", NULL, ATA_HORKAGE_NONCQ },
3116
3117 /* Devices with NCQ limits */
3118
3119 /* End Marker */
3120 { }
1da177e4 3121};
2e9edbf8 3122
f4b15fef
AC		 3123static int ata_strim(char *s, size_t len)
3124{
3125 len = strnlen(s, len);
3126
3127 /* ATAPI specifies that empty space is blank-filled; remove blanks */
3128 while ((len > 0) && (s[len - 1] == ' ')) {
3129 len--;
3130 s[len] = 0;
3131 }
3132 return len;
3133}
1da177e4 3134
6919a0a6 3135unsigned long ata_device_blacklisted(const struct ata_device *dev)
1da177e4 3136{
f4b15fef
AC		 3137 unsigned char model_num[40];
3138 unsigned char model_rev[16];
3139 unsigned int nlen, rlen;
6919a0a6 3140 const struct ata_blacklist_entry *ad = ata_device_blacklist;
3a778275 3141
f4b15fef
AC		 3142 ata_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
3143 sizeof(model_num));
3144 ata_id_string(dev->id, model_rev, ATA_ID_FW_REV_OFS,
3145 sizeof(model_rev));
3146 nlen = ata_strim(model_num, sizeof(model_num));
3147 rlen = ata_strim(model_rev, sizeof(model_rev));
1da177e4 3148
6919a0a6
AC		 3149 while (ad->model_num) {
3150 if (!strncmp(ad->model_num, model_num, nlen)) {
3151 if (ad->model_rev == NULL)
3152 return ad->horkage;
3153 if (!strncmp(ad->model_rev, model_rev, rlen))
3154 return ad->horkage;
f4b15fef 3155 }
6919a0a6 3156 ad++;
f4b15fef 3157 }
1da177e4
LT		 3158 return 0;
3159}
3160
6919a0a6
AC		 3161static int ata_dma_blacklisted(const struct ata_device *dev)
3162{
3163 /* We don't support polling DMA.
3164 * DMA blacklist those ATAPI devices with CDB-intr (and use PIO)
3165 * if the LLDD handles only interrupts in the HSM_ST_LAST state.
3166 */
3167 if ((dev->ap->flags & ATA_FLAG_PIO_POLLING) &&
3168 (dev->flags & ATA_DFLAG_CDB_INTR))
3169 return 1;
3170 return (ata_device_blacklisted(dev) & ATA_HORKAGE_NODMA) ? 1 : 0;
3171}
3172
a6d5a51c
TH		 3173/**
3174 * ata_dev_xfermask - Compute supported xfermask of the given device
a6d5a51c
TH		 3175 * @dev: Device to compute xfermask for
3176 *
acf356b1
TH		 3177 * Compute supported xfermask of @dev and store it in
3178 * dev->*_mask. This function is responsible for applying all
3179 * known limits including host controller limits, device
3180 * blacklist, etc...
a6d5a51c
TH		 3181 *
3182 * LOCKING:
3183 * None.
a6d5a51c 3184 */
3373efd8 3185static void ata_dev_xfermask(struct ata_device *dev)
1da177e4 3186{
3373efd8 3187 struct ata_port *ap = dev->ap;
cca3974e 3188 struct ata_host *host = ap->host;
a6d5a51c 3189 unsigned long xfer_mask;
1da177e4 3190
37deecb5 3191 /* controller modes available */
565083e1
TH		 3192 xfer_mask = ata_pack_xfermask(ap->pio_mask,
3193 ap->mwdma_mask, ap->udma_mask);
3194
3195 /* Apply cable rule here. Don't apply it early because when
3196 * we handle hot plug the cable type can itself change.
3197 */
3198 if (ap->cbl == ATA_CBL_PATA40)
3199 xfer_mask &= ~(0xF8 << ATA_SHIFT_UDMA);
fc085150
AC		 3200 /* Apply drive side cable rule. Unknown or 80 pin cables reported
3201 * host side are checked drive side as well. Cases where we know a
3202 * 40wire cable is used safely for 80 are not checked here.
3203 */
3204 if (ata_drive_40wire(dev->id) && (ap->cbl == ATA_CBL_PATA_UNK || ap->cbl == ATA_CBL_PATA80))
3205 xfer_mask &= ~(0xF8 << ATA_SHIFT_UDMA);
3206
1da177e4 3207
37deecb5
TH		 3208 xfer_mask &= ata_pack_xfermask(dev->pio_mask,
3209 dev->mwdma_mask, dev->udma_mask);
3210 xfer_mask &= ata_id_xfermask(dev->id);
565083e1 3211
b352e57d
AC		 3212 /*
3213 * CFA Advanced TrueIDE timings are not allowed on a shared
3214 * cable
3215 */
3216 if (ata_dev_pair(dev)) {
3217 /* No PIO5 or PIO6 */
3218 xfer_mask &= ~(0x03 << (ATA_SHIFT_PIO + 5));
3219 /* No MWDMA3 or MWDMA 4 */
3220 xfer_mask &= ~(0x03 << (ATA_SHIFT_MWDMA + 3));
3221 }
3222
37deecb5
TH		 3223 if (ata_dma_blacklisted(dev)) {
3224 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
f15a1daf
TH		 3225 ata_dev_printk(dev, KERN_WARNING,
3226 "device is on DMA blacklist, disabling DMA\n");
37deecb5 3227 }
a6d5a51c 3228
cca3974e 3229 if ((host->flags & ATA_HOST_SIMPLEX) && host->simplex_claimed) {
37deecb5
TH		 3230 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
3231 ata_dev_printk(dev, KERN_WARNING, "simplex DMA is claimed by "
3232 "other device, disabling DMA\n");
5444a6f4 3233 }
565083e1 3234
5444a6f4
AC		 3235 if (ap->ops->mode_filter)
3236 xfer_mask = ap->ops->mode_filter(ap, dev, xfer_mask);
3237
565083e1
TH		 3238 ata_unpack_xfermask(xfer_mask, &dev->pio_mask,
3239 &dev->mwdma_mask, &dev->udma_mask);
1da177e4
LT		 3240}
3241
1da177e4
LT		 3242/**
3243 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
1da177e4
LT		 3244 * @dev: Device to which command will be sent
3245 *
780a87f7
JG		 3246 * Issue SET FEATURES - XFER MODE command to device @dev
3247 * on port @ap.
3248 *
1da177e4 3249 * LOCKING:
0cba632b 3250 * PCI/etc. bus probe sem.
83206a29
TH		 3251 *
3252 * RETURNS:
3253 * 0 on success, AC_ERR_* mask otherwise.
1da177e4
LT		 3254 */
3255
3373efd8 3256static unsigned int ata_dev_set_xfermode(struct ata_device *dev)
1da177e4 3257{
a0123703 3258 struct ata_taskfile tf;
83206a29 3259 unsigned int err_mask;
1da177e4
LT		 3260
3261 /* set up set-features taskfile */
3262 DPRINTK("set features - xfer mode\n");
3263
3373efd8 3264 ata_tf_init(dev, &tf);
a0123703
TH		 3265 tf.command = ATA_CMD_SET_FEATURES;
3266 tf.feature = SETFEATURES_XFER;
3267 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3268 tf.protocol = ATA_PROT_NODATA;
3269 tf.nsect = dev->xfer_mode;
1da177e4 3270
3373efd8 3271 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
1da177e4 3272
83206a29
TH		 3273 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3274 return err_mask;
1da177e4
LT		 3275}
3276
8bf62ece
AL		 3277/**
3278 * ata_dev_init_params - Issue INIT DEV PARAMS command
8bf62ece 3279 * @dev: Device to which command will be sent
e2a7f77a
RD		 3280 * @heads: Number of heads (taskfile parameter)
3281 * @sectors: Number of sectors (taskfile parameter)
8bf62ece
AL		 3282 *
3283 * LOCKING:
6aff8f1f
TH		 3284 * Kernel thread context (may sleep)
3285 *
3286 * RETURNS:
3287 * 0 on success, AC_ERR_* mask otherwise.
8bf62ece 3288 */
3373efd8
TH		 3289static unsigned int ata_dev_init_params(struct ata_device *dev,
3290 u16 heads, u16 sectors)
8bf62ece 3291{
a0123703 3292 struct ata_taskfile tf;
6aff8f1f 3293 unsigned int err_mask;
8bf62ece
AL		 3294
3295 /* Number of sectors per track 1-255. Number of heads 1-16 */
3296 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
00b6f5e9 3297 return AC_ERR_INVALID;
8bf62ece
AL		 3298
3299 /* set up init dev params taskfile */
3300 DPRINTK("init dev params \n");
3301
3373efd8 3302 ata_tf_init(dev, &tf);
a0123703
TH		 3303 tf.command = ATA_CMD_INIT_DEV_PARAMS;
3304 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
3305 tf.protocol = ATA_PROT_NODATA;
3306 tf.nsect = sectors;
3307 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 3308
3373efd8 3309 err_mask = ata_exec_internal(dev, &tf, NULL, DMA_NONE, NULL, 0);
8bf62ece 3310
6aff8f1f
TH		 3311 DPRINTK("EXIT, err_mask=%x\n", err_mask);
3312 return err_mask;
8bf62ece
AL		 3313}
3314
1da177e4 3315/**
0cba632b
JG		 3316 * ata_sg_clean - Unmap DMA memory associated with command
3317 * @qc: Command containing DMA memory to be released
3318 *
3319 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 3320 *
3321 * LOCKING:
cca3974e 3322 * spin_lock_irqsave(host lock)
1da177e4
LT		 3323 */
3324
3325static void ata_sg_clean(struct ata_queued_cmd *qc)
3326{
3327 struct ata_port *ap = qc->ap;
cedc9a47 3328 struct scatterlist *sg = qc->__sg;
1da177e4 3329 int dir = qc->dma_dir;
cedc9a47 3330 void *pad_buf = NULL;
1da177e4 3331
a4631474
TH		 3332 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
3333 WARN_ON(sg == NULL);
1da177e4
LT		 3334
3335 if (qc->flags & ATA_QCFLAG_SINGLE)
f131883e 3336 WARN_ON(qc->n_elem > 1);
1da177e4 3337
2c13b7ce 3338 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 3339
cedc9a47
JG		 3340 /* if we padded the buffer out to 32-bit bound, and data
3341 * xfer direction is from-device, we must copy from the
3342 * pad buffer back into the supplied buffer
3343 */
3344 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
3345 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3346
3347 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d 3348 if (qc->n_elem)
2f1f610b 3349 dma_unmap_sg(ap->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 3350 /* restore last sg */
3351 sg[qc->orig_n_elem - 1].length += qc->pad_len;
3352 if (pad_buf) {
3353 struct scatterlist *psg = &qc->pad_sgent;
3354 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3355 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 3356 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3357 }
3358 } else {
2e242fa9 3359 if (qc->n_elem)
2f1f610b 3360 dma_unmap_single(ap->dev,
e1410f2d
JG		 3361 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
3362 dir);
cedc9a47
JG		 3363 /* restore sg */
3364 sg->length += qc->pad_len;
3365 if (pad_buf)
3366 memcpy(qc->buf_virt + sg->length - qc->pad_len,
3367 pad_buf, qc->pad_len);
3368 }
1da177e4
LT		 3369
3370 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 3371 qc->__sg = NULL;
1da177e4
LT		 3372}
3373
3374/**
3375 * ata_fill_sg - Fill PCI IDE PRD table
3376 * @qc: Metadata associated with taskfile to be transferred
3377 *
780a87f7
JG		 3378 * Fill PCI IDE PRD (scatter-gather) table with segments
3379 * associated with the current disk command.
3380 *
1da177e4 3381 * LOCKING:
cca3974e 3382 * spin_lock_irqsave(host lock)
1da177e4
LT		 3383 *
3384 */
3385static void ata_fill_sg(struct ata_queued_cmd *qc)
3386{
1da177e4 3387 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3388 struct scatterlist *sg;
3389 unsigned int idx;
1da177e4 3390
a4631474 3391 WARN_ON(qc->__sg == NULL);
f131883e 3392 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
1da177e4
LT		 3393
3394 idx = 0;
cedc9a47 3395 ata_for_each_sg(sg, qc) {
1da177e4
LT		 3396 u32 addr, offset;
3397 u32 sg_len, len;
3398
3399 /* determine if physical DMA addr spans 64K boundary.
3400 * Note h/w doesn't support 64-bit, so we unconditionally
3401 * truncate dma_addr_t to u32.
3402 */
3403 addr = (u32) sg_dma_address(sg);
3404 sg_len = sg_dma_len(sg);
3405
3406 while (sg_len) {
3407 offset = addr & 0xffff;
3408 len = sg_len;
3409 if ((offset + sg_len) > 0x10000)
3410 len = 0x10000 - offset;
3411
3412 ap->prd[idx].addr = cpu_to_le32(addr);
3413 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
3414 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
3415
3416 idx++;
3417 sg_len -= len;
3418 addr += len;
3419 }
3420 }
3421
3422 if (idx)
3423 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
3424}
3425/**
3426 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
3427 * @qc: Metadata associated with taskfile to check
3428 *
780a87f7
JG		 3429 * Allow low-level driver to filter ATA PACKET commands, returning
3430 * a status indicating whether or not it is OK to use DMA for the
3431 * supplied PACKET command.
3432 *
1da177e4 3433 * LOCKING:
cca3974e 3434 * spin_lock_irqsave(host lock)
0cba632b 3435 *
1da177e4
LT		 3436 * RETURNS: 0 when ATAPI DMA can be used
3437 * nonzero otherwise
3438 */
3439int ata_check_atapi_dma(struct ata_queued_cmd *qc)
3440{
3441 struct ata_port *ap = qc->ap;
3442 int rc = 0; /* Assume ATAPI DMA is OK by default */
3443
3444 if (ap->ops->check_atapi_dma)
3445 rc = ap->ops->check_atapi_dma(qc);
3446
3447 return rc;
3448}
3449/**
3450 * ata_qc_prep - Prepare taskfile for submission
3451 * @qc: Metadata associated with taskfile to be prepared
3452 *
780a87f7
JG		 3453 * Prepare ATA taskfile for submission.
3454 *
1da177e4 3455 * LOCKING:
cca3974e 3456 * spin_lock_irqsave(host lock)
1da177e4
LT		 3457 */
3458void ata_qc_prep(struct ata_queued_cmd *qc)
3459{
3460 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
3461 return;
3462
3463 ata_fill_sg(qc);
3464}
3465
e46834cd
BK		 3466void ata_noop_qc_prep(struct ata_queued_cmd *qc) { }
3467
0cba632b
JG		 3468/**
3469 * ata_sg_init_one - Associate command with memory buffer
3470 * @qc: Command to be associated
3471 * @buf: Memory buffer
3472 * @buflen: Length of memory buffer, in bytes.
3473 *
3474 * Initialize the data-related elements of queued_cmd @qc
3475 * to point to a single memory buffer, @buf of byte length @buflen.
3476 *
3477 * LOCKING:
cca3974e 3478 * spin_lock_irqsave(host lock)
0cba632b
JG		 3479 */
3480
1da177e4
LT		 3481void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
3482{
3483 struct scatterlist *sg;
3484
3485 qc->flags |= ATA_QCFLAG_SINGLE;
3486
3487 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 3488 qc->__sg = &qc->sgent;
1da177e4 3489 qc->n_elem = 1;
cedc9a47 3490 qc->orig_n_elem = 1;
1da177e4 3491 qc->buf_virt = buf;
233277ca 3492 qc->nbytes = buflen;
1da177e4 3493
cedc9a47 3494 sg = qc->__sg;
f0612bbc 3495 sg_init_one(sg, buf, buflen);
1da177e4
LT		 3496}
3497
0cba632b
JG		 3498/**
3499 * ata_sg_init - Associate command with scatter-gather table.
3500 * @qc: Command to be associated
3501 * @sg: Scatter-gather table.
3502 * @n_elem: Number of elements in s/g table.
3503 *
3504 * Initialize the data-related elements of queued_cmd @qc
3505 * to point to a scatter-gather table @sg, containing @n_elem
3506 * elements.
3507 *
3508 * LOCKING:
cca3974e 3509 * spin_lock_irqsave(host lock)
0cba632b
JG		 3510 */
3511
1da177e4
LT		 3512void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
3513 unsigned int n_elem)
3514{
3515 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 3516 qc->__sg = sg;
1da177e4 3517 qc->n_elem = n_elem;
cedc9a47 3518 qc->orig_n_elem = n_elem;
1da177e4
LT		 3519}
3520
3521/**
0cba632b
JG		 3522 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
3523 * @qc: Command with memory buffer to be mapped.
3524 *
3525 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 3526 *
3527 * LOCKING:
cca3974e 3528 * spin_lock_irqsave(host lock)
1da177e4
LT		 3529 *
3530 * RETURNS:
0cba632b 3531 * Zero on success, negative on error.
1da177e4
LT		 3532 */
3533
3534static int ata_sg_setup_one(struct ata_queued_cmd *qc)
3535{
3536 struct ata_port *ap = qc->ap;
3537 int dir = qc->dma_dir;
cedc9a47 3538 struct scatterlist *sg = qc->__sg;
1da177e4 3539 dma_addr_t dma_address;
2e242fa9 3540 int trim_sg = 0;
1da177e4 3541
cedc9a47
JG		 3542 /* we must lengthen transfers to end on a 32-bit boundary */
3543 qc->pad_len = sg->length & 3;
3544 if (qc->pad_len) {
3545 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3546 struct scatterlist *psg = &qc->pad_sgent;
3547
a4631474 3548 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3549
3550 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3551
3552 if (qc->tf.flags & ATA_TFLAG_WRITE)
3553 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
3554 qc->pad_len);
3555
3556 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3557 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3558 /* trim sg */
3559 sg->length -= qc->pad_len;
2e242fa9
TH		 3560 if (sg->length == 0)
3561 trim_sg = 1;
cedc9a47
JG		 3562
3563 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
3564 sg->length, qc->pad_len);
3565 }
3566
2e242fa9
TH		 3567 if (trim_sg) {
3568 qc->n_elem--;
e1410f2d
JG		 3569 goto skip_map;
3570 }
3571
2f1f610b 3572 dma_address = dma_map_single(ap->dev, qc->buf_virt,
32529e01 3573 sg->length, dir);
537a95d9
TH		 3574 if (dma_mapping_error(dma_address)) {
3575 /* restore sg */
3576 sg->length += qc->pad_len;
1da177e4 3577 return -1;
537a95d9 3578 }
1da177e4
LT		 3579
3580 sg_dma_address(sg) = dma_address;
32529e01 3581 sg_dma_len(sg) = sg->length;
1da177e4 3582
2e242fa9 3583skip_map:
1da177e4
LT		 3584 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
3585 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3586
3587 return 0;
3588}
3589
3590/**
0cba632b
JG		 3591 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
3592 * @qc: Command with scatter-gather table to be mapped.
3593 *
3594 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 3595 *
3596 * LOCKING:
cca3974e 3597 * spin_lock_irqsave(host lock)
1da177e4
LT		 3598 *
3599 * RETURNS:
0cba632b 3600 * Zero on success, negative on error.
1da177e4
LT		 3601 *
3602 */
3603
3604static int ata_sg_setup(struct ata_queued_cmd *qc)
3605{
3606 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3607 struct scatterlist *sg = qc->__sg;
3608 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 3609 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 3610
3611 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 3612 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 3613
cedc9a47
JG		 3614 /* we must lengthen transfers to end on a 32-bit boundary */
3615 qc->pad_len = lsg->length & 3;
3616 if (qc->pad_len) {
3617 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3618 struct scatterlist *psg = &qc->pad_sgent;
3619 unsigned int offset;
3620
a4631474 3621 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3622
3623 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3624
3625 /*
3626 * psg->page/offset are used to copy to-be-written
3627 * data in this function or read data in ata_sg_clean.
3628 */
3629 offset = lsg->offset + lsg->length - qc->pad_len;
3630 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
3631 psg->offset = offset_in_page(offset);
3632
3633 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3634 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3635 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 3636 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3637 }
3638
3639 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3640 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3641 /* trim last sg */
3642 lsg->length -= qc->pad_len;
e1410f2d
JG		 3643 if (lsg->length == 0)
3644 trim_sg = 1;
cedc9a47
JG		 3645
3646 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
3647 qc->n_elem - 1, lsg->length, qc->pad_len);
3648 }
3649
e1410f2d
JG		 3650 pre_n_elem = qc->n_elem;
3651 if (trim_sg && pre_n_elem)
3652 pre_n_elem--;
3653
3654 if (!pre_n_elem) {
3655 n_elem = 0;
3656 goto skip_map;
3657 }
3658
1da177e4 3659 dir = qc->dma_dir;
2f1f610b 3660 n_elem = dma_map_sg(ap->dev, sg, pre_n_elem, dir);
537a95d9
TH		 3661 if (n_elem < 1) {
3662 /* restore last sg */
3663 lsg->length += qc->pad_len;
1da177e4 3664 return -1;
537a95d9 3665 }
1da177e4
LT		 3666
3667 DPRINTK("%d sg elements mapped\n", n_elem);
3668
e1410f2d 3669skip_map:
1da177e4
LT		 3670 qc->n_elem = n_elem;
3671
3672 return 0;
3673}
3674
0baab86b 3675/**
c893a3ae 3676 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3677 * @buf: Buffer to swap
3678 * @buf_words: Number of 16-bit words in buffer.
3679 *
3680 * Swap halves of 16-bit words if needed to convert from
3681 * little-endian byte order to native cpu byte order, or
3682 * vice-versa.
3683 *
3684 * LOCKING:
6f0ef4fa 3685 * Inherited from caller.
0baab86b 3686 */
1da177e4
LT		 3687void swap_buf_le16(u16 *buf, unsigned int buf_words)
3688{
3689#ifdef __BIG_ENDIAN
3690 unsigned int i;
3691
3692 for (i = 0; i < buf_words; i++)
3693 buf[i] = le16_to_cpu(buf[i]);
3694#endif /* __BIG_ENDIAN */
3695}
3696
6ae4cfb5
AL		 3697/**
3698 * ata_mmio_data_xfer - Transfer data by MMIO
bf717b11 3699 * @adev: device for this I/O
6ae4cfb5
AL		 3700 * @buf: data buffer
3701 * @buflen: buffer length
344babaa 3702 * @write_data: read/write
6ae4cfb5
AL		 3703 *
3704 * Transfer data from/to the device data register by MMIO.
3705 *
3706 * LOCKING:
3707 * Inherited from caller.
6ae4cfb5
AL		 3708 */
3709
88574551 3710void ata_mmio_data_xfer(struct ata_device *adev, unsigned char *buf,
a6b2c5d4 3711 unsigned int buflen, int write_data)
1da177e4 3712{
a6b2c5d4 3713 struct ata_port *ap = adev->ap;
1da177e4
LT		 3714 unsigned int i;
3715 unsigned int words = buflen >> 1;
3716 u16 *buf16 = (u16 *) buf;
3717 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3718
6ae4cfb5 3719 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3720 if (write_data) {
3721 for (i = 0; i < words; i++)
3722 writew(le16_to_cpu(buf16[i]), mmio);
3723 } else {
3724 for (i = 0; i < words; i++)
3725 buf16[i] = cpu_to_le16(readw(mmio));
3726 }
6ae4cfb5
AL		 3727
3728 /* Transfer trailing 1 byte, if any. */
3729 if (unlikely(buflen & 0x01)) {
3730 u16 align_buf[1] = { 0 };
3731 unsigned char *trailing_buf = buf + buflen - 1;
3732
3733 if (write_data) {
3734 memcpy(align_buf, trailing_buf, 1);
3735 writew(le16_to_cpu(align_buf[0]), mmio);
3736 } else {
3737 align_buf[0] = cpu_to_le16(readw(mmio));
3738 memcpy(trailing_buf, align_buf, 1);
3739 }
3740 }
1da177e4
LT		 3741}
3742
6ae4cfb5
AL		 3743/**
3744 * ata_pio_data_xfer - Transfer data by PIO
a6b2c5d4 3745 * @adev: device to target
6ae4cfb5
AL		 3746 * @buf: data buffer
3747 * @buflen: buffer length
344babaa 3748 * @write_data: read/write
6ae4cfb5
AL		 3749 *
3750 * Transfer data from/to the device data register by PIO.
3751 *
3752 * LOCKING:
3753 * Inherited from caller.
6ae4cfb5
AL		 3754 */
3755
88574551 3756void ata_pio_data_xfer(struct ata_device *adev, unsigned char *buf,
a6b2c5d4 3757 unsigned int buflen, int write_data)
1da177e4 3758{
a6b2c5d4 3759 struct ata_port *ap = adev->ap;
6ae4cfb5 3760 unsigned int words = buflen >> 1;
1da177e4 3761
6ae4cfb5 3762 /* Transfer multiple of 2 bytes */
1da177e4 3763 if (write_data)
6ae4cfb5 3764 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3765 else
6ae4cfb5
AL		 3766 insw(ap->ioaddr.data_addr, buf, words);
3767
3768 /* Transfer trailing 1 byte, if any. */
3769 if (unlikely(buflen & 0x01)) {
3770 u16 align_buf[1] = { 0 };
3771 unsigned char *trailing_buf = buf + buflen - 1;
3772
3773 if (write_data) {
3774 memcpy(align_buf, trailing_buf, 1);
3775 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3776 } else {
3777 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3778 memcpy(trailing_buf, align_buf, 1);
3779 }
3780 }
1da177e4
LT		 3781}
3782
75e99585
AC		 3783/**
3784 * ata_pio_data_xfer_noirq - Transfer data by PIO
3785 * @adev: device to target
3786 * @buf: data buffer
3787 * @buflen: buffer length
3788 * @write_data: read/write
3789 *
88574551 3790 * Transfer data from/to the device data register by PIO. Do the
75e99585
AC		 3791 * transfer with interrupts disabled.
3792 *
3793 * LOCKING:
3794 * Inherited from caller.
3795 */
3796
3797void ata_pio_data_xfer_noirq(struct ata_device *adev, unsigned char *buf,
3798 unsigned int buflen, int write_data)
3799{
3800 unsigned long flags;
3801 local_irq_save(flags);
3802 ata_pio_data_xfer(adev, buf, buflen, write_data);
3803 local_irq_restore(flags);
3804}
3805
3806
6ae4cfb5
AL		 3807/**
3808 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3809 * @qc: Command on going
3810 *
3811 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3812 *
3813 * LOCKING:
3814 * Inherited from caller.
3815 */
3816
1da177e4
LT		 3817static void ata_pio_sector(struct ata_queued_cmd *qc)
3818{
3819 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3820 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3821 struct ata_port *ap = qc->ap;
3822 struct page *page;
3823 unsigned int offset;
3824 unsigned char *buf;
3825
3826 if (qc->cursect == (qc->nsect - 1))
14be71f4 3827 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3828
3829 page = sg[qc->cursg].page;
3830 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3831
3832 /* get the current page and offset */
3833 page = nth_page(page, (offset >> PAGE_SHIFT));
3834 offset %= PAGE_SIZE;
3835
1da177e4
LT		 3836 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3837
91b8b313
AL		 3838 if (PageHighMem(page)) {
3839 unsigned long flags;
3840
a6b2c5d4 3841 /* FIXME: use a bounce buffer */
91b8b313
AL		 3842 local_irq_save(flags);
3843 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3844
91b8b313 3845 /* do the actual data transfer */
a6b2c5d4 3846 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
1da177e4 3847
91b8b313
AL		 3848 kunmap_atomic(buf, KM_IRQ0);
3849 local_irq_restore(flags);
3850 } else {
3851 buf = page_address(page);
a6b2c5d4 3852 ap->ops->data_xfer(qc->dev, buf + offset, ATA_SECT_SIZE, do_write);
91b8b313 3853 }
1da177e4
LT		 3854
3855 qc->cursect++;
3856 qc->cursg_ofs++;
3857
32529e01 3858 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3859 qc->cursg++;
3860 qc->cursg_ofs = 0;
3861 }
1da177e4 3862}
1da177e4 3863
07f6f7d0
AL		 3864/**
3865 * ata_pio_sectors - Transfer one or many 512-byte sectors.
3866 * @qc: Command on going
3867 *
c81e29b4 3868 * Transfer one or many ATA_SECT_SIZE of data from/to the
07f6f7d0
AL		 3869 * ATA device for the DRQ request.
3870 *
3871 * LOCKING:
3872 * Inherited from caller.
3873 */
1da177e4 3874
07f6f7d0
AL		 3875static void ata_pio_sectors(struct ata_queued_cmd *qc)
3876{
3877 if (is_multi_taskfile(&qc->tf)) {
3878 /* READ/WRITE MULTIPLE */
3879 unsigned int nsect;
3880
587005de 3881 WARN_ON(qc->dev->multi_count == 0);
1da177e4 3882
07f6f7d0
AL		 3883 nsect = min(qc->nsect - qc->cursect, qc->dev->multi_count);
3884 while (nsect--)
3885 ata_pio_sector(qc);
3886 } else
3887 ata_pio_sector(qc);
3888}
3889
c71c1857
AL		 3890/**
3891 * atapi_send_cdb - Write CDB bytes to hardware
3892 * @ap: Port to which ATAPI device is attached.
3893 * @qc: Taskfile currently active
3894 *
3895 * When device has indicated its readiness to accept
3896 * a CDB, this function is called. Send the CDB.
3897 *
3898 * LOCKING:
3899 * caller.
3900 */
3901
3902static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
3903{
3904 /* send SCSI cdb */
3905 DPRINTK("send cdb\n");
db024d53 3906 WARN_ON(qc->dev->cdb_len < 12);
c71c1857 3907
a6b2c5d4 3908 ap->ops->data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
c71c1857
AL		 3909 ata_altstatus(ap); /* flush */
3910
3911 switch (qc->tf.protocol) {
3912 case ATA_PROT_ATAPI:
3913 ap->hsm_task_state = HSM_ST;
3914 break;
3915 case ATA_PROT_ATAPI_NODATA:
3916 ap->hsm_task_state = HSM_ST_LAST;
3917 break;
3918 case ATA_PROT_ATAPI_DMA:
3919 ap->hsm_task_state = HSM_ST_LAST;
3920 /* initiate bmdma */
3921 ap->ops->bmdma_start(qc);
3922 break;
3923 }
1da177e4
LT		 3924}
3925
6ae4cfb5
AL		 3926/**
3927 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3928 * @qc: Command on going
3929 * @bytes: number of bytes
3930 *
3931 * Transfer Transfer data from/to the ATAPI device.
3932 *
3933 * LOCKING:
3934 * Inherited from caller.
3935 *
3936 */
3937
1da177e4
LT		 3938static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3939{
3940 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3941 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3942 struct ata_port *ap = qc->ap;
3943 struct page *page;
3944 unsigned char *buf;
3945 unsigned int offset, count;
3946
563a6e1f 3947 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3948 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3949
3950next_sg:
563a6e1f 3951 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3952 /*
563a6e1f
AL		 3953 * The end of qc->sg is reached and the device expects
3954 * more data to transfer. In order not to overrun qc->sg
3955 * and fulfill length specified in the byte count register,
3956 * - for read case, discard trailing data from the device
3957 * - for write case, padding zero data to the device
3958 */
3959 u16 pad_buf[1] = { 0 };
3960 unsigned int words = bytes >> 1;
3961 unsigned int i;
3962
3963 if (words) /* warning if bytes > 1 */
f15a1daf
TH		 3964 ata_dev_printk(qc->dev, KERN_WARNING,
3965 "%u bytes trailing data\n", bytes);
563a6e1f
AL		 3966
3967 for (i = 0; i < words; i++)
a6b2c5d4 3968 ap->ops->data_xfer(qc->dev, (unsigned char*)pad_buf, 2, do_write);
563a6e1f 3969
14be71f4 3970 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3971 return;
3972 }
3973
cedc9a47 3974 sg = &qc->__sg[qc->cursg];
1da177e4 3975
1da177e4
LT		 3976 page = sg->page;
3977 offset = sg->offset + qc->cursg_ofs;
3978
3979 /* get the current page and offset */
3980 page = nth_page(page, (offset >> PAGE_SHIFT));
3981 offset %= PAGE_SIZE;
3982
6952df03 3983 /* don't overrun current sg */
32529e01 3984 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3985
3986 /* don't cross page boundaries */
3987 count = min(count, (unsigned int)PAGE_SIZE - offset);
3988
7282aa4b
AL		 3989 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3990
91b8b313
AL		 3991 if (PageHighMem(page)) {
3992 unsigned long flags;
3993
a6b2c5d4 3994 /* FIXME: use bounce buffer */
91b8b313
AL		 3995 local_irq_save(flags);
3996 buf = kmap_atomic(page, KM_IRQ0);
083958d3 3997
91b8b313 3998 /* do the actual data transfer */
a6b2c5d4 3999 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
7282aa4b 4000
91b8b313
AL		 4001 kunmap_atomic(buf, KM_IRQ0);
4002 local_irq_restore(flags);
4003 } else {
4004 buf = page_address(page);
a6b2c5d4 4005 ap->ops->data_xfer(qc->dev, buf + offset, count, do_write);
91b8b313 4006 }
1da177e4
LT		 4007
4008 bytes -= count;
4009 qc->curbytes += count;
4010 qc->cursg_ofs += count;
4011
32529e01 4012 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 4013 qc->cursg++;
4014 qc->cursg_ofs = 0;
4015 }
4016
563a6e1f 4017 if (bytes)
1da177e4 4018 goto next_sg;
1da177e4
LT		 4019}
4020
6ae4cfb5
AL		 4021/**
4022 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
4023 * @qc: Command on going
4024 *
4025 * Transfer Transfer data from/to the ATAPI device.
4026 *
4027 * LOCKING:
4028 * Inherited from caller.
6ae4cfb5
AL		 4029 */
4030
1da177e4
LT		 4031static void atapi_pio_bytes(struct ata_queued_cmd *qc)
4032{
4033 struct ata_port *ap = qc->ap;
4034 struct ata_device *dev = qc->dev;
4035 unsigned int ireason, bc_lo, bc_hi, bytes;
4036 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
4037
eec4c3f3
AL		 4038 /* Abuse qc->result_tf for temp storage of intermediate TF
4039 * here to save some kernel stack usage.
4040 * For normal completion, qc->result_tf is not relevant. For
4041 * error, qc->result_tf is later overwritten by ata_qc_complete().
4042 * So, the correctness of qc->result_tf is not affected.
4043 */
4044 ap->ops->tf_read(ap, &qc->result_tf);
4045 ireason = qc->result_tf.nsect;
4046 bc_lo = qc->result_tf.lbam;
4047 bc_hi = qc->result_tf.lbah;
1da177e4
LT		 4048 bytes = (bc_hi << 8) | bc_lo;
4049
4050 /* shall be cleared to zero, indicating xfer of data */
4051 if (ireason & (1 << 0))
4052 goto err_out;
4053
4054 /* make sure transfer direction matches expected */
4055 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
4056 if (do_write != i_write)
4057 goto err_out;
4058
312f7da2
AL		 4059 VPRINTK("ata%u: xfering %d bytes\n", ap->id, bytes);
4060
1da177e4
LT		 4061 __atapi_pio_bytes(qc, bytes);
4062
4063 return;
4064
4065err_out:
f15a1daf 4066 ata_dev_printk(dev, KERN_INFO, "ATAPI check failed\n");
11a56d24 4067 qc->err_mask |= AC_ERR_HSM;
14be71f4 4068 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 4069}
4070
4071/**
c234fb00
AL		 4072 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
4073 * @ap: the target ata_port
4074 * @qc: qc on going
1da177e4 4075 *
c234fb00
AL		 4076 * RETURNS:
4077 * 1 if ok in workqueue, 0 otherwise.
1da177e4 4078 */
c234fb00
AL		 4079
4080static inline int ata_hsm_ok_in_wq(struct ata_port *ap, struct ata_queued_cmd *qc)
1da177e4 4081{
c234fb00
AL		 4082 if (qc->tf.flags & ATA_TFLAG_POLLING)
4083 return 1;
1da177e4 4084
c234fb00
AL		 4085 if (ap->hsm_task_state == HSM_ST_FIRST) {
4086 if (qc->tf.protocol == ATA_PROT_PIO &&
4087 (qc->tf.flags & ATA_TFLAG_WRITE))
4088 return 1;
1da177e4 4089
c234fb00
AL		 4090 if (is_atapi_taskfile(&qc->tf) &&
4091 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
4092 return 1;
fe79e683
AL		 4093 }
4094
c234fb00
AL		 4095 return 0;
4096}
1da177e4 4097
c17ea20d
TH		 4098/**
4099 * ata_hsm_qc_complete - finish a qc running on standard HSM
4100 * @qc: Command to complete
4101 * @in_wq: 1 if called from workqueue, 0 otherwise
4102 *
4103 * Finish @qc which is running on standard HSM.
4104 *
4105 * LOCKING:
cca3974e 4106 * If @in_wq is zero, spin_lock_irqsave(host lock).
c17ea20d
TH		 4107 * Otherwise, none on entry and grabs host lock.
4108 */
4109static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
4110{
4111 struct ata_port *ap = qc->ap;
4112 unsigned long flags;
4113
4114 if (ap->ops->error_handler) {
4115 if (in_wq) {
ba6a1308 4116 spin_lock_irqsave(ap->lock, flags);
c17ea20d 4117
cca3974e
JG		 4118 /* EH might have kicked in while host lock is
4119 * released.
c17ea20d
TH		 4120 */
4121 qc = ata_qc_from_tag(ap, qc->tag);
4122 if (qc) {
4123 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
4124 ata_irq_on(ap);
4125 ata_qc_complete(qc);
4126 } else
4127 ata_port_freeze(ap);
4128 }
4129
ba6a1308 4130 spin_unlock_irqrestore(ap->lock, flags);
c17ea20d
TH		 4131 } else {
4132 if (likely(!(qc->err_mask & AC_ERR_HSM)))
4133 ata_qc_complete(qc);
4134 else
4135 ata_port_freeze(ap);
4136 }
4137 } else {
4138 if (in_wq) {
ba6a1308 4139 spin_lock_irqsave(ap->lock, flags);
c17ea20d
TH		 4140 ata_irq_on(ap);
4141 ata_qc_complete(qc);
ba6a1308 4142 spin_unlock_irqrestore(ap->lock, flags);
c17ea20d
TH		 4143 } else
4144 ata_qc_complete(qc);
4145 }
1da177e4 4146
c81e29b4 4147 ata_altstatus(ap); /* flush */
c17ea20d
TH		 4148}
4149
bb5cb290
AL		 4150/**
4151 * ata_hsm_move - move the HSM to the next state.
4152 * @ap: the target ata_port
4153 * @qc: qc on going
4154 * @status: current device status
4155 * @in_wq: 1 if called from workqueue, 0 otherwise
4156 *
4157 * RETURNS:
4158 * 1 when poll next status needed, 0 otherwise.
4159 */
9a1004d0
TH		 4160int ata_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
4161 u8 status, int in_wq)
e2cec771 4162{
bb5cb290
AL		 4163 unsigned long flags = 0;
4164 int poll_next;
4165
6912ccd5
AL		 4166 WARN_ON((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
4167
bb5cb290
AL		 4168 /* Make sure ata_qc_issue_prot() does not throw things
4169 * like DMA polling into the workqueue. Notice that
4170 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
4171 */
c234fb00 4172 WARN_ON(in_wq != ata_hsm_ok_in_wq(ap, qc));
bb5cb290 4173
e2cec771 4174fsm_start:
999bb6f4
AL		 4175 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
4176 ap->id, qc->tf.protocol, ap->hsm_task_state, status);
4177
e2cec771
AL		 4178 switch (ap->hsm_task_state) {
4179 case HSM_ST_FIRST:
bb5cb290
AL		 4180 /* Send first data block or PACKET CDB */
4181
4182 /* If polling, we will stay in the work queue after
4183 * sending the data. Otherwise, interrupt handler
4184 * takes over after sending the data.
4185 */
4186 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
4187
e2cec771 4188 /* check device status */
3655d1d3
AL		 4189 if (unlikely((status & ATA_DRQ) == 0)) {
4190 /* handle BSY=0, DRQ=0 as error */
4191 if (likely(status & (ATA_ERR | ATA_DF)))
4192 /* device stops HSM for abort/error */
4193 qc->err_mask |= AC_ERR_DEV;
4194 else
4195 /* HSM violation. Let EH handle this */
4196 qc->err_mask |= AC_ERR_HSM;
4197
14be71f4 4198 ap->hsm_task_state = HSM_ST_ERR;
e2cec771 4199 goto fsm_start;
1da177e4
LT		 4200 }
4201
71601958
AL		 4202 /* Device should not ask for data transfer (DRQ=1)
4203 * when it finds something wrong.
eee6c32f
AL		 4204 * We ignore DRQ here and stop the HSM by
4205 * changing hsm_task_state to HSM_ST_ERR and
4206 * let the EH abort the command or reset the device.
71601958
AL		 4207 */
4208 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4209 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4210 ap->id, status);
3655d1d3 4211 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4212 ap->hsm_task_state = HSM_ST_ERR;
4213 goto fsm_start;
71601958 4214 }
1da177e4 4215
bb5cb290
AL		 4216 /* Send the CDB (atapi) or the first data block (ata pio out).
4217 * During the state transition, interrupt handler shouldn't
4218 * be invoked before the data transfer is complete and
4219 * hsm_task_state is changed. Hence, the following locking.
4220 */
4221 if (in_wq)
ba6a1308 4222 spin_lock_irqsave(ap->lock, flags);
1da177e4 4223
bb5cb290
AL		 4224 if (qc->tf.protocol == ATA_PROT_PIO) {
4225 /* PIO data out protocol.
4226 * send first data block.
4227 */
0565c26d 4228
bb5cb290
AL		 4229 /* ata_pio_sectors() might change the state
4230 * to HSM_ST_LAST. so, the state is changed here
4231 * before ata_pio_sectors().
4232 */
4233 ap->hsm_task_state = HSM_ST;
4234 ata_pio_sectors(qc);
4235 ata_altstatus(ap); /* flush */
4236 } else
4237 /* send CDB */
4238 atapi_send_cdb(ap, qc);
4239
4240 if (in_wq)
ba6a1308 4241 spin_unlock_irqrestore(ap->lock, flags);
bb5cb290
AL		 4242
4243 /* if polling, ata_pio_task() handles the rest.
4244 * otherwise, interrupt handler takes over from here.
4245 */
e2cec771 4246 break;
1c848984 4247
e2cec771
AL		 4248 case HSM_ST:
4249 /* complete command or read/write the data register */
4250 if (qc->tf.protocol == ATA_PROT_ATAPI) {
4251 /* ATAPI PIO protocol */
4252 if ((status & ATA_DRQ) == 0) {
3655d1d3
AL		 4253 /* No more data to transfer or device error.
4254 * Device error will be tagged in HSM_ST_LAST.
4255 */
e2cec771
AL		 4256 ap->hsm_task_state = HSM_ST_LAST;
4257 goto fsm_start;
4258 }
1da177e4 4259
71601958
AL		 4260 /* Device should not ask for data transfer (DRQ=1)
4261 * when it finds something wrong.
eee6c32f
AL		 4262 * We ignore DRQ here and stop the HSM by
4263 * changing hsm_task_state to HSM_ST_ERR and
4264 * let the EH abort the command or reset the device.
71601958
AL		 4265 */
4266 if (unlikely(status & (ATA_ERR | ATA_DF))) {
4267 printk(KERN_WARNING "ata%d: DRQ=1 with device error, dev_stat 0x%X\n",
4268 ap->id, status);
3655d1d3 4269 qc->err_mask |= AC_ERR_HSM;
eee6c32f
AL		 4270 ap->hsm_task_state = HSM_ST_ERR;
4271 goto fsm_start;
71601958 4272 }
1da177e4 4273
e2cec771 4274 atapi_pio_bytes(qc);
7fb6ec28 4275
e2cec771
AL		 4276 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
4277 /* bad ireason reported by device */
4278 goto fsm_start;
1da177e4 4279
e2cec771
AL		 4280 } else {
4281 /* ATA PIO protocol */
4282 if (unlikely((status & ATA_DRQ) == 0)) {
4283 /* handle BSY=0, DRQ=0 as error */
3655d1d3
AL		 4284 if (likely(status & (ATA_ERR | ATA_DF)))
4285 /* device stops HSM for abort/error */
4286 qc->err_mask |= AC_ERR_DEV;
4287 else
4288 /* HSM violation. Let EH handle this */
4289 qc->err_mask |= AC_ERR_HSM;
4290
e2cec771
AL		 4291 ap->hsm_task_state = HSM_ST_ERR;
4292 goto fsm_start;
4293 }
1da177e4 4294
eee6c32f
AL		 4295 /* For PIO reads, some devices may ask for
4296 * data transfer (DRQ=1) alone with ERR=1.
4297 * We respect DRQ here and transfer one
4298 * block of junk data before changing the
4299 * hsm_task_state to HSM_ST_ERR.
4300 *
4301 * For PIO writes, ERR=1 DRQ=1 doesn't make
4302 * sense since the data block has been
4303 * transferred to the device.
71601958
AL		 4304 */
4305 if (unlikely(status & (ATA_ERR | ATA_DF))) {
71601958
AL		 4306 /* data might be corrputed */
4307 qc->err_mask |= AC_ERR_DEV;
eee6c32f
AL		 4308
4309 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
4310 ata_pio_sectors(qc);
4311 ata_altstatus(ap);
4312 status = ata_wait_idle(ap);
4313 }
4314
3655d1d3
AL		 4315 if (status & (ATA_BUSY | ATA_DRQ))
4316 qc->err_mask |= AC_ERR_HSM;
4317
eee6c32f
AL		 4318 /* ata_pio_sectors() might change the
4319 * state to HSM_ST_LAST. so, the state
4320 * is changed after ata_pio_sectors().
4321 */
4322 ap->hsm_task_state = HSM_ST_ERR;
4323 goto fsm_start;
71601958
AL		 4324 }
4325
e2cec771
AL		 4326 ata_pio_sectors(qc);
4327
4328 if (ap->hsm_task_state == HSM_ST_LAST &&
4329 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
4330 /* all data read */
4331 ata_altstatus(ap);
52a32205 4332 status = ata_wait_idle(ap);
e2cec771
AL		 4333 goto fsm_start;
4334 }
4335 }
4336
4337 ata_altstatus(ap); /* flush */
bb5cb290 4338 poll_next = 1;
1da177e4
LT		 4339 break;
4340
14be71f4 4341 case HSM_ST_LAST:
6912ccd5
AL		 4342 if (unlikely(!ata_ok(status))) {
4343 qc->err_mask |= __ac_err_mask(status);
e2cec771
AL		 4344 ap->hsm_task_state = HSM_ST_ERR;
4345 goto fsm_start;
4346 }
4347
4348 /* no more data to transfer */
4332a771
AL		 4349 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
4350 ap->id, qc->dev->devno, status);
e2cec771 4351
6912ccd5
AL		 4352 WARN_ON(qc->err_mask);
4353
e2cec771 4354 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 4355
e2cec771 4356 /* complete taskfile transaction */
c17ea20d 4357 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4358
4359 poll_next = 0;
1da177e4
LT		 4360 break;
4361
14be71f4 4362 case HSM_ST_ERR:
e2cec771
AL		 4363 /* make sure qc->err_mask is available to
4364 * know what's wrong and recover
4365 */
4366 WARN_ON(qc->err_mask == 0);
4367
4368 ap->hsm_task_state = HSM_ST_IDLE;
bb5cb290 4369
999bb6f4 4370 /* complete taskfile transaction */
c17ea20d 4371 ata_hsm_qc_complete(qc, in_wq);
bb5cb290
AL		 4372
4373 poll_next = 0;
e2cec771
AL		 4374 break;
4375 default:
bb5cb290 4376 poll_next = 0;
6912ccd5 4377 BUG();
1da177e4
LT		 4378 }
4379
bb5cb290 4380 return poll_next;
1da177e4
LT		 4381}
4382
1da177e4 4383static void ata_pio_task(void *_data)
8061f5f0 4384{
c91af2c8
TH		 4385 struct ata_queued_cmd *qc = _data;
4386 struct ata_port *ap = qc->ap;
8061f5f0 4387 u8 status;
a1af3734 4388 int poll_next;
8061f5f0 4389
7fb6ec28 4390fsm_start:
a1af3734 4391 WARN_ON(ap->hsm_task_state == HSM_ST_IDLE);
8061f5f0 4392
a1af3734
AL		 4393 /*
4394 * This is purely heuristic. This is a fast path.
4395 * Sometimes when we enter, BSY will be cleared in
4396 * a chk-status or two. If not, the drive is probably seeking
4397 * or something. Snooze for a couple msecs, then
4398 * chk-status again. If still busy, queue delayed work.
4399 */
4400 status = ata_busy_wait(ap, ATA_BUSY, 5);
4401 if (status & ATA_BUSY) {
4402 msleep(2);
4403 status = ata_busy_wait(ap, ATA_BUSY, 10);
4404 if (status & ATA_BUSY) {
31ce6dae 4405 ata_port_queue_task(ap, ata_pio_task, qc, ATA_SHORT_PAUSE);
a1af3734
AL		 4406 return;
4407 }
8061f5f0
TH		 4408 }
4409
a1af3734
AL		 4410 /* move the HSM */
4411 poll_next = ata_hsm_move(ap, qc, status, 1);
8061f5f0 4412
a1af3734
AL		 4413 /* another command or interrupt handler
4414 * may be running at this point.
4415 */
4416 if (poll_next)
7fb6ec28 4417 goto fsm_start;
8061f5f0
TH		 4418}
4419
1da177e4
LT		 4420/**
4421 * ata_qc_new - Request an available ATA command, for queueing
4422 * @ap: Port associated with device @dev
4423 * @dev: Device from whom we request an available command structure
4424 *
4425 * LOCKING:
0cba632b 4426 * None.
1da177e4
LT		 4427 */
4428
4429static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
4430{
4431 struct ata_queued_cmd *qc = NULL;
4432 unsigned int i;
4433
e3180499 4434 /* no command while frozen */
b51e9e5d 4435 if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
e3180499
TH		 4436 return NULL;
4437
2ab7db1f
TH		 4438 /* the last tag is reserved for internal command. */
4439 for (i = 0; i < ATA_MAX_QUEUE - 1; i++)
6cec4a39 4440 if (!test_and_set_bit(i, &ap->qc_allocated)) {
f69499f4 4441 qc = __ata_qc_from_tag(ap, i);
1da177e4
LT		 4442 break;
4443 }
4444
4445 if (qc)
4446 qc->tag = i;
4447
4448 return qc;
4449}
4450
4451/**
4452 * ata_qc_new_init - Request an available ATA command, and initialize it
1da177e4
LT		 4453 * @dev: Device from whom we request an available command structure
4454 *
4455 * LOCKING:
0cba632b 4456 * None.
1da177e4
LT		 4457 */
4458
3373efd8 4459struct ata_queued_cmd *ata_qc_new_init(struct ata_device *dev)
1da177e4 4460{
3373efd8 4461 struct ata_port *ap = dev->ap;
1da177e4
LT		 4462 struct ata_queued_cmd *qc;
4463
4464 qc = ata_qc_new(ap);
4465 if (qc) {
1da177e4
LT		 4466 qc->scsicmd = NULL;
4467 qc->ap = ap;
4468 qc->dev = dev;
1da177e4 4469
2c13b7ce 4470 ata_qc_reinit(qc);
1da177e4
LT		 4471 }
4472
4473 return qc;
4474}
4475
1da177e4
LT		 4476/**
4477 * ata_qc_free - free unused ata_queued_cmd
4478 * @qc: Command to complete
4479 *
4480 * Designed to free unused ata_queued_cmd object
4481 * in case something prevents using it.
4482 *
4483 * LOCKING:
cca3974e 4484 * spin_lock_irqsave(host lock)
1da177e4
LT		 4485 */
4486void ata_qc_free(struct ata_queued_cmd *qc)
4487{
4ba946e9
TH		 4488 struct ata_port *ap = qc->ap;
4489 unsigned int tag;
4490
a4631474 4491 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 4492
4ba946e9
TH		 4493 qc->flags = 0;
4494 tag = qc->tag;
4495 if (likely(ata_tag_valid(tag))) {
4ba946e9 4496 qc->tag = ATA_TAG_POISON;
6cec4a39 4497 clear_bit(tag, &ap->qc_allocated);
4ba946e9 4498 }
1da177e4
LT		 4499}
4500
76014427 4501void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 4502{
dedaf2b0
TH		 4503 struct ata_port *ap = qc->ap;
4504
a4631474
TH		 4505 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
4506 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 4507
4508 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
4509 ata_sg_clean(qc);
4510
7401abf2 4511 /* command should be marked inactive atomically with qc completion */
dedaf2b0
TH		 4512 if (qc->tf.protocol == ATA_PROT_NCQ)
4513 ap->sactive &= ~(1 << qc->tag);
4514 else
4515 ap->active_tag = ATA_TAG_POISON;
7401abf2 4516
3f3791d3
AL		 4517 /* atapi: mark qc as inactive to prevent the interrupt handler
4518 * from completing the command twice later, before the error handler
4519 * is called. (when rc != 0 and atapi request sense is needed)
4520 */
4521 qc->flags &= ~ATA_QCFLAG_ACTIVE;
dedaf2b0 4522 ap->qc_active &= ~(1 << qc->tag);
3f3791d3 4523
1da177e4 4524 /* call completion callback */
77853bf2 4525 qc->complete_fn(qc);
1da177e4
LT		 4526}
4527
f686bcb8
TH		 4528/**
4529 * ata_qc_complete - Complete an active ATA command
4530 * @qc: Command to complete
4531 * @err_mask: ATA Status register contents
4532 *
4533 * Indicate to the mid and upper layers that an ATA
4534 * command has completed, with either an ok or not-ok status.
4535 *
4536 * LOCKING:
cca3974e 4537 * spin_lock_irqsave(host lock)
f686bcb8
TH		 4538 */
4539void ata_qc_complete(struct ata_queued_cmd *qc)
4540{
4541 struct ata_port *ap = qc->ap;
4542
4543 /* XXX: New EH and old EH use different mechanisms to
4544 * synchronize EH with regular execution path.
4545 *
4546 * In new EH, a failed qc is marked with ATA_QCFLAG_FAILED.
4547 * Normal execution path is responsible for not accessing a
4548 * failed qc. libata core enforces the rule by returning NULL
4549 * from ata_qc_from_tag() for failed qcs.
4550 *
4551 * Old EH depends on ata_qc_complete() nullifying completion
4552 * requests if ATA_QCFLAG_EH_SCHEDULED is set. Old EH does
4553 * not synchronize with interrupt handler. Only PIO task is
4554 * taken care of.
4555 */
4556 if (ap->ops->error_handler) {
b51e9e5d 4557 WARN_ON(ap->pflags & ATA_PFLAG_FROZEN);
f686bcb8
TH		 4558
4559 if (unlikely(qc->err_mask))
4560 qc->flags |= ATA_QCFLAG_FAILED;
4561
4562 if (unlikely(qc->flags & ATA_QCFLAG_FAILED)) {
4563 if (!ata_tag_internal(qc->tag)) {
4564 /* always fill result TF for failed qc */
4565 ap->ops->tf_read(ap, &qc->result_tf);
4566 ata_qc_schedule_eh(qc);
4567 return;
4568 }
4569 }
4570
4571 /* read result TF if requested */
4572 if (qc->flags & ATA_QCFLAG_RESULT_TF)
4573 ap->ops->tf_read(ap, &qc->result_tf);
4574
4575 __ata_qc_complete(qc);
4576 } else {
4577 if (qc->flags & ATA_QCFLAG_EH_SCHEDULED)
4578 return;
4579
4580 /* read result TF if failed or requested */
4581 if (qc->err_mask || qc->flags & ATA_QCFLAG_RESULT_TF)
4582 ap->ops->tf_read(ap, &qc->result_tf);
4583
4584 __ata_qc_complete(qc);
4585 }
4586}
4587
dedaf2b0
TH		 4588/**
4589 * ata_qc_complete_multiple - Complete multiple qcs successfully
4590 * @ap: port in question
4591 * @qc_active: new qc_active mask
4592 * @finish_qc: LLDD callback invoked before completing a qc
4593 *
4594 * Complete in-flight commands. This functions is meant to be
4595 * called from low-level driver's interrupt routine to complete
4596 * requests normally. ap->qc_active and @qc_active is compared
4597 * and commands are completed accordingly.
4598 *
4599 * LOCKING:
cca3974e 4600 * spin_lock_irqsave(host lock)
dedaf2b0
TH		 4601 *
4602 * RETURNS:
4603 * Number of completed commands on success, -errno otherwise.
4604 */
4605int ata_qc_complete_multiple(struct ata_port *ap, u32 qc_active,
4606 void (*finish_qc)(struct ata_queued_cmd *))
4607{
4608 int nr_done = 0;
4609 u32 done_mask;
4610 int i;
4611
4612 done_mask = ap->qc_active ^ qc_active;
4613
4614 if (unlikely(done_mask & qc_active)) {
4615 ata_port_printk(ap, KERN_ERR, "illegal qc_active transition "
4616 "(%08x->%08x)\n", ap->qc_active, qc_active);
4617 return -EINVAL;
4618 }
4619
4620 for (i = 0; i < ATA_MAX_QUEUE; i++) {
4621 struct ata_queued_cmd *qc;
4622
4623 if (!(done_mask & (1 << i)))
4624 continue;
4625
4626 if ((qc = ata_qc_from_tag(ap, i))) {
4627 if (finish_qc)
4628 finish_qc(qc);
4629 ata_qc_complete(qc);
4630 nr_done++;
4631 }
4632 }
4633
4634 return nr_done;
4635}
4636
1da177e4
LT		 4637static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
4638{
4639 struct ata_port *ap = qc->ap;
4640
4641 switch (qc->tf.protocol) {
3dc1d881 4642 case ATA_PROT_NCQ:
1da177e4
LT		 4643 case ATA_PROT_DMA:
4644 case ATA_PROT_ATAPI_DMA:
4645 return 1;
4646
4647 case ATA_PROT_ATAPI:
4648 case ATA_PROT_PIO:
1da177e4
LT		 4649 if (ap->flags & ATA_FLAG_PIO_DMA)
4650 return 1;
4651
4652 /* fall through */
4653
4654 default:
4655 return 0;
4656 }
4657
4658 /* never reached */
4659}
4660
4661/**
4662 * ata_qc_issue - issue taskfile to device
4663 * @qc: command to issue to device
4664 *
4665 * Prepare an ATA command to submission to device.
4666 * This includes mapping the data into a DMA-able
4667 * area, filling in the S/G table, and finally
4668 * writing the taskfile to hardware, starting the command.
4669 *
4670 * LOCKING:
cca3974e 4671 * spin_lock_irqsave(host lock)
1da177e4 4672 */
8e0e694a 4673void ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 4674{
4675 struct ata_port *ap = qc->ap;
4676
dedaf2b0
TH		 4677 /* Make sure only one non-NCQ command is outstanding. The
4678 * check is skipped for old EH because it reuses active qc to
4679 * request ATAPI sense.
4680 */
4681 WARN_ON(ap->ops->error_handler && ata_tag_valid(ap->active_tag));
4682
4683 if (qc->tf.protocol == ATA_PROT_NCQ) {
4684 WARN_ON(ap->sactive & (1 << qc->tag));
4685 ap->sactive |= 1 << qc->tag;
4686 } else {
4687 WARN_ON(ap->sactive);
4688 ap->active_tag = qc->tag;
4689 }
4690
e4a70e76 4691 qc->flags |= ATA_QCFLAG_ACTIVE;
dedaf2b0 4692 ap->qc_active |= 1 << qc->tag;
e4a70e76 4693
1da177e4
LT		 4694 if (ata_should_dma_map(qc)) {
4695 if (qc->flags & ATA_QCFLAG_SG) {
4696 if (ata_sg_setup(qc))
8e436af9 4697 goto sg_err;
1da177e4
LT		 4698 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
4699 if (ata_sg_setup_one(qc))
8e436af9 4700 goto sg_err;
1da177e4
LT		 4701 }
4702 } else {
4703 qc->flags &= ~ATA_QCFLAG_DMAMAP;
4704 }
4705
4706 ap->ops->qc_prep(qc);
4707
8e0e694a
TH		 4708 qc->err_mask |= ap->ops->qc_issue(qc);
4709 if (unlikely(qc->err_mask))
4710 goto err;
4711 return;
1da177e4 4712
8e436af9
TH		 4713sg_err:
4714 qc->flags &= ~ATA_QCFLAG_DMAMAP;
8e0e694a
TH		 4715 qc->err_mask |= AC_ERR_SYSTEM;
4716err:
4717 ata_qc_complete(qc);
1da177e4
LT		 4718}
4719
4720/**
4721 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
4722 * @qc: command to issue to device
4723 *
4724 * Using various libata functions and hooks, this function
4725 * starts an ATA command. ATA commands are grouped into
4726 * classes called "protocols", and issuing each type of protocol
4727 * is slightly different.
4728 *
0baab86b
EF		 4729 * May be used as the qc_issue() entry in ata_port_operations.
4730 *
1da177e4 4731 * LOCKING:
cca3974e 4732 * spin_lock_irqsave(host lock)
1da177e4
LT		 4733 *
4734 * RETURNS:
9a3d9eb0 4735 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 4736 */
4737
9a3d9eb0 4738unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 4739{
4740 struct ata_port *ap = qc->ap;
4741
e50362ec
AL		 4742 /* Use polling pio if the LLD doesn't handle
4743 * interrupt driven pio and atapi CDB interrupt.
4744 */
4745 if (ap->flags & ATA_FLAG_PIO_POLLING) {
4746 switch (qc->tf.protocol) {
4747 case ATA_PROT_PIO:
4748 case ATA_PROT_ATAPI:
4749 case ATA_PROT_ATAPI_NODATA:
4750 qc->tf.flags |= ATA_TFLAG_POLLING;
4751 break;
4752 case ATA_PROT_ATAPI_DMA:
4753 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
3a778275 4754 /* see ata_dma_blacklisted() */
e50362ec
AL		 4755 BUG();
4756 break;
4757 default:
4758 break;
4759 }
4760 }
4761
312f7da2 4762 /* select the device */
1da177e4
LT		 4763 ata_dev_select(ap, qc->dev->devno, 1, 0);
4764
312f7da2 4765 /* start the command */
1da177e4
LT		 4766 switch (qc->tf.protocol) {
4767 case ATA_PROT_NODATA:
312f7da2
AL		 4768 if (qc->tf.flags & ATA_TFLAG_POLLING)
4769 ata_qc_set_polling(qc);
4770
e5338254 4771 ata_tf_to_host(ap, &qc->tf);
312f7da2
AL		 4772 ap->hsm_task_state = HSM_ST_LAST;
4773
4774 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4775 ata_port_queue_task(ap, ata_pio_task, qc, 0);
312f7da2 4776
1da177e4
LT		 4777 break;
4778
4779 case ATA_PROT_DMA:
587005de 4780 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4781
1da177e4
LT		 4782 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4783 ap->ops->bmdma_setup(qc); /* set up bmdma */
4784 ap->ops->bmdma_start(qc); /* initiate bmdma */
312f7da2 4785 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 4786 break;
4787
312f7da2
AL		 4788 case ATA_PROT_PIO:
4789 if (qc->tf.flags & ATA_TFLAG_POLLING)
4790 ata_qc_set_polling(qc);
1da177e4 4791
e5338254 4792 ata_tf_to_host(ap, &qc->tf);
312f7da2 4793
54f00389
AL		 4794 if (qc->tf.flags & ATA_TFLAG_WRITE) {
4795 /* PIO data out protocol */
4796 ap->hsm_task_state = HSM_ST_FIRST;
31ce6dae 4797 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4798
4799 /* always send first data block using
e27486db 4800 * the ata_pio_task() codepath.
54f00389 4801 */
312f7da2 4802 } else {
54f00389
AL		 4803 /* PIO data in protocol */
4804 ap->hsm_task_state = HSM_ST;
4805
4806 if (qc->tf.flags & ATA_TFLAG_POLLING)
31ce6dae 4807 ata_port_queue_task(ap, ata_pio_task, qc, 0);
54f00389
AL		 4808
4809 /* if polling, ata_pio_task() handles the rest.
4810 * otherwise, interrupt handler takes over from here.
4811 */
312f7da2
AL		 4812 }
4813
1da177e4
LT		 4814 break;
4815
1da177e4 4816 case ATA_PROT_ATAPI:
1da177e4 4817 case ATA_PROT_ATAPI_NODATA:
312f7da2
AL		 4818 if (qc->tf.flags & ATA_TFLAG_POLLING)
4819 ata_qc_set_polling(qc);
4820
e5338254 4821 ata_tf_to_host(ap, &qc->tf);
f6ef65e6 4822
312f7da2
AL		 4823 ap->hsm_task_state = HSM_ST_FIRST;
4824
4825 /* send cdb by polling if no cdb interrupt */
4826 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
4827 (qc->tf.flags & ATA_TFLAG_POLLING))
31ce6dae 4828 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4829 break;
4830
4831 case ATA_PROT_ATAPI_DMA:
587005de 4832 WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
312f7da2 4833
1da177e4
LT		 4834 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4835 ap->ops->bmdma_setup(qc); /* set up bmdma */
312f7da2
AL		 4836 ap->hsm_task_state = HSM_ST_FIRST;
4837
4838 /* send cdb by polling if no cdb interrupt */
4839 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
31ce6dae 4840 ata_port_queue_task(ap, ata_pio_task, qc, 0);
1da177e4
LT		 4841 break;
4842
4843 default:
4844 WARN_ON(1);
9a3d9eb0 4845 return AC_ERR_SYSTEM;
1da177e4
LT		 4846 }
4847
4848 return 0;
4849}
4850
1da177e4
LT		 4851/**
4852 * ata_host_intr - Handle host interrupt for given (port, task)
4853 * @ap: Port on which interrupt arrived (possibly...)
4854 * @qc: Taskfile currently active in engine
4855 *
4856 * Handle host interrupt for given queued command. Currently,
4857 * only DMA interrupts are handled. All other commands are
4858 * handled via polling with interrupts disabled (nIEN bit).
4859 *
4860 * LOCKING:
cca3974e 4861 * spin_lock_irqsave(host lock)
1da177e4
LT		 4862 *
4863 * RETURNS:
4864 * One if interrupt was handled, zero if not (shared irq).
4865 */
4866
4867inline unsigned int ata_host_intr (struct ata_port *ap,
4868 struct ata_queued_cmd *qc)
4869{
312f7da2 4870 u8 status, host_stat = 0;
1da177e4 4871
312f7da2
AL		 4872 VPRINTK("ata%u: protocol %d task_state %d\n",
4873 ap->id, qc->tf.protocol, ap->hsm_task_state);
1da177e4 4874
312f7da2
AL		 4875 /* Check whether we are expecting interrupt in this state */
4876 switch (ap->hsm_task_state) {
4877 case HSM_ST_FIRST:
6912ccd5
AL		 4878 /* Some pre-ATAPI-4 devices assert INTRQ
4879 * at this state when ready to receive CDB.
4880 */
1da177e4 4881
312f7da2
AL		 4882 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
4883 * The flag was turned on only for atapi devices.
4884 * No need to check is_atapi_taskfile(&qc->tf) again.
4885 */
4886 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1da177e4 4887 goto idle_irq;
1da177e4 4888 break;
312f7da2
AL		 4889 case HSM_ST_LAST:
4890 if (qc->tf.protocol == ATA_PROT_DMA ||
4891 qc->tf.protocol == ATA_PROT_ATAPI_DMA) {
4892 /* check status of DMA engine */
4893 host_stat = ap->ops->bmdma_status(ap);
4894 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4895
4896 /* if it's not our irq... */
4897 if (!(host_stat & ATA_DMA_INTR))
4898 goto idle_irq;
4899
4900 /* before we do anything else, clear DMA-Start bit */
4901 ap->ops->bmdma_stop(qc);
a4f16610
AL		 4902
4903 if (unlikely(host_stat & ATA_DMA_ERR)) {
4904 /* error when transfering data to/from memory */
4905 qc->err_mask |= AC_ERR_HOST_BUS;
4906 ap->hsm_task_state = HSM_ST_ERR;
4907 }
312f7da2
AL		 4908 }
4909 break;
4910 case HSM_ST:
4911 break;
1da177e4
LT		 4912 default:
4913 goto idle_irq;
4914 }
4915
312f7da2
AL		 4916 /* check altstatus */
4917 status = ata_altstatus(ap);
4918 if (status & ATA_BUSY)
4919 goto idle_irq;
1da177e4 4920
312f7da2
AL		 4921 /* check main status, clearing INTRQ */
4922 status = ata_chk_status(ap);
4923 if (unlikely(status & ATA_BUSY))
4924 goto idle_irq;
1da177e4 4925
312f7da2
AL		 4926 /* ack bmdma irq events */
4927 ap->ops->irq_clear(ap);
1da177e4 4928
bb5cb290 4929 ata_hsm_move(ap, qc, status, 0);
1da177e4
LT		 4930 return 1; /* irq handled */
4931
4932idle_irq:
4933 ap->stats.idle_irq++;
4934
4935#ifdef ATA_IRQ_TRAP
4936 if ((ap->stats.idle_irq % 1000) == 0) {
1da177e4 4937 ata_irq_ack(ap, 0); /* debug trap */
f15a1daf 4938 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
23cfce89 4939 return 1;
1da177e4
LT		 4940 }
4941#endif
4942 return 0; /* irq not handled */
4943}
4944
4945/**
4946 * ata_interrupt - Default ATA host interrupt handler
0cba632b 4947 * @irq: irq line (unused)
cca3974e 4948 * @dev_instance: pointer to our ata_host information structure
1da177e4 4949 *
0cba632b
JG		 4950 * Default interrupt handler for PCI IDE devices. Calls
4951 * ata_host_intr() for each port that is not disabled.
4952 *
1da177e4 4953 * LOCKING:
cca3974e 4954 * Obtains host lock during operation.
1da177e4
LT		 4955 *
4956 * RETURNS:
0cba632b 4957 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4958 */
4959
7d12e780 4960irqreturn_t ata_interrupt (int irq, void *dev_instance)
1da177e4 4961{
cca3974e 4962 struct ata_host *host = dev_instance;
1da177e4
LT		 4963 unsigned int i;
4964 unsigned int handled = 0;
4965 unsigned long flags;
4966
4967 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
cca3974e 4968 spin_lock_irqsave(&host->lock, flags);
1da177e4 4969
cca3974e 4970 for (i = 0; i < host->n_ports; i++) {
1da177e4
LT		 4971 struct ata_port *ap;
4972
cca3974e 4973 ap = host->ports[i];
c1389503 4974 if (ap &&
029f5468 4975 !(ap->flags & ATA_FLAG_DISABLED)) {
1da177e4
LT		 4976 struct ata_queued_cmd *qc;
4977
4978 qc = ata_qc_from_tag(ap, ap->active_tag);
312f7da2 4979 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
21b1ed74 4980 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4981 handled |= ata_host_intr(ap, qc);
4982 }
4983 }
4984
cca3974e 4985 spin_unlock_irqrestore(&host->lock, flags);
1da177e4
LT		 4986
4987 return IRQ_RETVAL(handled);
4988}
4989
34bf2170
TH		 4990/**
4991 * sata_scr_valid - test whether SCRs are accessible
4992 * @ap: ATA port to test SCR accessibility for
4993 *
4994 * Test whether SCRs are accessible for @ap.
4995 *
4996 * LOCKING:
4997 * None.
4998 *
4999 * RETURNS:
5000 * 1 if SCRs are accessible, 0 otherwise.
5001 */
5002int sata_scr_valid(struct ata_port *ap)
5003{
5004 return ap->cbl == ATA_CBL_SATA && ap->ops->scr_read;
5005}
5006
5007/**
5008 * sata_scr_read - read SCR register of the specified port
5009 * @ap: ATA port to read SCR for
5010 * @reg: SCR to read
5011 * @val: Place to store read value
5012 *
5013 * Read SCR register @reg of @ap into *@val. This function is
5014 * guaranteed to succeed if the cable type of the port is SATA
5015 * and the port implements ->scr_read.
5016 *
5017 * LOCKING:
5018 * None.
5019 *
5020 * RETURNS:
5021 * 0 on success, negative errno on failure.
5022 */
5023int sata_scr_read(struct ata_port *ap, int reg, u32 *val)
5024{
5025 if (sata_scr_valid(ap)) {
5026 *val = ap->ops->scr_read(ap, reg);
5027 return 0;
5028 }
5029 return -EOPNOTSUPP;
5030}
5031
5032/**
5033 * sata_scr_write - write SCR register of the specified port
5034 * @ap: ATA port to write SCR for
5035 * @reg: SCR to write
5036 * @val: value to write
5037 *
5038 * Write @val to SCR register @reg of @ap. This function is
5039 * guaranteed to succeed if the cable type of the port is SATA
5040 * and the port implements ->scr_read.
5041 *
5042 * LOCKING:
5043 * None.
5044 *
5045 * RETURNS:
5046 * 0 on success, negative errno on failure.
5047 */
5048int sata_scr_write(struct ata_port *ap, int reg, u32 val)
5049{
5050 if (sata_scr_valid(ap)) {
5051 ap->ops->scr_write(ap, reg, val);
5052 return 0;
5053 }
5054 return -EOPNOTSUPP;
5055}
5056
5057/**
5058 * sata_scr_write_flush - write SCR register of the specified port and flush
5059 * @ap: ATA port to write SCR for
5060 * @reg: SCR to write
5061 * @val: value to write
5062 *
5063 * This function is identical to sata_scr_write() except that this
5064 * function performs flush after writing to the register.
5065 *
5066 * LOCKING:
5067 * None.
5068 *
5069 * RETURNS:
5070 * 0 on success, negative errno on failure.
5071 */
5072int sata_scr_write_flush(struct ata_port *ap, int reg, u32 val)
5073{
5074 if (sata_scr_valid(ap)) {
5075 ap->ops->scr_write(ap, reg, val);
5076 ap->ops->scr_read(ap, reg);
5077 return 0;
5078 }
5079 return -EOPNOTSUPP;
5080}
5081
5082/**
5083 * ata_port_online - test whether the given port is online
5084 * @ap: ATA port to test
5085 *
5086 * Test whether @ap is online. Note that this function returns 0
5087 * if online status of @ap cannot be obtained, so
5088 * ata_port_online(ap) != !ata_port_offline(ap).
5089 *
5090 * LOCKING:
5091 * None.
5092 *
5093 * RETURNS:
5094 * 1 if the port online status is available and online.
5095 */
5096int ata_port_online(struct ata_port *ap)
5097{
5098 u32 sstatus;
5099
5100 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) == 0x3)
5101 return 1;
5102 return 0;
5103}
5104
5105/**
5106 * ata_port_offline - test whether the given port is offline
5107 * @ap: ATA port to test
5108 *
5109 * Test whether @ap is offline. Note that this function returns
5110 * 0 if offline status of @ap cannot be obtained, so
5111 * ata_port_online(ap) != !ata_port_offline(ap).
5112 *
5113 * LOCKING:
5114 * None.
5115 *
5116 * RETURNS:
5117 * 1 if the port offline status is available and offline.
5118 */
5119int ata_port_offline(struct ata_port *ap)
5120{
5121 u32 sstatus;
5122
5123 if (!sata_scr_read(ap, SCR_STATUS, &sstatus) && (sstatus & 0xf) != 0x3)
5124 return 1;
5125 return 0;
5126}
0baab86b 5127
77b08fb5 5128int ata_flush_cache(struct ata_device *dev)
9b847548 5129{
977e6b9f 5130 unsigned int err_mask;
9b847548
JA		 5131 u8 cmd;
5132
5133 if (!ata_try_flush_cache(dev))
5134 return 0;
5135
6fc49adb 5136 if (dev->flags & ATA_DFLAG_FLUSH_EXT)
9b847548
JA		 5137 cmd = ATA_CMD_FLUSH_EXT;
5138 else
5139 cmd = ATA_CMD_FLUSH;
5140
977e6b9f
TH		 5141 err_mask = ata_do_simple_cmd(dev, cmd);
5142 if (err_mask) {
5143 ata_dev_printk(dev, KERN_ERR, "failed to flush cache\n");
5144 return -EIO;
5145 }
5146
5147 return 0;
9b847548
JA		 5148}
5149
cca3974e
JG		 5150static int ata_host_request_pm(struct ata_host *host, pm_message_t mesg,
5151 unsigned int action, unsigned int ehi_flags,
5152 int wait)
500530f6
TH		 5153{
5154 unsigned long flags;
5155 int i, rc;
5156
cca3974e
JG		 5157 for (i = 0; i < host->n_ports; i++) {
5158 struct ata_port *ap = host->ports[i];
500530f6
TH		 5159
5160 /* Previous resume operation might still be in
5161 * progress. Wait for PM_PENDING to clear.
5162 */
5163 if (ap->pflags & ATA_PFLAG_PM_PENDING) {
5164 ata_port_wait_eh(ap);
5165 WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
5166 }
5167
5168 /* request PM ops to EH */
5169 spin_lock_irqsave(ap->lock, flags);
5170
5171 ap->pm_mesg = mesg;
5172 if (wait) {
5173 rc = 0;
5174 ap->pm_result = &rc;
5175 }
5176
5177 ap->pflags |= ATA_PFLAG_PM_PENDING;
5178 ap->eh_info.action |= action;
5179 ap->eh_info.flags |= ehi_flags;
5180
5181 ata_port_schedule_eh(ap);
5182
5183 spin_unlock_irqrestore(ap->lock, flags);
5184
5185 /* wait and check result */
5186 if (wait) {
5187 ata_port_wait_eh(ap);
5188 WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
5189 if (rc)
5190 return rc;
5191 }
5192 }
5193
5194 return 0;
5195}
5196
5197/**
cca3974e
JG		 5198 * ata_host_suspend - suspend host
5199 * @host: host to suspend
500530f6
TH		 5200 * @mesg: PM message
5201 *
cca3974e 5202 * Suspend @host. Actual operation is performed by EH. This
500530f6
TH		 5203 * function requests EH to perform PM operations and waits for EH
5204 * to finish.
5205 *
5206 * LOCKING:
5207 * Kernel thread context (may sleep).
5208 *
5209 * RETURNS:
5210 * 0 on success, -errno on failure.
5211 */
cca3974e 5212int ata_host_suspend(struct ata_host *host, pm_message_t mesg)
500530f6
TH		 5213{
5214 int i, j, rc;
5215
cca3974e 5216 rc = ata_host_request_pm(host, mesg, 0, ATA_EHI_QUIET, 1);
500530f6
TH		 5217 if (rc)
5218 goto fail;
5219
5220 /* EH is quiescent now. Fail if we have any ready device.
5221 * This happens if hotplug occurs between completion of device
5222 * suspension and here.
5223 */
cca3974e
JG		 5224 for (i = 0; i < host->n_ports; i++) {
5225 struct ata_port *ap = host->ports[i];
500530f6
TH		 5226
5227 for (j = 0; j < ATA_MAX_DEVICES; j++) {
5228 struct ata_device *dev = &ap->device[j];
5229
5230 if (ata_dev_ready(dev)) {
5231 ata_port_printk(ap, KERN_WARNING,
5232 "suspend failed, device %d "
5233 "still active\n", dev->devno);
5234 rc = -EBUSY;
5235 goto fail;
5236 }
5237 }
5238 }
5239
cca3974e 5240 host->dev->power.power_state = mesg;
500530f6
TH		 5241 return 0;
5242
5243 fail:
cca3974e 5244 ata_host_resume(host);
500530f6
TH		 5245 return rc;
5246}
5247
5248/**
cca3974e
JG		 5249 * ata_host_resume - resume host
5250 * @host: host to resume
500530f6 5251 *
cca3974e 5252 * Resume @host. Actual operation is performed by EH. This
500530f6
TH		 5253 * function requests EH to perform PM operations and returns.
5254 * Note that all resume operations are performed parallely.
5255 *
5256 * LOCKING:
5257 * Kernel thread context (may sleep).
5258 */
cca3974e 5259void ata_host_resume(struct ata_host *host)
500530f6 5260{
cca3974e
JG		 5261 ata_host_request_pm(host, PMSG_ON, ATA_EH_SOFTRESET,
5262 ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET, 0);
5263 host->dev->power.power_state = PMSG_ON;
500530f6
TH		 5264}
5265
c893a3ae
RD		 5266/**
5267 * ata_port_start - Set port up for dma.
5268 * @ap: Port to initialize
5269 *
5270 * Called just after data structures for each port are
5271 * initialized. Allocates space for PRD table.
5272 *
5273 * May be used as the port_start() entry in ata_port_operations.
5274 *
5275 * LOCKING:
5276 * Inherited from caller.
5277 */
5278
1da177e4
LT		 5279int ata_port_start (struct ata_port *ap)
5280{
2f1f610b 5281 struct device *dev = ap->dev;
6037d6bb 5282 int rc;
1da177e4
LT		 5283
5284 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
5285 if (!ap->prd)
5286 return -ENOMEM;
5287
6037d6bb
JG		 5288 rc = ata_pad_alloc(ap, dev);
5289 if (rc) {
cedc9a47 5290 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5291 return rc;
cedc9a47
JG		 5292 }
5293
1da177e4
LT		 5294 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
5295
5296 return 0;
5297}
5298
0baab86b
EF		 5299
5300/**
5301 * ata_port_stop - Undo ata_port_start()
5302 * @ap: Port to shut down
5303 *
5304 * Frees the PRD table.
5305 *
5306 * May be used as the port_stop() entry in ata_port_operations.
5307 *
5308 * LOCKING:
6f0ef4fa 5309 * Inherited from caller.
0baab86b
EF		 5310 */
5311
1da177e4
LT		 5312void ata_port_stop (struct ata_port *ap)
5313{
2f1f610b 5314 struct device *dev = ap->dev;
1da177e4
LT		 5315
5316 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 5317 ata_pad_free(ap, dev);
1da177e4
LT		 5318}
5319
cca3974e 5320void ata_host_stop (struct ata_host *host)
aa8f0dc6 5321{
cca3974e
JG		 5322 if (host->mmio_base)
5323 iounmap(host->mmio_base);
aa8f0dc6
JG		 5324}
5325
3ef3b43d
TH		 5326/**
5327 * ata_dev_init - Initialize an ata_device structure
5328 * @dev: Device structure to initialize
5329 *
5330 * Initialize @dev in preparation for probing.
5331 *
5332 * LOCKING:
5333 * Inherited from caller.
5334 */
5335void ata_dev_init(struct ata_device *dev)
5336{
5337 struct ata_port *ap = dev->ap;
72fa4b74
TH		 5338 unsigned long flags;
5339
5a04bf4b
TH		 5340 /* SATA spd limit is bound to the first device */
5341 ap->sata_spd_limit = ap->hw_sata_spd_limit;
5342
72fa4b74
TH		 5343 /* High bits of dev->flags are used to record warm plug
5344 * requests which occur asynchronously. Synchronize using
cca3974e 5345 * host lock.
72fa4b74 5346 */
ba6a1308 5347 spin_lock_irqsave(ap->lock, flags);
72fa4b74 5348 dev->flags &= ~ATA_DFLAG_INIT_MASK;
ba6a1308 5349 spin_unlock_irqrestore(ap->lock, flags);
3ef3b43d 5350
72fa4b74
TH		 5351 memset((void *)dev + ATA_DEVICE_CLEAR_OFFSET, 0,
5352 sizeof(*dev) - ATA_DEVICE_CLEAR_OFFSET);
3ef3b43d
TH		 5353 dev->pio_mask = UINT_MAX;
5354 dev->mwdma_mask = UINT_MAX;
5355 dev->udma_mask = UINT_MAX;
5356}
5357
1da177e4 5358/**
155a8a9c 5359 * ata_port_init - Initialize an ata_port structure
1da177e4 5360 * @ap: Structure to initialize
cca3974e 5361 * @host: Collection of hosts to which @ap belongs
1da177e4
LT		 5362 * @ent: Probe information provided by low-level driver
5363 * @port_no: Port number associated with this ata_port
5364 *
155a8a9c 5365 * Initialize a new ata_port structure.
0cba632b 5366 *
1da177e4 5367 * LOCKING:
0cba632b 5368 * Inherited from caller.
1da177e4 5369 */
cca3974e 5370void ata_port_init(struct ata_port *ap, struct ata_host *host,
155a8a9c 5371 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 5372{
5373 unsigned int i;
5374
cca3974e 5375 ap->lock = &host->lock;
198e0fed 5376 ap->flags = ATA_FLAG_DISABLED;
155a8a9c 5377 ap->id = ata_unique_id++;
1da177e4 5378 ap->ctl = ATA_DEVCTL_OBS;
cca3974e 5379 ap->host = host;
2f1f610b 5380 ap->dev = ent->dev;
1da177e4 5381 ap->port_no = port_no;
fea63e38
TH		 5382 if (port_no == 1 && ent->pinfo2) {
5383 ap->pio_mask = ent->pinfo2->pio_mask;
5384 ap->mwdma_mask = ent->pinfo2->mwdma_mask;
5385 ap->udma_mask = ent->pinfo2->udma_mask;
5386 ap->flags |= ent->pinfo2->flags;
5387 ap->ops = ent->pinfo2->port_ops;
5388 } else {
5389 ap->pio_mask = ent->pio_mask;
5390 ap->mwdma_mask = ent->mwdma_mask;
5391 ap->udma_mask = ent->udma_mask;
5392 ap->flags |= ent->port_flags;
5393 ap->ops = ent->port_ops;
5394 }
5a04bf4b 5395 ap->hw_sata_spd_limit = UINT_MAX;
1da177e4
LT		 5396 ap->active_tag = ATA_TAG_POISON;
5397 ap->last_ctl = 0xFF;
bd5d825c
BP		 5398
5399#if defined(ATA_VERBOSE_DEBUG)
5400 /* turn on all debugging levels */
5401 ap->msg_enable = 0x00FF;
5402#elif defined(ATA_DEBUG)
5403 ap->msg_enable = ATA_MSG_DRV | ATA_MSG_INFO | ATA_MSG_CTL | ATA_MSG_WARN | ATA_MSG_ERR;
88574551 5404#else
0dd4b21f 5405 ap->msg_enable = ATA_MSG_DRV | ATA_MSG_ERR | ATA_MSG_WARN;
bd5d825c 5406#endif
1da177e4 5407
86e45b6b 5408 INIT_WORK(&ap->port_task, NULL, NULL);
580b2102 5409 INIT_WORK(&ap->hotplug_task, ata_scsi_hotplug, ap);
3057ac3c 5410 INIT_WORK(&ap->scsi_rescan_task, ata_scsi_dev_rescan, ap);
a72ec4ce 5411 INIT_LIST_HEAD(&ap->eh_done_q);
c6cf9e99 5412 init_waitqueue_head(&ap->eh_wait_q);
1da177e4 5413
838df628
TH		 5414 /* set cable type */
5415 ap->cbl = ATA_CBL_NONE;
5416 if (ap->flags & ATA_FLAG_SATA)
5417 ap->cbl = ATA_CBL_SATA;
5418
acf356b1
TH		 5419 for (i = 0; i < ATA_MAX_DEVICES; i++) {
5420 struct ata_device *dev = &ap->device[i];
38d87234 5421 dev->ap = ap;
72fa4b74 5422 dev->devno = i;
3ef3b43d 5423 ata_dev_init(dev);
acf356b1 5424 }
1da177e4
LT		 5425
5426#ifdef ATA_IRQ_TRAP
5427 ap->stats.unhandled_irq = 1;
5428 ap->stats.idle_irq = 1;
5429#endif
5430
5431 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
5432}
5433
155a8a9c 5434/**
4608c160
TH		 5435 * ata_port_init_shost - Initialize SCSI host associated with ATA port
5436 * @ap: ATA port to initialize SCSI host for
5437 * @shost: SCSI host associated with @ap
155a8a9c 5438 *
4608c160 5439 * Initialize SCSI host @shost associated with ATA port @ap.
155a8a9c
BK		 5440 *
5441 * LOCKING:
5442 * Inherited from caller.
5443 */
4608c160 5444static void ata_port_init_shost(struct ata_port *ap, struct Scsi_Host *shost)
155a8a9c 5445{
cca3974e 5446 ap->scsi_host = shost;
155a8a9c 5447
4608c160
TH		 5448 shost->unique_id = ap->id;
5449 shost->max_id = 16;
5450 shost->max_lun = 1;
5451 shost->max_channel = 1;
5452 shost->max_cmd_len = 12;
155a8a9c
BK		 5453}
5454
1da177e4 5455/**
996139f1 5456 * ata_port_add - Attach low-level ATA driver to system
1da177e4 5457 * @ent: Information provided by low-level driver
cca3974e 5458 * @host: Collections of ports to which we add
1da177e4
LT		 5459 * @port_no: Port number associated with this host
5460 *
0cba632b
JG		 5461 * Attach low-level ATA driver to system.
5462 *
1da177e4 5463 * LOCKING:
0cba632b 5464 * PCI/etc. bus probe sem.
1da177e4
LT		 5465 *
5466 * RETURNS:
0cba632b 5467 * New ata_port on success, for NULL on error.
1da177e4 5468 */
996139f1 5469static struct ata_port * ata_port_add(const struct ata_probe_ent *ent,
cca3974e 5470 struct ata_host *host,
1da177e4
LT		 5471 unsigned int port_no)
5472{
996139f1 5473 struct Scsi_Host *shost;
1da177e4 5474 struct ata_port *ap;
1da177e4
LT		 5475
5476 DPRINTK("ENTER\n");
aec5c3c1 5477
52783c5d 5478 if (!ent->port_ops->error_handler &&
cca3974e 5479 !(ent->port_flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST))) {
aec5c3c1
TH		 5480 printk(KERN_ERR "ata%u: no reset mechanism available\n",
5481 port_no);
5482 return NULL;
5483 }
5484
996139f1
JG		 5485 shost = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
5486 if (!shost)
1da177e4
LT		 5487 return NULL;
5488
996139f1 5489 shost->transportt = &ata_scsi_transport_template;
30afc84c 5490
996139f1 5491 ap = ata_shost_to_port(shost);
1da177e4 5492
cca3974e 5493 ata_port_init(ap, host, ent, port_no);
996139f1 5494 ata_port_init_shost(ap, shost);
1da177e4 5495
1da177e4 5496 return ap;
1da177e4
LT		 5497}
5498
b03732f0 5499/**
cca3974e
JG		 5500 * ata_sas_host_init - Initialize a host struct
5501 * @host: host to initialize
5502 * @dev: device host is attached to
5503 * @flags: host flags
5504 * @ops: port_ops
b03732f0
BK		 5505 *
5506 * LOCKING:
5507 * PCI/etc. bus probe sem.
5508 *
5509 */
5510
cca3974e
JG		 5511void ata_host_init(struct ata_host *host, struct device *dev,
5512 unsigned long flags, const struct ata_port_operations *ops)
b03732f0 5513{
cca3974e
JG		 5514 spin_lock_init(&host->lock);
5515 host->dev = dev;
5516 host->flags = flags;
5517 host->ops = ops;
b03732f0
BK		 5518}
5519
1da177e4 5520/**
0cba632b
JG		 5521 * ata_device_add - Register hardware device with ATA and SCSI layers
5522 * @ent: Probe information describing hardware device to be registered
5523 *
5524 * This function processes the information provided in the probe
5525 * information struct @ent, allocates the necessary ATA and SCSI
5526 * host information structures, initializes them, and registers
5527 * everything with requisite kernel subsystems.
5528 *
5529 * This function requests irqs, probes the ATA bus, and probes
5530 * the SCSI bus.
1da177e4
LT		 5531 *
5532 * LOCKING:
0cba632b 5533 * PCI/etc. bus probe sem.
1da177e4
LT		 5534 *
5535 * RETURNS:
0cba632b 5536 * Number of ports registered. Zero on error (no ports registered).
1da177e4 5537 */
057ace5e 5538int ata_device_add(const struct ata_probe_ent *ent)
1da177e4 5539{
6d0500df 5540 unsigned int i;
1da177e4 5541 struct device *dev = ent->dev;
cca3974e 5542 struct ata_host *host;
39b07ce6 5543 int rc;
1da177e4
LT		 5544
5545 DPRINTK("ENTER\n");
02f076aa
AC		 5546
5547 if (ent->irq == 0) {
5548 dev_printk(KERN_ERR, dev, "is not available: No interrupt assigned.\n");
5549 return 0;
5550 }
1da177e4 5551 /* alloc a container for our list of ATA ports (buses) */
cca3974e
JG		 5552 host = kzalloc(sizeof(struct ata_host) +
5553 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
5554 if (!host)
1da177e4 5555 return 0;
1da177e4 5556
cca3974e
JG		 5557 ata_host_init(host, dev, ent->_host_flags, ent->port_ops);
5558 host->n_ports = ent->n_ports;
5559 host->irq = ent->irq;
5560 host->irq2 = ent->irq2;
5561 host->mmio_base = ent->mmio_base;
5562 host->private_data = ent->private_data;
1da177e4
LT		 5563
5564 /* register each port bound to this device */
cca3974e 5565 for (i = 0; i < host->n_ports; i++) {
1da177e4
LT		 5566 struct ata_port *ap;
5567 unsigned long xfer_mode_mask;
2ec7df04 5568 int irq_line = ent->irq;
1da177e4 5569
cca3974e 5570 ap = ata_port_add(ent, host, i);
c38778c3 5571 host->ports[i] = ap;
1da177e4
LT		 5572 if (!ap)
5573 goto err_out;
5574
dd5b06c4
TH		 5575 /* dummy? */
5576 if (ent->dummy_port_mask & (1 << i)) {
5577 ata_port_printk(ap, KERN_INFO, "DUMMY\n");
5578 ap->ops = &ata_dummy_port_ops;
5579 continue;
5580 }
5581
5582 /* start port */
5583 rc = ap->ops->port_start(ap);
5584 if (rc) {
cca3974e
JG		 5585 host->ports[i] = NULL;
5586 scsi_host_put(ap->scsi_host);
dd5b06c4
TH		 5587 goto err_out;
5588 }
5589
2ec7df04
AC		 5590 /* Report the secondary IRQ for second channel legacy */
5591 if (i == 1 && ent->irq2)
5592 irq_line = ent->irq2;
5593
1da177e4
LT		 5594 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
5595 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
5596 (ap->pio_mask << ATA_SHIFT_PIO);
5597
5598 /* print per-port info to dmesg */
f15a1daf 5599 ata_port_printk(ap, KERN_INFO, "%cATA max %s cmd 0x%lX "
2ec7df04 5600 "ctl 0x%lX bmdma 0x%lX irq %d\n",
f15a1daf
TH		 5601 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
5602 ata_mode_string(xfer_mode_mask),
5603 ap->ioaddr.cmd_addr,
5604 ap->ioaddr.ctl_addr,
5605 ap->ioaddr.bmdma_addr,
2ec7df04 5606 irq_line);
1da177e4
LT		 5607
5608 ata_chk_status(ap);
cca3974e 5609 host->ops->irq_clear(ap);
e3180499 5610 ata_eh_freeze_port(ap); /* freeze port before requesting IRQ */
1da177e4
LT		 5611 }
5612
2ec7df04 5613 /* obtain irq, that may be shared between channels */
39b07ce6 5614 rc = request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
cca3974e 5615 DRV_NAME, host);
39b07ce6
JG		 5616 if (rc) {
5617 dev_printk(KERN_ERR, dev, "irq %lu request failed: %d\n",
5618 ent->irq, rc);
1da177e4 5619 goto err_out;
39b07ce6 5620 }
1da177e4 5621
2ec7df04
AC		 5622 /* do we have a second IRQ for the other channel, eg legacy mode */
5623 if (ent->irq2) {
5624 /* We will get weird core code crashes later if this is true
5625 so trap it now */
5626 BUG_ON(ent->irq == ent->irq2);
5627
5628 rc = request_irq(ent->irq2, ent->port_ops->irq_handler, ent->irq_flags,
cca3974e 5629 DRV_NAME, host);
2ec7df04
AC		 5630 if (rc) {
5631 dev_printk(KERN_ERR, dev, "irq %lu request failed: %d\n",
5632 ent->irq2, rc);
5633 goto err_out_free_irq;
5634 }
5635 }
5636
1da177e4
LT		 5637 /* perform each probe synchronously */
5638 DPRINTK("probe begin\n");
cca3974e
JG		 5639 for (i = 0; i < host->n_ports; i++) {
5640 struct ata_port *ap = host->ports[i];
5a04bf4b 5641 u32 scontrol;
1da177e4
LT		 5642 int rc;
5643
5a04bf4b
TH		 5644 /* init sata_spd_limit to the current value */
5645 if (sata_scr_read(ap, SCR_CONTROL, &scontrol) == 0) {
5646 int spd = (scontrol >> 4) & 0xf;
5647 ap->hw_sata_spd_limit &= (1 << spd) - 1;
5648 }
5649 ap->sata_spd_limit = ap->hw_sata_spd_limit;
5650
cca3974e 5651 rc = scsi_add_host(ap->scsi_host, dev);
1da177e4 5652 if (rc) {
f15a1daf 5653 ata_port_printk(ap, KERN_ERR, "scsi_add_host failed\n");
1da177e4
LT		 5654 /* FIXME: do something useful here */
5655 /* FIXME: handle unconditional calls to
5656 * scsi_scan_host and ata_host_remove, below,
5657 * at the very least
5658 */
5659 }
3e706399 5660
52783c5d 5661 if (ap->ops->error_handler) {
1cdaf534 5662 struct ata_eh_info *ehi = &ap->eh_info;
3e706399
TH		 5663 unsigned long flags;
5664
5665 ata_port_probe(ap);
5666
5667 /* kick EH for boot probing */
ba6a1308 5668 spin_lock_irqsave(ap->lock, flags);
3e706399 5669
1cdaf534
TH		 5670 ehi->probe_mask = (1 << ATA_MAX_DEVICES) - 1;
5671 ehi->action |= ATA_EH_SOFTRESET;
5672 ehi->flags |= ATA_EHI_NO_AUTOPSY | ATA_EHI_QUIET;
3e706399 5673
b51e9e5d 5674 ap->pflags |= ATA_PFLAG_LOADING;
3e706399
TH		 5675 ata_port_schedule_eh(ap);
5676
ba6a1308 5677 spin_unlock_irqrestore(ap->lock, flags);
3e706399
TH		 5678
5679 /* wait for EH to finish */
5680 ata_port_wait_eh(ap);
5681 } else {
5682 DPRINTK("ata%u: bus probe begin\n", ap->id);
5683 rc = ata_bus_probe(ap);
5684 DPRINTK("ata%u: bus probe end\n", ap->id);
5685
5686 if (rc) {
5687 /* FIXME: do something useful here?
5688 * Current libata behavior will
5689 * tear down everything when
5690 * the module is removed
5691 * or the h/w is unplugged.
5692 */
5693 }
5694 }
1da177e4
LT		 5695 }
5696
5697 /* probes are done, now scan each port's disk(s) */
c893a3ae 5698 DPRINTK("host probe begin\n");
cca3974e
JG		 5699 for (i = 0; i < host->n_ports; i++) {
5700 struct ata_port *ap = host->ports[i];
1da177e4 5701
644dd0cc 5702 ata_scsi_scan_host(ap);
1da177e4
LT		 5703 }
5704
cca3974e 5705 dev_set_drvdata(dev, host);
1da177e4
LT		 5706
5707 VPRINTK("EXIT, returning %u\n", ent->n_ports);
5708 return ent->n_ports; /* success */
5709
2ec7df04 5710err_out_free_irq:
cca3974e 5711 free_irq(ent->irq, host);
1da177e4 5712err_out:
cca3974e
JG		 5713 for (i = 0; i < host->n_ports; i++) {
5714 struct ata_port *ap = host->ports[i];
77f3f879
TH		 5715 if (ap) {
5716 ap->ops->port_stop(ap);
cca3974e 5717 scsi_host_put(ap->scsi_host);
77f3f879 5718 }
1da177e4 5719 }
6d0500df 5720
cca3974e 5721 kfree(host);
1da177e4
LT		 5722 VPRINTK("EXIT, returning 0\n");
5723 return 0;
5724}
5725
720ba126
TH		 5726/**
5727 * ata_port_detach - Detach ATA port in prepration of device removal
5728 * @ap: ATA port to be detached
5729 *
5730 * Detach all ATA devices and the associated SCSI devices of @ap;
5731 * then, remove the associated SCSI host. @ap is guaranteed to
5732 * be quiescent on return from this function.
5733 *
5734 * LOCKING:
5735 * Kernel thread context (may sleep).
5736 */
5737void ata_port_detach(struct ata_port *ap)
5738{
5739 unsigned long flags;
5740 int i;
5741
5742 if (!ap->ops->error_handler)
c3cf30a9 5743 goto skip_eh;
720ba126
TH		 5744
5745 /* tell EH we're leaving & flush EH */
ba6a1308 5746 spin_lock_irqsave(ap->lock, flags);
b51e9e5d 5747 ap->pflags |= ATA_PFLAG_UNLOADING;
ba6a1308 5748 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5749
5750 ata_port_wait_eh(ap);
5751
5752 /* EH is now guaranteed to see UNLOADING, so no new device
5753 * will be attached. Disable all existing devices.
5754 */
ba6a1308 5755 spin_lock_irqsave(ap->lock, flags);
720ba126
TH		 5756
5757 for (i = 0; i < ATA_MAX_DEVICES; i++)
5758 ata_dev_disable(&ap->device[i]);
5759
ba6a1308 5760 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5761
5762 /* Final freeze & EH. All in-flight commands are aborted. EH
5763 * will be skipped and retrials will be terminated with bad
5764 * target.
5765 */
ba6a1308 5766 spin_lock_irqsave(ap->lock, flags);
720ba126 5767 ata_port_freeze(ap); /* won't be thawed */
ba6a1308 5768 spin_unlock_irqrestore(ap->lock, flags);
720ba126
TH		 5769
5770 ata_port_wait_eh(ap);
5771
5772 /* Flush hotplug task. The sequence is similar to
5773 * ata_port_flush_task().
5774 */
5775 flush_workqueue(ata_aux_wq);
5776 cancel_delayed_work(&ap->hotplug_task);
5777 flush_workqueue(ata_aux_wq);
5778
c3cf30a9 5779 skip_eh:
720ba126 5780 /* remove the associated SCSI host */
cca3974e 5781 scsi_remove_host(ap->scsi_host);
720ba126
TH		 5782}
5783
17b14451 5784/**
cca3974e
JG		 5785 * ata_host_remove - PCI layer callback for device removal
5786 * @host: ATA host set that was removed
17b14451 5787 *
2e9edbf8 5788 * Unregister all objects associated with this host set. Free those
17b14451
AC		 5789 * objects.
5790 *
5791 * LOCKING:
5792 * Inherited from calling layer (may sleep).
5793 */
5794
cca3974e 5795void ata_host_remove(struct ata_host *host)
17b14451 5796{
17b14451
AC		 5797 unsigned int i;
5798
cca3974e
JG		 5799 for (i = 0; i < host->n_ports; i++)
5800 ata_port_detach(host->ports[i]);
17b14451 5801
cca3974e
JG		 5802 free_irq(host->irq, host);
5803 if (host->irq2)
5804 free_irq(host->irq2, host);
17b14451 5805
cca3974e
JG		 5806 for (i = 0; i < host->n_ports; i++) {
5807 struct ata_port *ap = host->ports[i];
17b14451 5808
cca3974e 5809 ata_scsi_release(ap->scsi_host);
17b14451
AC		 5810
5811 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
5812 struct ata_ioports *ioaddr = &ap->ioaddr;
5813
2ec7df04
AC		 5814 /* FIXME: Add -ac IDE pci mods to remove these special cases */
5815 if (ioaddr->cmd_addr == ATA_PRIMARY_CMD)
5816 release_region(ATA_PRIMARY_CMD, 8);
5817 else if (ioaddr->cmd_addr == ATA_SECONDARY_CMD)
5818 release_region(ATA_SECONDARY_CMD, 8);
17b14451
AC		 5819 }
5820
cca3974e 5821 scsi_host_put(ap->scsi_host);
17b14451
AC		 5822 }
5823
cca3974e
JG		 5824 if (host->ops->host_stop)
5825 host->ops->host_stop(host);
17b14451 5826
cca3974e 5827 kfree(host);
17b14451
AC		 5828}
5829
1da177e4
LT		 5830/**
5831 * ata_scsi_release - SCSI layer callback hook for host unload
4f931374 5832 * @shost: libata host to be unloaded
1da177e4
LT		 5833 *
5834 * Performs all duties necessary to shut down a libata port...
5835 * Kill port kthread, disable port, and release resources.
5836 *
5837 * LOCKING:
5838 * Inherited from SCSI layer.
5839 *
5840 * RETURNS:
5841 * One.
5842 */
5843
cca3974e 5844int ata_scsi_release(struct Scsi_Host *shost)
1da177e4 5845{
cca3974e 5846 struct ata_port *ap = ata_shost_to_port(shost);
1da177e4
LT		 5847
5848 DPRINTK("ENTER\n");
5849
5850 ap->ops->port_disable(ap);
6543bc07 5851 ap->ops->port_stop(ap);
1da177e4
LT		 5852
5853 DPRINTK("EXIT\n");
5854 return 1;
5855}
5856
f6d950e2
BK		 5857struct ata_probe_ent *
5858ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
5859{
5860 struct ata_probe_ent *probe_ent;
5861
5862 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
5863 if (!probe_ent) {
5864 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
5865 kobject_name(&(dev->kobj)));
5866 return NULL;
5867 }
5868
5869 INIT_LIST_HEAD(&probe_ent->node);
5870 probe_ent->dev = dev;
5871
5872 probe_ent->sht = port->sht;
cca3974e 5873 probe_ent->port_flags = port->flags;
f6d950e2
BK		 5874 probe_ent->pio_mask = port->pio_mask;
5875 probe_ent->mwdma_mask = port->mwdma_mask;
5876 probe_ent->udma_mask = port->udma_mask;
5877 probe_ent->port_ops = port->port_ops;
d639ca94 5878 probe_ent->private_data = port->private_data;
f6d950e2
BK		 5879
5880 return probe_ent;
5881}
5882
1da177e4
LT		 5883/**
5884 * ata_std_ports - initialize ioaddr with standard port offsets.
5885 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 5886 *
5887 * Utility function which initializes data_addr, error_addr,
5888 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
5889 * device_addr, status_addr, and command_addr to standard offsets
5890 * relative to cmd_addr.
5891 *
5892 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 5893 */
0baab86b 5894
1da177e4
LT		 5895void ata_std_ports(struct ata_ioports *ioaddr)
5896{
5897 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
5898 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
5899 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
5900 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
5901 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
5902 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
5903 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
5904 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
5905 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
5906 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
5907}
5908
0baab86b 5909
374b1873
JG		 5910#ifdef CONFIG_PCI
5911
cca3974e 5912void ata_pci_host_stop (struct ata_host *host)
374b1873 5913{
cca3974e 5914 struct pci_dev *pdev = to_pci_dev(host->dev);
374b1873 5915
cca3974e 5916 pci_iounmap(pdev, host->mmio_base);
374b1873
JG		 5917}
5918
1da177e4
LT		 5919/**
5920 * ata_pci_remove_one - PCI layer callback for device removal
5921 * @pdev: PCI device that was removed
5922 *
5923 * PCI layer indicates to libata via this hook that
6f0ef4fa 5924 * hot-unplug or module unload event has occurred.
1da177e4
LT		 5925 * Handle this by unregistering all objects associated
5926 * with this PCI device. Free those objects. Then finally
5927 * release PCI resources and disable device.
5928 *
5929 * LOCKING:
5930 * Inherited from PCI layer (may sleep).
5931 */
5932
5933void ata_pci_remove_one (struct pci_dev *pdev)
5934{
5935 struct device *dev = pci_dev_to_dev(pdev);
cca3974e 5936 struct ata_host *host = dev_get_drvdata(dev);
1da177e4 5937
cca3974e 5938 ata_host_remove(host);
f0eb62b8 5939
1da177e4
LT		 5940 pci_release_regions(pdev);
5941 pci_disable_device(pdev);
5942 dev_set_drvdata(dev, NULL);
5943}
5944
5945/* move to PCI subsystem */
057ace5e 5946int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 5947{
5948 unsigned long tmp = 0;
5949
5950 switch (bits->width) {
5951 case 1: {
5952 u8 tmp8 = 0;
5953 pci_read_config_byte(pdev, bits->reg, &tmp8);
5954 tmp = tmp8;
5955 break;
5956 }
5957 case 2: {
5958 u16 tmp16 = 0;
5959 pci_read_config_word(pdev, bits->reg, &tmp16);
5960 tmp = tmp16;
5961 break;
5962 }
5963 case 4: {
5964 u32 tmp32 = 0;
5965 pci_read_config_dword(pdev, bits->reg, &tmp32);
5966 tmp = tmp32;
5967 break;
5968 }
5969
5970 default:
5971 return -EINVAL;
5972 }
5973
5974 tmp &= bits->mask;
5975
5976 return (tmp == bits->val) ? 1 : 0;
5977}
9b847548 5978
3c5100c1 5979void ata_pci_device_do_suspend(struct pci_dev *pdev, pm_message_t mesg)
9b847548
JA		 5980{
5981 pci_save_state(pdev);
500530f6 5982
3c5100c1 5983 if (mesg.event == PM_EVENT_SUSPEND) {
500530f6
TH		 5984 pci_disable_device(pdev);
5985 pci_set_power_state(pdev, PCI_D3hot);
5986 }
9b847548
JA		 5987}
5988
500530f6 5989void ata_pci_device_do_resume(struct pci_dev *pdev)
9b847548
JA		 5990{
5991 pci_set_power_state(pdev, PCI_D0);
5992 pci_restore_state(pdev);
5993 pci_enable_device(pdev);
5994 pci_set_master(pdev);
500530f6
TH		 5995}
5996
3c5100c1 5997int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
500530f6 5998{
cca3974e 5999 struct ata_host *host = dev_get_drvdata(&pdev->dev);
500530f6
TH		 6000 int rc = 0;
6001
cca3974e 6002 rc = ata_host_suspend(host, mesg);
500530f6
TH		 6003 if (rc)
6004 return rc;
6005
3c5100c1 6006 ata_pci_device_do_suspend(pdev, mesg);
500530f6
TH		 6007
6008 return 0;
6009}
6010
6011int ata_pci_device_resume(struct pci_dev *pdev)
6012{
cca3974e 6013 struct ata_host *host = dev_get_drvdata(&pdev->dev);
500530f6
TH		 6014
6015 ata_pci_device_do_resume(pdev);
cca3974e 6016 ata_host_resume(host);
9b847548
JA		 6017 return 0;
6018}
1da177e4
LT		 6019#endif /* CONFIG_PCI */
6020
6021
1da177e4
LT		 6022static int __init ata_init(void)
6023{
a8601e5f 6024 ata_probe_timeout *= HZ;
1da177e4
LT		 6025 ata_wq = create_workqueue("ata");
6026 if (!ata_wq)
6027 return -ENOMEM;
6028
453b07ac
TH		 6029 ata_aux_wq = create_singlethread_workqueue("ata_aux");
6030 if (!ata_aux_wq) {
6031 destroy_workqueue(ata_wq);
6032 return -ENOMEM;
6033 }
6034
1da177e4
LT		 6035 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
6036 return 0;
6037}
6038
6039static void __exit ata_exit(void)
6040{
6041 destroy_workqueue(ata_wq);
453b07ac 6042 destroy_workqueue(ata_aux_wq);
1da177e4
LT		 6043}
6044
a4625085 6045subsys_initcall(ata_init);
1da177e4
LT		 6046module_exit(ata_exit);
6047
67846b30 6048static unsigned long ratelimit_time;
34af946a 6049static DEFINE_SPINLOCK(ata_ratelimit_lock);
67846b30
JG		 6050
6051int ata_ratelimit(void)
6052{
6053 int rc;
6054 unsigned long flags;
6055
6056 spin_lock_irqsave(&ata_ratelimit_lock, flags);
6057
6058 if (time_after(jiffies, ratelimit_time)) {
6059 rc = 1;
6060 ratelimit_time = jiffies + (HZ/5);
6061 } else
6062 rc = 0;
6063
6064 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
6065
6066 return rc;
6067}
6068
c22daff4
TH		 6069/**
6070 * ata_wait_register - wait until register value changes
6071 * @reg: IO-mapped register
6072 * @mask: Mask to apply to read register value
6073 * @val: Wait condition
6074 * @interval_msec: polling interval in milliseconds
6075 * @timeout_msec: timeout in milliseconds
6076 *
6077 * Waiting for some bits of register to change is a common
6078 * operation for ATA controllers. This function reads 32bit LE
6079 * IO-mapped register @reg and tests for the following condition.
6080 *
6081 * (*@reg & mask) != val
6082 *
6083 * If the condition is met, it returns; otherwise, the process is
6084 * repeated after @interval_msec until timeout.
6085 *
6086 * LOCKING:
6087 * Kernel thread context (may sleep)
6088 *
6089 * RETURNS:
6090 * The final register value.
6091 */
6092u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
6093 unsigned long interval_msec,
6094 unsigned long timeout_msec)
6095{
6096 unsigned long timeout;
6097 u32 tmp;
6098
6099 tmp = ioread32(reg);
6100
6101 /* Calculate timeout _after_ the first read to make sure
6102 * preceding writes reach the controller before starting to
6103 * eat away the timeout.
6104 */
6105 timeout = jiffies + (timeout_msec * HZ) / 1000;
6106
6107 while ((tmp & mask) == val && time_before(jiffies, timeout)) {
6108 msleep(interval_msec);
6109 tmp = ioread32(reg);
6110 }
6111
6112 return tmp;
6113}
6114
dd5b06c4
TH		 6115/*
6116 * Dummy port_ops
6117 */
6118static void ata_dummy_noret(struct ata_port *ap) { }
6119static int ata_dummy_ret0(struct ata_port *ap) { return 0; }
6120static void ata_dummy_qc_noret(struct ata_queued_cmd *qc) { }
6121
6122static u8 ata_dummy_check_status(struct ata_port *ap)
6123{
6124 return ATA_DRDY;
6125}
6126
6127static unsigned int ata_dummy_qc_issue(struct ata_queued_cmd *qc)
6128{
6129 return AC_ERR_SYSTEM;
6130}
6131
6132const struct ata_port_operations ata_dummy_port_ops = {
6133 .port_disable = ata_port_disable,
6134 .check_status = ata_dummy_check_status,
6135 .check_altstatus = ata_dummy_check_status,
6136 .dev_select = ata_noop_dev_select,
6137 .qc_prep = ata_noop_qc_prep,
6138 .qc_issue = ata_dummy_qc_issue,
6139 .freeze = ata_dummy_noret,
6140 .thaw = ata_dummy_noret,
6141 .error_handler = ata_dummy_noret,
6142 .post_internal_cmd = ata_dummy_qc_noret,
6143 .irq_clear = ata_dummy_noret,
6144 .port_start = ata_dummy_ret0,
6145 .port_stop = ata_dummy_noret,
6146};
6147
1da177e4
LT		 6148/*
6149 * libata is essentially a library of internal helper functions for
6150 * low-level ATA host controller drivers. As such, the API/ABI is
6151 * likely to change as new drivers are added and updated.
6152 * Do not depend on ABI/API stability.
6153 */
6154
e9c83914
TH		 6155EXPORT_SYMBOL_GPL(sata_deb_timing_normal);
6156EXPORT_SYMBOL_GPL(sata_deb_timing_hotplug);
6157EXPORT_SYMBOL_GPL(sata_deb_timing_long);
dd5b06c4 6158EXPORT_SYMBOL_GPL(ata_dummy_port_ops);
1da177e4
LT		 6159EXPORT_SYMBOL_GPL(ata_std_bios_param);
6160EXPORT_SYMBOL_GPL(ata_std_ports);
cca3974e 6161EXPORT_SYMBOL_GPL(ata_host_init);
1da177e4 6162EXPORT_SYMBOL_GPL(ata_device_add);
720ba126 6163EXPORT_SYMBOL_GPL(ata_port_detach);
cca3974e 6164EXPORT_SYMBOL_GPL(ata_host_remove);
1da177e4
LT		 6165EXPORT_SYMBOL_GPL(ata_sg_init);
6166EXPORT_SYMBOL_GPL(ata_sg_init_one);
9a1004d0 6167EXPORT_SYMBOL_GPL(ata_hsm_move);
f686bcb8 6168EXPORT_SYMBOL_GPL(ata_qc_complete);
dedaf2b0 6169EXPORT_SYMBOL_GPL(ata_qc_complete_multiple);
1da177e4 6170EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
1da177e4
LT		 6171EXPORT_SYMBOL_GPL(ata_tf_load);
6172EXPORT_SYMBOL_GPL(ata_tf_read);
6173EXPORT_SYMBOL_GPL(ata_noop_dev_select);
6174EXPORT_SYMBOL_GPL(ata_std_dev_select);
6175EXPORT_SYMBOL_GPL(ata_tf_to_fis);
6176EXPORT_SYMBOL_GPL(ata_tf_from_fis);
6177EXPORT_SYMBOL_GPL(ata_check_status);
6178EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 6179EXPORT_SYMBOL_GPL(ata_exec_command);
6180EXPORT_SYMBOL_GPL(ata_port_start);
6181EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 6182EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4 6183EXPORT_SYMBOL_GPL(ata_interrupt);
a6b2c5d4
AC		 6184EXPORT_SYMBOL_GPL(ata_mmio_data_xfer);
6185EXPORT_SYMBOL_GPL(ata_pio_data_xfer);
75e99585 6186EXPORT_SYMBOL_GPL(ata_pio_data_xfer_noirq);
1da177e4 6187EXPORT_SYMBOL_GPL(ata_qc_prep);
e46834cd 6188EXPORT_SYMBOL_GPL(ata_noop_qc_prep);
1da177e4
LT		 6189EXPORT_SYMBOL_GPL(ata_bmdma_setup);
6190EXPORT_SYMBOL_GPL(ata_bmdma_start);
6191EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
6192EXPORT_SYMBOL_GPL(ata_bmdma_status);
6193EXPORT_SYMBOL_GPL(ata_bmdma_stop);
6d97dbd7
TH		 6194EXPORT_SYMBOL_GPL(ata_bmdma_freeze);
6195EXPORT_SYMBOL_GPL(ata_bmdma_thaw);
6196EXPORT_SYMBOL_GPL(ata_bmdma_drive_eh);
6197EXPORT_SYMBOL_GPL(ata_bmdma_error_handler);
6198EXPORT_SYMBOL_GPL(ata_bmdma_post_internal_cmd);
1da177e4 6199EXPORT_SYMBOL_GPL(ata_port_probe);
3c567b7d 6200EXPORT_SYMBOL_GPL(sata_set_spd);
d7bb4cc7
TH		 6201EXPORT_SYMBOL_GPL(sata_phy_debounce);
6202EXPORT_SYMBOL_GPL(sata_phy_resume);
1da177e4
LT		 6203EXPORT_SYMBOL_GPL(sata_phy_reset);
6204EXPORT_SYMBOL_GPL(__sata_phy_reset);
6205EXPORT_SYMBOL_GPL(ata_bus_reset);
f5914a46 6206EXPORT_SYMBOL_GPL(ata_std_prereset);
c2bd5804 6207EXPORT_SYMBOL_GPL(ata_std_softreset);
b6103f6d 6208EXPORT_SYMBOL_GPL(sata_port_hardreset);
c2bd5804
TH		 6209EXPORT_SYMBOL_GPL(sata_std_hardreset);
6210EXPORT_SYMBOL_GPL(ata_std_postreset);
2e9edbf8
JG		 6211EXPORT_SYMBOL_GPL(ata_dev_classify);
6212EXPORT_SYMBOL_GPL(ata_dev_pair);
1da177e4 6213EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 6214EXPORT_SYMBOL_GPL(ata_ratelimit);
c22daff4 6215EXPORT_SYMBOL_GPL(ata_wait_register);
6f8b9958 6216EXPORT_SYMBOL_GPL(ata_busy_sleep);
86e45b6b 6217EXPORT_SYMBOL_GPL(ata_port_queue_task);
1da177e4
LT		 6218EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
6219EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
1da177e4 6220EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
83c47bcb 6221EXPORT_SYMBOL_GPL(ata_scsi_slave_destroy);
a6e6ce8e 6222EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
1da177e4
LT		 6223EXPORT_SYMBOL_GPL(ata_scsi_release);
6224EXPORT_SYMBOL_GPL(ata_host_intr);
34bf2170
TH		 6225EXPORT_SYMBOL_GPL(sata_scr_valid);
6226EXPORT_SYMBOL_GPL(sata_scr_read);
6227EXPORT_SYMBOL_GPL(sata_scr_write);
6228EXPORT_SYMBOL_GPL(sata_scr_write_flush);
6229EXPORT_SYMBOL_GPL(ata_port_online);
6230EXPORT_SYMBOL_GPL(ata_port_offline);
cca3974e
JG		 6231EXPORT_SYMBOL_GPL(ata_host_suspend);
6232EXPORT_SYMBOL_GPL(ata_host_resume);
6a62a04d
TH		 6233EXPORT_SYMBOL_GPL(ata_id_string);
6234EXPORT_SYMBOL_GPL(ata_id_c_string);
6919a0a6 6235EXPORT_SYMBOL_GPL(ata_device_blacklisted);
1da177e4
LT		 6236EXPORT_SYMBOL_GPL(ata_scsi_simulate);
6237
1bc4ccff 6238EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 6239EXPORT_SYMBOL_GPL(ata_timing_compute);
6240EXPORT_SYMBOL_GPL(ata_timing_merge);
6241
1da177e4
LT		 6242#ifdef CONFIG_PCI
6243EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 6244EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 6245EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
6246EXPORT_SYMBOL_GPL(ata_pci_init_one);
6247EXPORT_SYMBOL_GPL(ata_pci_remove_one);
500530f6
TH		 6248EXPORT_SYMBOL_GPL(ata_pci_device_do_suspend);
6249EXPORT_SYMBOL_GPL(ata_pci_device_do_resume);
9b847548
JA		 6250EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
6251EXPORT_SYMBOL_GPL(ata_pci_device_resume);
67951ade
AC		 6252EXPORT_SYMBOL_GPL(ata_pci_default_filter);
6253EXPORT_SYMBOL_GPL(ata_pci_clear_simplex);
1da177e4 6254#endif /* CONFIG_PCI */
9b847548 6255
9b847548
JA		 6256EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
6257EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
ece1d636 6258
ece1d636 6259EXPORT_SYMBOL_GPL(ata_eng_timeout);
7b70fc03
TH		 6260EXPORT_SYMBOL_GPL(ata_port_schedule_eh);
6261EXPORT_SYMBOL_GPL(ata_port_abort);
e3180499
TH		 6262EXPORT_SYMBOL_GPL(ata_port_freeze);
6263EXPORT_SYMBOL_GPL(ata_eh_freeze_port);
6264EXPORT_SYMBOL_GPL(ata_eh_thaw_port);
ece1d636
TH		 6265EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
6266EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
022bdb07 6267EXPORT_SYMBOL_GPL(ata_do_eh);
Clone of davem's net-next-2.6 tree