]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/ata/libahci.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ahci: implement AHCI_HFLAG_NO_FPDMA_AA and update NV quirks
[net-next-2.6.git] / drivers / ata / libahci.c
CommitLineData
365cfa1e
AV		 1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/blkdev.h>
39#include <linux/delay.h>
40#include <linux/interrupt.h>
41#include <linux/dma-mapping.h>
42#include <linux/device.h>
43#include <scsi/scsi_host.h>
44#include <scsi/scsi_cmnd.h>
45#include <linux/libata.h>
46#include "ahci.h"
47
48static int ahci_skip_host_reset;
49int ahci_ignore_sss;
50EXPORT_SYMBOL_GPL(ahci_ignore_sss);
51
52module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
53MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
54
55module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
56MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
57
58static int ahci_enable_alpm(struct ata_port *ap,
59 enum link_pm policy);
60static void ahci_disable_alpm(struct ata_port *ap);
61static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
62static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
63 size_t size);
64static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
65 ssize_t size);
66
67
68
69static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
70static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
71static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
72static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
73static int ahci_port_start(struct ata_port *ap);
74static void ahci_port_stop(struct ata_port *ap);
75static void ahci_qc_prep(struct ata_queued_cmd *qc);
76static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
77static void ahci_freeze(struct ata_port *ap);
78static void ahci_thaw(struct ata_port *ap);
79static void ahci_enable_fbs(struct ata_port *ap);
80static void ahci_disable_fbs(struct ata_port *ap);
81static void ahci_pmp_attach(struct ata_port *ap);
82static void ahci_pmp_detach(struct ata_port *ap);
83static int ahci_softreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85static int ahci_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87static void ahci_postreset(struct ata_link *link, unsigned int *class);
88static void ahci_error_handler(struct ata_port *ap);
89static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
90static int ahci_port_resume(struct ata_port *ap);
91static void ahci_dev_config(struct ata_device *dev);
92static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
93 u32 opts);
94#ifdef CONFIG_PM
95static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
96#endif
97static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100static void ahci_init_sw_activity(struct ata_link *link);
101
102static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110
111static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
112static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
113static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
114static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
115
116static struct device_attribute *ahci_shost_attrs[] = {
117 &dev_attr_link_power_management_policy,
118 &dev_attr_em_message_type,
119 &dev_attr_em_message,
120 &dev_attr_ahci_host_caps,
121 &dev_attr_ahci_host_cap2,
122 &dev_attr_ahci_host_version,
123 &dev_attr_ahci_port_cmd,
124 NULL
125};
126
127static struct device_attribute *ahci_sdev_attrs[] = {
128 &dev_attr_sw_activity,
129 &dev_attr_unload_heads,
130 NULL
131};
132
133struct scsi_host_template ahci_sht = {
134 ATA_NCQ_SHT("ahci"),
135 .can_queue = AHCI_MAX_CMDS - 1,
136 .sg_tablesize = AHCI_MAX_SG,
137 .dma_boundary = AHCI_DMA_BOUNDARY,
138 .shost_attrs = ahci_shost_attrs,
139 .sdev_attrs = ahci_sdev_attrs,
140};
141EXPORT_SYMBOL_GPL(ahci_sht);
142
143struct ata_port_operations ahci_ops = {
144 .inherits = &sata_pmp_port_ops,
145
146 .qc_defer = ahci_pmp_qc_defer,
147 .qc_prep = ahci_qc_prep,
148 .qc_issue = ahci_qc_issue,
149 .qc_fill_rtf = ahci_qc_fill_rtf,
150
151 .freeze = ahci_freeze,
152 .thaw = ahci_thaw,
153 .softreset = ahci_softreset,
154 .hardreset = ahci_hardreset,
155 .postreset = ahci_postreset,
156 .pmp_softreset = ahci_softreset,
157 .error_handler = ahci_error_handler,
158 .post_internal_cmd = ahci_post_internal_cmd,
159 .dev_config = ahci_dev_config,
160
161 .scr_read = ahci_scr_read,
162 .scr_write = ahci_scr_write,
163 .pmp_attach = ahci_pmp_attach,
164 .pmp_detach = ahci_pmp_detach,
165
166 .enable_pm = ahci_enable_alpm,
167 .disable_pm = ahci_disable_alpm,
168 .em_show = ahci_led_show,
169 .em_store = ahci_led_store,
170 .sw_activity_show = ahci_activity_show,
171 .sw_activity_store = ahci_activity_store,
172#ifdef CONFIG_PM
173 .port_suspend = ahci_port_suspend,
174 .port_resume = ahci_port_resume,
175#endif
176 .port_start = ahci_port_start,
177 .port_stop = ahci_port_stop,
178};
179EXPORT_SYMBOL_GPL(ahci_ops);
180
181int ahci_em_messages = 1;
182EXPORT_SYMBOL_GPL(ahci_em_messages);
183module_param(ahci_em_messages, int, 0444);
184/* add other LED protocol types when they become supported */
185MODULE_PARM_DESC(ahci_em_messages,
186 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
187
188static void ahci_enable_ahci(void __iomem *mmio)
189{
190 int i;
191 u32 tmp;
192
193 /* turn on AHCI_EN */
194 tmp = readl(mmio + HOST_CTL);
195 if (tmp & HOST_AHCI_EN)
196 return;
197
198 /* Some controllers need AHCI_EN to be written multiple times.
199 * Try a few times before giving up.
200 */
201 for (i = 0; i < 5; i++) {
202 tmp |= HOST_AHCI_EN;
203 writel(tmp, mmio + HOST_CTL);
204 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
205 if (tmp & HOST_AHCI_EN)
206 return;
207 msleep(10);
208 }
209
210 WARN_ON(1);
211}
212
213static ssize_t ahci_show_host_caps(struct device *dev,
214 struct device_attribute *attr, char *buf)
215{
216 struct Scsi_Host *shost = class_to_shost(dev);
217 struct ata_port *ap = ata_shost_to_port(shost);
218 struct ahci_host_priv *hpriv = ap->host->private_data;
219
220 return sprintf(buf, "%x\n", hpriv->cap);
221}
222
223static ssize_t ahci_show_host_cap2(struct device *dev,
224 struct device_attribute *attr, char *buf)
225{
226 struct Scsi_Host *shost = class_to_shost(dev);
227 struct ata_port *ap = ata_shost_to_port(shost);
228 struct ahci_host_priv *hpriv = ap->host->private_data;
229
230 return sprintf(buf, "%x\n", hpriv->cap2);
231}
232
233static ssize_t ahci_show_host_version(struct device *dev,
234 struct device_attribute *attr, char *buf)
235{
236 struct Scsi_Host *shost = class_to_shost(dev);
237 struct ata_port *ap = ata_shost_to_port(shost);
238 struct ahci_host_priv *hpriv = ap->host->private_data;
239 void __iomem *mmio = hpriv->mmio;
240
241 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
242}
243
244static ssize_t ahci_show_port_cmd(struct device *dev,
245 struct device_attribute *attr, char *buf)
246{
247 struct Scsi_Host *shost = class_to_shost(dev);
248 struct ata_port *ap = ata_shost_to_port(shost);
249 void __iomem *port_mmio = ahci_port_base(ap);
250
251 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
252}
253
254/**
255 * ahci_save_initial_config - Save and fixup initial config values
256 * @dev: target AHCI device
257 * @hpriv: host private area to store config values
258 * @force_port_map: force port map to a specified value
259 * @mask_port_map: mask out particular bits from port map
260 *
261 * Some registers containing configuration info might be setup by
262 * BIOS and might be cleared on reset. This function saves the
263 * initial values of those registers into @hpriv such that they
264 * can be restored after controller reset.
265 *
266 * If inconsistent, config values are fixed up by this function.
267 *
268 * LOCKING:
269 * None.
270 */
271void ahci_save_initial_config(struct device *dev,
272 struct ahci_host_priv *hpriv,
273 unsigned int force_port_map,
274 unsigned int mask_port_map)
275{
276 void __iomem *mmio = hpriv->mmio;
277 u32 cap, cap2, vers, port_map;
278 int i;
279
280 /* make sure AHCI mode is enabled before accessing CAP */
281 ahci_enable_ahci(mmio);
282
283 /* Values prefixed with saved_ are written back to host after
284 * reset. Values without are used for driver operation.
285 */
286 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
287 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
288
289 /* CAP2 register is only defined for AHCI 1.2 and later */
290 vers = readl(mmio + HOST_VERSION);
291 if ((vers >> 16) > 1 ||
292 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
293 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
294 else
295 hpriv->saved_cap2 = cap2 = 0;
296
297 /* some chips have errata preventing 64bit use */
298 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
299 dev_printk(KERN_INFO, dev,
300 "controller can't do 64bit DMA, forcing 32bit\n");
301 cap &= ~HOST_CAP_64;
302 }
303
304 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
305 dev_printk(KERN_INFO, dev,
306 "controller can't do NCQ, turning off CAP_NCQ\n");
307 cap &= ~HOST_CAP_NCQ;
308 }
309
310 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
311 dev_printk(KERN_INFO, dev,
312 "controller can do NCQ, turning on CAP_NCQ\n");
313 cap |= HOST_CAP_NCQ;
314 }
315
316 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
317 dev_printk(KERN_INFO, dev,
318 "controller can't do PMP, turning off CAP_PMP\n");
319 cap &= ~HOST_CAP_PMP;
320 }
321
322 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
323 dev_printk(KERN_INFO, dev,
324 "controller can't do SNTF, turning off CAP_SNTF\n");
325 cap &= ~HOST_CAP_SNTF;
326 }
327
328 if (force_port_map && port_map != force_port_map) {
329 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
330 port_map, force_port_map);
331 port_map = force_port_map;
332 }
333
334 if (mask_port_map) {
335 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
336 port_map,
337 port_map & mask_port_map);
338 port_map &= mask_port_map;
339 }
340
341 /* cross check port_map and cap.n_ports */
342 if (port_map) {
343 int map_ports = 0;
344
345 for (i = 0; i < AHCI_MAX_PORTS; i++)
346 if (port_map & (1 << i))
347 map_ports++;
348
349 /* If PI has more ports than n_ports, whine, clear
350 * port_map and let it be generated from n_ports.
351 */
352 if (map_ports > ahci_nr_ports(cap)) {
353 dev_printk(KERN_WARNING, dev,
354 "implemented port map (0x%x) contains more "
355 "ports than nr_ports (%u), using nr_ports\n",
356 port_map, ahci_nr_ports(cap));
357 port_map = 0;
358 }
359 }
360
361 /* fabricate port_map from cap.nr_ports */
362 if (!port_map) {
363 port_map = (1 << ahci_nr_ports(cap)) - 1;
364 dev_printk(KERN_WARNING, dev,
365 "forcing PORTS_IMPL to 0x%x\n", port_map);
366
367 /* write the fixed up value to the PI register */
368 hpriv->saved_port_map = port_map;
369 }
370
371 /* record values to use during operation */
372 hpriv->cap = cap;
373 hpriv->cap2 = cap2;
374 hpriv->port_map = port_map;
375}
376EXPORT_SYMBOL_GPL(ahci_save_initial_config);
377
378/**
379 * ahci_restore_initial_config - Restore initial config
380 * @host: target ATA host
381 *
382 * Restore initial config stored by ahci_save_initial_config().
383 *
384 * LOCKING:
385 * None.
386 */
387static void ahci_restore_initial_config(struct ata_host *host)
388{
389 struct ahci_host_priv *hpriv = host->private_data;
390 void __iomem *mmio = hpriv->mmio;
391
392 writel(hpriv->saved_cap, mmio + HOST_CAP);
393 if (hpriv->saved_cap2)
394 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
395 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
396 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
397}
398
399static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
400{
401 static const int offset[] = {
402 [SCR_STATUS] = PORT_SCR_STAT,
403 [SCR_CONTROL] = PORT_SCR_CTL,
404 [SCR_ERROR] = PORT_SCR_ERR,
405 [SCR_ACTIVE] = PORT_SCR_ACT,
406 [SCR_NOTIFICATION] = PORT_SCR_NTF,
407 };
408 struct ahci_host_priv *hpriv = ap->host->private_data;
409
410 if (sc_reg < ARRAY_SIZE(offset) &&
411 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
412 return offset[sc_reg];
413 return 0;
414}
415
416static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
417{
418 void __iomem *port_mmio = ahci_port_base(link->ap);
419 int offset = ahci_scr_offset(link->ap, sc_reg);
420
421 if (offset) {
422 *val = readl(port_mmio + offset);
423 return 0;
424 }
425 return -EINVAL;
426}
427
428static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
429{
430 void __iomem *port_mmio = ahci_port_base(link->ap);
431 int offset = ahci_scr_offset(link->ap, sc_reg);
432
433 if (offset) {
434 writel(val, port_mmio + offset);
435 return 0;
436 }
437 return -EINVAL;
438}
439
96d60303
MG		 440static int ahci_is_device_present(void __iomem *port_mmio)
441{
442 u8 status = readl(port_mmio + PORT_TFDATA) & 0xff;
443
444 /* Make sure PxTFD.STS.BSY and PxTFD.STS.DRQ are 0 */
445 if (status & (ATA_BUSY | ATA_DRQ))
446 return 0;
447
448 /* Make sure PxSSTS.DET is 3h */
449 status = readl(port_mmio + PORT_SCR_STAT) & 0xf;
450 if (status != 3)
451 return 0;
452 return 1;
453}
454
365cfa1e
AV		 455void ahci_start_engine(struct ata_port *ap)
456{
457 void __iomem *port_mmio = ahci_port_base(ap);
458 u32 tmp;
459
96d60303
MG		 460 if (!ahci_is_device_present(port_mmio))
461 return;
462
365cfa1e
AV		 463 /* start DMA */
464 tmp = readl(port_mmio + PORT_CMD);
465 tmp |= PORT_CMD_START;
466 writel(tmp, port_mmio + PORT_CMD);
467 readl(port_mmio + PORT_CMD); /* flush */
468}
469EXPORT_SYMBOL_GPL(ahci_start_engine);
470
471int ahci_stop_engine(struct ata_port *ap)
472{
473 void __iomem *port_mmio = ahci_port_base(ap);
474 u32 tmp;
475
476 tmp = readl(port_mmio + PORT_CMD);
477
478 /* check if the HBA is idle */
479 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
480 return 0;
481
482 /* setting HBA to idle */
483 tmp &= ~PORT_CMD_START;
484 writel(tmp, port_mmio + PORT_CMD);
485
486 /* wait for engine to stop. This could be as long as 500 msec */
487 tmp = ata_wait_register(port_mmio + PORT_CMD,
488 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
489 if (tmp & PORT_CMD_LIST_ON)
490 return -EIO;
491
492 return 0;
493}
494EXPORT_SYMBOL_GPL(ahci_stop_engine);
495
496static void ahci_start_fis_rx(struct ata_port *ap)
497{
498 void __iomem *port_mmio = ahci_port_base(ap);
499 struct ahci_host_priv *hpriv = ap->host->private_data;
500 struct ahci_port_priv *pp = ap->private_data;
501 u32 tmp;
502
503 /* set FIS registers */
504 if (hpriv->cap & HOST_CAP_64)
505 writel((pp->cmd_slot_dma >> 16) >> 16,
506 port_mmio + PORT_LST_ADDR_HI);
507 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
508
509 if (hpriv->cap & HOST_CAP_64)
510 writel((pp->rx_fis_dma >> 16) >> 16,
511 port_mmio + PORT_FIS_ADDR_HI);
512 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
513
514 /* enable FIS reception */
515 tmp = readl(port_mmio + PORT_CMD);
516 tmp |= PORT_CMD_FIS_RX;
517 writel(tmp, port_mmio + PORT_CMD);
518
519 /* flush */
520 readl(port_mmio + PORT_CMD);
521}
522
523static int ahci_stop_fis_rx(struct ata_port *ap)
524{
525 void __iomem *port_mmio = ahci_port_base(ap);
526 u32 tmp;
527
528 /* disable FIS reception */
529 tmp = readl(port_mmio + PORT_CMD);
530 tmp &= ~PORT_CMD_FIS_RX;
531 writel(tmp, port_mmio + PORT_CMD);
532
533 /* wait for completion, spec says 500ms, give it 1000 */
534 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
535 PORT_CMD_FIS_ON, 10, 1000);
536 if (tmp & PORT_CMD_FIS_ON)
537 return -EBUSY;
538
539 return 0;
540}
541
542static void ahci_power_up(struct ata_port *ap)
543{
544 struct ahci_host_priv *hpriv = ap->host->private_data;
545 void __iomem *port_mmio = ahci_port_base(ap);
546 u32 cmd;
547
548 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
549
550 /* spin up device */
551 if (hpriv->cap & HOST_CAP_SSS) {
552 cmd |= PORT_CMD_SPIN_UP;
553 writel(cmd, port_mmio + PORT_CMD);
554 }
555
556 /* wake up link */
557 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
558}
559
560static void ahci_disable_alpm(struct ata_port *ap)
561{
562 struct ahci_host_priv *hpriv = ap->host->private_data;
563 void __iomem *port_mmio = ahci_port_base(ap);
564 u32 cmd;
565 struct ahci_port_priv *pp = ap->private_data;
566
567 /* IPM bits should be disabled by libata-core */
568 /* get the existing command bits */
569 cmd = readl(port_mmio + PORT_CMD);
570
571 /* disable ALPM and ASP */
572 cmd &= ~PORT_CMD_ASP;
573 cmd &= ~PORT_CMD_ALPE;
574
575 /* force the interface back to active */
576 cmd |= PORT_CMD_ICC_ACTIVE;
577
578 /* write out new cmd value */
579 writel(cmd, port_mmio + PORT_CMD);
580 cmd = readl(port_mmio + PORT_CMD);
581
582 /* wait 10ms to be sure we've come out of any low power state */
583 msleep(10);
584
585 /* clear out any PhyRdy stuff from interrupt status */
586 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
587
588 /* go ahead and clean out PhyRdy Change from Serror too */
589 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
590
591 /*
592 * Clear flag to indicate that we should ignore all PhyRdy
593 * state changes
594 */
595 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
596
597 /*
598 * Enable interrupts on Phy Ready.
599 */
600 pp->intr_mask |= PORT_IRQ_PHYRDY;
601 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
602
603 /*
604 * don't change the link pm policy - we can be called
605 * just to turn of link pm temporarily
606 */
607}
608
609static int ahci_enable_alpm(struct ata_port *ap,
610 enum link_pm policy)
611{
612 struct ahci_host_priv *hpriv = ap->host->private_data;
613 void __iomem *port_mmio = ahci_port_base(ap);
614 u32 cmd;
615 struct ahci_port_priv *pp = ap->private_data;
616 u32 asp;
617
618 /* Make sure the host is capable of link power management */
619 if (!(hpriv->cap & HOST_CAP_ALPM))
620 return -EINVAL;
621
622 switch (policy) {
623 case MAX_PERFORMANCE:
624 case NOT_AVAILABLE:
625 /*
626 * if we came here with NOT_AVAILABLE,
627 * it just means this is the first time we
628 * have tried to enable - default to max performance,
629 * and let the user go to lower power modes on request.
630 */
631 ahci_disable_alpm(ap);
632 return 0;
633 case MIN_POWER:
634 /* configure HBA to enter SLUMBER */
635 asp = PORT_CMD_ASP;
636 break;
637 case MEDIUM_POWER:
638 /* configure HBA to enter PARTIAL */
639 asp = 0;
640 break;
641 default:
642 return -EINVAL;
643 }
644
645 /*
646 * Disable interrupts on Phy Ready. This keeps us from
647 * getting woken up due to spurious phy ready interrupts
648 * TBD - Hot plug should be done via polling now, is
649 * that even supported?
650 */
651 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
652 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
653
654 /*
655 * Set a flag to indicate that we should ignore all PhyRdy
656 * state changes since these can happen now whenever we
657 * change link state
658 */
659 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
660
661 /* get the existing command bits */
662 cmd = readl(port_mmio + PORT_CMD);
663
664 /*
665 * Set ASP based on Policy
666 */
667 cmd |= asp;
668
669 /*
670 * Setting this bit will instruct the HBA to aggressively
671 * enter a lower power link state when it's appropriate and
672 * based on the value set above for ASP
673 */
674 cmd |= PORT_CMD_ALPE;
675
676 /* write out new cmd value */
677 writel(cmd, port_mmio + PORT_CMD);
678 cmd = readl(port_mmio + PORT_CMD);
679
680 /* IPM bits should be set by libata-core */
681 return 0;
682}
683
684#ifdef CONFIG_PM
685static void ahci_power_down(struct ata_port *ap)
686{
687 struct ahci_host_priv *hpriv = ap->host->private_data;
688 void __iomem *port_mmio = ahci_port_base(ap);
689 u32 cmd, scontrol;
690
691 if (!(hpriv->cap & HOST_CAP_SSS))
692 return;
693
694 /* put device into listen mode, first set PxSCTL.DET to 0 */
695 scontrol = readl(port_mmio + PORT_SCR_CTL);
696 scontrol &= ~0xf;
697 writel(scontrol, port_mmio + PORT_SCR_CTL);
698
699 /* then set PxCMD.SUD to 0 */
700 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
701 cmd &= ~PORT_CMD_SPIN_UP;
702 writel(cmd, port_mmio + PORT_CMD);
703}
704#endif
705
706static void ahci_start_port(struct ata_port *ap)
707{
708 struct ahci_port_priv *pp = ap->private_data;
709 struct ata_link *link;
710 struct ahci_em_priv *emp;
711 ssize_t rc;
712 int i;
713
714 /* enable FIS reception */
715 ahci_start_fis_rx(ap);
716
717 /* enable DMA */
718 ahci_start_engine(ap);
719
720 /* turn on LEDs */
721 if (ap->flags & ATA_FLAG_EM) {
722 ata_for_each_link(link, ap, EDGE) {
723 emp = &pp->em_priv[link->pmp];
724
725 /* EM Transmit bit maybe busy during init */
726 for (i = 0; i < EM_MAX_RETRY; i++) {
727 rc = ahci_transmit_led_message(ap,
728 emp->led_state,
729 4);
730 if (rc == -EBUSY)
731 msleep(1);
732 else
733 break;
734 }
735 }
736 }
737
738 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
739 ata_for_each_link(link, ap, EDGE)
740 ahci_init_sw_activity(link);
741
742}
743
744static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
745{
746 int rc;
747
748 /* disable DMA */
749 rc = ahci_stop_engine(ap);
750 if (rc) {
751 *emsg = "failed to stop engine";
752 return rc;
753 }
754
755 /* disable FIS reception */
756 rc = ahci_stop_fis_rx(ap);
757 if (rc) {
758 *emsg = "failed stop FIS RX";
759 return rc;
760 }
761
762 return 0;
763}
764
765int ahci_reset_controller(struct ata_host *host)
766{
767 struct ahci_host_priv *hpriv = host->private_data;
768 void __iomem *mmio = hpriv->mmio;
769 u32 tmp;
770
771 /* we must be in AHCI mode, before using anything
772 * AHCI-specific, such as HOST_RESET.
773 */
774 ahci_enable_ahci(mmio);
775
776 /* global controller reset */
777 if (!ahci_skip_host_reset) {
778 tmp = readl(mmio + HOST_CTL);
779 if ((tmp & HOST_RESET) == 0) {
780 writel(tmp | HOST_RESET, mmio + HOST_CTL);
781 readl(mmio + HOST_CTL); /* flush */
782 }
783
784 /*
785 * to perform host reset, OS should set HOST_RESET
786 * and poll until this bit is read to be "0".
787 * reset must complete within 1 second, or
788 * the hardware should be considered fried.
789 */
790 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
791 HOST_RESET, 10, 1000);
792
793 if (tmp & HOST_RESET) {
794 dev_printk(KERN_ERR, host->dev,
795 "controller reset failed (0x%x)\n", tmp);
796 return -EIO;
797 }
798
799 /* turn on AHCI mode */
800 ahci_enable_ahci(mmio);
801
802 /* Some registers might be cleared on reset. Restore
803 * initial values.
804 */
805 ahci_restore_initial_config(host);
806 } else
807 dev_printk(KERN_INFO, host->dev,
808 "skipping global host reset\n");
809
810 return 0;
811}
812EXPORT_SYMBOL_GPL(ahci_reset_controller);
813
814static void ahci_sw_activity(struct ata_link *link)
815{
816 struct ata_port *ap = link->ap;
817 struct ahci_port_priv *pp = ap->private_data;
818 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
819
820 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
821 return;
822
823 emp->activity++;
824 if (!timer_pending(&emp->timer))
825 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
826}
827
828static void ahci_sw_activity_blink(unsigned long arg)
829{
830 struct ata_link *link = (struct ata_link *)arg;
831 struct ata_port *ap = link->ap;
832 struct ahci_port_priv *pp = ap->private_data;
833 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
834 unsigned long led_message = emp->led_state;
835 u32 activity_led_state;
836 unsigned long flags;
837
838 led_message &= EM_MSG_LED_VALUE;
839 led_message |= ap->port_no | (link->pmp << 8);
840
841 /* check to see if we've had activity. If so,
842 * toggle state of LED and reset timer. If not,
843 * turn LED to desired idle state.
844 */
845 spin_lock_irqsave(ap->lock, flags);
846 if (emp->saved_activity != emp->activity) {
847 emp->saved_activity = emp->activity;
848 /* get the current LED state */
849 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
850
851 if (activity_led_state)
852 activity_led_state = 0;
853 else
854 activity_led_state = 1;
855
856 /* clear old state */
857 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
858
859 /* toggle state */
860 led_message |= (activity_led_state << 16);
861 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
862 } else {
863 /* switch to idle */
864 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
865 if (emp->blink_policy == BLINK_OFF)
866 led_message |= (1 << 16);
867 }
868 spin_unlock_irqrestore(ap->lock, flags);
869 ahci_transmit_led_message(ap, led_message, 4);
870}
871
872static void ahci_init_sw_activity(struct ata_link *link)
873{
874 struct ata_port *ap = link->ap;
875 struct ahci_port_priv *pp = ap->private_data;
876 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
877
878 /* init activity stats, setup timer */
879 emp->saved_activity = emp->activity = 0;
880 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
881
882 /* check our blink policy and set flag for link if it's enabled */
883 if (emp->blink_policy)
884 link->flags |= ATA_LFLAG_SW_ACTIVITY;
885}
886
887int ahci_reset_em(struct ata_host *host)
888{
889 struct ahci_host_priv *hpriv = host->private_data;
890 void __iomem *mmio = hpriv->mmio;
891 u32 em_ctl;
892
893 em_ctl = readl(mmio + HOST_EM_CTL);
894 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
895 return -EINVAL;
896
897 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
898 return 0;
899}
900EXPORT_SYMBOL_GPL(ahci_reset_em);
901
902static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
903 ssize_t size)
904{
905 struct ahci_host_priv *hpriv = ap->host->private_data;
906 struct ahci_port_priv *pp = ap->private_data;
907 void __iomem *mmio = hpriv->mmio;
908 u32 em_ctl;
909 u32 message[] = {0, 0};
910 unsigned long flags;
911 int pmp;
912 struct ahci_em_priv *emp;
913
914 /* get the slot number from the message */
915 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
916 if (pmp < EM_MAX_SLOTS)
917 emp = &pp->em_priv[pmp];
918 else
919 return -EINVAL;
920
921 spin_lock_irqsave(ap->lock, flags);
922
923 /*
924 * if we are still busy transmitting a previous message,
925 * do not allow
926 */
927 em_ctl = readl(mmio + HOST_EM_CTL);
928 if (em_ctl & EM_CTL_TM) {
929 spin_unlock_irqrestore(ap->lock, flags);
930 return -EBUSY;
931 }
932
933 /*
934 * create message header - this is all zero except for
935 * the message size, which is 4 bytes.
936 */
937 message[0] |= (4 << 8);
938
939 /* ignore 0:4 of byte zero, fill in port info yourself */
940 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
941
942 /* write message to EM_LOC */
943 writel(message[0], mmio + hpriv->em_loc);
944 writel(message[1], mmio + hpriv->em_loc+4);
945
946 /* save off new led state for port/slot */
947 emp->led_state = state;
948
949 /*
950 * tell hardware to transmit the message
951 */
952 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
953
954 spin_unlock_irqrestore(ap->lock, flags);
955 return size;
956}
957
958static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
959{
960 struct ahci_port_priv *pp = ap->private_data;
961 struct ata_link *link;
962 struct ahci_em_priv *emp;
963 int rc = 0;
964
965 ata_for_each_link(link, ap, EDGE) {
966 emp = &pp->em_priv[link->pmp];
967 rc += sprintf(buf, "%lx\n", emp->led_state);
968 }
969 return rc;
970}
971
972static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
973 size_t size)
974{
975 int state;
976 int pmp;
977 struct ahci_port_priv *pp = ap->private_data;
978 struct ahci_em_priv *emp;
979
980 state = simple_strtoul(buf, NULL, 0);
981
982 /* get the slot number from the message */
983 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
984 if (pmp < EM_MAX_SLOTS)
985 emp = &pp->em_priv[pmp];
986 else
987 return -EINVAL;
988
989 /* mask off the activity bits if we are in sw_activity
990 * mode, user should turn off sw_activity before setting
991 * activity led through em_message
992 */
993 if (emp->blink_policy)
994 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
995
996 return ahci_transmit_led_message(ap, state, size);
997}
998
999static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1000{
1001 struct ata_link *link = dev->link;
1002 struct ata_port *ap = link->ap;
1003 struct ahci_port_priv *pp = ap->private_data;
1004 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1005 u32 port_led_state = emp->led_state;
1006
1007 /* save the desired Activity LED behavior */
1008 if (val == OFF) {
1009 /* clear LFLAG */
1010 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1011
1012 /* set the LED to OFF */
1013 port_led_state &= EM_MSG_LED_VALUE_OFF;
1014 port_led_state |= (ap->port_no | (link->pmp << 8));
1015 ahci_transmit_led_message(ap, port_led_state, 4);
1016 } else {
1017 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1018 if (val == BLINK_OFF) {
1019 /* set LED to ON for idle */
1020 port_led_state &= EM_MSG_LED_VALUE_OFF;
1021 port_led_state |= (ap->port_no | (link->pmp << 8));
1022 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1023 ahci_transmit_led_message(ap, port_led_state, 4);
1024 }
1025 }
1026 emp->blink_policy = val;
1027 return 0;
1028}
1029
1030static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1031{
1032 struct ata_link *link = dev->link;
1033 struct ata_port *ap = link->ap;
1034 struct ahci_port_priv *pp = ap->private_data;
1035 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1036
1037 /* display the saved value of activity behavior for this
1038 * disk.
1039 */
1040 return sprintf(buf, "%d\n", emp->blink_policy);
1041}
1042
1043static void ahci_port_init(struct device *dev, struct ata_port *ap,
1044 int port_no, void __iomem *mmio,
1045 void __iomem *port_mmio)
1046{
1047 const char *emsg = NULL;
1048 int rc;
1049 u32 tmp;
1050
1051 /* make sure port is not active */
1052 rc = ahci_deinit_port(ap, &emsg);
1053 if (rc)
1054 dev_warn(dev, "%s (%d)\n", emsg, rc);
1055
1056 /* clear SError */
1057 tmp = readl(port_mmio + PORT_SCR_ERR);
1058 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1059 writel(tmp, port_mmio + PORT_SCR_ERR);
1060
1061 /* clear port IRQ */
1062 tmp = readl(port_mmio + PORT_IRQ_STAT);
1063 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1064 if (tmp)
1065 writel(tmp, port_mmio + PORT_IRQ_STAT);
1066
1067 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1068}
1069
1070void ahci_init_controller(struct ata_host *host)
1071{
1072 struct ahci_host_priv *hpriv = host->private_data;
1073 void __iomem *mmio = hpriv->mmio;
1074 int i;
1075 void __iomem *port_mmio;
1076 u32 tmp;
1077
1078 for (i = 0; i < host->n_ports; i++) {
1079 struct ata_port *ap = host->ports[i];
1080
1081 port_mmio = ahci_port_base(ap);
1082 if (ata_port_is_dummy(ap))
1083 continue;
1084
1085 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1086 }
1087
1088 tmp = readl(mmio + HOST_CTL);
1089 VPRINTK("HOST_CTL 0x%x\n", tmp);
1090 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1091 tmp = readl(mmio + HOST_CTL);
1092 VPRINTK("HOST_CTL 0x%x\n", tmp);
1093}
1094EXPORT_SYMBOL_GPL(ahci_init_controller);
1095
1096static void ahci_dev_config(struct ata_device *dev)
1097{
1098 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1099
1100 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1101 dev->max_sectors = 255;
1102 ata_dev_printk(dev, KERN_INFO,
1103 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1104 }
1105}
1106
1107static unsigned int ahci_dev_classify(struct ata_port *ap)
1108{
1109 void __iomem *port_mmio = ahci_port_base(ap);
1110 struct ata_taskfile tf;
1111 u32 tmp;
1112
1113 tmp = readl(port_mmio + PORT_SIG);
1114 tf.lbah = (tmp >> 24) & 0xff;
1115 tf.lbam = (tmp >> 16) & 0xff;
1116 tf.lbal = (tmp >> 8) & 0xff;
1117 tf.nsect = (tmp) & 0xff;
1118
1119 return ata_dev_classify(&tf);
1120}
1121
1122static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1123 u32 opts)
1124{
1125 dma_addr_t cmd_tbl_dma;
1126
1127 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1128
1129 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1130 pp->cmd_slot[tag].status = 0;
1131 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1132 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1133}
1134
1135int ahci_kick_engine(struct ata_port *ap)
1136{
1137 void __iomem *port_mmio = ahci_port_base(ap);
1138 struct ahci_host_priv *hpriv = ap->host->private_data;
1139 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1140 u32 tmp;
1141 int busy, rc;
1142
1143 /* stop engine */
1144 rc = ahci_stop_engine(ap);
1145 if (rc)
1146 goto out_restart;
1147
1148 /* need to do CLO?
1149 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1150 */
1151 busy = status & (ATA_BUSY | ATA_DRQ);
1152 if (!busy && !sata_pmp_attached(ap)) {
1153 rc = 0;
1154 goto out_restart;
1155 }
1156
1157 if (!(hpriv->cap & HOST_CAP_CLO)) {
1158 rc = -EOPNOTSUPP;
1159 goto out_restart;
1160 }
1161
1162 /* perform CLO */
1163 tmp = readl(port_mmio + PORT_CMD);
1164 tmp |= PORT_CMD_CLO;
1165 writel(tmp, port_mmio + PORT_CMD);
1166
1167 rc = 0;
1168 tmp = ata_wait_register(port_mmio + PORT_CMD,
1169 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1170 if (tmp & PORT_CMD_CLO)
1171 rc = -EIO;
1172
1173 /* restart engine */
1174 out_restart:
1175 ahci_start_engine(ap);
1176 return rc;
1177}
1178EXPORT_SYMBOL_GPL(ahci_kick_engine);
1179
1180static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1181 struct ata_taskfile *tf, int is_cmd, u16 flags,
1182 unsigned long timeout_msec)
1183{
1184 const u32 cmd_fis_len = 5; /* five dwords */
1185 struct ahci_port_priv *pp = ap->private_data;
1186 void __iomem *port_mmio = ahci_port_base(ap);
1187 u8 *fis = pp->cmd_tbl;
1188 u32 tmp;
1189
1190 /* prep the command */
1191 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1192 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1193
1194 /* issue & wait */
1195 writel(1, port_mmio + PORT_CMD_ISSUE);
1196
1197 if (timeout_msec) {
1198 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1199 1, timeout_msec);
1200 if (tmp & 0x1) {
1201 ahci_kick_engine(ap);
1202 return -EBUSY;
1203 }
1204 } else
1205 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1206
1207 return 0;
1208}
1209
1210int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1211 int pmp, unsigned long deadline,
1212 int (*check_ready)(struct ata_link *link))
1213{
1214 struct ata_port *ap = link->ap;
1215 struct ahci_host_priv *hpriv = ap->host->private_data;
1216 const char *reason = NULL;
1217 unsigned long now, msecs;
1218 struct ata_taskfile tf;
1219 int rc;
1220
1221 DPRINTK("ENTER\n");
1222
1223 /* prepare for SRST (AHCI-1.1 10.4.1) */
1224 rc = ahci_kick_engine(ap);
1225 if (rc && rc != -EOPNOTSUPP)
1226 ata_link_printk(link, KERN_WARNING,
1227 "failed to reset engine (errno=%d)\n", rc);
1228
1229 ata_tf_init(link->device, &tf);
1230
1231 /* issue the first D2H Register FIS */
1232 msecs = 0;
1233 now = jiffies;
1234 if (time_after(now, deadline))
1235 msecs = jiffies_to_msecs(deadline - now);
1236
1237 tf.ctl |= ATA_SRST;
1238 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1239 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1240 rc = -EIO;
1241 reason = "1st FIS failed";
1242 goto fail;
1243 }
1244
1245 /* spec says at least 5us, but be generous and sleep for 1ms */
1246 msleep(1);
1247
1248 /* issue the second D2H Register FIS */
1249 tf.ctl &= ~ATA_SRST;
1250 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1251
1252 /* wait for link to become ready */
1253 rc = ata_wait_after_reset(link, deadline, check_ready);
1254 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1255 /*
1256 * Workaround for cases where link online status can't
1257 * be trusted. Treat device readiness timeout as link
1258 * offline.
1259 */
1260 ata_link_printk(link, KERN_INFO,
1261 "device not ready, treating as offline\n");
1262 *class = ATA_DEV_NONE;
1263 } else if (rc) {
1264 /* link occupied, -ENODEV too is an error */
1265 reason = "device not ready";
1266 goto fail;
1267 } else
1268 *class = ahci_dev_classify(ap);
1269
1270 DPRINTK("EXIT, class=%u\n", *class);
1271 return 0;
1272
1273 fail:
1274 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1275 return rc;
1276}
1277
1278int ahci_check_ready(struct ata_link *link)
1279{
1280 void __iomem *port_mmio = ahci_port_base(link->ap);
1281 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1282
1283 return ata_check_ready(status);
1284}
1285EXPORT_SYMBOL_GPL(ahci_check_ready);
1286
1287static int ahci_softreset(struct ata_link *link, unsigned int *class,
1288 unsigned long deadline)
1289{
1290 int pmp = sata_srst_pmp(link);
1291
1292 DPRINTK("ENTER\n");
1293
1294 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1295}
1296EXPORT_SYMBOL_GPL(ahci_do_softreset);
1297
1298static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1299 unsigned long deadline)
1300{
1301 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1302 struct ata_port *ap = link->ap;
1303 struct ahci_port_priv *pp = ap->private_data;
1304 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1305 struct ata_taskfile tf;
1306 bool online;
1307 int rc;
1308
1309 DPRINTK("ENTER\n");
1310
1311 ahci_stop_engine(ap);
1312
1313 /* clear D2H reception area to properly wait for D2H FIS */
1314 ata_tf_init(link->device, &tf);
1315 tf.command = 0x80;
1316 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1317
1318 rc = sata_link_hardreset(link, timing, deadline, &online,
1319 ahci_check_ready);
1320
1321 ahci_start_engine(ap);
1322
1323 if (online)
1324 *class = ahci_dev_classify(ap);
1325
1326 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1327 return rc;
1328}
1329
1330static void ahci_postreset(struct ata_link *link, unsigned int *class)
1331{
1332 struct ata_port *ap = link->ap;
1333 void __iomem *port_mmio = ahci_port_base(ap);
1334 u32 new_tmp, tmp;
1335
1336 ata_std_postreset(link, class);
1337
1338 /* Make sure port's ATAPI bit is set appropriately */
1339 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1340 if (*class == ATA_DEV_ATAPI)
1341 new_tmp |= PORT_CMD_ATAPI;
1342 else
1343 new_tmp &= ~PORT_CMD_ATAPI;
1344 if (new_tmp != tmp) {
1345 writel(new_tmp, port_mmio + PORT_CMD);
1346 readl(port_mmio + PORT_CMD); /* flush */
1347 }
1348}
1349
1350static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1351{
1352 struct scatterlist *sg;
1353 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1354 unsigned int si;
1355
1356 VPRINTK("ENTER\n");
1357
1358 /*
1359 * Next, the S/G list.
1360 */
1361 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1362 dma_addr_t addr = sg_dma_address(sg);
1363 u32 sg_len = sg_dma_len(sg);
1364
1365 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1366 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1367 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1368 }
1369
1370 return si;
1371}
1372
1373static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1374{
1375 struct ata_port *ap = qc->ap;
1376 struct ahci_port_priv *pp = ap->private_data;
1377
1378 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1379 return ata_std_qc_defer(qc);
1380 else
1381 return sata_pmp_qc_defer_cmd_switch(qc);
1382}
1383
1384static void ahci_qc_prep(struct ata_queued_cmd *qc)
1385{
1386 struct ata_port *ap = qc->ap;
1387 struct ahci_port_priv *pp = ap->private_data;
1388 int is_atapi = ata_is_atapi(qc->tf.protocol);
1389 void *cmd_tbl;
1390 u32 opts;
1391 const u32 cmd_fis_len = 5; /* five dwords */
1392 unsigned int n_elem;
1393
1394 /*
1395 * Fill in command table information. First, the header,
1396 * a SATA Register - Host to Device command FIS.
1397 */
1398 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1399
1400 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1401 if (is_atapi) {
1402 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1403 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1404 }
1405
1406 n_elem = 0;
1407 if (qc->flags & ATA_QCFLAG_DMAMAP)
1408 n_elem = ahci_fill_sg(qc, cmd_tbl);
1409
1410 /*
1411 * Fill in command slot information.
1412 */
1413 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1414 if (qc->tf.flags & ATA_TFLAG_WRITE)
1415 opts |= AHCI_CMD_WRITE;
1416 if (is_atapi)
1417 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1418
1419 ahci_fill_cmd_slot(pp, qc->tag, opts);
1420}
1421
1422static void ahci_fbs_dec_intr(struct ata_port *ap)
1423{
1424 struct ahci_port_priv *pp = ap->private_data;
1425 void __iomem *port_mmio = ahci_port_base(ap);
1426 u32 fbs = readl(port_mmio + PORT_FBS);
1427 int retries = 3;
1428
1429 DPRINTK("ENTER\n");
1430 BUG_ON(!pp->fbs_enabled);
1431
1432 /* time to wait for DEC is not specified by AHCI spec,
1433 * add a retry loop for safety.
1434 */
1435 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1436 fbs = readl(port_mmio + PORT_FBS);
1437 while ((fbs & PORT_FBS_DEC) && retries--) {
1438 udelay(1);
1439 fbs = readl(port_mmio + PORT_FBS);
1440 }
1441
1442 if (fbs & PORT_FBS_DEC)
1443 dev_printk(KERN_ERR, ap->host->dev,
1444 "failed to clear device error\n");
1445}
1446
1447static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1448{
1449 struct ahci_host_priv *hpriv = ap->host->private_data;
1450 struct ahci_port_priv *pp = ap->private_data;
1451 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1452 struct ata_link *link = NULL;
1453 struct ata_queued_cmd *active_qc;
1454 struct ata_eh_info *active_ehi;
1455 bool fbs_need_dec = false;
1456 u32 serror;
1457
1458 /* determine active link with error */
1459 if (pp->fbs_enabled) {
1460 void __iomem *port_mmio = ahci_port_base(ap);
1461 u32 fbs = readl(port_mmio + PORT_FBS);
1462 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1463
1464 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1465 ata_link_online(&ap->pmp_link[pmp])) {
1466 link = &ap->pmp_link[pmp];
1467 fbs_need_dec = true;
1468 }
1469
1470 } else
1471 ata_for_each_link(link, ap, EDGE)
1472 if (ata_link_active(link))
1473 break;
1474
1475 if (!link)
1476 link = &ap->link;
1477
1478 active_qc = ata_qc_from_tag(ap, link->active_tag);
1479 active_ehi = &link->eh_info;
1480
1481 /* record irq stat */
1482 ata_ehi_clear_desc(host_ehi);
1483 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1484
1485 /* AHCI needs SError cleared; otherwise, it might lock up */
1486 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1487 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1488 host_ehi->serror |= serror;
1489
1490 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1491 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1492 irq_stat &= ~PORT_IRQ_IF_ERR;
1493
1494 if (irq_stat & PORT_IRQ_TF_ERR) {
1495 /* If qc is active, charge it; otherwise, the active
1496 * link. There's no active qc on NCQ errors. It will
1497 * be determined by EH by reading log page 10h.
1498 */
1499 if (active_qc)
1500 active_qc->err_mask |= AC_ERR_DEV;
1501 else
1502 active_ehi->err_mask |= AC_ERR_DEV;
1503
1504 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1505 host_ehi->serror &= ~SERR_INTERNAL;
1506 }
1507
1508 if (irq_stat & PORT_IRQ_UNK_FIS) {
1509 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1510
1511 active_ehi->err_mask |= AC_ERR_HSM;
1512 active_ehi->action |= ATA_EH_RESET;
1513 ata_ehi_push_desc(active_ehi,
1514 "unknown FIS %08x %08x %08x %08x" ,
1515 unk[0], unk[1], unk[2], unk[3]);
1516 }
1517
1518 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1519 active_ehi->err_mask |= AC_ERR_HSM;
1520 active_ehi->action |= ATA_EH_RESET;
1521 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1522 }
1523
1524 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1525 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1526 host_ehi->action |= ATA_EH_RESET;
1527 ata_ehi_push_desc(host_ehi, "host bus error");
1528 }
1529
1530 if (irq_stat & PORT_IRQ_IF_ERR) {
1531 if (fbs_need_dec)
1532 active_ehi->err_mask |= AC_ERR_DEV;
1533 else {
1534 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1535 host_ehi->action |= ATA_EH_RESET;
1536 }
1537
1538 ata_ehi_push_desc(host_ehi, "interface fatal error");
1539 }
1540
1541 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1542 ata_ehi_hotplugged(host_ehi);
1543 ata_ehi_push_desc(host_ehi, "%s",
1544 irq_stat & PORT_IRQ_CONNECT ?
1545 "connection status changed" : "PHY RDY changed");
1546 }
1547
1548 /* okay, let's hand over to EH */
1549
1550 if (irq_stat & PORT_IRQ_FREEZE)
1551 ata_port_freeze(ap);
1552 else if (fbs_need_dec) {
1553 ata_link_abort(link);
1554 ahci_fbs_dec_intr(ap);
1555 } else
1556 ata_port_abort(ap);
1557}
1558
1559static void ahci_port_intr(struct ata_port *ap)
1560{
1561 void __iomem *port_mmio = ahci_port_base(ap);
1562 struct ata_eh_info *ehi = &ap->link.eh_info;
1563 struct ahci_port_priv *pp = ap->private_data;
1564 struct ahci_host_priv *hpriv = ap->host->private_data;
1565 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1566 u32 status, qc_active = 0;
1567 int rc;
1568
1569 status = readl(port_mmio + PORT_IRQ_STAT);
1570 writel(status, port_mmio + PORT_IRQ_STAT);
1571
1572 /* ignore BAD_PMP while resetting */
1573 if (unlikely(resetting))
1574 status &= ~PORT_IRQ_BAD_PMP;
1575
1576 /* If we are getting PhyRdy, this is
1577 * just a power state change, we should
1578 * clear out this, plus the PhyRdy/Comm
1579 * Wake bits from Serror
1580 */
1581 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1582 (status & PORT_IRQ_PHYRDY)) {
1583 status &= ~PORT_IRQ_PHYRDY;
1584 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1585 }
1586
1587 if (unlikely(status & PORT_IRQ_ERROR)) {
1588 ahci_error_intr(ap, status);
1589 return;
1590 }
1591
1592 if (status & PORT_IRQ_SDB_FIS) {
1593 /* If SNotification is available, leave notification
1594 * handling to sata_async_notification(). If not,
1595 * emulate it by snooping SDB FIS RX area.
1596 *
1597 * Snooping FIS RX area is probably cheaper than
1598 * poking SNotification but some constrollers which
1599 * implement SNotification, ICH9 for example, don't
1600 * store AN SDB FIS into receive area.
1601 */
1602 if (hpriv->cap & HOST_CAP_SNTF)
1603 sata_async_notification(ap);
1604 else {
1605 /* If the 'N' bit in word 0 of the FIS is set,
1606 * we just received asynchronous notification.
1607 * Tell libata about it.
1608 *
1609 * Lack of SNotification should not appear in
1610 * ahci 1.2, so the workaround is unnecessary
1611 * when FBS is enabled.
1612 */
1613 if (pp->fbs_enabled)
1614 WARN_ON_ONCE(1);
1615 else {
1616 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1617 u32 f0 = le32_to_cpu(f[0]);
1618 if (f0 & (1 << 15))
1619 sata_async_notification(ap);
1620 }
1621 }
1622 }
1623
1624 /* pp->active_link is not reliable once FBS is enabled, both
1625 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1626 * NCQ and non-NCQ commands may be in flight at the same time.
1627 */
1628 if (pp->fbs_enabled) {
1629 if (ap->qc_active) {
1630 qc_active = readl(port_mmio + PORT_SCR_ACT);
1631 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1632 }
1633 } else {
1634 /* pp->active_link is valid iff any command is in flight */
1635 if (ap->qc_active && pp->active_link->sactive)
1636 qc_active = readl(port_mmio + PORT_SCR_ACT);
1637 else
1638 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1639 }
1640
1641
1642 rc = ata_qc_complete_multiple(ap, qc_active);
1643
1644 /* while resetting, invalid completions are expected */
1645 if (unlikely(rc < 0 && !resetting)) {
1646 ehi->err_mask |= AC_ERR_HSM;
1647 ehi->action |= ATA_EH_RESET;
1648 ata_port_freeze(ap);
1649 }
1650}
1651
1652irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1653{
1654 struct ata_host *host = dev_instance;
1655 struct ahci_host_priv *hpriv;
1656 unsigned int i, handled = 0;
1657 void __iomem *mmio;
1658 u32 irq_stat, irq_masked;
1659
1660 VPRINTK("ENTER\n");
1661
1662 hpriv = host->private_data;
1663 mmio = hpriv->mmio;
1664
1665 /* sigh. 0xffffffff is a valid return from h/w */
1666 irq_stat = readl(mmio + HOST_IRQ_STAT);
1667 if (!irq_stat)
1668 return IRQ_NONE;
1669
1670 irq_masked = irq_stat & hpriv->port_map;
1671
1672 spin_lock(&host->lock);
1673
1674 for (i = 0; i < host->n_ports; i++) {
1675 struct ata_port *ap;
1676
1677 if (!(irq_masked & (1 << i)))
1678 continue;
1679
1680 ap = host->ports[i];
1681 if (ap) {
1682 ahci_port_intr(ap);
1683 VPRINTK("port %u\n", i);
1684 } else {
1685 VPRINTK("port %u (no irq)\n", i);
1686 if (ata_ratelimit())
1687 dev_printk(KERN_WARNING, host->dev,
1688 "interrupt on disabled port %u\n", i);
1689 }
1690
1691 handled = 1;
1692 }
1693
1694 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1695 * it should be cleared after all the port events are cleared;
1696 * otherwise, it will raise a spurious interrupt after each
1697 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1698 * information.
1699 *
1700 * Also, use the unmasked value to clear interrupt as spurious
1701 * pending event on a dummy port might cause screaming IRQ.
1702 */
1703 writel(irq_stat, mmio + HOST_IRQ_STAT);
1704
1705 spin_unlock(&host->lock);
1706
1707 VPRINTK("EXIT\n");
1708
1709 return IRQ_RETVAL(handled);
1710}
1711EXPORT_SYMBOL_GPL(ahci_interrupt);
1712
1713static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1714{
1715 struct ata_port *ap = qc->ap;
1716 void __iomem *port_mmio = ahci_port_base(ap);
1717 struct ahci_port_priv *pp = ap->private_data;
1718
1719 /* Keep track of the currently active link. It will be used
1720 * in completion path to determine whether NCQ phase is in
1721 * progress.
1722 */
1723 pp->active_link = qc->dev->link;
1724
1725 if (qc->tf.protocol == ATA_PROT_NCQ)
1726 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1727
1728 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1729 u32 fbs = readl(port_mmio + PORT_FBS);
1730 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1731 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1732 writel(fbs, port_mmio + PORT_FBS);
1733 pp->fbs_last_dev = qc->dev->link->pmp;
1734 }
1735
1736 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1737
1738 ahci_sw_activity(qc->dev->link);
1739
1740 return 0;
1741}
1742
1743static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1744{
1745 struct ahci_port_priv *pp = qc->ap->private_data;
1746 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1747
1748 if (pp->fbs_enabled)
1749 d2h_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1750
1751 ata_tf_from_fis(d2h_fis, &qc->result_tf);
1752 return true;
1753}
1754
1755static void ahci_freeze(struct ata_port *ap)
1756{
1757 void __iomem *port_mmio = ahci_port_base(ap);
1758
1759 /* turn IRQ off */
1760 writel(0, port_mmio + PORT_IRQ_MASK);
1761}
1762
1763static void ahci_thaw(struct ata_port *ap)
1764{
1765 struct ahci_host_priv *hpriv = ap->host->private_data;
1766 void __iomem *mmio = hpriv->mmio;
1767 void __iomem *port_mmio = ahci_port_base(ap);
1768 u32 tmp;
1769 struct ahci_port_priv *pp = ap->private_data;
1770
1771 /* clear IRQ */
1772 tmp = readl(port_mmio + PORT_IRQ_STAT);
1773 writel(tmp, port_mmio + PORT_IRQ_STAT);
1774 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1775
1776 /* turn IRQ back on */
1777 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1778}
1779
1780static void ahci_error_handler(struct ata_port *ap)
1781{
1782 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1783 /* restart engine */
1784 ahci_stop_engine(ap);
1785 ahci_start_engine(ap);
1786 }
1787
1788 sata_pmp_error_handler(ap);
1789}
1790
1791static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1792{
1793 struct ata_port *ap = qc->ap;
1794
1795 /* make DMA engine forget about the failed command */
1796 if (qc->flags & ATA_QCFLAG_FAILED)
1797 ahci_kick_engine(ap);
1798}
1799
1800static void ahci_enable_fbs(struct ata_port *ap)
1801{
1802 struct ahci_port_priv *pp = ap->private_data;
1803 void __iomem *port_mmio = ahci_port_base(ap);
1804 u32 fbs;
1805 int rc;
1806
1807 if (!pp->fbs_supported)
1808 return;
1809
1810 fbs = readl(port_mmio + PORT_FBS);
1811 if (fbs & PORT_FBS_EN) {
1812 pp->fbs_enabled = true;
1813 pp->fbs_last_dev = -1; /* initialization */
1814 return;
1815 }
1816
1817 rc = ahci_stop_engine(ap);
1818 if (rc)
1819 return;
1820
1821 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1822 fbs = readl(port_mmio + PORT_FBS);
1823 if (fbs & PORT_FBS_EN) {
1824 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1825 pp->fbs_enabled = true;
1826 pp->fbs_last_dev = -1; /* initialization */
1827 } else
1828 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1829
1830 ahci_start_engine(ap);
1831}
1832
1833static void ahci_disable_fbs(struct ata_port *ap)
1834{
1835 struct ahci_port_priv *pp = ap->private_data;
1836 void __iomem *port_mmio = ahci_port_base(ap);
1837 u32 fbs;
1838 int rc;
1839
1840 if (!pp->fbs_supported)
1841 return;
1842
1843 fbs = readl(port_mmio + PORT_FBS);
1844 if ((fbs & PORT_FBS_EN) == 0) {
1845 pp->fbs_enabled = false;
1846 return;
1847 }
1848
1849 rc = ahci_stop_engine(ap);
1850 if (rc)
1851 return;
1852
1853 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1854 fbs = readl(port_mmio + PORT_FBS);
1855 if (fbs & PORT_FBS_EN)
1856 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1857 else {
1858 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1859 pp->fbs_enabled = false;
1860 }
1861
1862 ahci_start_engine(ap);
1863}
1864
1865static void ahci_pmp_attach(struct ata_port *ap)
1866{
1867 void __iomem *port_mmio = ahci_port_base(ap);
1868 struct ahci_port_priv *pp = ap->private_data;
1869 u32 cmd;
1870
1871 cmd = readl(port_mmio + PORT_CMD);
1872 cmd |= PORT_CMD_PMP;
1873 writel(cmd, port_mmio + PORT_CMD);
1874
1875 ahci_enable_fbs(ap);
1876
1877 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1878 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1879}
1880
1881static void ahci_pmp_detach(struct ata_port *ap)
1882{
1883 void __iomem *port_mmio = ahci_port_base(ap);
1884 struct ahci_port_priv *pp = ap->private_data;
1885 u32 cmd;
1886
1887 ahci_disable_fbs(ap);
1888
1889 cmd = readl(port_mmio + PORT_CMD);
1890 cmd &= ~PORT_CMD_PMP;
1891 writel(cmd, port_mmio + PORT_CMD);
1892
1893 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1894 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1895}
1896
1897static int ahci_port_resume(struct ata_port *ap)
1898{
1899 ahci_power_up(ap);
1900 ahci_start_port(ap);
1901
1902 if (sata_pmp_attached(ap))
1903 ahci_pmp_attach(ap);
1904 else
1905 ahci_pmp_detach(ap);
1906
1907 return 0;
1908}
1909
1910#ifdef CONFIG_PM
1911static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1912{
1913 const char *emsg = NULL;
1914 int rc;
1915
1916 rc = ahci_deinit_port(ap, &emsg);
1917 if (rc == 0)
1918 ahci_power_down(ap);
1919 else {
1920 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1921 ahci_start_port(ap);
1922 }
1923
1924 return rc;
1925}
1926#endif
1927
1928static int ahci_port_start(struct ata_port *ap)
1929{
1930 struct ahci_host_priv *hpriv = ap->host->private_data;
1931 struct device *dev = ap->host->dev;
1932 struct ahci_port_priv *pp;
1933 void *mem;
1934 dma_addr_t mem_dma;
1935 size_t dma_sz, rx_fis_sz;
1936
1937 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1938 if (!pp)
1939 return -ENOMEM;
1940
1941 /* check FBS capability */
1942 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
1943 void __iomem *port_mmio = ahci_port_base(ap);
1944 u32 cmd = readl(port_mmio + PORT_CMD);
1945 if (cmd & PORT_CMD_FBSCP)
1946 pp->fbs_supported = true;
1947 else
1948 dev_printk(KERN_WARNING, dev,
1949 "The port is not capable of FBS\n");
1950 }
1951
1952 if (pp->fbs_supported) {
1953 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
1954 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
1955 } else {
1956 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
1957 rx_fis_sz = AHCI_RX_FIS_SZ;
1958 }
1959
1960 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
1961 if (!mem)
1962 return -ENOMEM;
1963 memset(mem, 0, dma_sz);
1964
1965 /*
1966 * First item in chunk of DMA memory: 32-slot command table,
1967 * 32 bytes each in size
1968 */
1969 pp->cmd_slot = mem;
1970 pp->cmd_slot_dma = mem_dma;
1971
1972 mem += AHCI_CMD_SLOT_SZ;
1973 mem_dma += AHCI_CMD_SLOT_SZ;
1974
1975 /*
1976 * Second item: Received-FIS area
1977 */
1978 pp->rx_fis = mem;
1979 pp->rx_fis_dma = mem_dma;
1980
1981 mem += rx_fis_sz;
1982 mem_dma += rx_fis_sz;
1983
1984 /*
1985 * Third item: data area for storing a single command
1986 * and its scatter-gather table
1987 */
1988 pp->cmd_tbl = mem;
1989 pp->cmd_tbl_dma = mem_dma;
1990
1991 /*
1992 * Save off initial list of interrupts to be enabled.
1993 * This could be changed later
1994 */
1995 pp->intr_mask = DEF_PORT_IRQ;
1996
1997 ap->private_data = pp;
1998
1999 /* engage engines, captain */
2000 return ahci_port_resume(ap);
2001}
2002
2003static void ahci_port_stop(struct ata_port *ap)
2004{
2005 const char *emsg = NULL;
2006 int rc;
2007
2008 /* de-initialize port */
2009 rc = ahci_deinit_port(ap, &emsg);
2010 if (rc)
2011 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2012}
2013
2014void ahci_print_info(struct ata_host *host, const char *scc_s)
2015{
2016 struct ahci_host_priv *hpriv = host->private_data;
2017 void __iomem *mmio = hpriv->mmio;
2018 u32 vers, cap, cap2, impl, speed;
2019 const char *speed_s;
2020
2021 vers = readl(mmio + HOST_VERSION);
2022 cap = hpriv->cap;
2023 cap2 = hpriv->cap2;
2024 impl = hpriv->port_map;
2025
2026 speed = (cap >> 20) & 0xf;
2027 if (speed == 1)
2028 speed_s = "1.5";
2029 else if (speed == 2)
2030 speed_s = "3";
2031 else if (speed == 3)
2032 speed_s = "6";
2033 else
2034 speed_s = "?";
2035
2036 dev_info(host->dev,
2037 "AHCI %02x%02x.%02x%02x "
2038 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2039 ,
2040
2041 (vers >> 24) & 0xff,
2042 (vers >> 16) & 0xff,
2043 (vers >> 8) & 0xff,
2044 vers & 0xff,
2045
2046 ((cap >> 8) & 0x1f) + 1,
2047 (cap & 0x1f) + 1,
2048 speed_s,
2049 impl,
2050 scc_s);
2051
2052 dev_info(host->dev,
2053 "flags: "
2054 "%s%s%s%s%s%s%s"
2055 "%s%s%s%s%s%s%s"
2056 "%s%s%s%s%s%s\n"
2057 ,
2058
2059 cap & HOST_CAP_64 ? "64bit " : "",
2060 cap & HOST_CAP_NCQ ? "ncq " : "",
2061 cap & HOST_CAP_SNTF ? "sntf " : "",
2062 cap & HOST_CAP_MPS ? "ilck " : "",
2063 cap & HOST_CAP_SSS ? "stag " : "",
2064 cap & HOST_CAP_ALPM ? "pm " : "",
2065 cap & HOST_CAP_LED ? "led " : "",
2066 cap & HOST_CAP_CLO ? "clo " : "",
2067 cap & HOST_CAP_ONLY ? "only " : "",
2068 cap & HOST_CAP_PMP ? "pmp " : "",
2069 cap & HOST_CAP_FBS ? "fbs " : "",
2070 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2071 cap & HOST_CAP_SSC ? "slum " : "",
2072 cap & HOST_CAP_PART ? "part " : "",
2073 cap & HOST_CAP_CCC ? "ccc " : "",
2074 cap & HOST_CAP_EMS ? "ems " : "",
2075 cap & HOST_CAP_SXS ? "sxs " : "",
2076 cap2 & HOST_CAP2_APST ? "apst " : "",
2077 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2078 cap2 & HOST_CAP2_BOH ? "boh " : ""
2079 );
2080}
2081EXPORT_SYMBOL_GPL(ahci_print_info);
2082
2083void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2084 struct ata_port_info *pi)
2085{
2086 u8 messages;
2087 void __iomem *mmio = hpriv->mmio;
2088 u32 em_loc = readl(mmio + HOST_EM_LOC);
2089 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2090
2091 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2092 return;
2093
2094 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2095
2096 /* we only support LED message type right now */
2097 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2098 /* store em_loc */
2099 hpriv->em_loc = ((em_loc >> 16) * 4);
2100 pi->flags |= ATA_FLAG_EM;
2101 if (!(em_ctl & EM_CTL_ALHD))
2102 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2103 }
2104}
2105EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2106
2107MODULE_AUTHOR("Jeff Garzik");
2108MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2109MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree