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libata: ahci enclosure management led sync
[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
a22e6444
TH		 52static int ahci_skip_host_reset;
53module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
31556594
KCA		 56static int ahci_enable_alpm(struct ata_port *ap,
57 enum link_pm policy);
58static void ahci_disable_alpm(struct ata_port *ap);
18f7ba4c
KCA		 59static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
61 size_t size);
62static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
63 ssize_t size);
64#define MAX_SLOTS 8
1da177e4
LT		 65
66enum {
67 AHCI_PCI_BAR = 5,
648a88be 68 AHCI_MAX_PORTS = 32,
1da177e4
LT		 69 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
12fad3f9 71 AHCI_MAX_CMDS = 32,
dd410ff1 72 AHCI_CMD_SZ = 32,
12fad3f9 73 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 74 AHCI_RX_FIS_SZ = 256,
a0ea7328 75 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 76 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 80 AHCI_RX_FIS_SZ,
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
4b10e559 84 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 85 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 87
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 89 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 90 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 91
92 board_ahci = 0,
7a234aff
TH		 93 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
95 board_ahci_sb600 = 3,
96 board_ahci_mv = 4,
e39fc8c9 97 board_ahci_sb700 = 5,
e297d99e 98 board_ahci_mcp65 = 6,
9a3b103c 99 board_ahci_nopmp = 7,
1da177e4
LT		 100
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
18f7ba4c
KCA		 107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
1da177e4
LT		 109
110 /* HOST_CTL bits */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
114
115 /* HOST_CAP bits */
18f7ba4c 116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
0be0aa98 117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 125
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 142
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
152
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
162
78cd52d0
TH		 163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
164 PORT_IRQ_IF_ERR |
165 PORT_IRQ_CONNECT |
4296971d 166 PORT_IRQ_PHYRDY |
7d50b60b
TH		 167 PORT_IRQ_UNK_FIS |
168 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
170 PORT_IRQ_TF_ERR |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 175
176 /* PORT_CMD bits */
31556594
KCA		 177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 184 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
188
0be0aa98 189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 193
417a1a6d
TH		 194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
e297d99e 204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
417a1a6d 205
bf2af2a2 206 /* ap->flags bits */
1188c0d8
TH		 207
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
211 ATA_FLAG_IPM,
c4f7792c
TH		 212
213 ICH_MAP = 0x90, /* ICH MAP register */
18f7ba4c
KCA		 214
215 /* em_ctl bits */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
1da177e4
LT		 219};
220
221struct ahci_cmd_hdr {
4ca4e439
AV		 222 __le32 opts;
223 __le32 status;
224 __le32 tbl_addr;
225 __le32 tbl_addr_hi;
226 __le32 reserved[4];
1da177e4
LT		 227};
228
229struct ahci_sg {
4ca4e439
AV		 230 __le32 addr;
231 __le32 addr_hi;
232 __le32 reserved;
233 __le32 flags_size;
1da177e4
LT		 234};
235
18f7ba4c
KCA		 236struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
242};
243
1da177e4 244struct ahci_host_priv {
417a1a6d 245 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
18f7ba4c 250 u32 em_loc; /* enclosure management location */
1da177e4
LT		 251};
252
253struct ahci_port_priv {
7d50b60b 254 struct ata_link *active_link;
1da177e4
LT		 255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
257 void *cmd_tbl;
258 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 259 void *rx_fis;
260 dma_addr_t rx_fis_dma;
0291f95f 261 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
afb2d552 264 unsigned int ncq_saw_sdb:1;
a7384925 265 u32 intr_mask; /* interrupts to enable */
18f7ba4c
KCA		 266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
267 * per PM slot */
1da177e4
LT		 268};
269
82ef04fb
TH		 270static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
271static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
2dcb407e 272static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 273static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
4c9bf4e7 274static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
1da177e4
LT		 275static int ahci_port_start(struct ata_port *ap);
276static void ahci_port_stop(struct ata_port *ap);
1da177e4 277static void ahci_qc_prep(struct ata_queued_cmd *qc);
78cd52d0
TH		 278static void ahci_freeze(struct ata_port *ap);
279static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 280static void ahci_pmp_attach(struct ata_port *ap);
281static void ahci_pmp_detach(struct ata_port *ap);
a1efdaba
TH		 282static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
bd17243a
SH		 284static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
a1efdaba
TH		 286static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292static void ahci_postreset(struct ata_link *link, unsigned int *class);
78cd52d0
TH		 293static void ahci_error_handler(struct ata_port *ap);
294static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 295static int ahci_port_resume(struct ata_port *ap);
a878539e 296static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 297static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
299 u32 opts);
438ac6d5 300#ifdef CONFIG_PM
c1332875 301static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 302static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 304#endif
18f7ba4c
KCA		 305static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308static void ahci_init_sw_activity(struct ata_link *link);
1da177e4 309
ee959b00
TJ		 310static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
18f7ba4c
KCA		 312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
314 NULL
315};
316
317static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
45fabbb7 319 &dev_attr_unload_heads,
31556594
KCA		 320 NULL
321};
322
193515d5 323static struct scsi_host_template ahci_sht = {
68d1d07b 324 ATA_NCQ_SHT(DRV_NAME),
12fad3f9 325 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4 326 .sg_tablesize = AHCI_MAX_SG,
1da177e4 327 .dma_boundary = AHCI_DMA_BOUNDARY,
31556594 328 .shost_attrs = ahci_shost_attrs,
18f7ba4c 329 .sdev_attrs = ahci_sdev_attrs,
1da177e4
LT		 330};
331
029cfd6b
TH		 332static struct ata_port_operations ahci_ops = {
333 .inherits = &sata_pmp_port_ops,
334
7d50b60b 335 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 336 .qc_prep = ahci_qc_prep,
337 .qc_issue = ahci_qc_issue,
4c9bf4e7 338 .qc_fill_rtf = ahci_qc_fill_rtf,
1da177e4 339
78cd52d0
TH		 340 .freeze = ahci_freeze,
341 .thaw = ahci_thaw,
a1efdaba
TH		 342 .softreset = ahci_softreset,
343 .hardreset = ahci_hardreset,
344 .postreset = ahci_postreset,
071f44b1 345 .pmp_softreset = ahci_softreset,
78cd52d0
TH		 346 .error_handler = ahci_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
6bd99b4e
TH		 348 .dev_config = ahci_dev_config,
349
ad616ffb
TH		 350 .scr_read = ahci_scr_read,
351 .scr_write = ahci_scr_write,
7d50b60b
TH		 352 .pmp_attach = ahci_pmp_attach,
353 .pmp_detach = ahci_pmp_detach,
7d50b60b 354
029cfd6b
TH		 355 .enable_pm = ahci_enable_alpm,
356 .disable_pm = ahci_disable_alpm,
18f7ba4c
KCA		 357 .em_show = ahci_led_show,
358 .em_store = ahci_led_store,
359 .sw_activity_show = ahci_activity_show,
360 .sw_activity_store = ahci_activity_store,
438ac6d5 361#ifdef CONFIG_PM
ad616ffb
TH		 362 .port_suspend = ahci_port_suspend,
363 .port_resume = ahci_port_resume,
438ac6d5 364#endif
ad616ffb
TH		 365 .port_start = ahci_port_start,
366 .port_stop = ahci_port_stop,
367};
368
029cfd6b
TH		 369static struct ata_port_operations ahci_vt8251_ops = {
370 .inherits = &ahci_ops,
a1efdaba 371 .hardreset = ahci_vt8251_hardreset,
029cfd6b 372};
edc93052 373
029cfd6b
TH		 374static struct ata_port_operations ahci_p5wdh_ops = {
375 .inherits = &ahci_ops,
a1efdaba 376 .hardreset = ahci_p5wdh_hardreset,
edc93052
TH		 377};
378
bd17243a
SH		 379static struct ata_port_operations ahci_sb600_ops = {
380 .inherits = &ahci_ops,
381 .softreset = ahci_sb600_softreset,
382 .pmp_softreset = ahci_sb600_softreset,
383};
384
417a1a6d
TH		 385#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
386
98ac62de 387static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 388 /* board_ahci */
389 {
1188c0d8 390 .flags = AHCI_FLAG_COMMON,
7da79312 391 .pio_mask = 0x1f, /* pio0-4 */
469248ab 392 .udma_mask = ATA_UDMA6,
1da177e4
LT		 393 .port_ops = &ahci_ops,
394 },
bf2af2a2
BJ		 395 /* board_ahci_vt8251 */
396 {
6949b914 397 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 398 .flags = AHCI_FLAG_COMMON,
bf2af2a2 399 .pio_mask = 0x1f, /* pio0-4 */
469248ab 400 .udma_mask = ATA_UDMA6,
ad616ffb 401 .port_ops = &ahci_vt8251_ops,
bf2af2a2 402 },
41669553
TH		 403 /* board_ahci_ign_iferr */
404 {
417a1a6d
TH		 405 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
406 .flags = AHCI_FLAG_COMMON,
41669553 407 .pio_mask = 0x1f, /* pio0-4 */
469248ab 408 .udma_mask = ATA_UDMA6,
41669553
TH		 409 .port_ops = &ahci_ops,
410 },
55a61604
CH		 411 /* board_ahci_sb600 */
412 {
417a1a6d 413 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
22b5e7a7 414 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
bd17243a 415 AHCI_HFLAG_SECT255),
417a1a6d 416 .flags = AHCI_FLAG_COMMON,
55a61604 417 .pio_mask = 0x1f, /* pio0-4 */
469248ab 418 .udma_mask = ATA_UDMA6,
bd17243a 419 .port_ops = &ahci_sb600_ops,
55a61604 420 },
cd70c266
JG		 421 /* board_ahci_mv */
422 {
417a1a6d 423 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
17248461 424 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
cd70c266 425 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 426 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
cd70c266
JG		 427 .pio_mask = 0x1f, /* pio0-4 */
428 .udma_mask = ATA_UDMA6,
429 .port_ops = &ahci_ops,
430 },
e39fc8c9
SH		 431 /* board_ahci_sb700 */
432 {
bd17243a 433 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
e39fc8c9 434 .flags = AHCI_FLAG_COMMON,
e39fc8c9
SH		 435 .pio_mask = 0x1f, /* pio0-4 */
436 .udma_mask = ATA_UDMA6,
bd17243a 437 .port_ops = &ahci_sb600_ops,
e39fc8c9 438 },
e297d99e
TH		 439 /* board_ahci_mcp65 */
440 {
441 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
442 .flags = AHCI_FLAG_COMMON,
443 .pio_mask = 0x1f, /* pio0-4 */
444 .udma_mask = ATA_UDMA6,
445 .port_ops = &ahci_ops,
446 },
9a3b103c
TH		 447 /* board_ahci_nopmp */
448 {
449 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
450 .flags = AHCI_FLAG_COMMON,
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = ATA_UDMA6,
453 .port_ops = &ahci_ops,
454 },
1da177e4
LT		 455};
456
3b7d697d 457static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 458 /* Intel */
54bb3a94
JG		 459 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
460 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
461 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
462 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
463 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 464 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 465 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
468 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 469 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
472 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
474 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
479 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
484 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
485 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 486 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
487 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 488 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
489 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
adcb5308 490 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
8e48b6b3 491 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
adcb5308 492 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
8e48b6b3 493 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
fe7fa31a 494
e34bb370
TH		 495 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
496 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
497 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 498
499 /* ATI */
c65ec1c2 500 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 501 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
504 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
505 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
506 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 507
508 /* VIA */
54bb3a94 509 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 510 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 511
512 /* NVIDIA */
e297d99e
TH		 513 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
6fbf5ba4
PC		 521 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 525 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 533 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 557 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 561 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
70d562cf 569 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
3072c379 577 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
580 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
fe7fa31a 581
95916edd 582 /* SiS */
20e2de4a
TH		 583 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
584 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
585 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 586
cd70c266
JG		 587 /* Marvell */
588 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
c40e7cb8 589 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
cd70c266 590
c77a036b
MN		 591 /* Promise */
592 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
593
415ae2b5
JG		 594 /* Generic, PCI class code for AHCI */
595 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 596 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 597
1da177e4
LT		 598 { } /* terminate list */
599};
600
601
602static struct pci_driver ahci_pci_driver = {
603 .name = DRV_NAME,
604 .id_table = ahci_pci_tbl,
605 .probe = ahci_init_one,
24dc5f33 606 .remove = ata_pci_remove_one,
438ac6d5 607#ifdef CONFIG_PM
c1332875
TH		 608 .suspend = ahci_pci_device_suspend,
609 .resume = ahci_pci_device_resume,
438ac6d5 610#endif
1da177e4
LT		 611};
612
18f7ba4c
KCA		 613static int ahci_em_messages = 1;
614module_param(ahci_em_messages, int, 0444);
615/* add other LED protocol types when they become supported */
616MODULE_PARM_DESC(ahci_em_messages,
617 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
1da177e4 618
5b66c829
AC		 619#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
620static int marvell_enable;
621#else
622static int marvell_enable = 1;
623#endif
624module_param(marvell_enable, int, 0644);
625MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
626
627
98fa4b60
TH		 628static inline int ahci_nr_ports(u32 cap)
629{
630 return (cap & 0x1f) + 1;
631}
632
dab632e8
JG		 633static inline void __iomem *__ahci_port_base(struct ata_host *host,
634 unsigned int port_no)
1da177e4 635{
dab632e8 636 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 637
dab632e8
JG		 638 return mmio + 0x100 + (port_no * 0x80);
639}
640
641static inline void __iomem *ahci_port_base(struct ata_port *ap)
642{
643 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 644}
645
b710a1f4
TH		 646static void ahci_enable_ahci(void __iomem *mmio)
647{
15fe982e 648 int i;
b710a1f4
TH		 649 u32 tmp;
650
651 /* turn on AHCI_EN */
652 tmp = readl(mmio + HOST_CTL);
15fe982e
TH		 653 if (tmp & HOST_AHCI_EN)
654 return;
655
656 /* Some controllers need AHCI_EN to be written multiple times.
657 * Try a few times before giving up.
658 */
659 for (i = 0; i < 5; i++) {
b710a1f4
TH		 660 tmp |= HOST_AHCI_EN;
661 writel(tmp, mmio + HOST_CTL);
662 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
15fe982e
TH		 663 if (tmp & HOST_AHCI_EN)
664 return;
665 msleep(10);
b710a1f4 666 }
15fe982e
TH		 667
668 WARN_ON(1);
b710a1f4
TH		 669}
670
d447df14
TH		 671/**
672 * ahci_save_initial_config - Save and fixup initial config values
4447d351 673 * @pdev: target PCI device
4447d351 674 * @hpriv: host private area to store config values
d447df14
TH		 675 *
676 * Some registers containing configuration info might be setup by
677 * BIOS and might be cleared on reset. This function saves the
678 * initial values of those registers into @hpriv such that they
679 * can be restored after controller reset.
680 *
681 * If inconsistent, config values are fixed up by this function.
682 *
683 * LOCKING:
684 * None.
685 */
4447d351 686static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 687 struct ahci_host_priv *hpriv)
d447df14 688{
4447d351 689 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 690 u32 cap, port_map;
17199b18 691 int i;
c40e7cb8 692 int mv;
d447df14 693
b710a1f4
TH		 694 /* make sure AHCI mode is enabled before accessing CAP */
695 ahci_enable_ahci(mmio);
696
d447df14
TH		 697 /* Values prefixed with saved_ are written back to host after
698 * reset. Values without are used for driver operation.
699 */
700 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
701 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
702
274c1fde 703 /* some chips have errata preventing 64bit use */
417a1a6d 704 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 705 dev_printk(KERN_INFO, &pdev->dev,
706 "controller can't do 64bit DMA, forcing 32bit\n");
707 cap &= ~HOST_CAP_64;
708 }
709
417a1a6d 710 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 711 dev_printk(KERN_INFO, &pdev->dev,
712 "controller can't do NCQ, turning off CAP_NCQ\n");
713 cap &= ~HOST_CAP_NCQ;
714 }
715
e297d99e
TH		 716 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
717 dev_printk(KERN_INFO, &pdev->dev,
718 "controller can do NCQ, turning on CAP_NCQ\n");
719 cap |= HOST_CAP_NCQ;
720 }
721
258cd846 722 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 723 dev_printk(KERN_INFO, &pdev->dev,
724 "controller can't do PMP, turning off CAP_PMP\n");
725 cap &= ~HOST_CAP_PMP;
726 }
727
d799e083
TH		 728 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
729 port_map != 1) {
730 dev_printk(KERN_INFO, &pdev->dev,
731 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
732 port_map, 1);
733 port_map = 1;
734 }
735
cd70c266
JG		 736 /*
737 * Temporary Marvell 6145 hack: PATA port presence
738 * is asserted through the standard AHCI port
739 * presence register, as bit 4 (counting from 0)
740 */
417a1a6d 741 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 742 if (pdev->device == 0x6121)
743 mv = 0x3;
744 else
745 mv = 0xf;
cd70c266
JG		 746 dev_printk(KERN_ERR, &pdev->dev,
747 "MV_AHCI HACK: port_map %x -> %x\n",
c40e7cb8
JAR		 748 port_map,
749 port_map & mv);
5b66c829
AC		 750 dev_printk(KERN_ERR, &pdev->dev,
751 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
cd70c266 752
c40e7cb8 753 port_map &= mv;
cd70c266
JG		 754 }
755
17199b18 756 /* cross check port_map and cap.n_ports */
7a234aff 757 if (port_map) {
837f5f8f 758 int map_ports = 0;
17199b18 759
837f5f8f
TH		 760 for (i = 0; i < AHCI_MAX_PORTS; i++)
761 if (port_map & (1 << i))
762 map_ports++;
17199b18 763
837f5f8f
TH		 764 /* If PI has more ports than n_ports, whine, clear
765 * port_map and let it be generated from n_ports.
17199b18 766 */
837f5f8f 767 if (map_ports > ahci_nr_ports(cap)) {
4447d351 768 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 769 "implemented port map (0x%x) contains more "
770 "ports than nr_ports (%u), using nr_ports\n",
771 port_map, ahci_nr_ports(cap));
7a234aff
TH		 772 port_map = 0;
773 }
774 }
775
776 /* fabricate port_map from cap.nr_ports */
777 if (!port_map) {
17199b18 778 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 779 dev_printk(KERN_WARNING, &pdev->dev,
780 "forcing PORTS_IMPL to 0x%x\n", port_map);
781
782 /* write the fixed up value to the PI register */
783 hpriv->saved_port_map = port_map;
17199b18
TH		 784 }
785
d447df14
TH		 786 /* record values to use during operation */
787 hpriv->cap = cap;
788 hpriv->port_map = port_map;
789}
790
791/**
792 * ahci_restore_initial_config - Restore initial config
4447d351 793 * @host: target ATA host
d447df14
TH		 794 *
795 * Restore initial config stored by ahci_save_initial_config().
796 *
797 * LOCKING:
798 * None.
799 */
4447d351 800static void ahci_restore_initial_config(struct ata_host *host)
d447df14 801{
4447d351
TH		 802 struct ahci_host_priv *hpriv = host->private_data;
803 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
804
d447df14
TH		 805 writel(hpriv->saved_cap, mmio + HOST_CAP);
806 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
807 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
808}
809
203ef6c4 810static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 811{
203ef6c4
TH		 812 static const int offset[] = {
813 [SCR_STATUS] = PORT_SCR_STAT,
814 [SCR_CONTROL] = PORT_SCR_CTL,
815 [SCR_ERROR] = PORT_SCR_ERR,
816 [SCR_ACTIVE] = PORT_SCR_ACT,
817 [SCR_NOTIFICATION] = PORT_SCR_NTF,
818 };
819 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 820
203ef6c4
TH		 821 if (sc_reg < ARRAY_SIZE(offset) &&
822 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
823 return offset[sc_reg];
da3dbb17 824 return 0;
1da177e4
LT		 825}
826
82ef04fb 827static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
1da177e4 828{
82ef04fb
TH		 829 void __iomem *port_mmio = ahci_port_base(link->ap);
830 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 831
832 if (offset) {
833 *val = readl(port_mmio + offset);
834 return 0;
1da177e4 835 }
203ef6c4
TH		 836 return -EINVAL;
837}
1da177e4 838
82ef04fb 839static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
203ef6c4 840{
82ef04fb
TH		 841 void __iomem *port_mmio = ahci_port_base(link->ap);
842 int offset = ahci_scr_offset(link->ap, sc_reg);
203ef6c4
TH		 843
844 if (offset) {
845 writel(val, port_mmio + offset);
846 return 0;
847 }
848 return -EINVAL;
1da177e4
LT		 849}
850
4447d351 851static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 852{
4447d351 853 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 854 u32 tmp;
855
d8fcd116 856 /* start DMA */
9f592056 857 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 858 tmp |= PORT_CMD_START;
859 writel(tmp, port_mmio + PORT_CMD);
860 readl(port_mmio + PORT_CMD); /* flush */
861}
862
4447d351 863static int ahci_stop_engine(struct ata_port *ap)
254950cd 864{
4447d351 865 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 866 u32 tmp;
867
868 tmp = readl(port_mmio + PORT_CMD);
869
d8fcd116 870 /* check if the HBA is idle */
254950cd
TH		 871 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
872 return 0;
873
d8fcd116 874 /* setting HBA to idle */
254950cd
TH		 875 tmp &= ~PORT_CMD_START;
876 writel(tmp, port_mmio + PORT_CMD);
877
d8fcd116 878 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 879 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 880 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 881 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 882 return -EIO;
883
884 return 0;
885}
886
4447d351 887static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 888{
4447d351
TH		 889 void __iomem *port_mmio = ahci_port_base(ap);
890 struct ahci_host_priv *hpriv = ap->host->private_data;
891 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 892 u32 tmp;
893
894 /* set FIS registers */
4447d351
TH		 895 if (hpriv->cap & HOST_CAP_64)
896 writel((pp->cmd_slot_dma >> 16) >> 16,
897 port_mmio + PORT_LST_ADDR_HI);
898 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 899
4447d351
TH		 900 if (hpriv->cap & HOST_CAP_64)
901 writel((pp->rx_fis_dma >> 16) >> 16,
902 port_mmio + PORT_FIS_ADDR_HI);
903 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 904
905 /* enable FIS reception */
906 tmp = readl(port_mmio + PORT_CMD);
907 tmp |= PORT_CMD_FIS_RX;
908 writel(tmp, port_mmio + PORT_CMD);
909
910 /* flush */
911 readl(port_mmio + PORT_CMD);
912}
913
4447d351 914static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 915{
4447d351 916 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 917 u32 tmp;
918
919 /* disable FIS reception */
920 tmp = readl(port_mmio + PORT_CMD);
921 tmp &= ~PORT_CMD_FIS_RX;
922 writel(tmp, port_mmio + PORT_CMD);
923
924 /* wait for completion, spec says 500ms, give it 1000 */
925 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
926 PORT_CMD_FIS_ON, 10, 1000);
927 if (tmp & PORT_CMD_FIS_ON)
928 return -EBUSY;
929
930 return 0;
931}
932
4447d351 933static void ahci_power_up(struct ata_port *ap)
0be0aa98 934{
4447d351
TH		 935 struct ahci_host_priv *hpriv = ap->host->private_data;
936 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 937 u32 cmd;
938
939 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
940
941 /* spin up device */
4447d351 942 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 943 cmd |= PORT_CMD_SPIN_UP;
944 writel(cmd, port_mmio + PORT_CMD);
945 }
946
947 /* wake up link */
948 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
949}
950
31556594
KCA		 951static void ahci_disable_alpm(struct ata_port *ap)
952{
953 struct ahci_host_priv *hpriv = ap->host->private_data;
954 void __iomem *port_mmio = ahci_port_base(ap);
955 u32 cmd;
956 struct ahci_port_priv *pp = ap->private_data;
957
958 /* IPM bits should be disabled by libata-core */
959 /* get the existing command bits */
960 cmd = readl(port_mmio + PORT_CMD);
961
962 /* disable ALPM and ASP */
963 cmd &= ~PORT_CMD_ASP;
964 cmd &= ~PORT_CMD_ALPE;
965
966 /* force the interface back to active */
967 cmd |= PORT_CMD_ICC_ACTIVE;
968
969 /* write out new cmd value */
970 writel(cmd, port_mmio + PORT_CMD);
971 cmd = readl(port_mmio + PORT_CMD);
972
973 /* wait 10ms to be sure we've come out of any low power state */
974 msleep(10);
975
976 /* clear out any PhyRdy stuff from interrupt status */
977 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
978
979 /* go ahead and clean out PhyRdy Change from Serror too */
82ef04fb 980 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 981
982 /*
983 * Clear flag to indicate that we should ignore all PhyRdy
984 * state changes
985 */
986 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
987
988 /*
989 * Enable interrupts on Phy Ready.
990 */
991 pp->intr_mask |= PORT_IRQ_PHYRDY;
992 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
993
994 /*
995 * don't change the link pm policy - we can be called
996 * just to turn of link pm temporarily
997 */
998}
999
1000static int ahci_enable_alpm(struct ata_port *ap,
1001 enum link_pm policy)
1002{
1003 struct ahci_host_priv *hpriv = ap->host->private_data;
1004 void __iomem *port_mmio = ahci_port_base(ap);
1005 u32 cmd;
1006 struct ahci_port_priv *pp = ap->private_data;
1007 u32 asp;
1008
1009 /* Make sure the host is capable of link power management */
1010 if (!(hpriv->cap & HOST_CAP_ALPM))
1011 return -EINVAL;
1012
1013 switch (policy) {
1014 case MAX_PERFORMANCE:
1015 case NOT_AVAILABLE:
1016 /*
1017 * if we came here with NOT_AVAILABLE,
1018 * it just means this is the first time we
1019 * have tried to enable - default to max performance,
1020 * and let the user go to lower power modes on request.
1021 */
1022 ahci_disable_alpm(ap);
1023 return 0;
1024 case MIN_POWER:
1025 /* configure HBA to enter SLUMBER */
1026 asp = PORT_CMD_ASP;
1027 break;
1028 case MEDIUM_POWER:
1029 /* configure HBA to enter PARTIAL */
1030 asp = 0;
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035
1036 /*
1037 * Disable interrupts on Phy Ready. This keeps us from
1038 * getting woken up due to spurious phy ready interrupts
1039 * TBD - Hot plug should be done via polling now, is
1040 * that even supported?
1041 */
1042 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1043 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1044
1045 /*
1046 * Set a flag to indicate that we should ignore all PhyRdy
1047 * state changes since these can happen now whenever we
1048 * change link state
1049 */
1050 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1051
1052 /* get the existing command bits */
1053 cmd = readl(port_mmio + PORT_CMD);
1054
1055 /*
1056 * Set ASP based on Policy
1057 */
1058 cmd |= asp;
1059
1060 /*
1061 * Setting this bit will instruct the HBA to aggressively
1062 * enter a lower power link state when it's appropriate and
1063 * based on the value set above for ASP
1064 */
1065 cmd |= PORT_CMD_ALPE;
1066
1067 /* write out new cmd value */
1068 writel(cmd, port_mmio + PORT_CMD);
1069 cmd = readl(port_mmio + PORT_CMD);
1070
1071 /* IPM bits should be set by libata-core */
1072 return 0;
1073}
1074
438ac6d5 1075#ifdef CONFIG_PM
4447d351 1076static void ahci_power_down(struct ata_port *ap)
0be0aa98 1077{
4447d351
TH		 1078 struct ahci_host_priv *hpriv = ap->host->private_data;
1079 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1080 u32 cmd, scontrol;
1081
4447d351 1082 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1083 return;
0be0aa98 1084
07c53dac
TH		 1085 /* put device into listen mode, first set PxSCTL.DET to 0 */
1086 scontrol = readl(port_mmio + PORT_SCR_CTL);
1087 scontrol &= ~0xf;
1088 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1089
07c53dac
TH		 1090 /* then set PxCMD.SUD to 0 */
1091 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1092 cmd &= ~PORT_CMD_SPIN_UP;
1093 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1094}
438ac6d5 1095#endif
0be0aa98 1096
df69c9c5 1097static void ahci_start_port(struct ata_port *ap)
0be0aa98 1098{
18f7ba4c
KCA		 1099 struct ahci_port_priv *pp = ap->private_data;
1100 struct ata_link *link;
1101 struct ahci_em_priv *emp;
1102
0be0aa98 1103 /* enable FIS reception */
4447d351 1104 ahci_start_fis_rx(ap);
0be0aa98
TH		 1105
1106 /* enable DMA */
4447d351 1107 ahci_start_engine(ap);
18f7ba4c
KCA		 1108
1109 /* turn on LEDs */
1110 if (ap->flags & ATA_FLAG_EM) {
1111 ata_port_for_each_link(link, ap) {
1112 emp = &pp->em_priv[link->pmp];
1113 ahci_transmit_led_message(ap, emp->led_state, 4);
1114 }
1115 }
1116
1117 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1118 ata_port_for_each_link(link, ap)
1119 ahci_init_sw_activity(link);
1120
0be0aa98
TH		 1121}
1122
4447d351 1123static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1124{
1125 int rc;
1126
1127 /* disable DMA */
4447d351 1128 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1129 if (rc) {
1130 *emsg = "failed to stop engine";
1131 return rc;
1132 }
1133
1134 /* disable FIS reception */
4447d351 1135 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1136 if (rc) {
1137 *emsg = "failed stop FIS RX";
1138 return rc;
1139 }
1140
0be0aa98
TH		 1141 return 0;
1142}
1143
4447d351 1144static int ahci_reset_controller(struct ata_host *host)
d91542c1 1145{
4447d351 1146 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1147 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1148 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1149 u32 tmp;
d91542c1 1150
3cc3eb11
JG		 1151 /* we must be in AHCI mode, before using anything
1152 * AHCI-specific, such as HOST_RESET.
1153 */
b710a1f4 1154 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1155
1156 /* global controller reset */
a22e6444
TH		 1157 if (!ahci_skip_host_reset) {
1158 tmp = readl(mmio + HOST_CTL);
1159 if ((tmp & HOST_RESET) == 0) {
1160 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1161 readl(mmio + HOST_CTL); /* flush */
1162 }
d91542c1 1163
24920c8a
ZR		 1164 /*
1165 * to perform host reset, OS should set HOST_RESET
1166 * and poll until this bit is read to be "0".
1167 * reset must complete within 1 second, or
a22e6444
TH		 1168 * the hardware should be considered fried.
1169 */
24920c8a
ZR		 1170 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1171 HOST_RESET, 10, 1000);
d91542c1 1172
a22e6444
TH		 1173 if (tmp & HOST_RESET) {
1174 dev_printk(KERN_ERR, host->dev,
1175 "controller reset failed (0x%x)\n", tmp);
1176 return -EIO;
1177 }
d91542c1 1178
a22e6444
TH		 1179 /* turn on AHCI mode */
1180 ahci_enable_ahci(mmio);
98fa4b60 1181
a22e6444
TH		 1182 /* Some registers might be cleared on reset. Restore
1183 * initial values.
1184 */
1185 ahci_restore_initial_config(host);
1186 } else
1187 dev_printk(KERN_INFO, host->dev,
1188 "skipping global host reset\n");
d91542c1
TH		 1189
1190 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1191 u16 tmp16;
1192
1193 /* configure PCS */
1194 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1195 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1196 tmp16 |= hpriv->port_map;
1197 pci_write_config_word(pdev, 0x92, tmp16);
1198 }
d91542c1
TH		 1199 }
1200
1201 return 0;
1202}
1203
18f7ba4c
KCA		 1204static void ahci_sw_activity(struct ata_link *link)
1205{
1206 struct ata_port *ap = link->ap;
1207 struct ahci_port_priv *pp = ap->private_data;
1208 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1209
1210 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1211 return;
1212
1213 emp->activity++;
1214 if (!timer_pending(&emp->timer))
1215 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1216}
1217
1218static void ahci_sw_activity_blink(unsigned long arg)
1219{
1220 struct ata_link *link = (struct ata_link *)arg;
1221 struct ata_port *ap = link->ap;
1222 struct ahci_port_priv *pp = ap->private_data;
1223 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1224 unsigned long led_message = emp->led_state;
1225 u32 activity_led_state;
eb40963c 1226 unsigned long flags;
18f7ba4c
KCA		 1227
1228 led_message &= 0xffff0000;
1229 led_message |= ap->port_no | (link->pmp << 8);
1230
1231 /* check to see if we've had activity. If so,
1232 * toggle state of LED and reset timer. If not,
1233 * turn LED to desired idle state.
1234 */
eb40963c 1235 spin_lock_irqsave(ap->lock, flags);
18f7ba4c
KCA		 1236 if (emp->saved_activity != emp->activity) {
1237 emp->saved_activity = emp->activity;
1238 /* get the current LED state */
1239 activity_led_state = led_message & 0x00010000;
1240
1241 if (activity_led_state)
1242 activity_led_state = 0;
1243 else
1244 activity_led_state = 1;
1245
1246 /* clear old state */
1247 led_message &= 0xfff8ffff;
1248
1249 /* toggle state */
1250 led_message |= (activity_led_state << 16);
1251 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1252 } else {
1253 /* switch to idle */
1254 led_message &= 0xfff8ffff;
1255 if (emp->blink_policy == BLINK_OFF)
1256 led_message |= (1 << 16);
1257 }
eb40963c 1258 spin_unlock_irqrestore(ap->lock, flags);
18f7ba4c
KCA		 1259 ahci_transmit_led_message(ap, led_message, 4);
1260}
1261
1262static void ahci_init_sw_activity(struct ata_link *link)
1263{
1264 struct ata_port *ap = link->ap;
1265 struct ahci_port_priv *pp = ap->private_data;
1266 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1267
1268 /* init activity stats, setup timer */
1269 emp->saved_activity = emp->activity = 0;
1270 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1271
1272 /* check our blink policy and set flag for link if it's enabled */
1273 if (emp->blink_policy)
1274 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1275}
1276
1277static int ahci_reset_em(struct ata_host *host)
1278{
1279 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1280 u32 em_ctl;
1281
1282 em_ctl = readl(mmio + HOST_EM_CTL);
1283 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1284 return -EINVAL;
1285
1286 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1287 return 0;
1288}
1289
1290static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1291 ssize_t size)
1292{
1293 struct ahci_host_priv *hpriv = ap->host->private_data;
1294 struct ahci_port_priv *pp = ap->private_data;
1295 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1296 u32 em_ctl;
1297 u32 message[] = {0, 0};
93082f0b 1298 unsigned long flags;
18f7ba4c
KCA		 1299 int pmp;
1300 struct ahci_em_priv *emp;
1301
1302 /* get the slot number from the message */
1303 pmp = (state & 0x0000ff00) >> 8;
1304 if (pmp < MAX_SLOTS)
1305 emp = &pp->em_priv[pmp];
1306 else
1307 return -EINVAL;
1308
1309 spin_lock_irqsave(ap->lock, flags);
1310
1311 /*
1312 * if we are still busy transmitting a previous message,
1313 * do not allow
1314 */
1315 em_ctl = readl(mmio + HOST_EM_CTL);
1316 if (em_ctl & EM_CTL_TM) {
1317 spin_unlock_irqrestore(ap->lock, flags);
1318 return -EINVAL;
1319 }
1320
1321 /*
1322 * create message header - this is all zero except for
1323 * the message size, which is 4 bytes.
1324 */
1325 message[0] |= (4 << 8);
1326
1327 /* ignore 0:4 of byte zero, fill in port info yourself */
1328 message[1] = ((state & 0xfffffff0) | ap->port_no);
1329
1330 /* write message to EM_LOC */
1331 writel(message[0], mmio + hpriv->em_loc);
1332 writel(message[1], mmio + hpriv->em_loc+4);
1333
1334 /* save off new led state for port/slot */
1335 emp->led_state = message[1];
1336
1337 /*
1338 * tell hardware to transmit the message
1339 */
1340 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1341
1342 spin_unlock_irqrestore(ap->lock, flags);
1343 return size;
1344}
1345
1346static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1347{
1348 struct ahci_port_priv *pp = ap->private_data;
1349 struct ata_link *link;
1350 struct ahci_em_priv *emp;
1351 int rc = 0;
1352
1353 ata_port_for_each_link(link, ap) {
1354 emp = &pp->em_priv[link->pmp];
1355 rc += sprintf(buf, "%lx\n", emp->led_state);
1356 }
1357 return rc;
1358}
1359
1360static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1361 size_t size)
1362{
1363 int state;
1364 int pmp;
1365 struct ahci_port_priv *pp = ap->private_data;
1366 struct ahci_em_priv *emp;
1367
1368 state = simple_strtoul(buf, NULL, 0);
1369
1370 /* get the slot number from the message */
1371 pmp = (state & 0x0000ff00) >> 8;
1372 if (pmp < MAX_SLOTS)
1373 emp = &pp->em_priv[pmp];
1374 else
1375 return -EINVAL;
1376
1377 /* mask off the activity bits if we are in sw_activity
1378 * mode, user should turn off sw_activity before setting
1379 * activity led through em_message
1380 */
1381 if (emp->blink_policy)
1382 state &= 0xfff8ffff;
1383
1384 return ahci_transmit_led_message(ap, state, size);
1385}
1386
1387static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1388{
1389 struct ata_link *link = dev->link;
1390 struct ata_port *ap = link->ap;
1391 struct ahci_port_priv *pp = ap->private_data;
1392 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1393 u32 port_led_state = emp->led_state;
1394
1395 /* save the desired Activity LED behavior */
1396 if (val == OFF) {
1397 /* clear LFLAG */
1398 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1399
1400 /* set the LED to OFF */
1401 port_led_state &= 0xfff80000;
1402 port_led_state |= (ap->port_no | (link->pmp << 8));
1403 ahci_transmit_led_message(ap, port_led_state, 4);
1404 } else {
1405 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1406 if (val == BLINK_OFF) {
1407 /* set LED to ON for idle */
1408 port_led_state &= 0xfff80000;
1409 port_led_state |= (ap->port_no | (link->pmp << 8));
1410 port_led_state |= 0x00010000; /* check this */
1411 ahci_transmit_led_message(ap, port_led_state, 4);
1412 }
1413 }
1414 emp->blink_policy = val;
1415 return 0;
1416}
1417
1418static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1419{
1420 struct ata_link *link = dev->link;
1421 struct ata_port *ap = link->ap;
1422 struct ahci_port_priv *pp = ap->private_data;
1423 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1424
1425 /* display the saved value of activity behavior for this
1426 * disk.
1427 */
1428 return sprintf(buf, "%d\n", emp->blink_policy);
1429}
1430
2bcd866b
JG		 1431static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1432 int port_no, void __iomem *mmio,
1433 void __iomem *port_mmio)
1434{
1435 const char *emsg = NULL;
1436 int rc;
1437 u32 tmp;
1438
1439 /* make sure port is not active */
1440 rc = ahci_deinit_port(ap, &emsg);
1441 if (rc)
1442 dev_printk(KERN_WARNING, &pdev->dev,
1443 "%s (%d)\n", emsg, rc);
1444
1445 /* clear SError */
1446 tmp = readl(port_mmio + PORT_SCR_ERR);
1447 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1448 writel(tmp, port_mmio + PORT_SCR_ERR);
1449
1450 /* clear port IRQ */
1451 tmp = readl(port_mmio + PORT_IRQ_STAT);
1452 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1453 if (tmp)
1454 writel(tmp, port_mmio + PORT_IRQ_STAT);
1455
1456 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1457}
1458
4447d351 1459static void ahci_init_controller(struct ata_host *host)
d91542c1 1460{
417a1a6d 1461 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1462 struct pci_dev *pdev = to_pci_dev(host->dev);
1463 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1464 int i;
cd70c266 1465 void __iomem *port_mmio;
d91542c1 1466 u32 tmp;
c40e7cb8 1467 int mv;
d91542c1 1468
417a1a6d 1469 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
c40e7cb8
JAR		 1470 if (pdev->device == 0x6121)
1471 mv = 2;
1472 else
1473 mv = 4;
1474 port_mmio = __ahci_port_base(host, mv);
cd70c266
JG		 1475
1476 writel(0, port_mmio + PORT_IRQ_MASK);
1477
1478 /* clear port IRQ */
1479 tmp = readl(port_mmio + PORT_IRQ_STAT);
1480 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1481 if (tmp)
1482 writel(tmp, port_mmio + PORT_IRQ_STAT);
1483 }
1484
4447d351
TH		 1485 for (i = 0; i < host->n_ports; i++) {
1486 struct ata_port *ap = host->ports[i];
d91542c1 1487
cd70c266 1488 port_mmio = ahci_port_base(ap);
4447d351 1489 if (ata_port_is_dummy(ap))
d91542c1 1490 continue;
d91542c1 1491
2bcd866b 1492 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1493 }
1494
1495 tmp = readl(mmio + HOST_CTL);
1496 VPRINTK("HOST_CTL 0x%x\n", tmp);
1497 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1498 tmp = readl(mmio + HOST_CTL);
1499 VPRINTK("HOST_CTL 0x%x\n", tmp);
1500}
1501
a878539e
JG		 1502static void ahci_dev_config(struct ata_device *dev)
1503{
1504 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1505
4cde32fc 1506 if (hpriv->flags & AHCI_HFLAG_SECT255) {
a878539e 1507 dev->max_sectors = 255;
4cde32fc
JG		 1508 ata_dev_printk(dev, KERN_INFO,
1509 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1510 }
a878539e
JG		 1511}
1512
422b7595 1513static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1514{
4447d351 1515 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1516 struct ata_taskfile tf;
422b7595
TH		 1517 u32 tmp;
1518
1519 tmp = readl(port_mmio + PORT_SIG);
1520 tf.lbah = (tmp >> 24) & 0xff;
1521 tf.lbam = (tmp >> 16) & 0xff;
1522 tf.lbal = (tmp >> 8) & 0xff;
1523 tf.nsect = (tmp) & 0xff;
1524
1525 return ata_dev_classify(&tf);
1526}
1527
12fad3f9
TH		 1528static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1529 u32 opts)
cc9278ed 1530{
12fad3f9
TH		 1531 dma_addr_t cmd_tbl_dma;
1532
1533 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1534
1535 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1536 pp->cmd_slot[tag].status = 0;
1537 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1538 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1539}
1540
d2e75dff 1541static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1542{
350756f6 1543 void __iomem *port_mmio = ahci_port_base(ap);
cca3974e 1544 struct ahci_host_priv *hpriv = ap->host->private_data;
520d06f9 1545 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
bf2af2a2 1546 u32 tmp;
d2e75dff 1547 int busy, rc;
bf2af2a2 1548
d2e75dff 1549 /* do we need to kick the port? */
520d06f9 1550 busy = status & (ATA_BUSY | ATA_DRQ);
d2e75dff
TH		 1551 if (!busy && !force_restart)
1552 return 0;
1553
1554 /* stop engine */
1555 rc = ahci_stop_engine(ap);
1556 if (rc)
1557 goto out_restart;
1558
1559 /* need to do CLO? */
1560 if (!busy) {
1561 rc = 0;
1562 goto out_restart;
1563 }
1564
1565 if (!(hpriv->cap & HOST_CAP_CLO)) {
1566 rc = -EOPNOTSUPP;
1567 goto out_restart;
1568 }
bf2af2a2 1569
d2e75dff 1570 /* perform CLO */
bf2af2a2
BJ		 1571 tmp = readl(port_mmio + PORT_CMD);
1572 tmp |= PORT_CMD_CLO;
1573 writel(tmp, port_mmio + PORT_CMD);
1574
d2e75dff 1575 rc = 0;
bf2af2a2
BJ		 1576 tmp = ata_wait_register(port_mmio + PORT_CMD,
1577 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1578 if (tmp & PORT_CMD_CLO)
d2e75dff 1579 rc = -EIO;
bf2af2a2 1580
d2e75dff
TH		 1581 /* restart engine */
1582 out_restart:
1583 ahci_start_engine(ap);
1584 return rc;
bf2af2a2
BJ		 1585}
1586
91c4a2e0
TH		 1587static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1588 struct ata_taskfile *tf, int is_cmd, u16 flags,
1589 unsigned long timeout_msec)
bf2af2a2 1590{
91c4a2e0 1591 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1592 struct ahci_port_priv *pp = ap->private_data;
4447d351 1593 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1594 u8 *fis = pp->cmd_tbl;
1595 u32 tmp;
1596
1597 /* prep the command */
1598 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1599 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1600
1601 /* issue & wait */
1602 writel(1, port_mmio + PORT_CMD_ISSUE);
1603
1604 if (timeout_msec) {
1605 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1606 1, timeout_msec);
1607 if (tmp & 0x1) {
1608 ahci_kick_engine(ap, 1);
1609 return -EBUSY;
1610 }
1611 } else
1612 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1613
1614 return 0;
1615}
1616
bd17243a
SH		 1617static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1618 int pmp, unsigned long deadline,
1619 int (*check_ready)(struct ata_link *link))
91c4a2e0 1620{
cc0680a5 1621 struct ata_port *ap = link->ap;
4658f79b 1622 const char *reason = NULL;
2cbb79eb 1623 unsigned long now, msecs;
4658f79b 1624 struct ata_taskfile tf;
4658f79b
TH		 1625 int rc;
1626
1627 DPRINTK("ENTER\n");
1628
1629 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1630 rc = ahci_kick_engine(ap, 1);
994056d7 1631 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1632 ata_link_printk(link, KERN_WARNING,
994056d7 1633 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1634
cc0680a5 1635 ata_tf_init(link->device, &tf);
4658f79b
TH		 1636
1637 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1638 msecs = 0;
1639 now = jiffies;
1640 if (time_after(now, deadline))
1641 msecs = jiffies_to_msecs(deadline - now);
1642
4658f79b 1643 tf.ctl |= ATA_SRST;
a9cf5e85 1644 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1645 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1646 rc = -EIO;
1647 reason = "1st FIS failed";
1648 goto fail;
1649 }
1650
1651 /* spec says at least 5us, but be generous and sleep for 1ms */
1652 msleep(1);
1653
1654 /* issue the second D2H Register FIS */
4658f79b 1655 tf.ctl &= ~ATA_SRST;
a9cf5e85 1656 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1657
705e76be 1658 /* wait for link to become ready */
bd17243a 1659 rc = ata_wait_after_reset(link, deadline, check_ready);
9b89391c
TH		 1660 /* link occupied, -ENODEV too is an error */
1661 if (rc) {
1662 reason = "device not ready";
1663 goto fail;
4658f79b 1664 }
9b89391c 1665 *class = ahci_dev_classify(ap);
4658f79b
TH		 1666
1667 DPRINTK("EXIT, class=%u\n", *class);
1668 return 0;
1669
4658f79b 1670 fail:
cc0680a5 1671 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1672 return rc;
1673}
1674
bd17243a
SH		 1675static int ahci_check_ready(struct ata_link *link)
1676{
1677 void __iomem *port_mmio = ahci_port_base(link->ap);
1678 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1679
1680 return ata_check_ready(status);
1681}
1682
1683static int ahci_softreset(struct ata_link *link, unsigned int *class,
1684 unsigned long deadline)
1685{
1686 int pmp = sata_srst_pmp(link);
1687
1688 DPRINTK("ENTER\n");
1689
1690 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1691}
1692
1693static int ahci_sb600_check_ready(struct ata_link *link)
1694{
1695 void __iomem *port_mmio = ahci_port_base(link->ap);
1696 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1697 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1698
1699 /*
1700 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1701 * which can save timeout delay.
1702 */
1703 if (irq_status & PORT_IRQ_BAD_PMP)
1704 return -EIO;
1705
1706 return ata_check_ready(status);
1707}
1708
1709static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1710 unsigned long deadline)
1711{
1712 struct ata_port *ap = link->ap;
1713 void __iomem *port_mmio = ahci_port_base(ap);
1714 int pmp = sata_srst_pmp(link);
1715 int rc;
1716 u32 irq_sts;
1717
1718 DPRINTK("ENTER\n");
1719
1720 rc = ahci_do_softreset(link, class, pmp, deadline,
1721 ahci_sb600_check_ready);
1722
1723 /*
1724 * Soft reset fails on some ATI chips with IPMS set when PMP
1725 * is enabled but SATA HDD/ODD is connected to SATA port,
1726 * do soft reset again to port 0.
1727 */
1728 if (rc == -EIO) {
1729 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1730 if (irq_sts & PORT_IRQ_BAD_PMP) {
1731 ata_link_printk(link, KERN_WARNING,
1732 "failed due to HW bug, retry pmp=0\n");
1733 rc = ahci_do_softreset(link, class, 0, deadline,
1734 ahci_check_ready);
1735 }
1736 }
1737
1738 return rc;
1739}
1740
cc0680a5 1741static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1742 unsigned long deadline)
422b7595 1743{
9dadd45b 1744 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
cc0680a5 1745 struct ata_port *ap = link->ap;
4296971d
TH		 1746 struct ahci_port_priv *pp = ap->private_data;
1747 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1748 struct ata_taskfile tf;
9dadd45b 1749 bool online;
4bd00f6a
TH		 1750 int rc;
1751
1752 DPRINTK("ENTER\n");
1da177e4 1753
4447d351 1754 ahci_stop_engine(ap);
4296971d
TH		 1755
1756 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1757 ata_tf_init(link->device, &tf);
dfd7a3db 1758 tf.command = 0x80;
9977126c 1759 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1760
9dadd45b
TH		 1761 rc = sata_link_hardreset(link, timing, deadline, &online,
1762 ahci_check_ready);
4296971d 1763
4447d351 1764 ahci_start_engine(ap);
1da177e4 1765
9dadd45b 1766 if (online)
4bd00f6a 1767 *class = ahci_dev_classify(ap);
1da177e4 1768
4bd00f6a
TH		 1769 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1770 return rc;
1771}
1772
cc0680a5 1773static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1774 unsigned long deadline)
ad616ffb 1775{
cc0680a5 1776 struct ata_port *ap = link->ap;
9dadd45b 1777 bool online;
ad616ffb
TH		 1778 int rc;
1779
1780 DPRINTK("ENTER\n");
1781
4447d351 1782 ahci_stop_engine(ap);
ad616ffb 1783
cc0680a5 1784 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1785 deadline, &online, NULL);
ad616ffb 1786
4447d351 1787 ahci_start_engine(ap);
ad616ffb
TH		 1788
1789 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1790
1791 /* vt8251 doesn't clear BSY on signature FIS reception,
1792 * request follow-up softreset.
1793 */
9dadd45b 1794 return online ? -EAGAIN : rc;
ad616ffb
TH		 1795}
1796
edc93052
TH		 1797static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1798 unsigned long deadline)
1799{
1800 struct ata_port *ap = link->ap;
1801 struct ahci_port_priv *pp = ap->private_data;
1802 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1803 struct ata_taskfile tf;
9dadd45b 1804 bool online;
edc93052
TH		 1805 int rc;
1806
1807 ahci_stop_engine(ap);
1808
1809 /* clear D2H reception area to properly wait for D2H FIS */
1810 ata_tf_init(link->device, &tf);
1811 tf.command = 0x80;
1812 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1813
1814 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
9dadd45b 1815 deadline, &online, NULL);
edc93052
TH		 1816
1817 ahci_start_engine(ap);
1818
edc93052
TH		 1819 /* The pseudo configuration device on SIMG4726 attached to
1820 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1821 * hardreset if no device is attached to the first downstream
1822 * port && the pseudo device locks up on SRST w/ PMP==0. To
1823 * work around this, wait for !BSY only briefly. If BSY isn't
1824 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1825 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1826 *
1827 * Wait for two seconds. Devices attached to downstream port
1828 * which can't process the following IDENTIFY after this will
1829 * have to be reset again. For most cases, this should
1830 * suffice while making probing snappish enough.
1831 */
9dadd45b
TH		 1832 if (online) {
1833 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1834 ahci_check_ready);
1835 if (rc)
1836 ahci_kick_engine(ap, 0);
1837 }
9dadd45b 1838 return rc;
edc93052
TH		 1839}
1840
cc0680a5 1841static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1842{
cc0680a5 1843 struct ata_port *ap = link->ap;
4447d351 1844 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1845 u32 new_tmp, tmp;
1846
203c75b8 1847 ata_std_postreset(link, class);
02eaa666
JG		 1848
1849 /* Make sure port's ATAPI bit is set appropriately */
1850 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1851 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1852 new_tmp |= PORT_CMD_ATAPI;
1853 else
1854 new_tmp &= ~PORT_CMD_ATAPI;
1855 if (new_tmp != tmp) {
1856 writel(new_tmp, port_mmio + PORT_CMD);
1857 readl(port_mmio + PORT_CMD); /* flush */
1858 }
1da177e4
LT		 1859}
1860
12fad3f9 1861static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1862{
cedc9a47 1863 struct scatterlist *sg;
ff2aeb1e
TH		 1864 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1865 unsigned int si;
1da177e4
LT		 1866
1867 VPRINTK("ENTER\n");
1868
1869 /*
1870 * Next, the S/G list.
1871 */
ff2aeb1e 1872 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1873 dma_addr_t addr = sg_dma_address(sg);
1874 u32 sg_len = sg_dma_len(sg);
1875
ff2aeb1e
TH		 1876 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1877 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1878 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1879 }
828d09de 1880
ff2aeb1e 1881 return si;
1da177e4
LT		 1882}
1883
1884static void ahci_qc_prep(struct ata_queued_cmd *qc)
1885{
a0ea7328
JG		 1886 struct ata_port *ap = qc->ap;
1887 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1888 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1889 void *cmd_tbl;
1da177e4
LT		 1890 u32 opts;
1891 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1892 unsigned int n_elem;
1da177e4 1893
1da177e4
LT		 1894 /*
1895 * Fill in command table information. First, the header,
1896 * a SATA Register - Host to Device command FIS.
1897 */
12fad3f9
TH		 1898 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1899
7d50b60b 1900 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1901 if (is_atapi) {
12fad3f9
TH		 1902 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1903 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1904 }
1da177e4 1905
cc9278ed
TH		 1906 n_elem = 0;
1907 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1908 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1909
cc9278ed
TH		 1910 /*
1911 * Fill in command slot information.
1912 */
7d50b60b 1913 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1914 if (qc->tf.flags & ATA_TFLAG_WRITE)
1915 opts |= AHCI_CMD_WRITE;
1916 if (is_atapi)
4b10e559 1917 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1918
12fad3f9 1919 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1920}
1921
78cd52d0 1922static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1923{
417a1a6d 1924 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1925 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1926 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1927 struct ata_link *link = NULL;
1928 struct ata_queued_cmd *active_qc;
1929 struct ata_eh_info *active_ehi;
78cd52d0 1930 u32 serror;
1da177e4 1931
7d50b60b
TH		 1932 /* determine active link */
1933 ata_port_for_each_link(link, ap)
1934 if (ata_link_active(link))
1935 break;
1936 if (!link)
1937 link = &ap->link;
1938
1939 active_qc = ata_qc_from_tag(ap, link->active_tag);
1940 active_ehi = &link->eh_info;
1941
1942 /* record irq stat */
1943 ata_ehi_clear_desc(host_ehi);
1944 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1945
78cd52d0 1946 /* AHCI needs SError cleared; otherwise, it might lock up */
82ef04fb
TH		 1947 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1948 ahci_scr_write(&ap->link, SCR_ERROR, serror);
7d50b60b 1949 host_ehi->serror |= serror;
78cd52d0 1950
41669553 1951 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1952 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1953 irq_stat &= ~PORT_IRQ_IF_ERR;
1954
55a61604 1955 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1956 /* If qc is active, charge it; otherwise, the active
1957 * link. There's no active qc on NCQ errors. It will
1958 * be determined by EH by reading log page 10h.
1959 */
1960 if (active_qc)
1961 active_qc->err_mask |= AC_ERR_DEV;
1962 else
1963 active_ehi->err_mask |= AC_ERR_DEV;
1964
417a1a6d 1965 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1966 host_ehi->serror &= ~SERR_INTERNAL;
1967 }
1968
1969 if (irq_stat & PORT_IRQ_UNK_FIS) {
1970 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1971
1972 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1973 active_ehi->action |= ATA_EH_RESET;
7d50b60b
TH		 1974 ata_ehi_push_desc(active_ehi,
1975 "unknown FIS %08x %08x %08x %08x" ,
1976 unk[0], unk[1], unk[2], unk[3]);
1977 }
1978
071f44b1 1979 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
7d50b60b 1980 active_ehi->err_mask |= AC_ERR_HSM;
cf480626 1981 active_ehi->action |= ATA_EH_RESET;
7d50b60b 1982 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1983 }
78cd52d0
TH		 1984
1985 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b 1986 host_ehi->err_mask |= AC_ERR_HOST_BUS;
cf480626 1987 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1988 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1989 }
1990
78cd52d0 1991 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b 1992 host_ehi->err_mask |= AC_ERR_ATA_BUS;
cf480626 1993 host_ehi->action |= ATA_EH_RESET;
7d50b60b 1994 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1995 }
1da177e4 1996
78cd52d0 1997 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1998 ata_ehi_hotplugged(host_ehi);
1999 ata_ehi_push_desc(host_ehi, "%s",
2000 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 2001 "connection status changed" : "PHY RDY changed");
2002 }
2003
78cd52d0 2004 /* okay, let's hand over to EH */
a72ec4ce 2005
78cd52d0
TH		 2006 if (irq_stat & PORT_IRQ_FREEZE)
2007 ata_port_freeze(ap);
2008 else
2009 ata_port_abort(ap);
1da177e4
LT		 2010}
2011
df69c9c5 2012static void ahci_port_intr(struct ata_port *ap)
1da177e4 2013{
350756f6 2014 void __iomem *port_mmio = ahci_port_base(ap);
9af5c9c9 2015 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 2016 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 2017 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 2018 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 2019 u32 status, qc_active;
459ad688 2020 int rc;
1da177e4
LT		 2021
2022 status = readl(port_mmio + PORT_IRQ_STAT);
2023 writel(status, port_mmio + PORT_IRQ_STAT);
2024
b06ce3e5
TH		 2025 /* ignore BAD_PMP while resetting */
2026 if (unlikely(resetting))
2027 status &= ~PORT_IRQ_BAD_PMP;
2028
31556594
KCA		 2029 /* If we are getting PhyRdy, this is
2030 * just a power state change, we should
2031 * clear out this, plus the PhyRdy/Comm
2032 * Wake bits from Serror
2033 */
2034 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2035 (status & PORT_IRQ_PHYRDY)) {
2036 status &= ~PORT_IRQ_PHYRDY;
82ef04fb 2037 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
31556594
KCA		 2038 }
2039
78cd52d0
TH		 2040 if (unlikely(status & PORT_IRQ_ERROR)) {
2041 ahci_error_intr(ap, status);
2042 return;
1da177e4
LT		 2043 }
2044
2f294968 2045 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 2046 /* If SNotification is available, leave notification
2047 * handling to sata_async_notification(). If not,
2048 * emulate it by snooping SDB FIS RX area.
2049 *
2050 * Snooping FIS RX area is probably cheaper than
2051 * poking SNotification but some constrollers which
2052 * implement SNotification, ICH9 for example, don't
2053 * store AN SDB FIS into receive area.
2f294968 2054 */
5f226c6b 2055 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 2056 sata_async_notification(ap);
5f226c6b
TH		 2057 else {
2058 /* If the 'N' bit in word 0 of the FIS is set,
2059 * we just received asynchronous notification.
2060 * Tell libata about it.
2061 */
2062 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2063 u32 f0 = le32_to_cpu(f[0]);
2064
2065 if (f0 & (1 << 15))
2066 sata_async_notification(ap);
2067 }
2f294968
KCA		 2068 }
2069
7d50b60b
TH		 2070 /* pp->active_link is valid iff any command is in flight */
2071 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 2072 qc_active = readl(port_mmio + PORT_SCR_ACT);
2073 else
2074 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2075
79f97dad 2076 rc = ata_qc_complete_multiple(ap, qc_active);
b06ce3e5 2077
459ad688
TH		 2078 /* while resetting, invalid completions are expected */
2079 if (unlikely(rc < 0 && !resetting)) {
12fad3f9 2080 ehi->err_mask |= AC_ERR_HSM;
cf480626 2081 ehi->action |= ATA_EH_RESET;
12fad3f9 2082 ata_port_freeze(ap);
1da177e4 2083 }
1da177e4
LT		 2084}
2085
7d12e780 2086static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 2087{
cca3974e 2088 struct ata_host *host = dev_instance;
1da177e4
LT		 2089 struct ahci_host_priv *hpriv;
2090 unsigned int i, handled = 0;
ea6ba10b 2091 void __iomem *mmio;
d28f87aa 2092 u32 irq_stat, irq_masked;
1da177e4
LT		 2093
2094 VPRINTK("ENTER\n");
2095
cca3974e 2096 hpriv = host->private_data;
0d5ff566 2097 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2098
2099 /* sigh. 0xffffffff is a valid return from h/w */
2100 irq_stat = readl(mmio + HOST_IRQ_STAT);
1da177e4
LT		 2101 if (!irq_stat)
2102 return IRQ_NONE;
2103
d28f87aa
TH		 2104 irq_masked = irq_stat & hpriv->port_map;
2105
2dcb407e 2106 spin_lock(&host->lock);
1da177e4 2107
2dcb407e 2108 for (i = 0; i < host->n_ports; i++) {
1da177e4 2109 struct ata_port *ap;
1da177e4 2110
d28f87aa 2111 if (!(irq_masked & (1 << i)))
67846b30
JG		 2112 continue;
2113
cca3974e 2114 ap = host->ports[i];
67846b30 2115 if (ap) {
df69c9c5 2116 ahci_port_intr(ap);
67846b30
JG		 2117 VPRINTK("port %u\n", i);
2118 } else {
2119 VPRINTK("port %u (no irq)\n", i);
6971ed1f 2120 if (ata_ratelimit())
cca3974e 2121 dev_printk(KERN_WARNING, host->dev,
a9524a76 2122 "interrupt on disabled port %u\n", i);
1da177e4 2123 }
67846b30 2124
1da177e4
LT		 2125 handled = 1;
2126 }
2127
d28f87aa
TH		 2128 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2129 * it should be cleared after all the port events are cleared;
2130 * otherwise, it will raise a spurious interrupt after each
2131 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2132 * information.
2133 *
2134 * Also, use the unmasked value to clear interrupt as spurious
2135 * pending event on a dummy port might cause screaming IRQ.
2136 */
ea0c62f7
TH		 2137 writel(irq_stat, mmio + HOST_IRQ_STAT);
2138
cca3974e 2139 spin_unlock(&host->lock);
1da177e4
LT		 2140
2141 VPRINTK("EXIT\n");
2142
2143 return IRQ_RETVAL(handled);
2144}
2145
9a3d9eb0 2146static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 2147{
2148 struct ata_port *ap = qc->ap;
4447d351 2149 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 2150 struct ahci_port_priv *pp = ap->private_data;
2151
2152 /* Keep track of the currently active link. It will be used
2153 * in completion path to determine whether NCQ phase is in
2154 * progress.
2155 */
2156 pp->active_link = qc->dev->link;
1da177e4 2157
12fad3f9
TH		 2158 if (qc->tf.protocol == ATA_PROT_NCQ)
2159 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2160 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4 2161
18f7ba4c
KCA		 2162 ahci_sw_activity(qc->dev->link);
2163
1da177e4
LT		 2164 return 0;
2165}
2166
4c9bf4e7
TH		 2167static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2168{
2169 struct ahci_port_priv *pp = qc->ap->private_data;
2170 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2171
2172 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2173 return true;
2174}
2175
78cd52d0
TH		 2176static void ahci_freeze(struct ata_port *ap)
2177{
4447d351 2178 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 2179
2180 /* turn IRQ off */
2181 writel(0, port_mmio + PORT_IRQ_MASK);
2182}
2183
2184static void ahci_thaw(struct ata_port *ap)
2185{
0d5ff566 2186 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 2187 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 2188 u32 tmp;
a7384925 2189 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 2190
2191 /* clear IRQ */
2192 tmp = readl(port_mmio + PORT_IRQ_STAT);
2193 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 2194 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 2195
1c954a4d
TH		 2196 /* turn IRQ back on */
2197 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 2198}
2199
2200static void ahci_error_handler(struct ata_port *ap)
2201{
b51e9e5d 2202 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 2203 /* restart engine */
4447d351
TH		 2204 ahci_stop_engine(ap);
2205 ahci_start_engine(ap);
78cd52d0
TH		 2206 }
2207
a1efdaba 2208 sata_pmp_error_handler(ap);
edc93052
TH		 2209}
2210
78cd52d0
TH		 2211static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2212{
2213 struct ata_port *ap = qc->ap;
2214
d2e75dff
TH		 2215 /* make DMA engine forget about the failed command */
2216 if (qc->flags & ATA_QCFLAG_FAILED)
2217 ahci_kick_engine(ap, 1);
78cd52d0
TH		 2218}
2219
7d50b60b
TH		 2220static void ahci_pmp_attach(struct ata_port *ap)
2221{
2222 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2223 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2224 u32 cmd;
2225
2226 cmd = readl(port_mmio + PORT_CMD);
2227 cmd |= PORT_CMD_PMP;
2228 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2229
2230 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2231 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2232}
2233
2234static void ahci_pmp_detach(struct ata_port *ap)
2235{
2236 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 2237 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 2238 u32 cmd;
2239
2240 cmd = readl(port_mmio + PORT_CMD);
2241 cmd &= ~PORT_CMD_PMP;
2242 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 2243
2244 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2245 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 2246}
2247
028a2596
AD		 2248static int ahci_port_resume(struct ata_port *ap)
2249{
2250 ahci_power_up(ap);
2251 ahci_start_port(ap);
2252
071f44b1 2253 if (sata_pmp_attached(ap))
7d50b60b
TH		 2254 ahci_pmp_attach(ap);
2255 else
2256 ahci_pmp_detach(ap);
2257
028a2596
AD		 2258 return 0;
2259}
2260
438ac6d5 2261#ifdef CONFIG_PM
c1332875
TH		 2262static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2263{
c1332875
TH		 2264 const char *emsg = NULL;
2265 int rc;
2266
4447d351 2267 rc = ahci_deinit_port(ap, &emsg);
8e16f941 2268 if (rc == 0)
4447d351 2269 ahci_power_down(ap);
8e16f941 2270 else {
c1332875 2271 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 2272 ahci_start_port(ap);
c1332875
TH		 2273 }
2274
2275 return rc;
2276}
2277
c1332875
TH		 2278static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2279{
cca3974e 2280 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 2281 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 2282 u32 ctl;
2283
3a2d5b70 2284 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 2285 /* AHCI spec rev1.1 section 8.3.3:
2286 * Software must disable interrupts prior to requesting a
2287 * transition of the HBA to D3 state.
2288 */
2289 ctl = readl(mmio + HOST_CTL);
2290 ctl &= ~HOST_IRQ_EN;
2291 writel(ctl, mmio + HOST_CTL);
2292 readl(mmio + HOST_CTL); /* flush */
2293 }
2294
2295 return ata_pci_device_suspend(pdev, mesg);
2296}
2297
2298static int ahci_pci_device_resume(struct pci_dev *pdev)
2299{
cca3974e 2300 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 2301 int rc;
2302
553c4aa6
TH		 2303 rc = ata_pci_device_do_resume(pdev);
2304 if (rc)
2305 return rc;
c1332875
TH		 2306
2307 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 2308 rc = ahci_reset_controller(host);
c1332875
TH		 2309 if (rc)
2310 return rc;
2311
4447d351 2312 ahci_init_controller(host);
c1332875
TH		 2313 }
2314
cca3974e 2315 ata_host_resume(host);
c1332875
TH		 2316
2317 return 0;
2318}
438ac6d5 2319#endif
c1332875 2320
254950cd
TH		 2321static int ahci_port_start(struct ata_port *ap)
2322{
cca3974e 2323 struct device *dev = ap->host->dev;
254950cd 2324 struct ahci_port_priv *pp;
254950cd
TH		 2325 void *mem;
2326 dma_addr_t mem_dma;
254950cd 2327
24dc5f33 2328 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2329 if (!pp)
2330 return -ENOMEM;
254950cd 2331
24dc5f33
TH		 2332 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2333 GFP_KERNEL);
2334 if (!mem)
254950cd 2335 return -ENOMEM;
254950cd
TH		 2336 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2337
2338 /*
2339 * First item in chunk of DMA memory: 32-slot command table,
2340 * 32 bytes each in size
2341 */
2342 pp->cmd_slot = mem;
2343 pp->cmd_slot_dma = mem_dma;
2344
2345 mem += AHCI_CMD_SLOT_SZ;
2346 mem_dma += AHCI_CMD_SLOT_SZ;
2347
2348 /*
2349 * Second item: Received-FIS area
2350 */
2351 pp->rx_fis = mem;
2352 pp->rx_fis_dma = mem_dma;
2353
2354 mem += AHCI_RX_FIS_SZ;
2355 mem_dma += AHCI_RX_FIS_SZ;
2356
2357 /*
2358 * Third item: data area for storing a single command
2359 * and its scatter-gather table
2360 */
2361 pp->cmd_tbl = mem;
2362 pp->cmd_tbl_dma = mem_dma;
2363
a7384925 2364 /*
2dcb407e
JG		 2365 * Save off initial list of interrupts to be enabled.
2366 * This could be changed later
2367 */
a7384925
KCA		 2368 pp->intr_mask = DEF_PORT_IRQ;
2369
254950cd
TH		 2370 ap->private_data = pp;
2371
df69c9c5
JG		 2372 /* engage engines, captain */
2373 return ahci_port_resume(ap);
254950cd
TH		 2374}
2375
2376static void ahci_port_stop(struct ata_port *ap)
2377{
0be0aa98
TH		 2378 const char *emsg = NULL;
2379 int rc;
254950cd 2380
0be0aa98 2381 /* de-initialize port */
4447d351 2382 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2383 if (rc)
2384 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2385}
2386
4447d351 2387static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2388{
1da177e4 2389 int rc;
1da177e4 2390
1da177e4
LT		 2391 if (using_dac &&
2392 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2393 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2394 if (rc) {
2395 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2396 if (rc) {
a9524a76
JG		 2397 dev_printk(KERN_ERR, &pdev->dev,
2398 "64-bit DMA enable failed\n");
1da177e4
LT		 2399 return rc;
2400 }
2401 }
1da177e4
LT		 2402 } else {
2403 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2404 if (rc) {
a9524a76
JG		 2405 dev_printk(KERN_ERR, &pdev->dev,
2406 "32-bit DMA enable failed\n");
1da177e4
LT		 2407 return rc;
2408 }
2409 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2410 if (rc) {
a9524a76
JG		 2411 dev_printk(KERN_ERR, &pdev->dev,
2412 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2413 return rc;
2414 }
2415 }
1da177e4
LT		 2416 return 0;
2417}
2418
4447d351 2419static void ahci_print_info(struct ata_host *host)
1da177e4 2420{
4447d351
TH		 2421 struct ahci_host_priv *hpriv = host->private_data;
2422 struct pci_dev *pdev = to_pci_dev(host->dev);
2423 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2424 u32 vers, cap, impl, speed;
2425 const char *speed_s;
2426 u16 cc;
2427 const char *scc_s;
2428
2429 vers = readl(mmio + HOST_VERSION);
2430 cap = hpriv->cap;
2431 impl = hpriv->port_map;
2432
2433 speed = (cap >> 20) & 0xf;
2434 if (speed == 1)
2435 speed_s = "1.5";
2436 else if (speed == 2)
2437 speed_s = "3";
2438 else
2439 speed_s = "?";
2440
2441 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2442 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2443 scc_s = "IDE";
c9f89475 2444 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2445 scc_s = "SATA";
c9f89475 2446 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2447 scc_s = "RAID";
2448 else
2449 scc_s = "unknown";
2450
a9524a76
JG		 2451 dev_printk(KERN_INFO, &pdev->dev,
2452 "AHCI %02x%02x.%02x%02x "
1da177e4 2453 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2454 ,
1da177e4 2455
2dcb407e
JG		 2456 (vers >> 24) & 0xff,
2457 (vers >> 16) & 0xff,
2458 (vers >> 8) & 0xff,
2459 vers & 0xff,
1da177e4
LT		 2460
2461 ((cap >> 8) & 0x1f) + 1,
2462 (cap & 0x1f) + 1,
2463 speed_s,
2464 impl,
2465 scc_s);
2466
a9524a76
JG		 2467 dev_printk(KERN_INFO, &pdev->dev,
2468 "flags: "
203ef6c4 2469 "%s%s%s%s%s%s%s"
18f7ba4c
KCA		 2470 "%s%s%s%s%s%s%s"
2471 "%s\n"
2dcb407e 2472 ,
1da177e4
LT		 2473
2474 cap & (1 << 31) ? "64bit " : "",
2475 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2476 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2477 cap & (1 << 28) ? "ilck " : "",
2478 cap & (1 << 27) ? "stag " : "",
2479 cap & (1 << 26) ? "pm " : "",
2480 cap & (1 << 25) ? "led " : "",
2481
2482 cap & (1 << 24) ? "clo " : "",
2483 cap & (1 << 19) ? "nz " : "",
2484 cap & (1 << 18) ? "only " : "",
2485 cap & (1 << 17) ? "pmp " : "",
2486 cap & (1 << 15) ? "pio " : "",
2487 cap & (1 << 14) ? "slum " : "",
18f7ba4c
KCA		 2488 cap & (1 << 13) ? "part " : "",
2489 cap & (1 << 6) ? "ems ": ""
1da177e4
LT		 2490 );
2491}
2492
edc93052
TH		 2493/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2494 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2495 * support PMP and the 4726 either directly exports the device
2496 * attached to the first downstream port or acts as a hardware storage
2497 * controller and emulate a single ATA device (can be RAID 0/1 or some
2498 * other configuration).
2499 *
2500 * When there's no device attached to the first downstream port of the
2501 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2502 * configure the 4726. However, ATA emulation of the device is very
2503 * lame. It doesn't send signature D2H Reg FIS after the initial
2504 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2505 *
2506 * The following function works around the problem by always using
2507 * hardreset on the port and not depending on receiving signature FIS
2508 * afterward. If signature FIS isn't received soon, ATA class is
2509 * assumed without follow-up softreset.
2510 */
2511static void ahci_p5wdh_workaround(struct ata_host *host)
2512{
2513 static struct dmi_system_id sysids[] = {
2514 {
2515 .ident = "P5W DH Deluxe",
2516 .matches = {
2517 DMI_MATCH(DMI_SYS_VENDOR,
2518 "ASUSTEK COMPUTER INC"),
2519 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2520 },
2521 },
2522 { }
2523 };
2524 struct pci_dev *pdev = to_pci_dev(host->dev);
2525
2526 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2527 dmi_check_system(sysids)) {
2528 struct ata_port *ap = host->ports[1];
2529
2530 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2531 "Deluxe on-board SIMG4726 workaround\n");
2532
2533 ap->ops = &ahci_p5wdh_ops;
2534 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2535 }
2536}
2537
24dc5f33 2538static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2539{
2540 static int printed_version;
e297d99e
TH		 2541 unsigned int board_id = ent->driver_data;
2542 struct ata_port_info pi = ahci_port_info[board_id];
4447d351 2543 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2544 struct device *dev = &pdev->dev;
1da177e4 2545 struct ahci_host_priv *hpriv;
4447d351 2546 struct ata_host *host;
837f5f8f 2547 int n_ports, i, rc;
1da177e4
LT		 2548
2549 VPRINTK("ENTER\n");
2550
12fad3f9
TH		 2551 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2552
1da177e4 2553 if (!printed_version++)
a9524a76 2554 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2555
5b66c829
AC		 2556 /* The AHCI driver can only drive the SATA ports, the PATA driver
2557 can drive them all so if both drivers are selected make sure
2558 AHCI stays out of the way */
2559 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2560 return -ENODEV;
2561
4447d351 2562 /* acquire resources */
24dc5f33 2563 rc = pcim_enable_device(pdev);
1da177e4
LT		 2564 if (rc)
2565 return rc;
2566
dea55137
TH		 2567 /* AHCI controllers often implement SFF compatible interface.
2568 * Grab all PCI BARs just in case.
2569 */
2570 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2571 if (rc == -EBUSY)
24dc5f33 2572 pcim_pin_device(pdev);
0d5ff566 2573 if (rc)
24dc5f33 2574 return rc;
1da177e4 2575
c4f7792c
TH		 2576 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2577 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2578 u8 map;
2579
2580 /* ICH6s share the same PCI ID for both piix and ahci
2581 * modes. Enabling ahci mode while MAP indicates
2582 * combined mode is a bad idea. Yield to ata_piix.
2583 */
2584 pci_read_config_byte(pdev, ICH_MAP, &map);
2585 if (map & 0x3) {
2586 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2587 "combined mode, can't enable AHCI mode\n");
2588 return -ENODEV;
2589 }
2590 }
2591
24dc5f33
TH		 2592 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2593 if (!hpriv)
2594 return -ENOMEM;
417a1a6d
TH		 2595 hpriv->flags |= (unsigned long)pi.private_data;
2596
e297d99e
TH		 2597 /* MCP65 revision A1 and A2 can't do MSI */
2598 if (board_id == board_ahci_mcp65 &&
2599 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2600 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2601
417a1a6d
TH		 2602 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2603 pci_intx(pdev, 1);
1da177e4 2604
4447d351 2605 /* save initial config */
417a1a6d 2606 ahci_save_initial_config(pdev, hpriv);
1da177e4 2607
4447d351 2608 /* prepare host */
274c1fde 2609 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2610 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2611
7d50b60b
TH		 2612 if (hpriv->cap & HOST_CAP_PMP)
2613 pi.flags |= ATA_FLAG_PMP;
2614
18f7ba4c
KCA		 2615 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2616 u8 messages;
2617 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2618 u32 em_loc = readl(mmio + HOST_EM_LOC);
2619 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2620
2621 messages = (em_ctl & 0x000f0000) >> 16;
2622
2623 /* we only support LED message type right now */
2624 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2625 /* store em_loc */
2626 hpriv->em_loc = ((em_loc >> 16) * 4);
2627 pi.flags |= ATA_FLAG_EM;
2628 if (!(em_ctl & EM_CTL_ALHD))
2629 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2630 }
2631 }
2632
837f5f8f
TH		 2633 /* CAP.NP sometimes indicate the index of the last enabled
2634 * port, at other times, that of the last possible port, so
2635 * determining the maximum port number requires looking at
2636 * both CAP.NP and port_map.
2637 */
2638 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2639
2640 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2641 if (!host)
2642 return -ENOMEM;
2643 host->iomap = pcim_iomap_table(pdev);
2644 host->private_data = hpriv;
2645
18f7ba4c
KCA		 2646 if (pi.flags & ATA_FLAG_EM)
2647 ahci_reset_em(host);
2648
4447d351 2649 for (i = 0; i < host->n_ports; i++) {
dab632e8 2650 struct ata_port *ap = host->ports[i];
4447d351 2651
cbcdd875
TH		 2652 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2653 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2654 0x100 + ap->port_no * 0x80, "port");
2655
31556594
KCA		 2656 /* set initial link pm policy */
2657 ap->pm_policy = NOT_AVAILABLE;
2658
18f7ba4c
KCA		 2659 /* set enclosure management message type */
2660 if (ap->flags & ATA_FLAG_EM)
2661 ap->em_message_type = ahci_em_messages;
2662
2663
dab632e8 2664 /* disabled/not-implemented port */
350756f6 2665 if (!(hpriv->port_map & (1 << i)))
dab632e8 2666 ap->ops = &ata_dummy_port_ops;
4447d351 2667 }
d447df14 2668
edc93052
TH		 2669 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2670 ahci_p5wdh_workaround(host);
2671
4447d351
TH		 2672 /* initialize adapter */
2673 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2674 if (rc)
24dc5f33 2675 return rc;
1da177e4 2676
4447d351
TH		 2677 rc = ahci_reset_controller(host);
2678 if (rc)
2679 return rc;
1da177e4 2680
4447d351
TH		 2681 ahci_init_controller(host);
2682 ahci_print_info(host);
1da177e4 2683
4447d351
TH		 2684 pci_set_master(pdev);
2685 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2686 &ahci_sht);
907f4678 2687}
1da177e4
LT		 2688
2689static int __init ahci_init(void)
2690{
b7887196 2691 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2692}
2693
1da177e4
LT		 2694static void __exit ahci_exit(void)
2695{
2696 pci_unregister_driver(&ahci_pci_driver);
2697}
2698
2699
2700MODULE_AUTHOR("Jeff Garzik");
2701MODULE_DESCRIPTION("AHCI SATA low-level driver");
2702MODULE_LICENSE("GPL");
2703MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2704MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2705
2706module_init(ahci_init);
2707module_exit(ahci_exit);
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