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ahci: request all PCI BARs
[net-next-2.6.git] / drivers / ata / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
87507cfd 42#include <linux/dma-mapping.h>
a9524a76 43#include <linux/device.h>
edc93052 44#include <linux/dmi.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4 47#include <linux/libata.h>
1da177e4
LT		 48
49#define DRV_NAME "ahci"
7d50b60b 50#define DRV_VERSION "3.0"
1da177e4 51
31556594
KCA		 52static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54static void ahci_disable_alpm(struct ata_port *ap);
1da177e4
LT		 55
56enum {
57 AHCI_PCI_BAR = 5,
648a88be 58 AHCI_MAX_PORTS = 32,
1da177e4
LT		 59 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
be5d8218 61 AHCI_USE_CLUSTERING = 1,
12fad3f9 62 AHCI_MAX_CMDS = 32,
dd410ff1 63 AHCI_CMD_SZ = 32,
12fad3f9 64 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
1da177e4 65 AHCI_RX_FIS_SZ = 256,
a0ea7328 66 AHCI_CMD_TBL_CDB = 0x40,
dd410ff1
TH		 67 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
1da177e4
LT		 71 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
4b10e559 75 AHCI_CMD_PREFETCH = (1 << 7),
22b49985
TH		 76 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 78
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
0291f95f 80 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
78cd52d0 81 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
1da177e4
LT		 82
83 board_ahci = 0,
7a234aff
TH		 84 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
e39fc8c9 88 board_ahci_sb700 = 5,
1da177e4
LT		 89
90 /* global controller registers */
91 HOST_CAP = 0x00, /* host capabilities */
92 HOST_CTL = 0x04, /* global host control */
93 HOST_IRQ_STAT = 0x08, /* interrupt status */
94 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
95 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
96
97 /* HOST_CTL bits */
98 HOST_RESET = (1 << 0), /* reset controller; self-clear */
99 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
100 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
101
102 /* HOST_CAP bits */
0be0aa98 103 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
7d50b60b 104 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
22b49985 105 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
31556594 106 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
0be0aa98 107 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
203ef6c4 108 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
979db803 109 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
dd410ff1 110 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
1da177e4
LT		 111
112 /* registers for each SATA port */
113 PORT_LST_ADDR = 0x00, /* command list DMA addr */
114 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
115 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
116 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
117 PORT_IRQ_STAT = 0x10, /* interrupt status */
118 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
119 PORT_CMD = 0x18, /* port command */
120 PORT_TFDATA = 0x20, /* taskfile data */
121 PORT_SIG = 0x24, /* device TF signature */
122 PORT_CMD_ISSUE = 0x38, /* command issue */
1da177e4
LT		 123 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
124 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
125 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
126 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
203ef6c4 127 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
1da177e4
LT		 128
129 /* PORT_IRQ_{STAT,MASK} bits */
130 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
131 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
132 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
133 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
134 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
135 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
136 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
137 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
138
139 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
140 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
141 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
142 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
143 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
144 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
145 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
146 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
147 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
148
78cd52d0
TH		 149 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
150 PORT_IRQ_IF_ERR |
151 PORT_IRQ_CONNECT |
4296971d 152 PORT_IRQ_PHYRDY |
7d50b60b
TH		 153 PORT_IRQ_UNK_FIS |
154 PORT_IRQ_BAD_PMP,
78cd52d0
TH		 155 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
156 PORT_IRQ_TF_ERR |
157 PORT_IRQ_HBUS_DATA_ERR,
158 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
159 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
160 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
1da177e4
LT		 161
162 /* PORT_CMD bits */
31556594
KCA		 163 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
164 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
02eaa666 165 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
7d50b60b 166 PORT_CMD_PMP = (1 << 17), /* PMP attached */
1da177e4
LT		 167 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
168 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
169 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 170 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 171 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
172 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
173 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
174
0be0aa98 175 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
1da177e4
LT		 176 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
177 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
178 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4 179
417a1a6d
TH		 180 /* hpriv->flags bits */
181 AHCI_HFLAG_NO_NCQ = (1 << 0),
182 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
183 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
184 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
185 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
186 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
6949b914 187 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
31556594 188 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
a878539e 189 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
417a1a6d 190
bf2af2a2 191 /* ap->flags bits */
1188c0d8
TH		 192
193 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
194 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
31556594
KCA		 195 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
196 ATA_FLAG_IPM,
0c88758b 197 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
c4f7792c
TH		 198
199 ICH_MAP = 0x90, /* ICH MAP register */
1da177e4
LT		 200};
201
202struct ahci_cmd_hdr {
4ca4e439
AV		 203 __le32 opts;
204 __le32 status;
205 __le32 tbl_addr;
206 __le32 tbl_addr_hi;
207 __le32 reserved[4];
1da177e4
LT		 208};
209
210struct ahci_sg {
4ca4e439
AV		 211 __le32 addr;
212 __le32 addr_hi;
213 __le32 reserved;
214 __le32 flags_size;
1da177e4
LT		 215};
216
217struct ahci_host_priv {
417a1a6d 218 unsigned int flags; /* AHCI_HFLAG_* */
d447df14
TH		 219 u32 cap; /* cap to use */
220 u32 port_map; /* port map to use */
221 u32 saved_cap; /* saved initial cap */
222 u32 saved_port_map; /* saved initial port_map */
1da177e4
LT		 223};
224
225struct ahci_port_priv {
7d50b60b 226 struct ata_link *active_link;
1da177e4
LT		 227 struct ahci_cmd_hdr *cmd_slot;
228 dma_addr_t cmd_slot_dma;
229 void *cmd_tbl;
230 dma_addr_t cmd_tbl_dma;
1da177e4
LT		 231 void *rx_fis;
232 dma_addr_t rx_fis_dma;
0291f95f 233 /* for NCQ spurious interrupt analysis */
0291f95f
TH		 234 unsigned int ncq_saw_d2h:1;
235 unsigned int ncq_saw_dmas:1;
afb2d552 236 unsigned int ncq_saw_sdb:1;
a7384925 237 u32 intr_mask; /* interrupts to enable */
1da177e4
LT		 238};
239
da3dbb17
TH		 240static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
241static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
2dcb407e 242static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 243static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4 244static void ahci_irq_clear(struct ata_port *ap);
1da177e4
LT		 245static int ahci_port_start(struct ata_port *ap);
246static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 247static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
248static void ahci_qc_prep(struct ata_queued_cmd *qc);
249static u8 ahci_check_status(struct ata_port *ap);
78cd52d0
TH		 250static void ahci_freeze(struct ata_port *ap);
251static void ahci_thaw(struct ata_port *ap);
7d50b60b
TH		 252static void ahci_pmp_attach(struct ata_port *ap);
253static void ahci_pmp_detach(struct ata_port *ap);
78cd52d0 254static void ahci_error_handler(struct ata_port *ap);
ad616ffb 255static void ahci_vt8251_error_handler(struct ata_port *ap);
edc93052 256static void ahci_p5wdh_error_handler(struct ata_port *ap);
78cd52d0 257static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
df69c9c5 258static int ahci_port_resume(struct ata_port *ap);
a878539e 259static void ahci_dev_config(struct ata_device *dev);
dab632e8
JG		 260static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
261static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
262 u32 opts);
438ac6d5 263#ifdef CONFIG_PM
c1332875 264static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
c1332875
TH		 265static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
266static int ahci_pci_device_resume(struct pci_dev *pdev);
438ac6d5 267#endif
1da177e4 268
31556594
KCA		 269static struct class_device_attribute *ahci_shost_attrs[] = {
270 &class_device_attr_link_power_management_policy,
271 NULL
272};
273
193515d5 274static struct scsi_host_template ahci_sht = {
1da177e4
LT		 275 .module = THIS_MODULE,
276 .name = DRV_NAME,
277 .ioctl = ata_scsi_ioctl,
278 .queuecommand = ata_scsi_queuecmd,
12fad3f9
TH		 279 .change_queue_depth = ata_scsi_change_queue_depth,
280 .can_queue = AHCI_MAX_CMDS - 1,
1da177e4
LT		 281 .this_id = ATA_SHT_THIS_ID,
282 .sg_tablesize = AHCI_MAX_SG,
1da177e4
LT		 283 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
284 .emulated = ATA_SHT_EMULATED,
285 .use_clustering = AHCI_USE_CLUSTERING,
286 .proc_name = DRV_NAME,
287 .dma_boundary = AHCI_DMA_BOUNDARY,
288 .slave_configure = ata_scsi_slave_config,
ccf68c34 289 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 290 .bios_param = ata_std_bios_param,
31556594 291 .shost_attrs = ahci_shost_attrs,
1da177e4
LT		 292};
293
057ace5e 294static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 295 .check_status = ahci_check_status,
296 .check_altstatus = ahci_check_status,
1da177e4
LT		 297 .dev_select = ata_noop_dev_select,
298
a878539e
JG		 299 .dev_config = ahci_dev_config,
300
1da177e4
LT		 301 .tf_read = ahci_tf_read,
302
7d50b60b 303 .qc_defer = sata_pmp_qc_defer_cmd_switch,
1da177e4
LT		 304 .qc_prep = ahci_qc_prep,
305 .qc_issue = ahci_qc_issue,
306
1da177e4
LT		 307 .irq_clear = ahci_irq_clear,
308
309 .scr_read = ahci_scr_read,
310 .scr_write = ahci_scr_write,
311
78cd52d0
TH		 312 .freeze = ahci_freeze,
313 .thaw = ahci_thaw,
314
315 .error_handler = ahci_error_handler,
316 .post_internal_cmd = ahci_post_internal_cmd,
317
7d50b60b
TH		 318 .pmp_attach = ahci_pmp_attach,
319 .pmp_detach = ahci_pmp_detach,
7d50b60b 320
438ac6d5 321#ifdef CONFIG_PM
c1332875
TH		 322 .port_suspend = ahci_port_suspend,
323 .port_resume = ahci_port_resume,
438ac6d5 324#endif
31556594
KCA		 325 .enable_pm = ahci_enable_alpm,
326 .disable_pm = ahci_disable_alpm,
c1332875 327
1da177e4
LT		 328 .port_start = ahci_port_start,
329 .port_stop = ahci_port_stop,
1da177e4
LT		 330};
331
ad616ffb 332static const struct ata_port_operations ahci_vt8251_ops = {
ad616ffb
TH		 333 .check_status = ahci_check_status,
334 .check_altstatus = ahci_check_status,
335 .dev_select = ata_noop_dev_select,
336
337 .tf_read = ahci_tf_read,
338
7d50b60b 339 .qc_defer = sata_pmp_qc_defer_cmd_switch,
ad616ffb
TH		 340 .qc_prep = ahci_qc_prep,
341 .qc_issue = ahci_qc_issue,
342
ad616ffb
TH		 343 .irq_clear = ahci_irq_clear,
344
345 .scr_read = ahci_scr_read,
346 .scr_write = ahci_scr_write,
347
348 .freeze = ahci_freeze,
349 .thaw = ahci_thaw,
350
351 .error_handler = ahci_vt8251_error_handler,
352 .post_internal_cmd = ahci_post_internal_cmd,
353
7d50b60b
TH		 354 .pmp_attach = ahci_pmp_attach,
355 .pmp_detach = ahci_pmp_detach,
7d50b60b 356
438ac6d5 357#ifdef CONFIG_PM
ad616ffb
TH		 358 .port_suspend = ahci_port_suspend,
359 .port_resume = ahci_port_resume,
438ac6d5 360#endif
ad616ffb
TH		 361
362 .port_start = ahci_port_start,
363 .port_stop = ahci_port_stop,
364};
365
edc93052
TH		 366static const struct ata_port_operations ahci_p5wdh_ops = {
367 .check_status = ahci_check_status,
368 .check_altstatus = ahci_check_status,
369 .dev_select = ata_noop_dev_select,
370
371 .tf_read = ahci_tf_read,
372
373 .qc_defer = sata_pmp_qc_defer_cmd_switch,
374 .qc_prep = ahci_qc_prep,
375 .qc_issue = ahci_qc_issue,
376
377 .irq_clear = ahci_irq_clear,
378
379 .scr_read = ahci_scr_read,
380 .scr_write = ahci_scr_write,
381
382 .freeze = ahci_freeze,
383 .thaw = ahci_thaw,
384
385 .error_handler = ahci_p5wdh_error_handler,
386 .post_internal_cmd = ahci_post_internal_cmd,
387
388 .pmp_attach = ahci_pmp_attach,
389 .pmp_detach = ahci_pmp_detach,
390
391#ifdef CONFIG_PM
392 .port_suspend = ahci_port_suspend,
393 .port_resume = ahci_port_resume,
394#endif
395
396 .port_start = ahci_port_start,
397 .port_stop = ahci_port_stop,
398};
399
417a1a6d
TH		 400#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
401
98ac62de 402static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 403 /* board_ahci */
404 {
1188c0d8 405 .flags = AHCI_FLAG_COMMON,
0c88758b 406 .link_flags = AHCI_LFLAG_COMMON,
7da79312 407 .pio_mask = 0x1f, /* pio0-4 */
469248ab 408 .udma_mask = ATA_UDMA6,
1da177e4
LT		 409 .port_ops = &ahci_ops,
410 },
bf2af2a2
BJ		 411 /* board_ahci_vt8251 */
412 {
6949b914 413 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
417a1a6d 414 .flags = AHCI_FLAG_COMMON,
0c88758b 415 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
bf2af2a2 416 .pio_mask = 0x1f, /* pio0-4 */
469248ab 417 .udma_mask = ATA_UDMA6,
ad616ffb 418 .port_ops = &ahci_vt8251_ops,
bf2af2a2 419 },
41669553
TH		 420 /* board_ahci_ign_iferr */
421 {
417a1a6d
TH		 422 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
423 .flags = AHCI_FLAG_COMMON,
0c88758b 424 .link_flags = AHCI_LFLAG_COMMON,
41669553 425 .pio_mask = 0x1f, /* pio0-4 */
469248ab 426 .udma_mask = ATA_UDMA6,
41669553
TH		 427 .port_ops = &ahci_ops,
428 },
55a61604
CH		 429 /* board_ahci_sb600 */
430 {
417a1a6d 431 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
a878539e 432 AHCI_HFLAG_SECT255 | AHCI_HFLAG_NO_PMP),
417a1a6d 433 .flags = AHCI_FLAG_COMMON,
0c88758b 434 .link_flags = AHCI_LFLAG_COMMON,
55a61604 435 .pio_mask = 0x1f, /* pio0-4 */
469248ab 436 .udma_mask = ATA_UDMA6,
55a61604
CH		 437 .port_ops = &ahci_ops,
438 },
cd70c266
JG		 439 /* board_ahci_mv */
440 {
417a1a6d
TH		 441 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
442 AHCI_HFLAG_MV_PATA),
cd70c266 443 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
417a1a6d 444 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
0c88758b 445 .link_flags = AHCI_LFLAG_COMMON,
cd70c266
JG		 446 .pio_mask = 0x1f, /* pio0-4 */
447 .udma_mask = ATA_UDMA6,
448 .port_ops = &ahci_ops,
449 },
e39fc8c9
SH		 450 /* board_ahci_sb700 */
451 {
452 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
453 AHCI_HFLAG_NO_PMP),
454 .flags = AHCI_FLAG_COMMON,
455 .link_flags = AHCI_LFLAG_COMMON,
456 .pio_mask = 0x1f, /* pio0-4 */
457 .udma_mask = ATA_UDMA6,
458 .port_ops = &ahci_ops,
459 },
1da177e4
LT		 460};
461
3b7d697d 462static const struct pci_device_id ahci_pci_tbl[] = {
fe7fa31a 463 /* Intel */
54bb3a94
JG		 464 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
465 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
466 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
467 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
468 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
82490c09 469 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
54bb3a94
JG		 470 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
471 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
472 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
473 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
7a234aff
TH		 474 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
475 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
476 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
477 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
478 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
479 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
480 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
481 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
482 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
483 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
485 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
486 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
487 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
488 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
489 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
490 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
d4155e6f
JG		 491 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
492 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
16ad1ad9
JG		 493 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
494 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
fe7fa31a 495
e34bb370
TH		 496 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
497 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
498 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
fe7fa31a
JG		 499
500 /* ATI */
c65ec1c2 501 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
e39fc8c9
SH		 502 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
504 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
505 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
506 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
507 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
fe7fa31a
JG		 508
509 /* VIA */
54bb3a94 510 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
bf335542 511 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
fe7fa31a
JG		 512
513 /* NVIDIA */
54bb3a94
JG		 514 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
6fbf5ba4
PC		 518 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
519 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
520 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
521 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
522 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
895663cd
PC		 526 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
531 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
532 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
533 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
0522b286
PC		 534 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
543 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
544 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
545 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
555 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
556 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
557 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
6ba86958 558 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
7100819f
PC		 562 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
567 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
568 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
569 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
70d562cf 570 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
578 { PCI_VDEVICE(NVIDIA, 0x0bd0), board_ahci }, /* MCP7B */
579 { PCI_VDEVICE(NVIDIA, 0x0bd1), board_ahci }, /* MCP7B */
580 { PCI_VDEVICE(NVIDIA, 0x0bd2), board_ahci }, /* MCP7B */
581 { PCI_VDEVICE(NVIDIA, 0x0bd3), board_ahci }, /* MCP7B */
fe7fa31a 582
95916edd 583 /* SiS */
54bb3a94
JG		 584 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
585 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
586 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
95916edd 587
cd70c266
JG		 588 /* Marvell */
589 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
590
415ae2b5
JG		 591 /* Generic, PCI class code for AHCI */
592 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
c9f89475 593 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
415ae2b5 594
1da177e4
LT		 595 { } /* terminate list */
596};
597
598
599static struct pci_driver ahci_pci_driver = {
600 .name = DRV_NAME,
601 .id_table = ahci_pci_tbl,
602 .probe = ahci_init_one,
24dc5f33 603 .remove = ata_pci_remove_one,
438ac6d5 604#ifdef CONFIG_PM
c1332875
TH		 605 .suspend = ahci_pci_device_suspend,
606 .resume = ahci_pci_device_resume,
438ac6d5 607#endif
1da177e4
LT		 608};
609
610
98fa4b60
TH		 611static inline int ahci_nr_ports(u32 cap)
612{
613 return (cap & 0x1f) + 1;
614}
615
dab632e8
JG		 616static inline void __iomem *__ahci_port_base(struct ata_host *host,
617 unsigned int port_no)
1da177e4 618{
dab632e8 619 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
4447d351 620
dab632e8
JG		 621 return mmio + 0x100 + (port_no * 0x80);
622}
623
624static inline void __iomem *ahci_port_base(struct ata_port *ap)
625{
626 return __ahci_port_base(ap->host, ap->port_no);
1da177e4
LT		 627}
628
b710a1f4
TH		 629static void ahci_enable_ahci(void __iomem *mmio)
630{
631 u32 tmp;
632
633 /* turn on AHCI_EN */
634 tmp = readl(mmio + HOST_CTL);
635 if (!(tmp & HOST_AHCI_EN)) {
636 tmp |= HOST_AHCI_EN;
637 writel(tmp, mmio + HOST_CTL);
638 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
639 WARN_ON(!(tmp & HOST_AHCI_EN));
640 }
641}
642
d447df14
TH		 643/**
644 * ahci_save_initial_config - Save and fixup initial config values
4447d351 645 * @pdev: target PCI device
4447d351 646 * @hpriv: host private area to store config values
d447df14
TH		 647 *
648 * Some registers containing configuration info might be setup by
649 * BIOS and might be cleared on reset. This function saves the
650 * initial values of those registers into @hpriv such that they
651 * can be restored after controller reset.
652 *
653 * If inconsistent, config values are fixed up by this function.
654 *
655 * LOCKING:
656 * None.
657 */
4447d351 658static void ahci_save_initial_config(struct pci_dev *pdev,
4447d351 659 struct ahci_host_priv *hpriv)
d447df14 660{
4447d351 661 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
d447df14 662 u32 cap, port_map;
17199b18 663 int i;
d447df14 664
b710a1f4
TH		 665 /* make sure AHCI mode is enabled before accessing CAP */
666 ahci_enable_ahci(mmio);
667
d447df14
TH		 668 /* Values prefixed with saved_ are written back to host after
669 * reset. Values without are used for driver operation.
670 */
671 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
672 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
673
274c1fde 674 /* some chips have errata preventing 64bit use */
417a1a6d 675 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
c7a42156
TH		 676 dev_printk(KERN_INFO, &pdev->dev,
677 "controller can't do 64bit DMA, forcing 32bit\n");
678 cap &= ~HOST_CAP_64;
679 }
680
417a1a6d 681 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
274c1fde
TH		 682 dev_printk(KERN_INFO, &pdev->dev,
683 "controller can't do NCQ, turning off CAP_NCQ\n");
684 cap &= ~HOST_CAP_NCQ;
685 }
686
258cd846 687 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
6949b914
TH		 688 dev_printk(KERN_INFO, &pdev->dev,
689 "controller can't do PMP, turning off CAP_PMP\n");
690 cap &= ~HOST_CAP_PMP;
691 }
692
cd70c266
JG		 693 /*
694 * Temporary Marvell 6145 hack: PATA port presence
695 * is asserted through the standard AHCI port
696 * presence register, as bit 4 (counting from 0)
697 */
417a1a6d 698 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
cd70c266
JG		 699 dev_printk(KERN_ERR, &pdev->dev,
700 "MV_AHCI HACK: port_map %x -> %x\n",
701 hpriv->port_map,
702 hpriv->port_map & 0xf);
703
704 port_map &= 0xf;
705 }
706
17199b18 707 /* cross check port_map and cap.n_ports */
7a234aff 708 if (port_map) {
837f5f8f 709 int map_ports = 0;
17199b18 710
837f5f8f
TH		 711 for (i = 0; i < AHCI_MAX_PORTS; i++)
712 if (port_map & (1 << i))
713 map_ports++;
17199b18 714
837f5f8f
TH		 715 /* If PI has more ports than n_ports, whine, clear
716 * port_map and let it be generated from n_ports.
17199b18 717 */
837f5f8f 718 if (map_ports > ahci_nr_ports(cap)) {
4447d351 719 dev_printk(KERN_WARNING, &pdev->dev,
837f5f8f
TH		 720 "implemented port map (0x%x) contains more "
721 "ports than nr_ports (%u), using nr_ports\n",
722 port_map, ahci_nr_ports(cap));
7a234aff
TH		 723 port_map = 0;
724 }
725 }
726
727 /* fabricate port_map from cap.nr_ports */
728 if (!port_map) {
17199b18 729 port_map = (1 << ahci_nr_ports(cap)) - 1;
7a234aff
TH		 730 dev_printk(KERN_WARNING, &pdev->dev,
731 "forcing PORTS_IMPL to 0x%x\n", port_map);
732
733 /* write the fixed up value to the PI register */
734 hpriv->saved_port_map = port_map;
17199b18
TH		 735 }
736
d447df14
TH		 737 /* record values to use during operation */
738 hpriv->cap = cap;
739 hpriv->port_map = port_map;
740}
741
742/**
743 * ahci_restore_initial_config - Restore initial config
4447d351 744 * @host: target ATA host
d447df14
TH		 745 *
746 * Restore initial config stored by ahci_save_initial_config().
747 *
748 * LOCKING:
749 * None.
750 */
4447d351 751static void ahci_restore_initial_config(struct ata_host *host)
d447df14 752{
4447d351
TH		 753 struct ahci_host_priv *hpriv = host->private_data;
754 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
755
d447df14
TH		 756 writel(hpriv->saved_cap, mmio + HOST_CAP);
757 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
758 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
759}
760
203ef6c4 761static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
1da177e4 762{
203ef6c4
TH		 763 static const int offset[] = {
764 [SCR_STATUS] = PORT_SCR_STAT,
765 [SCR_CONTROL] = PORT_SCR_CTL,
766 [SCR_ERROR] = PORT_SCR_ERR,
767 [SCR_ACTIVE] = PORT_SCR_ACT,
768 [SCR_NOTIFICATION] = PORT_SCR_NTF,
769 };
770 struct ahci_host_priv *hpriv = ap->host->private_data;
1da177e4 771
203ef6c4
TH		 772 if (sc_reg < ARRAY_SIZE(offset) &&
773 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
774 return offset[sc_reg];
da3dbb17 775 return 0;
1da177e4
LT		 776}
777
203ef6c4 778static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
1da177e4 779{
203ef6c4
TH		 780 void __iomem *port_mmio = ahci_port_base(ap);
781 int offset = ahci_scr_offset(ap, sc_reg);
782
783 if (offset) {
784 *val = readl(port_mmio + offset);
785 return 0;
1da177e4 786 }
203ef6c4
TH		 787 return -EINVAL;
788}
1da177e4 789
203ef6c4
TH		 790static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
791{
792 void __iomem *port_mmio = ahci_port_base(ap);
793 int offset = ahci_scr_offset(ap, sc_reg);
794
795 if (offset) {
796 writel(val, port_mmio + offset);
797 return 0;
798 }
799 return -EINVAL;
1da177e4
LT		 800}
801
4447d351 802static void ahci_start_engine(struct ata_port *ap)
7c76d1e8 803{
4447d351 804 void __iomem *port_mmio = ahci_port_base(ap);
7c76d1e8
TH		 805 u32 tmp;
806
d8fcd116 807 /* start DMA */
9f592056 808 tmp = readl(port_mmio + PORT_CMD);
7c76d1e8
TH		 809 tmp |= PORT_CMD_START;
810 writel(tmp, port_mmio + PORT_CMD);
811 readl(port_mmio + PORT_CMD); /* flush */
812}
813
4447d351 814static int ahci_stop_engine(struct ata_port *ap)
254950cd 815{
4447d351 816 void __iomem *port_mmio = ahci_port_base(ap);
254950cd
TH		 817 u32 tmp;
818
819 tmp = readl(port_mmio + PORT_CMD);
820
d8fcd116 821 /* check if the HBA is idle */
254950cd
TH		 822 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
823 return 0;
824
d8fcd116 825 /* setting HBA to idle */
254950cd
TH		 826 tmp &= ~PORT_CMD_START;
827 writel(tmp, port_mmio + PORT_CMD);
828
d8fcd116 829 /* wait for engine to stop. This could be as long as 500 msec */
254950cd 830 tmp = ata_wait_register(port_mmio + PORT_CMD,
2dcb407e 831 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
d8fcd116 832 if (tmp & PORT_CMD_LIST_ON)
254950cd
TH		 833 return -EIO;
834
835 return 0;
836}
837
4447d351 838static void ahci_start_fis_rx(struct ata_port *ap)
0be0aa98 839{
4447d351
TH		 840 void __iomem *port_mmio = ahci_port_base(ap);
841 struct ahci_host_priv *hpriv = ap->host->private_data;
842 struct ahci_port_priv *pp = ap->private_data;
0be0aa98
TH		 843 u32 tmp;
844
845 /* set FIS registers */
4447d351
TH		 846 if (hpriv->cap & HOST_CAP_64)
847 writel((pp->cmd_slot_dma >> 16) >> 16,
848 port_mmio + PORT_LST_ADDR_HI);
849 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
0be0aa98 850
4447d351
TH		 851 if (hpriv->cap & HOST_CAP_64)
852 writel((pp->rx_fis_dma >> 16) >> 16,
853 port_mmio + PORT_FIS_ADDR_HI);
854 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
0be0aa98
TH		 855
856 /* enable FIS reception */
857 tmp = readl(port_mmio + PORT_CMD);
858 tmp |= PORT_CMD_FIS_RX;
859 writel(tmp, port_mmio + PORT_CMD);
860
861 /* flush */
862 readl(port_mmio + PORT_CMD);
863}
864
4447d351 865static int ahci_stop_fis_rx(struct ata_port *ap)
0be0aa98 866{
4447d351 867 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 868 u32 tmp;
869
870 /* disable FIS reception */
871 tmp = readl(port_mmio + PORT_CMD);
872 tmp &= ~PORT_CMD_FIS_RX;
873 writel(tmp, port_mmio + PORT_CMD);
874
875 /* wait for completion, spec says 500ms, give it 1000 */
876 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
877 PORT_CMD_FIS_ON, 10, 1000);
878 if (tmp & PORT_CMD_FIS_ON)
879 return -EBUSY;
880
881 return 0;
882}
883
4447d351 884static void ahci_power_up(struct ata_port *ap)
0be0aa98 885{
4447d351
TH		 886 struct ahci_host_priv *hpriv = ap->host->private_data;
887 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 888 u32 cmd;
889
890 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
891
892 /* spin up device */
4447d351 893 if (hpriv->cap & HOST_CAP_SSS) {
0be0aa98
TH		 894 cmd |= PORT_CMD_SPIN_UP;
895 writel(cmd, port_mmio + PORT_CMD);
896 }
897
898 /* wake up link */
899 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
900}
901
31556594
KCA		 902static void ahci_disable_alpm(struct ata_port *ap)
903{
904 struct ahci_host_priv *hpriv = ap->host->private_data;
905 void __iomem *port_mmio = ahci_port_base(ap);
906 u32 cmd;
907 struct ahci_port_priv *pp = ap->private_data;
908
909 /* IPM bits should be disabled by libata-core */
910 /* get the existing command bits */
911 cmd = readl(port_mmio + PORT_CMD);
912
913 /* disable ALPM and ASP */
914 cmd &= ~PORT_CMD_ASP;
915 cmd &= ~PORT_CMD_ALPE;
916
917 /* force the interface back to active */
918 cmd |= PORT_CMD_ICC_ACTIVE;
919
920 /* write out new cmd value */
921 writel(cmd, port_mmio + PORT_CMD);
922 cmd = readl(port_mmio + PORT_CMD);
923
924 /* wait 10ms to be sure we've come out of any low power state */
925 msleep(10);
926
927 /* clear out any PhyRdy stuff from interrupt status */
928 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
929
930 /* go ahead and clean out PhyRdy Change from Serror too */
931 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
932
933 /*
934 * Clear flag to indicate that we should ignore all PhyRdy
935 * state changes
936 */
937 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
938
939 /*
940 * Enable interrupts on Phy Ready.
941 */
942 pp->intr_mask |= PORT_IRQ_PHYRDY;
943 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
944
945 /*
946 * don't change the link pm policy - we can be called
947 * just to turn of link pm temporarily
948 */
949}
950
951static int ahci_enable_alpm(struct ata_port *ap,
952 enum link_pm policy)
953{
954 struct ahci_host_priv *hpriv = ap->host->private_data;
955 void __iomem *port_mmio = ahci_port_base(ap);
956 u32 cmd;
957 struct ahci_port_priv *pp = ap->private_data;
958 u32 asp;
959
960 /* Make sure the host is capable of link power management */
961 if (!(hpriv->cap & HOST_CAP_ALPM))
962 return -EINVAL;
963
964 switch (policy) {
965 case MAX_PERFORMANCE:
966 case NOT_AVAILABLE:
967 /*
968 * if we came here with NOT_AVAILABLE,
969 * it just means this is the first time we
970 * have tried to enable - default to max performance,
971 * and let the user go to lower power modes on request.
972 */
973 ahci_disable_alpm(ap);
974 return 0;
975 case MIN_POWER:
976 /* configure HBA to enter SLUMBER */
977 asp = PORT_CMD_ASP;
978 break;
979 case MEDIUM_POWER:
980 /* configure HBA to enter PARTIAL */
981 asp = 0;
982 break;
983 default:
984 return -EINVAL;
985 }
986
987 /*
988 * Disable interrupts on Phy Ready. This keeps us from
989 * getting woken up due to spurious phy ready interrupts
990 * TBD - Hot plug should be done via polling now, is
991 * that even supported?
992 */
993 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
994 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
995
996 /*
997 * Set a flag to indicate that we should ignore all PhyRdy
998 * state changes since these can happen now whenever we
999 * change link state
1000 */
1001 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1002
1003 /* get the existing command bits */
1004 cmd = readl(port_mmio + PORT_CMD);
1005
1006 /*
1007 * Set ASP based on Policy
1008 */
1009 cmd |= asp;
1010
1011 /*
1012 * Setting this bit will instruct the HBA to aggressively
1013 * enter a lower power link state when it's appropriate and
1014 * based on the value set above for ASP
1015 */
1016 cmd |= PORT_CMD_ALPE;
1017
1018 /* write out new cmd value */
1019 writel(cmd, port_mmio + PORT_CMD);
1020 cmd = readl(port_mmio + PORT_CMD);
1021
1022 /* IPM bits should be set by libata-core */
1023 return 0;
1024}
1025
438ac6d5 1026#ifdef CONFIG_PM
4447d351 1027static void ahci_power_down(struct ata_port *ap)
0be0aa98 1028{
4447d351
TH		 1029 struct ahci_host_priv *hpriv = ap->host->private_data;
1030 void __iomem *port_mmio = ahci_port_base(ap);
0be0aa98
TH		 1031 u32 cmd, scontrol;
1032
4447d351 1033 if (!(hpriv->cap & HOST_CAP_SSS))
07c53dac 1034 return;
0be0aa98 1035
07c53dac
TH		 1036 /* put device into listen mode, first set PxSCTL.DET to 0 */
1037 scontrol = readl(port_mmio + PORT_SCR_CTL);
1038 scontrol &= ~0xf;
1039 writel(scontrol, port_mmio + PORT_SCR_CTL);
0be0aa98 1040
07c53dac
TH		 1041 /* then set PxCMD.SUD to 0 */
1042 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1043 cmd &= ~PORT_CMD_SPIN_UP;
1044 writel(cmd, port_mmio + PORT_CMD);
0be0aa98 1045}
438ac6d5 1046#endif
0be0aa98 1047
df69c9c5 1048static void ahci_start_port(struct ata_port *ap)
0be0aa98 1049{
0be0aa98 1050 /* enable FIS reception */
4447d351 1051 ahci_start_fis_rx(ap);
0be0aa98
TH		 1052
1053 /* enable DMA */
4447d351 1054 ahci_start_engine(ap);
0be0aa98
TH		 1055}
1056
4447d351 1057static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
0be0aa98
TH		 1058{
1059 int rc;
1060
1061 /* disable DMA */
4447d351 1062 rc = ahci_stop_engine(ap);
0be0aa98
TH		 1063 if (rc) {
1064 *emsg = "failed to stop engine";
1065 return rc;
1066 }
1067
1068 /* disable FIS reception */
4447d351 1069 rc = ahci_stop_fis_rx(ap);
0be0aa98
TH		 1070 if (rc) {
1071 *emsg = "failed stop FIS RX";
1072 return rc;
1073 }
1074
0be0aa98
TH		 1075 return 0;
1076}
1077
4447d351 1078static int ahci_reset_controller(struct ata_host *host)
d91542c1 1079{
4447d351 1080 struct pci_dev *pdev = to_pci_dev(host->dev);
49f29090 1081 struct ahci_host_priv *hpriv = host->private_data;
4447d351 1082 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
d447df14 1083 u32 tmp;
d91542c1 1084
3cc3eb11
JG		 1085 /* we must be in AHCI mode, before using anything
1086 * AHCI-specific, such as HOST_RESET.
1087 */
b710a1f4 1088 ahci_enable_ahci(mmio);
3cc3eb11
JG		 1089
1090 /* global controller reset */
b710a1f4 1091 tmp = readl(mmio + HOST_CTL);
d91542c1
TH		 1092 if ((tmp & HOST_RESET) == 0) {
1093 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1094 readl(mmio + HOST_CTL); /* flush */
1095 }
1096
1097 /* reset must complete within 1 second, or
1098 * the hardware should be considered fried.
1099 */
1100 ssleep(1);
1101
1102 tmp = readl(mmio + HOST_CTL);
1103 if (tmp & HOST_RESET) {
4447d351 1104 dev_printk(KERN_ERR, host->dev,
d91542c1
TH		 1105 "controller reset failed (0x%x)\n", tmp);
1106 return -EIO;
1107 }
1108
98fa4b60 1109 /* turn on AHCI mode */
b710a1f4 1110 ahci_enable_ahci(mmio);
98fa4b60 1111
d447df14 1112 /* some registers might be cleared on reset. restore initial values */
4447d351 1113 ahci_restore_initial_config(host);
d91542c1
TH		 1114
1115 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1116 u16 tmp16;
1117
1118 /* configure PCS */
1119 pci_read_config_word(pdev, 0x92, &tmp16);
49f29090
TH		 1120 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1121 tmp16 |= hpriv->port_map;
1122 pci_write_config_word(pdev, 0x92, tmp16);
1123 }
d91542c1
TH		 1124 }
1125
1126 return 0;
1127}
1128
2bcd866b
JG		 1129static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1130 int port_no, void __iomem *mmio,
1131 void __iomem *port_mmio)
1132{
1133 const char *emsg = NULL;
1134 int rc;
1135 u32 tmp;
1136
1137 /* make sure port is not active */
1138 rc = ahci_deinit_port(ap, &emsg);
1139 if (rc)
1140 dev_printk(KERN_WARNING, &pdev->dev,
1141 "%s (%d)\n", emsg, rc);
1142
1143 /* clear SError */
1144 tmp = readl(port_mmio + PORT_SCR_ERR);
1145 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1146 writel(tmp, port_mmio + PORT_SCR_ERR);
1147
1148 /* clear port IRQ */
1149 tmp = readl(port_mmio + PORT_IRQ_STAT);
1150 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1151 if (tmp)
1152 writel(tmp, port_mmio + PORT_IRQ_STAT);
1153
1154 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1155}
1156
4447d351 1157static void ahci_init_controller(struct ata_host *host)
d91542c1 1158{
417a1a6d 1159 struct ahci_host_priv *hpriv = host->private_data;
4447d351
TH		 1160 struct pci_dev *pdev = to_pci_dev(host->dev);
1161 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2bcd866b 1162 int i;
cd70c266 1163 void __iomem *port_mmio;
d91542c1
TH		 1164 u32 tmp;
1165
417a1a6d 1166 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
cd70c266
JG		 1167 port_mmio = __ahci_port_base(host, 4);
1168
1169 writel(0, port_mmio + PORT_IRQ_MASK);
1170
1171 /* clear port IRQ */
1172 tmp = readl(port_mmio + PORT_IRQ_STAT);
1173 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1174 if (tmp)
1175 writel(tmp, port_mmio + PORT_IRQ_STAT);
1176 }
1177
4447d351
TH		 1178 for (i = 0; i < host->n_ports; i++) {
1179 struct ata_port *ap = host->ports[i];
d91542c1 1180
cd70c266 1181 port_mmio = ahci_port_base(ap);
4447d351 1182 if (ata_port_is_dummy(ap))
d91542c1 1183 continue;
d91542c1 1184
2bcd866b 1185 ahci_port_init(pdev, ap, i, mmio, port_mmio);
d91542c1
TH		 1186 }
1187
1188 tmp = readl(mmio + HOST_CTL);
1189 VPRINTK("HOST_CTL 0x%x\n", tmp);
1190 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1191 tmp = readl(mmio + HOST_CTL);
1192 VPRINTK("HOST_CTL 0x%x\n", tmp);
1193}
1194
a878539e
JG		 1195static void ahci_dev_config(struct ata_device *dev)
1196{
1197 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1198
1199 if (hpriv->flags & AHCI_HFLAG_SECT255)
1200 dev->max_sectors = 255;
1201}
1202
422b7595 1203static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4 1204{
4447d351 1205 void __iomem *port_mmio = ahci_port_base(ap);
1da177e4 1206 struct ata_taskfile tf;
422b7595
TH		 1207 u32 tmp;
1208
1209 tmp = readl(port_mmio + PORT_SIG);
1210 tf.lbah = (tmp >> 24) & 0xff;
1211 tf.lbam = (tmp >> 16) & 0xff;
1212 tf.lbal = (tmp >> 8) & 0xff;
1213 tf.nsect = (tmp) & 0xff;
1214
1215 return ata_dev_classify(&tf);
1216}
1217
12fad3f9
TH		 1218static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1219 u32 opts)
cc9278ed 1220{
12fad3f9
TH		 1221 dma_addr_t cmd_tbl_dma;
1222
1223 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1224
1225 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1226 pp->cmd_slot[tag].status = 0;
1227 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1228 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
cc9278ed
TH		 1229}
1230
d2e75dff 1231static int ahci_kick_engine(struct ata_port *ap, int force_restart)
4658f79b 1232{
0d5ff566 1233 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
cca3974e 1234 struct ahci_host_priv *hpriv = ap->host->private_data;
bf2af2a2 1235 u32 tmp;
d2e75dff 1236 int busy, rc;
bf2af2a2 1237
d2e75dff
TH		 1238 /* do we need to kick the port? */
1239 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1240 if (!busy && !force_restart)
1241 return 0;
1242
1243 /* stop engine */
1244 rc = ahci_stop_engine(ap);
1245 if (rc)
1246 goto out_restart;
1247
1248 /* need to do CLO? */
1249 if (!busy) {
1250 rc = 0;
1251 goto out_restart;
1252 }
1253
1254 if (!(hpriv->cap & HOST_CAP_CLO)) {
1255 rc = -EOPNOTSUPP;
1256 goto out_restart;
1257 }
bf2af2a2 1258
d2e75dff 1259 /* perform CLO */
bf2af2a2
BJ		 1260 tmp = readl(port_mmio + PORT_CMD);
1261 tmp |= PORT_CMD_CLO;
1262 writel(tmp, port_mmio + PORT_CMD);
1263
d2e75dff 1264 rc = 0;
bf2af2a2
BJ		 1265 tmp = ata_wait_register(port_mmio + PORT_CMD,
1266 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1267 if (tmp & PORT_CMD_CLO)
d2e75dff 1268 rc = -EIO;
bf2af2a2 1269
d2e75dff
TH		 1270 /* restart engine */
1271 out_restart:
1272 ahci_start_engine(ap);
1273 return rc;
bf2af2a2
BJ		 1274}
1275
91c4a2e0
TH		 1276static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1277 struct ata_taskfile *tf, int is_cmd, u16 flags,
1278 unsigned long timeout_msec)
bf2af2a2 1279{
91c4a2e0 1280 const u32 cmd_fis_len = 5; /* five dwords */
4658f79b 1281 struct ahci_port_priv *pp = ap->private_data;
4447d351 1282 void __iomem *port_mmio = ahci_port_base(ap);
91c4a2e0
TH		 1283 u8 *fis = pp->cmd_tbl;
1284 u32 tmp;
1285
1286 /* prep the command */
1287 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1288 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1289
1290 /* issue & wait */
1291 writel(1, port_mmio + PORT_CMD_ISSUE);
1292
1293 if (timeout_msec) {
1294 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1295 1, timeout_msec);
1296 if (tmp & 0x1) {
1297 ahci_kick_engine(ap, 1);
1298 return -EBUSY;
1299 }
1300 } else
1301 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1302
1303 return 0;
1304}
1305
cc0680a5 1306static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85 1307 int pmp, unsigned long deadline)
91c4a2e0 1308{
cc0680a5 1309 struct ata_port *ap = link->ap;
4658f79b 1310 const char *reason = NULL;
2cbb79eb 1311 unsigned long now, msecs;
4658f79b 1312 struct ata_taskfile tf;
4658f79b
TH		 1313 int rc;
1314
1315 DPRINTK("ENTER\n");
1316
cc0680a5 1317 if (ata_link_offline(link)) {
c2a65852
TH		 1318 DPRINTK("PHY reports no device\n");
1319 *class = ATA_DEV_NONE;
1320 return 0;
1321 }
1322
4658f79b 1323 /* prepare for SRST (AHCI-1.1 10.4.1) */
d2e75dff 1324 rc = ahci_kick_engine(ap, 1);
994056d7 1325 if (rc && rc != -EOPNOTSUPP)
cc0680a5 1326 ata_link_printk(link, KERN_WARNING,
994056d7 1327 "failed to reset engine (errno=%d)\n", rc);
4658f79b 1328
cc0680a5 1329 ata_tf_init(link->device, &tf);
4658f79b
TH		 1330
1331 /* issue the first D2H Register FIS */
2cbb79eb
TH		 1332 msecs = 0;
1333 now = jiffies;
1334 if (time_after(now, deadline))
1335 msecs = jiffies_to_msecs(deadline - now);
1336
4658f79b 1337 tf.ctl |= ATA_SRST;
a9cf5e85 1338 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
91c4a2e0 1339 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
4658f79b
TH		 1340 rc = -EIO;
1341 reason = "1st FIS failed";
1342 goto fail;
1343 }
1344
1345 /* spec says at least 5us, but be generous and sleep for 1ms */
1346 msleep(1);
1347
1348 /* issue the second D2H Register FIS */
4658f79b 1349 tf.ctl &= ~ATA_SRST;
a9cf5e85 1350 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
4658f79b 1351
88ff6eaf
TH		 1352 /* wait a while before checking status */
1353 ata_wait_after_reset(ap, deadline);
4658f79b 1354
9b89391c
TH		 1355 rc = ata_wait_ready(ap, deadline);
1356 /* link occupied, -ENODEV too is an error */
1357 if (rc) {
1358 reason = "device not ready";
1359 goto fail;
4658f79b 1360 }
9b89391c 1361 *class = ahci_dev_classify(ap);
4658f79b
TH		 1362
1363 DPRINTK("EXIT, class=%u\n", *class);
1364 return 0;
1365
4658f79b 1366 fail:
cc0680a5 1367 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
4658f79b
TH		 1368 return rc;
1369}
1370
cc0680a5 1371static int ahci_softreset(struct ata_link *link, unsigned int *class,
a9cf5e85
TH		 1372 unsigned long deadline)
1373{
7d50b60b
TH		 1374 int pmp = 0;
1375
1376 if (link->ap->flags & ATA_FLAG_PMP)
1377 pmp = SATA_PMP_CTRL_PORT;
1378
1379 return ahci_do_softreset(link, class, pmp, deadline);
a9cf5e85
TH		 1380}
1381
cc0680a5 1382static int ahci_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1383 unsigned long deadline)
422b7595 1384{
cc0680a5 1385 struct ata_port *ap = link->ap;
4296971d
TH		 1386 struct ahci_port_priv *pp = ap->private_data;
1387 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1388 struct ata_taskfile tf;
4bd00f6a
TH		 1389 int rc;
1390
1391 DPRINTK("ENTER\n");
1da177e4 1392
4447d351 1393 ahci_stop_engine(ap);
4296971d
TH		 1394
1395 /* clear D2H reception area to properly wait for D2H FIS */
cc0680a5 1396 ata_tf_init(link->device, &tf);
dfd7a3db 1397 tf.command = 0x80;
9977126c 1398 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
4296971d 1399
cc0680a5 1400 rc = sata_std_hardreset(link, class, deadline);
4296971d 1401
4447d351 1402 ahci_start_engine(ap);
1da177e4 1403
cc0680a5 1404 if (rc == 0 && ata_link_online(link))
4bd00f6a 1405 *class = ahci_dev_classify(ap);
7d50b60b 1406 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
4bd00f6a 1407 *class = ATA_DEV_NONE;
1da177e4 1408
4bd00f6a
TH		 1409 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1410 return rc;
1411}
1412
cc0680a5 1413static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
d4b2bab4 1414 unsigned long deadline)
ad616ffb 1415{
cc0680a5 1416 struct ata_port *ap = link->ap;
da3dbb17 1417 u32 serror;
ad616ffb
TH		 1418 int rc;
1419
1420 DPRINTK("ENTER\n");
1421
4447d351 1422 ahci_stop_engine(ap);
ad616ffb 1423
cc0680a5 1424 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
d4b2bab4 1425 deadline);
ad616ffb
TH		 1426
1427 /* vt8251 needs SError cleared for the port to operate */
da3dbb17
TH		 1428 ahci_scr_read(ap, SCR_ERROR, &serror);
1429 ahci_scr_write(ap, SCR_ERROR, serror);
ad616ffb 1430
4447d351 1431 ahci_start_engine(ap);
ad616ffb
TH		 1432
1433 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1434
1435 /* vt8251 doesn't clear BSY on signature FIS reception,
1436 * request follow-up softreset.
1437 */
1438 return rc ?: -EAGAIN;
1439}
1440
edc93052
TH		 1441static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1442 unsigned long deadline)
1443{
1444 struct ata_port *ap = link->ap;
1445 struct ahci_port_priv *pp = ap->private_data;
1446 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1447 struct ata_taskfile tf;
1448 int rc;
1449
1450 ahci_stop_engine(ap);
1451
1452 /* clear D2H reception area to properly wait for D2H FIS */
1453 ata_tf_init(link->device, &tf);
1454 tf.command = 0x80;
1455 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1456
1457 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1458 deadline);
1459
1460 ahci_start_engine(ap);
1461
1462 if (rc || ata_link_offline(link))
1463 return rc;
1464
1465 /* spec mandates ">= 2ms" before checking status */
1466 msleep(150);
1467
1468 /* The pseudo configuration device on SIMG4726 attached to
1469 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1470 * hardreset if no device is attached to the first downstream
1471 * port && the pseudo device locks up on SRST w/ PMP==0. To
1472 * work around this, wait for !BSY only briefly. If BSY isn't
1473 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1474 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1475 *
1476 * Wait for two seconds. Devices attached to downstream port
1477 * which can't process the following IDENTIFY after this will
1478 * have to be reset again. For most cases, this should
1479 * suffice while making probing snappish enough.
1480 */
1481 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1482 if (rc)
1483 ahci_kick_engine(ap, 0);
1484
1485 return 0;
1486}
1487
cc0680a5 1488static void ahci_postreset(struct ata_link *link, unsigned int *class)
4bd00f6a 1489{
cc0680a5 1490 struct ata_port *ap = link->ap;
4447d351 1491 void __iomem *port_mmio = ahci_port_base(ap);
4bd00f6a
TH		 1492 u32 new_tmp, tmp;
1493
cc0680a5 1494 ata_std_postreset(link, class);
02eaa666
JG		 1495
1496 /* Make sure port's ATAPI bit is set appropriately */
1497 new_tmp = tmp = readl(port_mmio + PORT_CMD);
4bd00f6a 1498 if (*class == ATA_DEV_ATAPI)
02eaa666
JG		 1499 new_tmp |= PORT_CMD_ATAPI;
1500 else
1501 new_tmp &= ~PORT_CMD_ATAPI;
1502 if (new_tmp != tmp) {
1503 writel(new_tmp, port_mmio + PORT_CMD);
1504 readl(port_mmio + PORT_CMD); /* flush */
1505 }
1da177e4
LT		 1506}
1507
7d50b60b
TH		 1508static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1509 unsigned long deadline)
1510{
1511 return ahci_do_softreset(link, class, link->pmp, deadline);
1512}
1513
1da177e4
LT		 1514static u8 ahci_check_status(struct ata_port *ap)
1515{
0d5ff566 1516 void __iomem *mmio = ap->ioaddr.cmd_addr;
1da177e4
LT		 1517
1518 return readl(mmio + PORT_TFDATA) & 0xFF;
1519}
1520
1da177e4
LT		 1521static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1522{
1523 struct ahci_port_priv *pp = ap->private_data;
1524 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1525
1526 ata_tf_from_fis(d2h_fis, tf);
1527}
1528
12fad3f9 1529static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1da177e4 1530{
cedc9a47 1531 struct scatterlist *sg;
ff2aeb1e
TH		 1532 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1533 unsigned int si;
1da177e4
LT		 1534
1535 VPRINTK("ENTER\n");
1536
1537 /*
1538 * Next, the S/G list.
1539 */
ff2aeb1e 1540 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 1541 dma_addr_t addr = sg_dma_address(sg);
1542 u32 sg_len = sg_dma_len(sg);
1543
ff2aeb1e
TH		 1544 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1545 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1546 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1da177e4 1547 }
828d09de 1548
ff2aeb1e 1549 return si;
1da177e4
LT		 1550}
1551
1552static void ahci_qc_prep(struct ata_queued_cmd *qc)
1553{
a0ea7328
JG		 1554 struct ata_port *ap = qc->ap;
1555 struct ahci_port_priv *pp = ap->private_data;
405e66b3 1556 int is_atapi = ata_is_atapi(qc->tf.protocol);
12fad3f9 1557 void *cmd_tbl;
1da177e4
LT		 1558 u32 opts;
1559 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 1560 unsigned int n_elem;
1da177e4 1561
1da177e4
LT		 1562 /*
1563 * Fill in command table information. First, the header,
1564 * a SATA Register - Host to Device command FIS.
1565 */
12fad3f9
TH		 1566 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1567
7d50b60b 1568 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
cc9278ed 1569 if (is_atapi) {
12fad3f9
TH		 1570 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1571 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
a0ea7328 1572 }
1da177e4 1573
cc9278ed
TH		 1574 n_elem = 0;
1575 if (qc->flags & ATA_QCFLAG_DMAMAP)
12fad3f9 1576 n_elem = ahci_fill_sg(qc, cmd_tbl);
1da177e4 1577
cc9278ed
TH		 1578 /*
1579 * Fill in command slot information.
1580 */
7d50b60b 1581 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
cc9278ed
TH		 1582 if (qc->tf.flags & ATA_TFLAG_WRITE)
1583 opts |= AHCI_CMD_WRITE;
1584 if (is_atapi)
4b10e559 1585 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
828d09de 1586
12fad3f9 1587 ahci_fill_cmd_slot(pp, qc->tag, opts);
1da177e4
LT		 1588}
1589
78cd52d0 1590static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1da177e4 1591{
417a1a6d 1592 struct ahci_host_priv *hpriv = ap->host->private_data;
78cd52d0 1593 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1594 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1595 struct ata_link *link = NULL;
1596 struct ata_queued_cmd *active_qc;
1597 struct ata_eh_info *active_ehi;
78cd52d0 1598 u32 serror;
1da177e4 1599
7d50b60b
TH		 1600 /* determine active link */
1601 ata_port_for_each_link(link, ap)
1602 if (ata_link_active(link))
1603 break;
1604 if (!link)
1605 link = &ap->link;
1606
1607 active_qc = ata_qc_from_tag(ap, link->active_tag);
1608 active_ehi = &link->eh_info;
1609
1610 /* record irq stat */
1611 ata_ehi_clear_desc(host_ehi);
1612 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1da177e4 1613
78cd52d0 1614 /* AHCI needs SError cleared; otherwise, it might lock up */
da3dbb17 1615 ahci_scr_read(ap, SCR_ERROR, &serror);
78cd52d0 1616 ahci_scr_write(ap, SCR_ERROR, serror);
7d50b60b 1617 host_ehi->serror |= serror;
78cd52d0 1618
41669553 1619 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
417a1a6d 1620 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
41669553
TH		 1621 irq_stat &= ~PORT_IRQ_IF_ERR;
1622
55a61604 1623 if (irq_stat & PORT_IRQ_TF_ERR) {
7d50b60b
TH		 1624 /* If qc is active, charge it; otherwise, the active
1625 * link. There's no active qc on NCQ errors. It will
1626 * be determined by EH by reading log page 10h.
1627 */
1628 if (active_qc)
1629 active_qc->err_mask |= AC_ERR_DEV;
1630 else
1631 active_ehi->err_mask |= AC_ERR_DEV;
1632
417a1a6d 1633 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
7d50b60b
TH		 1634 host_ehi->serror &= ~SERR_INTERNAL;
1635 }
1636
1637 if (irq_stat & PORT_IRQ_UNK_FIS) {
1638 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1639
1640 active_ehi->err_mask |= AC_ERR_HSM;
1641 active_ehi->action |= ATA_EH_SOFTRESET;
1642 ata_ehi_push_desc(active_ehi,
1643 "unknown FIS %08x %08x %08x %08x" ,
1644 unk[0], unk[1], unk[2], unk[3]);
1645 }
1646
1647 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1648 active_ehi->err_mask |= AC_ERR_HSM;
1649 active_ehi->action |= ATA_EH_SOFTRESET;
1650 ata_ehi_push_desc(active_ehi, "incorrect PMP");
55a61604 1651 }
78cd52d0
TH		 1652
1653 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
7d50b60b
TH		 1654 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1655 host_ehi->action |= ATA_EH_SOFTRESET;
1656 ata_ehi_push_desc(host_ehi, "host bus error");
1da177e4
LT		 1657 }
1658
78cd52d0 1659 if (irq_stat & PORT_IRQ_IF_ERR) {
7d50b60b
TH		 1660 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1661 host_ehi->action |= ATA_EH_SOFTRESET;
1662 ata_ehi_push_desc(host_ehi, "interface fatal error");
78cd52d0 1663 }
1da177e4 1664
78cd52d0 1665 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
7d50b60b
TH		 1666 ata_ehi_hotplugged(host_ehi);
1667 ata_ehi_push_desc(host_ehi, "%s",
1668 irq_stat & PORT_IRQ_CONNECT ?
78cd52d0
TH		 1669 "connection status changed" : "PHY RDY changed");
1670 }
1671
78cd52d0 1672 /* okay, let's hand over to EH */
a72ec4ce 1673
78cd52d0
TH		 1674 if (irq_stat & PORT_IRQ_FREEZE)
1675 ata_port_freeze(ap);
1676 else
1677 ata_port_abort(ap);
1da177e4
LT		 1678}
1679
df69c9c5 1680static void ahci_port_intr(struct ata_port *ap)
1da177e4 1681{
4447d351 1682 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
9af5c9c9 1683 struct ata_eh_info *ehi = &ap->link.eh_info;
0291f95f 1684 struct ahci_port_priv *pp = ap->private_data;
5f226c6b 1685 struct ahci_host_priv *hpriv = ap->host->private_data;
b06ce3e5 1686 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
12fad3f9 1687 u32 status, qc_active;
459ad688 1688 int rc;
1da177e4
LT		 1689
1690 status = readl(port_mmio + PORT_IRQ_STAT);
1691 writel(status, port_mmio + PORT_IRQ_STAT);
1692
b06ce3e5
TH		 1693 /* ignore BAD_PMP while resetting */
1694 if (unlikely(resetting))
1695 status &= ~PORT_IRQ_BAD_PMP;
1696
31556594
KCA		 1697 /* If we are getting PhyRdy, this is
1698 * just a power state change, we should
1699 * clear out this, plus the PhyRdy/Comm
1700 * Wake bits from Serror
1701 */
1702 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1703 (status & PORT_IRQ_PHYRDY)) {
1704 status &= ~PORT_IRQ_PHYRDY;
1705 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1706 }
1707
78cd52d0
TH		 1708 if (unlikely(status & PORT_IRQ_ERROR)) {
1709 ahci_error_intr(ap, status);
1710 return;
1da177e4
LT		 1711 }
1712
2f294968 1713 if (status & PORT_IRQ_SDB_FIS) {
5f226c6b
TH		 1714 /* If SNotification is available, leave notification
1715 * handling to sata_async_notification(). If not,
1716 * emulate it by snooping SDB FIS RX area.
1717 *
1718 * Snooping FIS RX area is probably cheaper than
1719 * poking SNotification but some constrollers which
1720 * implement SNotification, ICH9 for example, don't
1721 * store AN SDB FIS into receive area.
2f294968 1722 */
5f226c6b 1723 if (hpriv->cap & HOST_CAP_SNTF)
7d77b247 1724 sata_async_notification(ap);
5f226c6b
TH		 1725 else {
1726 /* If the 'N' bit in word 0 of the FIS is set,
1727 * we just received asynchronous notification.
1728 * Tell libata about it.
1729 */
1730 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1731 u32 f0 = le32_to_cpu(f[0]);
1732
1733 if (f0 & (1 << 15))
1734 sata_async_notification(ap);
1735 }
2f294968
KCA		 1736 }
1737
7d50b60b
TH		 1738 /* pp->active_link is valid iff any command is in flight */
1739 if (ap->qc_active && pp->active_link->sactive)
12fad3f9
TH		 1740 qc_active = readl(port_mmio + PORT_SCR_ACT);
1741 else
1742 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1743
1744 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
b06ce3e5 1745
459ad688
TH		 1746 /* while resetting, invalid completions are expected */
1747 if (unlikely(rc < 0 && !resetting)) {
12fad3f9
TH		 1748 ehi->err_mask |= AC_ERR_HSM;
1749 ehi->action |= ATA_EH_SOFTRESET;
1750 ata_port_freeze(ap);
1da177e4 1751 }
1da177e4
LT		 1752}
1753
1754static void ahci_irq_clear(struct ata_port *ap)
1755{
1756 /* TODO */
1757}
1758
7d12e780 1759static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1da177e4 1760{
cca3974e 1761 struct ata_host *host = dev_instance;
1da177e4
LT		 1762 struct ahci_host_priv *hpriv;
1763 unsigned int i, handled = 0;
ea6ba10b 1764 void __iomem *mmio;
1da177e4
LT		 1765 u32 irq_stat, irq_ack = 0;
1766
1767 VPRINTK("ENTER\n");
1768
cca3974e 1769 hpriv = host->private_data;
0d5ff566 1770 mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 1771
1772 /* sigh. 0xffffffff is a valid return from h/w */
1773 irq_stat = readl(mmio + HOST_IRQ_STAT);
1774 irq_stat &= hpriv->port_map;
1775 if (!irq_stat)
1776 return IRQ_NONE;
1777
2dcb407e 1778 spin_lock(&host->lock);
1da177e4 1779
2dcb407e 1780 for (i = 0; i < host->n_ports; i++) {
1da177e4 1781 struct ata_port *ap;
1da177e4 1782
67846b30
JG		 1783 if (!(irq_stat & (1 << i)))
1784 continue;
1785
cca3974e 1786 ap = host->ports[i];
67846b30 1787 if (ap) {
df69c9c5 1788 ahci_port_intr(ap);
67846b30
JG		 1789 VPRINTK("port %u\n", i);
1790 } else {
1791 VPRINTK("port %u (no irq)\n", i);
6971ed1f 1792 if (ata_ratelimit())
cca3974e 1793 dev_printk(KERN_WARNING, host->dev,
a9524a76 1794 "interrupt on disabled port %u\n", i);
1da177e4 1795 }
67846b30
JG		 1796
1797 irq_ack |= (1 << i);
1da177e4
LT		 1798 }
1799
1800 if (irq_ack) {
1801 writel(irq_ack, mmio + HOST_IRQ_STAT);
1802 handled = 1;
1803 }
1804
cca3974e 1805 spin_unlock(&host->lock);
1da177e4
LT		 1806
1807 VPRINTK("EXIT\n");
1808
1809 return IRQ_RETVAL(handled);
1810}
1811
9a3d9eb0 1812static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 1813{
1814 struct ata_port *ap = qc->ap;
4447d351 1815 void __iomem *port_mmio = ahci_port_base(ap);
7d50b60b
TH		 1816 struct ahci_port_priv *pp = ap->private_data;
1817
1818 /* Keep track of the currently active link. It will be used
1819 * in completion path to determine whether NCQ phase is in
1820 * progress.
1821 */
1822 pp->active_link = qc->dev->link;
1da177e4 1823
12fad3f9
TH		 1824 if (qc->tf.protocol == ATA_PROT_NCQ)
1825 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1826 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1da177e4
LT		 1827 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1828
1829 return 0;
1830}
1831
78cd52d0
TH		 1832static void ahci_freeze(struct ata_port *ap)
1833{
4447d351 1834 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0
TH		 1835
1836 /* turn IRQ off */
1837 writel(0, port_mmio + PORT_IRQ_MASK);
1838}
1839
1840static void ahci_thaw(struct ata_port *ap)
1841{
0d5ff566 1842 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
4447d351 1843 void __iomem *port_mmio = ahci_port_base(ap);
78cd52d0 1844 u32 tmp;
a7384925 1845 struct ahci_port_priv *pp = ap->private_data;
78cd52d0
TH		 1846
1847 /* clear IRQ */
1848 tmp = readl(port_mmio + PORT_IRQ_STAT);
1849 writel(tmp, port_mmio + PORT_IRQ_STAT);
a718728f 1850 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
78cd52d0 1851
1c954a4d
TH		 1852 /* turn IRQ back on */
1853 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
78cd52d0
TH		 1854}
1855
1856static void ahci_error_handler(struct ata_port *ap)
1857{
b51e9e5d 1858 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
78cd52d0 1859 /* restart engine */
4447d351
TH		 1860 ahci_stop_engine(ap);
1861 ahci_start_engine(ap);
78cd52d0
TH		 1862 }
1863
1864 /* perform recovery */
7d50b60b
TH		 1865 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1866 ahci_hardreset, ahci_postreset,
1867 sata_pmp_std_prereset, ahci_pmp_softreset,
1868 sata_pmp_std_hardreset, sata_pmp_std_postreset);
78cd52d0
TH		 1869}
1870
ad616ffb
TH		 1871static void ahci_vt8251_error_handler(struct ata_port *ap)
1872{
ad616ffb
TH		 1873 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1874 /* restart engine */
4447d351
TH		 1875 ahci_stop_engine(ap);
1876 ahci_start_engine(ap);
ad616ffb
TH		 1877 }
1878
1879 /* perform recovery */
1880 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1881 ahci_postreset);
1882}
1883
edc93052
TH		 1884static void ahci_p5wdh_error_handler(struct ata_port *ap)
1885{
1886 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1887 /* restart engine */
1888 ahci_stop_engine(ap);
1889 ahci_start_engine(ap);
1890 }
1891
1892 /* perform recovery */
1893 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1894 ahci_postreset);
1895}
1896
78cd52d0
TH		 1897static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1898{
1899 struct ata_port *ap = qc->ap;
1900
d2e75dff
TH		 1901 /* make DMA engine forget about the failed command */
1902 if (qc->flags & ATA_QCFLAG_FAILED)
1903 ahci_kick_engine(ap, 1);
78cd52d0
TH		 1904}
1905
7d50b60b
TH		 1906static void ahci_pmp_attach(struct ata_port *ap)
1907{
1908 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1909 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1910 u32 cmd;
1911
1912 cmd = readl(port_mmio + PORT_CMD);
1913 cmd |= PORT_CMD_PMP;
1914 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1915
1916 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1917 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1918}
1919
1920static void ahci_pmp_detach(struct ata_port *ap)
1921{
1922 void __iomem *port_mmio = ahci_port_base(ap);
1c954a4d 1923 struct ahci_port_priv *pp = ap->private_data;
7d50b60b
TH		 1924 u32 cmd;
1925
1926 cmd = readl(port_mmio + PORT_CMD);
1927 cmd &= ~PORT_CMD_PMP;
1928 writel(cmd, port_mmio + PORT_CMD);
1c954a4d
TH		 1929
1930 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1931 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
7d50b60b
TH		 1932}
1933
028a2596
AD		 1934static int ahci_port_resume(struct ata_port *ap)
1935{
1936 ahci_power_up(ap);
1937 ahci_start_port(ap);
1938
7d50b60b
TH		 1939 if (ap->nr_pmp_links)
1940 ahci_pmp_attach(ap);
1941 else
1942 ahci_pmp_detach(ap);
1943
028a2596
AD		 1944 return 0;
1945}
1946
438ac6d5 1947#ifdef CONFIG_PM
c1332875
TH		 1948static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1949{
c1332875
TH		 1950 const char *emsg = NULL;
1951 int rc;
1952
4447d351 1953 rc = ahci_deinit_port(ap, &emsg);
8e16f941 1954 if (rc == 0)
4447d351 1955 ahci_power_down(ap);
8e16f941 1956 else {
c1332875 1957 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
df69c9c5 1958 ahci_start_port(ap);
c1332875
TH		 1959 }
1960
1961 return rc;
1962}
1963
c1332875
TH		 1964static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1965{
cca3974e 1966 struct ata_host *host = dev_get_drvdata(&pdev->dev);
0d5ff566 1967 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
c1332875
TH		 1968 u32 ctl;
1969
3a2d5b70 1970 if (mesg.event & PM_EVENT_SLEEP) {
c1332875
TH		 1971 /* AHCI spec rev1.1 section 8.3.3:
1972 * Software must disable interrupts prior to requesting a
1973 * transition of the HBA to D3 state.
1974 */
1975 ctl = readl(mmio + HOST_CTL);
1976 ctl &= ~HOST_IRQ_EN;
1977 writel(ctl, mmio + HOST_CTL);
1978 readl(mmio + HOST_CTL); /* flush */
1979 }
1980
1981 return ata_pci_device_suspend(pdev, mesg);
1982}
1983
1984static int ahci_pci_device_resume(struct pci_dev *pdev)
1985{
cca3974e 1986 struct ata_host *host = dev_get_drvdata(&pdev->dev);
c1332875
TH		 1987 int rc;
1988
553c4aa6
TH		 1989 rc = ata_pci_device_do_resume(pdev);
1990 if (rc)
1991 return rc;
c1332875
TH		 1992
1993 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
4447d351 1994 rc = ahci_reset_controller(host);
c1332875
TH		 1995 if (rc)
1996 return rc;
1997
4447d351 1998 ahci_init_controller(host);
c1332875
TH		 1999 }
2000
cca3974e 2001 ata_host_resume(host);
c1332875
TH		 2002
2003 return 0;
2004}
438ac6d5 2005#endif
c1332875 2006
254950cd
TH		 2007static int ahci_port_start(struct ata_port *ap)
2008{
cca3974e 2009 struct device *dev = ap->host->dev;
254950cd 2010 struct ahci_port_priv *pp;
254950cd
TH		 2011 void *mem;
2012 dma_addr_t mem_dma;
254950cd 2013
24dc5f33 2014 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
254950cd
TH		 2015 if (!pp)
2016 return -ENOMEM;
254950cd 2017
24dc5f33
TH		 2018 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2019 GFP_KERNEL);
2020 if (!mem)
254950cd 2021 return -ENOMEM;
254950cd
TH		 2022 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2023
2024 /*
2025 * First item in chunk of DMA memory: 32-slot command table,
2026 * 32 bytes each in size
2027 */
2028 pp->cmd_slot = mem;
2029 pp->cmd_slot_dma = mem_dma;
2030
2031 mem += AHCI_CMD_SLOT_SZ;
2032 mem_dma += AHCI_CMD_SLOT_SZ;
2033
2034 /*
2035 * Second item: Received-FIS area
2036 */
2037 pp->rx_fis = mem;
2038 pp->rx_fis_dma = mem_dma;
2039
2040 mem += AHCI_RX_FIS_SZ;
2041 mem_dma += AHCI_RX_FIS_SZ;
2042
2043 /*
2044 * Third item: data area for storing a single command
2045 * and its scatter-gather table
2046 */
2047 pp->cmd_tbl = mem;
2048 pp->cmd_tbl_dma = mem_dma;
2049
a7384925 2050 /*
2dcb407e
JG		 2051 * Save off initial list of interrupts to be enabled.
2052 * This could be changed later
2053 */
a7384925
KCA		 2054 pp->intr_mask = DEF_PORT_IRQ;
2055
254950cd
TH		 2056 ap->private_data = pp;
2057
df69c9c5
JG		 2058 /* engage engines, captain */
2059 return ahci_port_resume(ap);
254950cd
TH		 2060}
2061
2062static void ahci_port_stop(struct ata_port *ap)
2063{
0be0aa98
TH		 2064 const char *emsg = NULL;
2065 int rc;
254950cd 2066
0be0aa98 2067 /* de-initialize port */
4447d351 2068 rc = ahci_deinit_port(ap, &emsg);
0be0aa98
TH		 2069 if (rc)
2070 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
254950cd
TH		 2071}
2072
4447d351 2073static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1da177e4 2074{
1da177e4 2075 int rc;
1da177e4 2076
1da177e4
LT		 2077 if (using_dac &&
2078 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2079 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2080 if (rc) {
2081 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2082 if (rc) {
a9524a76
JG		 2083 dev_printk(KERN_ERR, &pdev->dev,
2084 "64-bit DMA enable failed\n");
1da177e4
LT		 2085 return rc;
2086 }
2087 }
1da177e4
LT		 2088 } else {
2089 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2090 if (rc) {
a9524a76
JG		 2091 dev_printk(KERN_ERR, &pdev->dev,
2092 "32-bit DMA enable failed\n");
1da177e4
LT		 2093 return rc;
2094 }
2095 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2096 if (rc) {
a9524a76
JG		 2097 dev_printk(KERN_ERR, &pdev->dev,
2098 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 2099 return rc;
2100 }
2101 }
1da177e4
LT		 2102 return 0;
2103}
2104
4447d351 2105static void ahci_print_info(struct ata_host *host)
1da177e4 2106{
4447d351
TH		 2107 struct ahci_host_priv *hpriv = host->private_data;
2108 struct pci_dev *pdev = to_pci_dev(host->dev);
2109 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1da177e4
LT		 2110 u32 vers, cap, impl, speed;
2111 const char *speed_s;
2112 u16 cc;
2113 const char *scc_s;
2114
2115 vers = readl(mmio + HOST_VERSION);
2116 cap = hpriv->cap;
2117 impl = hpriv->port_map;
2118
2119 speed = (cap >> 20) & 0xf;
2120 if (speed == 1)
2121 speed_s = "1.5";
2122 else if (speed == 2)
2123 speed_s = "3";
2124 else
2125 speed_s = "?";
2126
2127 pci_read_config_word(pdev, 0x0a, &cc);
c9f89475 2128 if (cc == PCI_CLASS_STORAGE_IDE)
1da177e4 2129 scc_s = "IDE";
c9f89475 2130 else if (cc == PCI_CLASS_STORAGE_SATA)
1da177e4 2131 scc_s = "SATA";
c9f89475 2132 else if (cc == PCI_CLASS_STORAGE_RAID)
1da177e4
LT		 2133 scc_s = "RAID";
2134 else
2135 scc_s = "unknown";
2136
a9524a76
JG		 2137 dev_printk(KERN_INFO, &pdev->dev,
2138 "AHCI %02x%02x.%02x%02x "
1da177e4 2139 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2dcb407e 2140 ,
1da177e4 2141
2dcb407e
JG		 2142 (vers >> 24) & 0xff,
2143 (vers >> 16) & 0xff,
2144 (vers >> 8) & 0xff,
2145 vers & 0xff,
1da177e4
LT		 2146
2147 ((cap >> 8) & 0x1f) + 1,
2148 (cap & 0x1f) + 1,
2149 speed_s,
2150 impl,
2151 scc_s);
2152
a9524a76
JG		 2153 dev_printk(KERN_INFO, &pdev->dev,
2154 "flags: "
203ef6c4
TH		 2155 "%s%s%s%s%s%s%s"
2156 "%s%s%s%s%s%s%s\n"
2dcb407e 2157 ,
1da177e4
LT		 2158
2159 cap & (1 << 31) ? "64bit " : "",
2160 cap & (1 << 30) ? "ncq " : "",
203ef6c4 2161 cap & (1 << 29) ? "sntf " : "",
1da177e4
LT		 2162 cap & (1 << 28) ? "ilck " : "",
2163 cap & (1 << 27) ? "stag " : "",
2164 cap & (1 << 26) ? "pm " : "",
2165 cap & (1 << 25) ? "led " : "",
2166
2167 cap & (1 << 24) ? "clo " : "",
2168 cap & (1 << 19) ? "nz " : "",
2169 cap & (1 << 18) ? "only " : "",
2170 cap & (1 << 17) ? "pmp " : "",
2171 cap & (1 << 15) ? "pio " : "",
2172 cap & (1 << 14) ? "slum " : "",
2173 cap & (1 << 13) ? "part " : ""
2174 );
2175}
2176
edc93052
TH		 2177/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2178 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2179 * support PMP and the 4726 either directly exports the device
2180 * attached to the first downstream port or acts as a hardware storage
2181 * controller and emulate a single ATA device (can be RAID 0/1 or some
2182 * other configuration).
2183 *
2184 * When there's no device attached to the first downstream port of the
2185 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2186 * configure the 4726. However, ATA emulation of the device is very
2187 * lame. It doesn't send signature D2H Reg FIS after the initial
2188 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2189 *
2190 * The following function works around the problem by always using
2191 * hardreset on the port and not depending on receiving signature FIS
2192 * afterward. If signature FIS isn't received soon, ATA class is
2193 * assumed without follow-up softreset.
2194 */
2195static void ahci_p5wdh_workaround(struct ata_host *host)
2196{
2197 static struct dmi_system_id sysids[] = {
2198 {
2199 .ident = "P5W DH Deluxe",
2200 .matches = {
2201 DMI_MATCH(DMI_SYS_VENDOR,
2202 "ASUSTEK COMPUTER INC"),
2203 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2204 },
2205 },
2206 { }
2207 };
2208 struct pci_dev *pdev = to_pci_dev(host->dev);
2209
2210 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2211 dmi_check_system(sysids)) {
2212 struct ata_port *ap = host->ports[1];
2213
2214 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2215 "Deluxe on-board SIMG4726 workaround\n");
2216
2217 ap->ops = &ahci_p5wdh_ops;
2218 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2219 }
2220}
2221
24dc5f33 2222static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4
LT		 2223{
2224 static int printed_version;
4447d351
TH		 2225 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2226 const struct ata_port_info *ppi[] = { &pi, NULL };
24dc5f33 2227 struct device *dev = &pdev->dev;
1da177e4 2228 struct ahci_host_priv *hpriv;
4447d351 2229 struct ata_host *host;
837f5f8f 2230 int n_ports, i, rc;
1da177e4
LT		 2231
2232 VPRINTK("ENTER\n");
2233
12fad3f9
TH		 2234 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2235
1da177e4 2236 if (!printed_version++)
a9524a76 2237 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 2238
4447d351 2239 /* acquire resources */
24dc5f33 2240 rc = pcim_enable_device(pdev);
1da177e4
LT		 2241 if (rc)
2242 return rc;
2243
dea55137
TH		 2244 /* AHCI controllers often implement SFF compatible interface.
2245 * Grab all PCI BARs just in case.
2246 */
2247 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0d5ff566 2248 if (rc == -EBUSY)
24dc5f33 2249 pcim_pin_device(pdev);
0d5ff566 2250 if (rc)
24dc5f33 2251 return rc;
1da177e4 2252
c4f7792c
TH		 2253 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2254 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2255 u8 map;
2256
2257 /* ICH6s share the same PCI ID for both piix and ahci
2258 * modes. Enabling ahci mode while MAP indicates
2259 * combined mode is a bad idea. Yield to ata_piix.
2260 */
2261 pci_read_config_byte(pdev, ICH_MAP, &map);
2262 if (map & 0x3) {
2263 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2264 "combined mode, can't enable AHCI mode\n");
2265 return -ENODEV;
2266 }
2267 }
2268
24dc5f33
TH		 2269 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2270 if (!hpriv)
2271 return -ENOMEM;
417a1a6d
TH		 2272 hpriv->flags |= (unsigned long)pi.private_data;
2273
2274 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2275 pci_intx(pdev, 1);
1da177e4 2276
4447d351 2277 /* save initial config */
417a1a6d 2278 ahci_save_initial_config(pdev, hpriv);
1da177e4 2279
4447d351 2280 /* prepare host */
274c1fde 2281 if (hpriv->cap & HOST_CAP_NCQ)
4447d351 2282 pi.flags |= ATA_FLAG_NCQ;
1da177e4 2283
7d50b60b
TH		 2284 if (hpriv->cap & HOST_CAP_PMP)
2285 pi.flags |= ATA_FLAG_PMP;
2286
837f5f8f
TH		 2287 /* CAP.NP sometimes indicate the index of the last enabled
2288 * port, at other times, that of the last possible port, so
2289 * determining the maximum port number requires looking at
2290 * both CAP.NP and port_map.
2291 */
2292 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2293
2294 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4447d351
TH		 2295 if (!host)
2296 return -ENOMEM;
2297 host->iomap = pcim_iomap_table(pdev);
2298 host->private_data = hpriv;
2299
2300 for (i = 0; i < host->n_ports; i++) {
dab632e8
JG		 2301 struct ata_port *ap = host->ports[i];
2302 void __iomem *port_mmio = ahci_port_base(ap);
4447d351 2303
cbcdd875
TH		 2304 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2305 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2306 0x100 + ap->port_no * 0x80, "port");
2307
31556594
KCA		 2308 /* set initial link pm policy */
2309 ap->pm_policy = NOT_AVAILABLE;
2310
dab632e8 2311 /* standard SATA port setup */
203ef6c4 2312 if (hpriv->port_map & (1 << i))
4447d351 2313 ap->ioaddr.cmd_addr = port_mmio;
dab632e8
JG		 2314
2315 /* disabled/not-implemented port */
2316 else
2317 ap->ops = &ata_dummy_port_ops;
4447d351 2318 }
d447df14 2319
edc93052
TH		 2320 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2321 ahci_p5wdh_workaround(host);
2322
4447d351
TH		 2323 /* initialize adapter */
2324 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1da177e4 2325 if (rc)
24dc5f33 2326 return rc;
1da177e4 2327
4447d351
TH		 2328 rc = ahci_reset_controller(host);
2329 if (rc)
2330 return rc;
1da177e4 2331
4447d351
TH		 2332 ahci_init_controller(host);
2333 ahci_print_info(host);
1da177e4 2334
4447d351
TH		 2335 pci_set_master(pdev);
2336 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2337 &ahci_sht);
907f4678 2338}
1da177e4
LT		 2339
2340static int __init ahci_init(void)
2341{
b7887196 2342 return pci_register_driver(&ahci_pci_driver);
1da177e4
LT		 2343}
2344
1da177e4
LT		 2345static void __exit ahci_exit(void)
2346{
2347 pci_unregister_driver(&ahci_pci_driver);
2348}
2349
2350
2351MODULE_AUTHOR("Jeff Garzik");
2352MODULE_DESCRIPTION("AHCI SATA low-level driver");
2353MODULE_LICENSE("GPL");
2354MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 2355MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 2356
2357module_init(ahci_init);
2358module_exit(ahci_exit);
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