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1da177e4 LT |
1 | /* |
2 | * ahci.c - AHCI SATA support | |
3 | * | |
af36d7f0 JG |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004-2005 Red Hat, Inc. | |
9 | * | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * AHCI hardware documentation: | |
1da177e4 | 30 | * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
af36d7f0 | 31 | * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
1da177e4 LT |
32 | * |
33 | */ | |
34 | ||
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/sched.h> | |
87507cfd | 43 | #include <linux/dma-mapping.h> |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 | 45 | #include <scsi/scsi_host.h> |
193515d5 | 46 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
47 | #include <linux/libata.h> |
48 | #include <asm/io.h> | |
49 | ||
50 | #define DRV_NAME "ahci" | |
8676ce07 | 51 | #define DRV_VERSION "2.0" |
1da177e4 LT |
52 | |
53 | ||
54 | enum { | |
55 | AHCI_PCI_BAR = 5, | |
648a88be | 56 | AHCI_MAX_PORTS = 32, |
1da177e4 LT |
57 | AHCI_MAX_SG = 168, /* hardware max is 64K */ |
58 | AHCI_DMA_BOUNDARY = 0xffffffff, | |
59 | AHCI_USE_CLUSTERING = 0, | |
12fad3f9 | 60 | AHCI_MAX_CMDS = 32, |
dd410ff1 | 61 | AHCI_CMD_SZ = 32, |
12fad3f9 | 62 | AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ, |
1da177e4 | 63 | AHCI_RX_FIS_SZ = 256, |
a0ea7328 | 64 | AHCI_CMD_TBL_CDB = 0x40, |
dd410ff1 TH |
65 | AHCI_CMD_TBL_HDR_SZ = 0x80, |
66 | AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16), | |
67 | AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS, | |
68 | AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + | |
1da177e4 LT |
69 | AHCI_RX_FIS_SZ, |
70 | AHCI_IRQ_ON_SG = (1 << 31), | |
71 | AHCI_CMD_ATAPI = (1 << 5), | |
72 | AHCI_CMD_WRITE = (1 << 6), | |
4b10e559 | 73 | AHCI_CMD_PREFETCH = (1 << 7), |
22b49985 TH |
74 | AHCI_CMD_RESET = (1 << 8), |
75 | AHCI_CMD_CLR_BUSY = (1 << 10), | |
1da177e4 LT |
76 | |
77 | RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ | |
0291f95f | 78 | RX_FIS_SDB = 0x58, /* offset of SDB FIS data */ |
78cd52d0 | 79 | RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */ |
1da177e4 LT |
80 | |
81 | board_ahci = 0, | |
648a88be TH |
82 | board_ahci_pi = 1, |
83 | board_ahci_vt8251 = 2, | |
84 | board_ahci_ign_iferr = 3, | |
1da177e4 LT |
85 | |
86 | /* global controller registers */ | |
87 | HOST_CAP = 0x00, /* host capabilities */ | |
88 | HOST_CTL = 0x04, /* global host control */ | |
89 | HOST_IRQ_STAT = 0x08, /* interrupt status */ | |
90 | HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */ | |
91 | HOST_VERSION = 0x10, /* AHCI spec. version compliancy */ | |
92 | ||
93 | /* HOST_CTL bits */ | |
94 | HOST_RESET = (1 << 0), /* reset controller; self-clear */ | |
95 | HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ | |
96 | HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ | |
97 | ||
98 | /* HOST_CAP bits */ | |
0be0aa98 | 99 | HOST_CAP_SSC = (1 << 14), /* Slumber capable */ |
22b49985 | 100 | HOST_CAP_CLO = (1 << 24), /* Command List Override support */ |
0be0aa98 | 101 | HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ |
979db803 | 102 | HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ |
dd410ff1 | 103 | HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ |
1da177e4 LT |
104 | |
105 | /* registers for each SATA port */ | |
106 | PORT_LST_ADDR = 0x00, /* command list DMA addr */ | |
107 | PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */ | |
108 | PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */ | |
109 | PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */ | |
110 | PORT_IRQ_STAT = 0x10, /* interrupt status */ | |
111 | PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */ | |
112 | PORT_CMD = 0x18, /* port command */ | |
113 | PORT_TFDATA = 0x20, /* taskfile data */ | |
114 | PORT_SIG = 0x24, /* device TF signature */ | |
115 | PORT_CMD_ISSUE = 0x38, /* command issue */ | |
116 | PORT_SCR = 0x28, /* SATA phy register block */ | |
117 | PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */ | |
118 | PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */ | |
119 | PORT_SCR_ERR = 0x30, /* SATA phy register: SError */ | |
120 | PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */ | |
121 | ||
122 | /* PORT_IRQ_{STAT,MASK} bits */ | |
123 | PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ | |
124 | PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ | |
125 | PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ | |
126 | PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ | |
127 | PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ | |
128 | PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ | |
129 | PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ | |
130 | PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ | |
131 | ||
132 | PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ | |
133 | PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ | |
134 | PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ | |
135 | PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ | |
136 | PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ | |
137 | PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ | |
138 | PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ | |
139 | PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ | |
140 | PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ | |
141 | ||
78cd52d0 TH |
142 | PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | |
143 | PORT_IRQ_IF_ERR | | |
144 | PORT_IRQ_CONNECT | | |
4296971d | 145 | PORT_IRQ_PHYRDY | |
78cd52d0 TH |
146 | PORT_IRQ_UNK_FIS, |
147 | PORT_IRQ_ERROR = PORT_IRQ_FREEZE | | |
148 | PORT_IRQ_TF_ERR | | |
149 | PORT_IRQ_HBUS_DATA_ERR, | |
150 | DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | | |
151 | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | | |
152 | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, | |
1da177e4 LT |
153 | |
154 | /* PORT_CMD bits */ | |
02eaa666 | 155 | PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ |
1da177e4 LT |
156 | PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ |
157 | PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ | |
158 | PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ | |
22b49985 | 159 | PORT_CMD_CLO = (1 << 3), /* Command list override */ |
1da177e4 LT |
160 | PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ |
161 | PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ | |
162 | PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ | |
163 | ||
0be0aa98 | 164 | PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ |
1da177e4 LT |
165 | PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ |
166 | PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ | |
167 | PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ | |
4b0060f4 JG |
168 | |
169 | /* hpriv->flags bits */ | |
170 | AHCI_FLAG_MSI = (1 << 0), | |
bf2af2a2 BJ |
171 | |
172 | /* ap->flags bits */ | |
4aeb0e32 TH |
173 | AHCI_FLAG_NO_NCQ = (1 << 24), |
174 | AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */ | |
648a88be | 175 | AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */ |
1da177e4 LT |
176 | }; |
177 | ||
178 | struct ahci_cmd_hdr { | |
179 | u32 opts; | |
180 | u32 status; | |
181 | u32 tbl_addr; | |
182 | u32 tbl_addr_hi; | |
183 | u32 reserved[4]; | |
184 | }; | |
185 | ||
186 | struct ahci_sg { | |
187 | u32 addr; | |
188 | u32 addr_hi; | |
189 | u32 reserved; | |
190 | u32 flags_size; | |
191 | }; | |
192 | ||
193 | struct ahci_host_priv { | |
194 | unsigned long flags; | |
195 | u32 cap; /* cache of HOST_CAP register */ | |
196 | u32 port_map; /* cache of HOST_PORTS_IMPL reg */ | |
197 | }; | |
198 | ||
199 | struct ahci_port_priv { | |
200 | struct ahci_cmd_hdr *cmd_slot; | |
201 | dma_addr_t cmd_slot_dma; | |
202 | void *cmd_tbl; | |
203 | dma_addr_t cmd_tbl_dma; | |
1da177e4 LT |
204 | void *rx_fis; |
205 | dma_addr_t rx_fis_dma; | |
0291f95f TH |
206 | /* for NCQ spurious interrupt analysis */ |
207 | int ncq_saw_spurious_sdb_cnt; | |
208 | unsigned int ncq_saw_d2h:1; | |
209 | unsigned int ncq_saw_dmas:1; | |
1da177e4 LT |
210 | }; |
211 | ||
212 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
213 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
214 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
9a3d9eb0 | 215 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc); |
7d12e780 | 216 | static irqreturn_t ahci_interrupt (int irq, void *dev_instance); |
1da177e4 | 217 | static void ahci_irq_clear(struct ata_port *ap); |
1da177e4 LT |
218 | static int ahci_port_start(struct ata_port *ap); |
219 | static void ahci_port_stop(struct ata_port *ap); | |
1da177e4 LT |
220 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
221 | static void ahci_qc_prep(struct ata_queued_cmd *qc); | |
222 | static u8 ahci_check_status(struct ata_port *ap); | |
78cd52d0 TH |
223 | static void ahci_freeze(struct ata_port *ap); |
224 | static void ahci_thaw(struct ata_port *ap); | |
225 | static void ahci_error_handler(struct ata_port *ap); | |
ad616ffb | 226 | static void ahci_vt8251_error_handler(struct ata_port *ap); |
78cd52d0 | 227 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc); |
c1332875 TH |
228 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg); |
229 | static int ahci_port_resume(struct ata_port *ap); | |
230 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); | |
231 | static int ahci_pci_device_resume(struct pci_dev *pdev); | |
907f4678 | 232 | static void ahci_remove_one (struct pci_dev *pdev); |
1da177e4 | 233 | |
193515d5 | 234 | static struct scsi_host_template ahci_sht = { |
1da177e4 LT |
235 | .module = THIS_MODULE, |
236 | .name = DRV_NAME, | |
237 | .ioctl = ata_scsi_ioctl, | |
238 | .queuecommand = ata_scsi_queuecmd, | |
12fad3f9 TH |
239 | .change_queue_depth = ata_scsi_change_queue_depth, |
240 | .can_queue = AHCI_MAX_CMDS - 1, | |
1da177e4 LT |
241 | .this_id = ATA_SHT_THIS_ID, |
242 | .sg_tablesize = AHCI_MAX_SG, | |
1da177e4 LT |
243 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
244 | .emulated = ATA_SHT_EMULATED, | |
245 | .use_clustering = AHCI_USE_CLUSTERING, | |
246 | .proc_name = DRV_NAME, | |
247 | .dma_boundary = AHCI_DMA_BOUNDARY, | |
248 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 249 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 250 | .bios_param = ata_std_bios_param, |
c1332875 TH |
251 | .suspend = ata_scsi_device_suspend, |
252 | .resume = ata_scsi_device_resume, | |
1da177e4 LT |
253 | }; |
254 | ||
057ace5e | 255 | static const struct ata_port_operations ahci_ops = { |
1da177e4 LT |
256 | .port_disable = ata_port_disable, |
257 | ||
258 | .check_status = ahci_check_status, | |
259 | .check_altstatus = ahci_check_status, | |
1da177e4 LT |
260 | .dev_select = ata_noop_dev_select, |
261 | ||
262 | .tf_read = ahci_tf_read, | |
263 | ||
1da177e4 LT |
264 | .qc_prep = ahci_qc_prep, |
265 | .qc_issue = ahci_qc_issue, | |
266 | ||
1da177e4 LT |
267 | .irq_handler = ahci_interrupt, |
268 | .irq_clear = ahci_irq_clear, | |
269 | ||
270 | .scr_read = ahci_scr_read, | |
271 | .scr_write = ahci_scr_write, | |
272 | ||
78cd52d0 TH |
273 | .freeze = ahci_freeze, |
274 | .thaw = ahci_thaw, | |
275 | ||
276 | .error_handler = ahci_error_handler, | |
277 | .post_internal_cmd = ahci_post_internal_cmd, | |
278 | ||
c1332875 TH |
279 | .port_suspend = ahci_port_suspend, |
280 | .port_resume = ahci_port_resume, | |
281 | ||
1da177e4 LT |
282 | .port_start = ahci_port_start, |
283 | .port_stop = ahci_port_stop, | |
1da177e4 LT |
284 | }; |
285 | ||
ad616ffb TH |
286 | static const struct ata_port_operations ahci_vt8251_ops = { |
287 | .port_disable = ata_port_disable, | |
288 | ||
289 | .check_status = ahci_check_status, | |
290 | .check_altstatus = ahci_check_status, | |
291 | .dev_select = ata_noop_dev_select, | |
292 | ||
293 | .tf_read = ahci_tf_read, | |
294 | ||
295 | .qc_prep = ahci_qc_prep, | |
296 | .qc_issue = ahci_qc_issue, | |
297 | ||
298 | .irq_handler = ahci_interrupt, | |
299 | .irq_clear = ahci_irq_clear, | |
300 | ||
301 | .scr_read = ahci_scr_read, | |
302 | .scr_write = ahci_scr_write, | |
303 | ||
304 | .freeze = ahci_freeze, | |
305 | .thaw = ahci_thaw, | |
306 | ||
307 | .error_handler = ahci_vt8251_error_handler, | |
308 | .post_internal_cmd = ahci_post_internal_cmd, | |
309 | ||
310 | .port_suspend = ahci_port_suspend, | |
311 | .port_resume = ahci_port_resume, | |
312 | ||
313 | .port_start = ahci_port_start, | |
314 | .port_stop = ahci_port_stop, | |
315 | }; | |
316 | ||
98ac62de | 317 | static const struct ata_port_info ahci_port_info[] = { |
1da177e4 LT |
318 | /* board_ahci */ |
319 | { | |
320 | .sht = &ahci_sht, | |
cca3974e | 321 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
4296971d TH |
322 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
323 | ATA_FLAG_SKIP_D2H_BSY, | |
7da79312 | 324 | .pio_mask = 0x1f, /* pio0-4 */ |
1da177e4 LT |
325 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
326 | .port_ops = &ahci_ops, | |
327 | }, | |
648a88be TH |
328 | /* board_ahci_pi */ |
329 | { | |
330 | .sht = &ahci_sht, | |
331 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
332 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
333 | ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI, | |
334 | .pio_mask = 0x1f, /* pio0-4 */ | |
335 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
336 | .port_ops = &ahci_ops, | |
337 | }, | |
bf2af2a2 BJ |
338 | /* board_ahci_vt8251 */ |
339 | { | |
340 | .sht = &ahci_sht, | |
cca3974e | 341 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
bf2af2a2 | 342 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
ad616ffb TH |
343 | ATA_FLAG_SKIP_D2H_BSY | |
344 | ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ, | |
bf2af2a2 BJ |
345 | .pio_mask = 0x1f, /* pio0-4 */ |
346 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
ad616ffb | 347 | .port_ops = &ahci_vt8251_ops, |
bf2af2a2 | 348 | }, |
41669553 TH |
349 | /* board_ahci_ign_iferr */ |
350 | { | |
351 | .sht = &ahci_sht, | |
352 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
353 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | | |
354 | ATA_FLAG_SKIP_D2H_BSY | | |
355 | AHCI_FLAG_IGN_IRQ_IF_ERR, | |
356 | .pio_mask = 0x1f, /* pio0-4 */ | |
357 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
358 | .port_ops = &ahci_ops, | |
359 | }, | |
1da177e4 LT |
360 | }; |
361 | ||
3b7d697d | 362 | static const struct pci_device_id ahci_pci_tbl[] = { |
fe7fa31a | 363 | /* Intel */ |
54bb3a94 JG |
364 | { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */ |
365 | { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */ | |
366 | { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */ | |
367 | { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */ | |
368 | { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */ | |
82490c09 | 369 | { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */ |
54bb3a94 JG |
370 | { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */ |
371 | { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */ | |
372 | { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */ | |
373 | { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */ | |
648a88be TH |
374 | { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */ |
375 | { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */ | |
376 | { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */ | |
377 | { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */ | |
378 | { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */ | |
379 | { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */ | |
380 | { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */ | |
381 | { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */ | |
382 | { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */ | |
383 | { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */ | |
384 | { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */ | |
385 | { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */ | |
386 | { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */ | |
387 | { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */ | |
388 | { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */ | |
389 | { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */ | |
fe7fa31a JG |
390 | |
391 | /* JMicron */ | |
41669553 TH |
392 | { PCI_VDEVICE(JMICRON, 0x2360), board_ahci_ign_iferr }, /* JMB360 */ |
393 | { PCI_VDEVICE(JMICRON, 0x2361), board_ahci_ign_iferr }, /* JMB361 */ | |
394 | { PCI_VDEVICE(JMICRON, 0x2363), board_ahci_ign_iferr }, /* JMB363 */ | |
395 | { PCI_VDEVICE(JMICRON, 0x2365), board_ahci_ign_iferr }, /* JMB365 */ | |
396 | { PCI_VDEVICE(JMICRON, 0x2366), board_ahci_ign_iferr }, /* JMB366 */ | |
fe7fa31a JG |
397 | |
398 | /* ATI */ | |
54bb3a94 JG |
399 | { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */ |
400 | { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */ | |
fe7fa31a JG |
401 | |
402 | /* VIA */ | |
54bb3a94 | 403 | { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */ |
fe7fa31a JG |
404 | |
405 | /* NVIDIA */ | |
54bb3a94 JG |
406 | { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */ |
407 | { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */ | |
408 | { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */ | |
409 | { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */ | |
6fbf5ba4 PC |
410 | { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */ |
411 | { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */ | |
412 | { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */ | |
413 | { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */ | |
414 | { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */ | |
415 | { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */ | |
416 | { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */ | |
417 | { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */ | |
895663cd PC |
418 | { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */ |
419 | { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */ | |
420 | { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */ | |
421 | { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */ | |
422 | { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */ | |
423 | { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */ | |
424 | { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */ | |
425 | { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */ | |
fe7fa31a | 426 | |
95916edd | 427 | /* SiS */ |
54bb3a94 JG |
428 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
429 | { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */ | |
430 | { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */ | |
95916edd | 431 | |
415ae2b5 JG |
432 | /* Generic, PCI class code for AHCI */ |
433 | { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, | |
434 | 0x010601, 0xffffff, board_ahci }, | |
435 | ||
1da177e4 LT |
436 | { } /* terminate list */ |
437 | }; | |
438 | ||
439 | ||
440 | static struct pci_driver ahci_pci_driver = { | |
441 | .name = DRV_NAME, | |
442 | .id_table = ahci_pci_tbl, | |
443 | .probe = ahci_init_one, | |
c1332875 TH |
444 | .suspend = ahci_pci_device_suspend, |
445 | .resume = ahci_pci_device_resume, | |
907f4678 | 446 | .remove = ahci_remove_one, |
1da177e4 LT |
447 | }; |
448 | ||
449 | ||
98fa4b60 TH |
450 | static inline int ahci_nr_ports(u32 cap) |
451 | { | |
452 | return (cap & 0x1f) + 1; | |
453 | } | |
454 | ||
1da177e4 LT |
455 | static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port) |
456 | { | |
457 | return base + 0x100 + (port * 0x80); | |
458 | } | |
459 | ||
ea6ba10b | 460 | static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port) |
1da177e4 | 461 | { |
ea6ba10b | 462 | return (void __iomem *) ahci_port_base_ul((unsigned long)base, port); |
1da177e4 LT |
463 | } |
464 | ||
1da177e4 LT |
465 | static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in) |
466 | { | |
467 | unsigned int sc_reg; | |
468 | ||
469 | switch (sc_reg_in) { | |
470 | case SCR_STATUS: sc_reg = 0; break; | |
471 | case SCR_CONTROL: sc_reg = 1; break; | |
472 | case SCR_ERROR: sc_reg = 2; break; | |
473 | case SCR_ACTIVE: sc_reg = 3; break; | |
474 | default: | |
475 | return 0xffffffffU; | |
476 | } | |
477 | ||
1e4f2a96 | 478 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
479 | } |
480 | ||
481 | ||
482 | static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in, | |
483 | u32 val) | |
484 | { | |
485 | unsigned int sc_reg; | |
486 | ||
487 | switch (sc_reg_in) { | |
488 | case SCR_STATUS: sc_reg = 0; break; | |
489 | case SCR_CONTROL: sc_reg = 1; break; | |
490 | case SCR_ERROR: sc_reg = 2; break; | |
491 | case SCR_ACTIVE: sc_reg = 3; break; | |
492 | default: | |
493 | return; | |
494 | } | |
495 | ||
1e4f2a96 | 496 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
497 | } |
498 | ||
9f592056 | 499 | static void ahci_start_engine(void __iomem *port_mmio) |
7c76d1e8 | 500 | { |
7c76d1e8 TH |
501 | u32 tmp; |
502 | ||
d8fcd116 | 503 | /* start DMA */ |
9f592056 | 504 | tmp = readl(port_mmio + PORT_CMD); |
7c76d1e8 TH |
505 | tmp |= PORT_CMD_START; |
506 | writel(tmp, port_mmio + PORT_CMD); | |
507 | readl(port_mmio + PORT_CMD); /* flush */ | |
508 | } | |
509 | ||
254950cd TH |
510 | static int ahci_stop_engine(void __iomem *port_mmio) |
511 | { | |
512 | u32 tmp; | |
513 | ||
514 | tmp = readl(port_mmio + PORT_CMD); | |
515 | ||
d8fcd116 | 516 | /* check if the HBA is idle */ |
254950cd TH |
517 | if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0) |
518 | return 0; | |
519 | ||
d8fcd116 | 520 | /* setting HBA to idle */ |
254950cd TH |
521 | tmp &= ~PORT_CMD_START; |
522 | writel(tmp, port_mmio + PORT_CMD); | |
523 | ||
d8fcd116 | 524 | /* wait for engine to stop. This could be as long as 500 msec */ |
254950cd TH |
525 | tmp = ata_wait_register(port_mmio + PORT_CMD, |
526 | PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); | |
d8fcd116 | 527 | if (tmp & PORT_CMD_LIST_ON) |
254950cd TH |
528 | return -EIO; |
529 | ||
530 | return 0; | |
531 | } | |
532 | ||
0be0aa98 TH |
533 | static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap, |
534 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
535 | { | |
536 | u32 tmp; | |
537 | ||
538 | /* set FIS registers */ | |
539 | if (cap & HOST_CAP_64) | |
540 | writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI); | |
541 | writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR); | |
542 | ||
543 | if (cap & HOST_CAP_64) | |
544 | writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI); | |
545 | writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR); | |
546 | ||
547 | /* enable FIS reception */ | |
548 | tmp = readl(port_mmio + PORT_CMD); | |
549 | tmp |= PORT_CMD_FIS_RX; | |
550 | writel(tmp, port_mmio + PORT_CMD); | |
551 | ||
552 | /* flush */ | |
553 | readl(port_mmio + PORT_CMD); | |
554 | } | |
555 | ||
556 | static int ahci_stop_fis_rx(void __iomem *port_mmio) | |
557 | { | |
558 | u32 tmp; | |
559 | ||
560 | /* disable FIS reception */ | |
561 | tmp = readl(port_mmio + PORT_CMD); | |
562 | tmp &= ~PORT_CMD_FIS_RX; | |
563 | writel(tmp, port_mmio + PORT_CMD); | |
564 | ||
565 | /* wait for completion, spec says 500ms, give it 1000 */ | |
566 | tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON, | |
567 | PORT_CMD_FIS_ON, 10, 1000); | |
568 | if (tmp & PORT_CMD_FIS_ON) | |
569 | return -EBUSY; | |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | static void ahci_power_up(void __iomem *port_mmio, u32 cap) | |
575 | { | |
576 | u32 cmd; | |
577 | ||
578 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
579 | ||
580 | /* spin up device */ | |
581 | if (cap & HOST_CAP_SSS) { | |
582 | cmd |= PORT_CMD_SPIN_UP; | |
583 | writel(cmd, port_mmio + PORT_CMD); | |
584 | } | |
585 | ||
586 | /* wake up link */ | |
587 | writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD); | |
588 | } | |
589 | ||
590 | static void ahci_power_down(void __iomem *port_mmio, u32 cap) | |
591 | { | |
592 | u32 cmd, scontrol; | |
593 | ||
07c53dac TH |
594 | if (!(cap & HOST_CAP_SSS)) |
595 | return; | |
0be0aa98 | 596 | |
07c53dac TH |
597 | /* put device into listen mode, first set PxSCTL.DET to 0 */ |
598 | scontrol = readl(port_mmio + PORT_SCR_CTL); | |
599 | scontrol &= ~0xf; | |
600 | writel(scontrol, port_mmio + PORT_SCR_CTL); | |
0be0aa98 | 601 | |
07c53dac TH |
602 | /* then set PxCMD.SUD to 0 */ |
603 | cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK; | |
604 | cmd &= ~PORT_CMD_SPIN_UP; | |
605 | writel(cmd, port_mmio + PORT_CMD); | |
0be0aa98 TH |
606 | } |
607 | ||
608 | static void ahci_init_port(void __iomem *port_mmio, u32 cap, | |
609 | dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma) | |
610 | { | |
0be0aa98 TH |
611 | /* enable FIS reception */ |
612 | ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma); | |
613 | ||
614 | /* enable DMA */ | |
615 | ahci_start_engine(port_mmio); | |
616 | } | |
617 | ||
618 | static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg) | |
619 | { | |
620 | int rc; | |
621 | ||
622 | /* disable DMA */ | |
623 | rc = ahci_stop_engine(port_mmio); | |
624 | if (rc) { | |
625 | *emsg = "failed to stop engine"; | |
626 | return rc; | |
627 | } | |
628 | ||
629 | /* disable FIS reception */ | |
630 | rc = ahci_stop_fis_rx(port_mmio); | |
631 | if (rc) { | |
632 | *emsg = "failed stop FIS RX"; | |
633 | return rc; | |
634 | } | |
635 | ||
0be0aa98 TH |
636 | return 0; |
637 | } | |
638 | ||
d91542c1 TH |
639 | static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev) |
640 | { | |
98fa4b60 | 641 | u32 cap_save, impl_save, tmp; |
d91542c1 TH |
642 | |
643 | cap_save = readl(mmio + HOST_CAP); | |
98fa4b60 | 644 | impl_save = readl(mmio + HOST_PORTS_IMPL); |
d91542c1 TH |
645 | |
646 | /* global controller reset */ | |
647 | tmp = readl(mmio + HOST_CTL); | |
648 | if ((tmp & HOST_RESET) == 0) { | |
649 | writel(tmp | HOST_RESET, mmio + HOST_CTL); | |
650 | readl(mmio + HOST_CTL); /* flush */ | |
651 | } | |
652 | ||
653 | /* reset must complete within 1 second, or | |
654 | * the hardware should be considered fried. | |
655 | */ | |
656 | ssleep(1); | |
657 | ||
658 | tmp = readl(mmio + HOST_CTL); | |
659 | if (tmp & HOST_RESET) { | |
660 | dev_printk(KERN_ERR, &pdev->dev, | |
661 | "controller reset failed (0x%x)\n", tmp); | |
662 | return -EIO; | |
663 | } | |
664 | ||
98fa4b60 | 665 | /* turn on AHCI mode */ |
d91542c1 TH |
666 | writel(HOST_AHCI_EN, mmio + HOST_CTL); |
667 | (void) readl(mmio + HOST_CTL); /* flush */ | |
98fa4b60 TH |
668 | |
669 | /* These write-once registers are normally cleared on reset. | |
670 | * Restore BIOS values... which we HOPE were present before | |
671 | * reset. | |
672 | */ | |
673 | if (!impl_save) { | |
674 | impl_save = (1 << ahci_nr_ports(cap_save)) - 1; | |
675 | dev_printk(KERN_WARNING, &pdev->dev, | |
676 | "PORTS_IMPL is zero, forcing 0x%x\n", impl_save); | |
677 | } | |
d91542c1 | 678 | writel(cap_save, mmio + HOST_CAP); |
98fa4b60 | 679 | writel(impl_save, mmio + HOST_PORTS_IMPL); |
d91542c1 TH |
680 | (void) readl(mmio + HOST_PORTS_IMPL); /* flush */ |
681 | ||
682 | if (pdev->vendor == PCI_VENDOR_ID_INTEL) { | |
683 | u16 tmp16; | |
684 | ||
685 | /* configure PCS */ | |
686 | pci_read_config_word(pdev, 0x92, &tmp16); | |
687 | tmp16 |= 0xf; | |
688 | pci_write_config_word(pdev, 0x92, tmp16); | |
689 | } | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
694 | static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev, | |
648a88be TH |
695 | int n_ports, unsigned int port_flags, |
696 | struct ahci_host_priv *hpriv) | |
d91542c1 TH |
697 | { |
698 | int i, rc; | |
699 | u32 tmp; | |
700 | ||
701 | for (i = 0; i < n_ports; i++) { | |
702 | void __iomem *port_mmio = ahci_port_base(mmio, i); | |
703 | const char *emsg = NULL; | |
704 | ||
648a88be TH |
705 | if ((port_flags & AHCI_FLAG_HONOR_PI) && |
706 | !(hpriv->port_map & (1 << i))) | |
d91542c1 | 707 | continue; |
d91542c1 TH |
708 | |
709 | /* make sure port is not active */ | |
648a88be | 710 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); |
d91542c1 TH |
711 | if (rc) |
712 | dev_printk(KERN_WARNING, &pdev->dev, | |
713 | "%s (%d)\n", emsg, rc); | |
714 | ||
715 | /* clear SError */ | |
716 | tmp = readl(port_mmio + PORT_SCR_ERR); | |
717 | VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); | |
718 | writel(tmp, port_mmio + PORT_SCR_ERR); | |
719 | ||
f4b5cc87 | 720 | /* clear port IRQ */ |
d91542c1 TH |
721 | tmp = readl(port_mmio + PORT_IRQ_STAT); |
722 | VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); | |
723 | if (tmp) | |
724 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
725 | ||
726 | writel(1 << i, mmio + HOST_IRQ_STAT); | |
d91542c1 TH |
727 | } |
728 | ||
729 | tmp = readl(mmio + HOST_CTL); | |
730 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
731 | writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); | |
732 | tmp = readl(mmio + HOST_CTL); | |
733 | VPRINTK("HOST_CTL 0x%x\n", tmp); | |
734 | } | |
735 | ||
422b7595 | 736 | static unsigned int ahci_dev_classify(struct ata_port *ap) |
1da177e4 LT |
737 | { |
738 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
739 | struct ata_taskfile tf; | |
422b7595 TH |
740 | u32 tmp; |
741 | ||
742 | tmp = readl(port_mmio + PORT_SIG); | |
743 | tf.lbah = (tmp >> 24) & 0xff; | |
744 | tf.lbam = (tmp >> 16) & 0xff; | |
745 | tf.lbal = (tmp >> 8) & 0xff; | |
746 | tf.nsect = (tmp) & 0xff; | |
747 | ||
748 | return ata_dev_classify(&tf); | |
749 | } | |
750 | ||
12fad3f9 TH |
751 | static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag, |
752 | u32 opts) | |
cc9278ed | 753 | { |
12fad3f9 TH |
754 | dma_addr_t cmd_tbl_dma; |
755 | ||
756 | cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ; | |
757 | ||
758 | pp->cmd_slot[tag].opts = cpu_to_le32(opts); | |
759 | pp->cmd_slot[tag].status = 0; | |
760 | pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff); | |
761 | pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16); | |
cc9278ed TH |
762 | } |
763 | ||
bf2af2a2 | 764 | static int ahci_clo(struct ata_port *ap) |
4658f79b | 765 | { |
bf2af2a2 | 766 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
cca3974e | 767 | struct ahci_host_priv *hpriv = ap->host->private_data; |
bf2af2a2 BJ |
768 | u32 tmp; |
769 | ||
770 | if (!(hpriv->cap & HOST_CAP_CLO)) | |
771 | return -EOPNOTSUPP; | |
772 | ||
773 | tmp = readl(port_mmio + PORT_CMD); | |
774 | tmp |= PORT_CMD_CLO; | |
775 | writel(tmp, port_mmio + PORT_CMD); | |
776 | ||
777 | tmp = ata_wait_register(port_mmio + PORT_CMD, | |
778 | PORT_CMD_CLO, PORT_CMD_CLO, 1, 500); | |
779 | if (tmp & PORT_CMD_CLO) | |
780 | return -EIO; | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | static int ahci_softreset(struct ata_port *ap, unsigned int *class) | |
786 | { | |
4658f79b | 787 | struct ahci_port_priv *pp = ap->private_data; |
cca3974e | 788 | void __iomem *mmio = ap->host->mmio_base; |
4658f79b TH |
789 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
790 | const u32 cmd_fis_len = 5; /* five dwords */ | |
791 | const char *reason = NULL; | |
792 | struct ata_taskfile tf; | |
75fe1806 | 793 | u32 tmp; |
4658f79b TH |
794 | u8 *fis; |
795 | int rc; | |
796 | ||
797 | DPRINTK("ENTER\n"); | |
798 | ||
81952c54 | 799 | if (ata_port_offline(ap)) { |
c2a65852 TH |
800 | DPRINTK("PHY reports no device\n"); |
801 | *class = ATA_DEV_NONE; | |
802 | return 0; | |
803 | } | |
804 | ||
4658f79b | 805 | /* prepare for SRST (AHCI-1.1 10.4.1) */ |
5457f219 | 806 | rc = ahci_stop_engine(port_mmio); |
4658f79b TH |
807 | if (rc) { |
808 | reason = "failed to stop engine"; | |
809 | goto fail_restart; | |
810 | } | |
811 | ||
812 | /* check BUSY/DRQ, perform Command List Override if necessary */ | |
1244a19c | 813 | if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) { |
bf2af2a2 | 814 | rc = ahci_clo(ap); |
4658f79b | 815 | |
bf2af2a2 BJ |
816 | if (rc == -EOPNOTSUPP) { |
817 | reason = "port busy but CLO unavailable"; | |
818 | goto fail_restart; | |
819 | } else if (rc) { | |
820 | reason = "port busy but CLO failed"; | |
4658f79b TH |
821 | goto fail_restart; |
822 | } | |
823 | } | |
824 | ||
825 | /* restart engine */ | |
5457f219 | 826 | ahci_start_engine(port_mmio); |
4658f79b | 827 | |
3373efd8 | 828 | ata_tf_init(ap->device, &tf); |
4658f79b TH |
829 | fis = pp->cmd_tbl; |
830 | ||
831 | /* issue the first D2H Register FIS */ | |
12fad3f9 TH |
832 | ahci_fill_cmd_slot(pp, 0, |
833 | cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY); | |
4658f79b TH |
834 | |
835 | tf.ctl |= ATA_SRST; | |
836 | ata_tf_to_fis(&tf, fis, 0); | |
837 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
838 | ||
839 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
4658f79b | 840 | |
75fe1806 TH |
841 | tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500); |
842 | if (tmp & 0x1) { | |
4658f79b TH |
843 | rc = -EIO; |
844 | reason = "1st FIS failed"; | |
845 | goto fail; | |
846 | } | |
847 | ||
848 | /* spec says at least 5us, but be generous and sleep for 1ms */ | |
849 | msleep(1); | |
850 | ||
851 | /* issue the second D2H Register FIS */ | |
12fad3f9 | 852 | ahci_fill_cmd_slot(pp, 0, cmd_fis_len); |
4658f79b TH |
853 | |
854 | tf.ctl &= ~ATA_SRST; | |
855 | ata_tf_to_fis(&tf, fis, 0); | |
856 | fis[1] &= ~(1 << 7); /* turn off Command FIS bit */ | |
857 | ||
858 | writel(1, port_mmio + PORT_CMD_ISSUE); | |
859 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ | |
860 | ||
861 | /* spec mandates ">= 2ms" before checking status. | |
862 | * We wait 150ms, because that was the magic delay used for | |
863 | * ATAPI devices in Hale Landis's ATADRVR, for the period of time | |
864 | * between when the ATA command register is written, and then | |
865 | * status is checked. Because waiting for "a while" before | |
866 | * checking status is fine, post SRST, we perform this magic | |
867 | * delay here as well. | |
868 | */ | |
869 | msleep(150); | |
870 | ||
871 | *class = ATA_DEV_NONE; | |
81952c54 | 872 | if (ata_port_online(ap)) { |
4658f79b TH |
873 | if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) { |
874 | rc = -EIO; | |
875 | reason = "device not ready"; | |
876 | goto fail; | |
877 | } | |
878 | *class = ahci_dev_classify(ap); | |
879 | } | |
880 | ||
881 | DPRINTK("EXIT, class=%u\n", *class); | |
882 | return 0; | |
883 | ||
884 | fail_restart: | |
5457f219 | 885 | ahci_start_engine(port_mmio); |
4658f79b | 886 | fail: |
f15a1daf | 887 | ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason); |
4658f79b TH |
888 | return rc; |
889 | } | |
890 | ||
2bf2cb26 | 891 | static int ahci_hardreset(struct ata_port *ap, unsigned int *class) |
422b7595 | 892 | { |
4296971d TH |
893 | struct ahci_port_priv *pp = ap->private_data; |
894 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
895 | struct ata_taskfile tf; | |
cca3974e | 896 | void __iomem *mmio = ap->host->mmio_base; |
5457f219 | 897 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
4bd00f6a TH |
898 | int rc; |
899 | ||
900 | DPRINTK("ENTER\n"); | |
1da177e4 | 901 | |
5457f219 | 902 | ahci_stop_engine(port_mmio); |
4296971d TH |
903 | |
904 | /* clear D2H reception area to properly wait for D2H FIS */ | |
905 | ata_tf_init(ap->device, &tf); | |
906 | tf.command = 0xff; | |
907 | ata_tf_to_fis(&tf, d2h_fis, 0); | |
908 | ||
2bf2cb26 | 909 | rc = sata_std_hardreset(ap, class); |
4296971d | 910 | |
5457f219 | 911 | ahci_start_engine(port_mmio); |
1da177e4 | 912 | |
81952c54 | 913 | if (rc == 0 && ata_port_online(ap)) |
4bd00f6a TH |
914 | *class = ahci_dev_classify(ap); |
915 | if (*class == ATA_DEV_UNKNOWN) | |
916 | *class = ATA_DEV_NONE; | |
1da177e4 | 917 | |
4bd00f6a TH |
918 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); |
919 | return rc; | |
920 | } | |
921 | ||
ad616ffb TH |
922 | static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class) |
923 | { | |
924 | void __iomem *mmio = ap->host->mmio_base; | |
925 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
926 | int rc; | |
927 | ||
928 | DPRINTK("ENTER\n"); | |
929 | ||
930 | ahci_stop_engine(port_mmio); | |
931 | ||
932 | rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context)); | |
933 | ||
934 | /* vt8251 needs SError cleared for the port to operate */ | |
935 | ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR)); | |
936 | ||
937 | ahci_start_engine(port_mmio); | |
938 | ||
939 | DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); | |
940 | ||
941 | /* vt8251 doesn't clear BSY on signature FIS reception, | |
942 | * request follow-up softreset. | |
943 | */ | |
944 | return rc ?: -EAGAIN; | |
945 | } | |
946 | ||
4bd00f6a TH |
947 | static void ahci_postreset(struct ata_port *ap, unsigned int *class) |
948 | { | |
949 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; | |
950 | u32 new_tmp, tmp; | |
951 | ||
952 | ata_std_postreset(ap, class); | |
02eaa666 JG |
953 | |
954 | /* Make sure port's ATAPI bit is set appropriately */ | |
955 | new_tmp = tmp = readl(port_mmio + PORT_CMD); | |
4bd00f6a | 956 | if (*class == ATA_DEV_ATAPI) |
02eaa666 JG |
957 | new_tmp |= PORT_CMD_ATAPI; |
958 | else | |
959 | new_tmp &= ~PORT_CMD_ATAPI; | |
960 | if (new_tmp != tmp) { | |
961 | writel(new_tmp, port_mmio + PORT_CMD); | |
962 | readl(port_mmio + PORT_CMD); /* flush */ | |
963 | } | |
1da177e4 LT |
964 | } |
965 | ||
966 | static u8 ahci_check_status(struct ata_port *ap) | |
967 | { | |
1e4f2a96 | 968 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 LT |
969 | |
970 | return readl(mmio + PORT_TFDATA) & 0xFF; | |
971 | } | |
972 | ||
1da177e4 LT |
973 | static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
974 | { | |
975 | struct ahci_port_priv *pp = ap->private_data; | |
976 | u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; | |
977 | ||
978 | ata_tf_from_fis(d2h_fis, tf); | |
979 | } | |
980 | ||
12fad3f9 | 981 | static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
1da177e4 | 982 | { |
cedc9a47 JG |
983 | struct scatterlist *sg; |
984 | struct ahci_sg *ahci_sg; | |
828d09de | 985 | unsigned int n_sg = 0; |
1da177e4 LT |
986 | |
987 | VPRINTK("ENTER\n"); | |
988 | ||
989 | /* | |
990 | * Next, the S/G list. | |
991 | */ | |
12fad3f9 | 992 | ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
cedc9a47 JG |
993 | ata_for_each_sg(sg, qc) { |
994 | dma_addr_t addr = sg_dma_address(sg); | |
995 | u32 sg_len = sg_dma_len(sg); | |
996 | ||
997 | ahci_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
998 | ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
999 | ahci_sg->flags_size = cpu_to_le32(sg_len - 1); | |
828d09de | 1000 | |
cedc9a47 | 1001 | ahci_sg++; |
828d09de | 1002 | n_sg++; |
1da177e4 | 1003 | } |
828d09de JG |
1004 | |
1005 | return n_sg; | |
1da177e4 LT |
1006 | } |
1007 | ||
1008 | static void ahci_qc_prep(struct ata_queued_cmd *qc) | |
1009 | { | |
a0ea7328 JG |
1010 | struct ata_port *ap = qc->ap; |
1011 | struct ahci_port_priv *pp = ap->private_data; | |
cc9278ed | 1012 | int is_atapi = is_atapi_taskfile(&qc->tf); |
12fad3f9 | 1013 | void *cmd_tbl; |
1da177e4 LT |
1014 | u32 opts; |
1015 | const u32 cmd_fis_len = 5; /* five dwords */ | |
828d09de | 1016 | unsigned int n_elem; |
1da177e4 | 1017 | |
1da177e4 LT |
1018 | /* |
1019 | * Fill in command table information. First, the header, | |
1020 | * a SATA Register - Host to Device command FIS. | |
1021 | */ | |
12fad3f9 TH |
1022 | cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ; |
1023 | ||
1024 | ata_tf_to_fis(&qc->tf, cmd_tbl, 0); | |
cc9278ed | 1025 | if (is_atapi) { |
12fad3f9 TH |
1026 | memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
1027 | memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); | |
a0ea7328 | 1028 | } |
1da177e4 | 1029 | |
cc9278ed TH |
1030 | n_elem = 0; |
1031 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
12fad3f9 | 1032 | n_elem = ahci_fill_sg(qc, cmd_tbl); |
1da177e4 | 1033 | |
cc9278ed TH |
1034 | /* |
1035 | * Fill in command slot information. | |
1036 | */ | |
1037 | opts = cmd_fis_len | n_elem << 16; | |
1038 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
1039 | opts |= AHCI_CMD_WRITE; | |
1040 | if (is_atapi) | |
4b10e559 | 1041 | opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
828d09de | 1042 | |
12fad3f9 | 1043 | ahci_fill_cmd_slot(pp, qc->tag, opts); |
1da177e4 LT |
1044 | } |
1045 | ||
78cd52d0 | 1046 | static void ahci_error_intr(struct ata_port *ap, u32 irq_stat) |
1da177e4 | 1047 | { |
78cd52d0 TH |
1048 | struct ahci_port_priv *pp = ap->private_data; |
1049 | struct ata_eh_info *ehi = &ap->eh_info; | |
1050 | unsigned int err_mask = 0, action = 0; | |
1051 | struct ata_queued_cmd *qc; | |
1052 | u32 serror; | |
1da177e4 | 1053 | |
78cd52d0 | 1054 | ata_ehi_clear_desc(ehi); |
1da177e4 | 1055 | |
78cd52d0 TH |
1056 | /* AHCI needs SError cleared; otherwise, it might lock up */ |
1057 | serror = ahci_scr_read(ap, SCR_ERROR); | |
1058 | ahci_scr_write(ap, SCR_ERROR, serror); | |
1da177e4 | 1059 | |
78cd52d0 TH |
1060 | /* analyze @irq_stat */ |
1061 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); | |
1062 | ||
41669553 TH |
1063 | /* some controllers set IRQ_IF_ERR on device errors, ignore it */ |
1064 | if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR) | |
1065 | irq_stat &= ~PORT_IRQ_IF_ERR; | |
1066 | ||
78cd52d0 TH |
1067 | if (irq_stat & PORT_IRQ_TF_ERR) |
1068 | err_mask |= AC_ERR_DEV; | |
1069 | ||
1070 | if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) { | |
1071 | err_mask |= AC_ERR_HOST_BUS; | |
1072 | action |= ATA_EH_SOFTRESET; | |
1da177e4 LT |
1073 | } |
1074 | ||
78cd52d0 TH |
1075 | if (irq_stat & PORT_IRQ_IF_ERR) { |
1076 | err_mask |= AC_ERR_ATA_BUS; | |
1077 | action |= ATA_EH_SOFTRESET; | |
1078 | ata_ehi_push_desc(ehi, ", interface fatal error"); | |
1079 | } | |
1da177e4 | 1080 | |
78cd52d0 | 1081 | if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) { |
4296971d | 1082 | ata_ehi_hotplugged(ehi); |
78cd52d0 TH |
1083 | ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ? |
1084 | "connection status changed" : "PHY RDY changed"); | |
1085 | } | |
1086 | ||
1087 | if (irq_stat & PORT_IRQ_UNK_FIS) { | |
1088 | u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK); | |
1da177e4 | 1089 | |
78cd52d0 TH |
1090 | err_mask |= AC_ERR_HSM; |
1091 | action |= ATA_EH_SOFTRESET; | |
1092 | ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x", | |
1093 | unk[0], unk[1], unk[2], unk[3]); | |
1094 | } | |
1da177e4 | 1095 | |
78cd52d0 TH |
1096 | /* okay, let's hand over to EH */ |
1097 | ehi->serror |= serror; | |
1098 | ehi->action |= action; | |
b8f6153e | 1099 | |
1da177e4 | 1100 | qc = ata_qc_from_tag(ap, ap->active_tag); |
78cd52d0 TH |
1101 | if (qc) |
1102 | qc->err_mask |= err_mask; | |
1103 | else | |
1104 | ehi->err_mask |= err_mask; | |
a72ec4ce | 1105 | |
78cd52d0 TH |
1106 | if (irq_stat & PORT_IRQ_FREEZE) |
1107 | ata_port_freeze(ap); | |
1108 | else | |
1109 | ata_port_abort(ap); | |
1da177e4 LT |
1110 | } |
1111 | ||
78cd52d0 | 1112 | static void ahci_host_intr(struct ata_port *ap) |
1da177e4 | 1113 | { |
cca3974e | 1114 | void __iomem *mmio = ap->host->mmio_base; |
ea6ba10b | 1115 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
12fad3f9 | 1116 | struct ata_eh_info *ehi = &ap->eh_info; |
0291f95f | 1117 | struct ahci_port_priv *pp = ap->private_data; |
12fad3f9 | 1118 | u32 status, qc_active; |
0291f95f | 1119 | int rc, known_irq = 0; |
1da177e4 LT |
1120 | |
1121 | status = readl(port_mmio + PORT_IRQ_STAT); | |
1122 | writel(status, port_mmio + PORT_IRQ_STAT); | |
1123 | ||
78cd52d0 TH |
1124 | if (unlikely(status & PORT_IRQ_ERROR)) { |
1125 | ahci_error_intr(ap, status); | |
1126 | return; | |
1da177e4 LT |
1127 | } |
1128 | ||
12fad3f9 TH |
1129 | if (ap->sactive) |
1130 | qc_active = readl(port_mmio + PORT_SCR_ACT); | |
1131 | else | |
1132 | qc_active = readl(port_mmio + PORT_CMD_ISSUE); | |
1133 | ||
1134 | rc = ata_qc_complete_multiple(ap, qc_active, NULL); | |
1135 | if (rc > 0) | |
1136 | return; | |
1137 | if (rc < 0) { | |
1138 | ehi->err_mask |= AC_ERR_HSM; | |
1139 | ehi->action |= ATA_EH_SOFTRESET; | |
1140 | ata_port_freeze(ap); | |
1141 | return; | |
1da177e4 LT |
1142 | } |
1143 | ||
2a3917a8 TH |
1144 | /* hmmm... a spurious interupt */ |
1145 | ||
0291f95f TH |
1146 | /* if !NCQ, ignore. No modern ATA device has broken HSM |
1147 | * implementation for non-NCQ commands. | |
1148 | */ | |
1149 | if (!ap->sactive) | |
12fad3f9 TH |
1150 | return; |
1151 | ||
0291f95f TH |
1152 | if (status & PORT_IRQ_D2H_REG_FIS) { |
1153 | if (!pp->ncq_saw_d2h) | |
1154 | ata_port_printk(ap, KERN_INFO, | |
1155 | "D2H reg with I during NCQ, " | |
1156 | "this message won't be printed again\n"); | |
1157 | pp->ncq_saw_d2h = 1; | |
1158 | known_irq = 1; | |
1159 | } | |
1160 | ||
1161 | if (status & PORT_IRQ_DMAS_FIS) { | |
1162 | if (!pp->ncq_saw_dmas) | |
1163 | ata_port_printk(ap, KERN_INFO, | |
1164 | "DMAS FIS during NCQ, " | |
1165 | "this message won't be printed again\n"); | |
1166 | pp->ncq_saw_dmas = 1; | |
1167 | known_irq = 1; | |
1168 | } | |
1169 | ||
1170 | if (status & PORT_IRQ_SDB_FIS && | |
1171 | pp->ncq_saw_spurious_sdb_cnt < 10) { | |
1172 | /* SDB FIS containing spurious completions might be | |
1173 | * dangerous, we need to know more about them. Print | |
1174 | * more of it. | |
1175 | */ | |
1176 | const u32 *f = pp->rx_fis + RX_FIS_SDB; | |
1177 | ||
1178 | ata_port_printk(ap, KERN_INFO, "Spurious SDB FIS during NCQ " | |
1179 | "issue=0x%x SAct=0x%x FIS=%08x:%08x%s\n", | |
1180 | readl(port_mmio + PORT_CMD_ISSUE), | |
6096b63e TH |
1181 | readl(port_mmio + PORT_SCR_ACT), |
1182 | le32_to_cpu(f[0]), le32_to_cpu(f[1]), | |
0291f95f TH |
1183 | pp->ncq_saw_spurious_sdb_cnt < 10 ? |
1184 | "" : ", shutting up"); | |
1185 | ||
1186 | pp->ncq_saw_spurious_sdb_cnt++; | |
1187 | known_irq = 1; | |
1188 | } | |
2a3917a8 | 1189 | |
0291f95f | 1190 | if (!known_irq) |
78cd52d0 | 1191 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
0291f95f | 1192 | "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n", |
12fad3f9 | 1193 | status, ap->active_tag, ap->sactive); |
1da177e4 LT |
1194 | } |
1195 | ||
1196 | static void ahci_irq_clear(struct ata_port *ap) | |
1197 | { | |
1198 | /* TODO */ | |
1199 | } | |
1200 | ||
7d12e780 | 1201 | static irqreturn_t ahci_interrupt(int irq, void *dev_instance) |
1da177e4 | 1202 | { |
cca3974e | 1203 | struct ata_host *host = dev_instance; |
1da177e4 LT |
1204 | struct ahci_host_priv *hpriv; |
1205 | unsigned int i, handled = 0; | |
ea6ba10b | 1206 | void __iomem *mmio; |
1da177e4 LT |
1207 | u32 irq_stat, irq_ack = 0; |
1208 | ||
1209 | VPRINTK("ENTER\n"); | |
1210 | ||
cca3974e JG |
1211 | hpriv = host->private_data; |
1212 | mmio = host->mmio_base; | |
1da177e4 LT |
1213 | |
1214 | /* sigh. 0xffffffff is a valid return from h/w */ | |
1215 | irq_stat = readl(mmio + HOST_IRQ_STAT); | |
1216 | irq_stat &= hpriv->port_map; | |
1217 | if (!irq_stat) | |
1218 | return IRQ_NONE; | |
1219 | ||
cca3974e | 1220 | spin_lock(&host->lock); |
1da177e4 | 1221 | |
cca3974e | 1222 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 1223 | struct ata_port *ap; |
1da177e4 | 1224 | |
67846b30 JG |
1225 | if (!(irq_stat & (1 << i))) |
1226 | continue; | |
1227 | ||
cca3974e | 1228 | ap = host->ports[i]; |
67846b30 | 1229 | if (ap) { |
78cd52d0 | 1230 | ahci_host_intr(ap); |
67846b30 JG |
1231 | VPRINTK("port %u\n", i); |
1232 | } else { | |
1233 | VPRINTK("port %u (no irq)\n", i); | |
6971ed1f | 1234 | if (ata_ratelimit()) |
cca3974e | 1235 | dev_printk(KERN_WARNING, host->dev, |
a9524a76 | 1236 | "interrupt on disabled port %u\n", i); |
1da177e4 | 1237 | } |
67846b30 JG |
1238 | |
1239 | irq_ack |= (1 << i); | |
1da177e4 LT |
1240 | } |
1241 | ||
1242 | if (irq_ack) { | |
1243 | writel(irq_ack, mmio + HOST_IRQ_STAT); | |
1244 | handled = 1; | |
1245 | } | |
1246 | ||
cca3974e | 1247 | spin_unlock(&host->lock); |
1da177e4 LT |
1248 | |
1249 | VPRINTK("EXIT\n"); | |
1250 | ||
1251 | return IRQ_RETVAL(handled); | |
1252 | } | |
1253 | ||
9a3d9eb0 | 1254 | static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc) |
1da177e4 LT |
1255 | { |
1256 | struct ata_port *ap = qc->ap; | |
ea6ba10b | 1257 | void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr; |
1da177e4 | 1258 | |
12fad3f9 TH |
1259 | if (qc->tf.protocol == ATA_PROT_NCQ) |
1260 | writel(1 << qc->tag, port_mmio + PORT_SCR_ACT); | |
1261 | writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE); | |
1da177e4 LT |
1262 | readl(port_mmio + PORT_CMD_ISSUE); /* flush */ |
1263 | ||
1264 | return 0; | |
1265 | } | |
1266 | ||
78cd52d0 TH |
1267 | static void ahci_freeze(struct ata_port *ap) |
1268 | { | |
cca3974e | 1269 | void __iomem *mmio = ap->host->mmio_base; |
78cd52d0 TH |
1270 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1271 | ||
1272 | /* turn IRQ off */ | |
1273 | writel(0, port_mmio + PORT_IRQ_MASK); | |
1274 | } | |
1275 | ||
1276 | static void ahci_thaw(struct ata_port *ap) | |
1277 | { | |
cca3974e | 1278 | void __iomem *mmio = ap->host->mmio_base; |
78cd52d0 TH |
1279 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1280 | u32 tmp; | |
1281 | ||
1282 | /* clear IRQ */ | |
1283 | tmp = readl(port_mmio + PORT_IRQ_STAT); | |
1284 | writel(tmp, port_mmio + PORT_IRQ_STAT); | |
1285 | writel(1 << ap->id, mmio + HOST_IRQ_STAT); | |
1286 | ||
1287 | /* turn IRQ back on */ | |
1288 | writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); | |
1289 | } | |
1290 | ||
1291 | static void ahci_error_handler(struct ata_port *ap) | |
1292 | { | |
cca3974e | 1293 | void __iomem *mmio = ap->host->mmio_base; |
5457f219 | 1294 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1295 | ||
b51e9e5d | 1296 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
78cd52d0 | 1297 | /* restart engine */ |
5457f219 | 1298 | ahci_stop_engine(port_mmio); |
1299 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1300 | } |
1301 | ||
1302 | /* perform recovery */ | |
4aeb0e32 | 1303 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset, |
f5914a46 | 1304 | ahci_postreset); |
78cd52d0 TH |
1305 | } |
1306 | ||
ad616ffb TH |
1307 | static void ahci_vt8251_error_handler(struct ata_port *ap) |
1308 | { | |
1309 | void __iomem *mmio = ap->host->mmio_base; | |
1310 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); | |
1311 | ||
1312 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { | |
1313 | /* restart engine */ | |
1314 | ahci_stop_engine(port_mmio); | |
1315 | ahci_start_engine(port_mmio); | |
1316 | } | |
1317 | ||
1318 | /* perform recovery */ | |
1319 | ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset, | |
1320 | ahci_postreset); | |
1321 | } | |
1322 | ||
78cd52d0 TH |
1323 | static void ahci_post_internal_cmd(struct ata_queued_cmd *qc) |
1324 | { | |
1325 | struct ata_port *ap = qc->ap; | |
cca3974e | 1326 | void __iomem *mmio = ap->host->mmio_base; |
5457f219 | 1327 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
78cd52d0 TH |
1328 | |
1329 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1330 | qc->err_mask |= AC_ERR_OTHER; | |
1331 | ||
1332 | if (qc->err_mask) { | |
1333 | /* make DMA engine forget about the failed command */ | |
5457f219 | 1334 | ahci_stop_engine(port_mmio); |
1335 | ahci_start_engine(port_mmio); | |
78cd52d0 TH |
1336 | } |
1337 | } | |
1338 | ||
c1332875 TH |
1339 | static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg) |
1340 | { | |
cca3974e | 1341 | struct ahci_host_priv *hpriv = ap->host->private_data; |
c1332875 | 1342 | struct ahci_port_priv *pp = ap->private_data; |
cca3974e | 1343 | void __iomem *mmio = ap->host->mmio_base; |
c1332875 TH |
1344 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1345 | const char *emsg = NULL; | |
1346 | int rc; | |
1347 | ||
1348 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | |
8e16f941 TH |
1349 | if (rc == 0) |
1350 | ahci_power_down(port_mmio, hpriv->cap); | |
1351 | else { | |
c1332875 TH |
1352 | ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc); |
1353 | ahci_init_port(port_mmio, hpriv->cap, | |
1354 | pp->cmd_slot_dma, pp->rx_fis_dma); | |
1355 | } | |
1356 | ||
1357 | return rc; | |
1358 | } | |
1359 | ||
1360 | static int ahci_port_resume(struct ata_port *ap) | |
1361 | { | |
1362 | struct ahci_port_priv *pp = ap->private_data; | |
cca3974e JG |
1363 | struct ahci_host_priv *hpriv = ap->host->private_data; |
1364 | void __iomem *mmio = ap->host->mmio_base; | |
c1332875 TH |
1365 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1366 | ||
8e16f941 | 1367 | ahci_power_up(port_mmio, hpriv->cap); |
c1332875 TH |
1368 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) | |
1374 | { | |
cca3974e JG |
1375 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1376 | void __iomem *mmio = host->mmio_base; | |
c1332875 TH |
1377 | u32 ctl; |
1378 | ||
1379 | if (mesg.event == PM_EVENT_SUSPEND) { | |
1380 | /* AHCI spec rev1.1 section 8.3.3: | |
1381 | * Software must disable interrupts prior to requesting a | |
1382 | * transition of the HBA to D3 state. | |
1383 | */ | |
1384 | ctl = readl(mmio + HOST_CTL); | |
1385 | ctl &= ~HOST_IRQ_EN; | |
1386 | writel(ctl, mmio + HOST_CTL); | |
1387 | readl(mmio + HOST_CTL); /* flush */ | |
1388 | } | |
1389 | ||
1390 | return ata_pci_device_suspend(pdev, mesg); | |
1391 | } | |
1392 | ||
1393 | static int ahci_pci_device_resume(struct pci_dev *pdev) | |
1394 | { | |
cca3974e JG |
1395 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
1396 | struct ahci_host_priv *hpriv = host->private_data; | |
1397 | void __iomem *mmio = host->mmio_base; | |
c1332875 TH |
1398 | int rc; |
1399 | ||
1400 | ata_pci_device_do_resume(pdev); | |
1401 | ||
1402 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { | |
1403 | rc = ahci_reset_controller(mmio, pdev); | |
1404 | if (rc) | |
1405 | return rc; | |
1406 | ||
648a88be TH |
1407 | ahci_init_controller(mmio, pdev, host->n_ports, |
1408 | host->ports[0]->flags, hpriv); | |
c1332875 TH |
1409 | } |
1410 | ||
cca3974e | 1411 | ata_host_resume(host); |
c1332875 TH |
1412 | |
1413 | return 0; | |
1414 | } | |
1415 | ||
254950cd TH |
1416 | static int ahci_port_start(struct ata_port *ap) |
1417 | { | |
cca3974e JG |
1418 | struct device *dev = ap->host->dev; |
1419 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
254950cd | 1420 | struct ahci_port_priv *pp; |
cca3974e | 1421 | void __iomem *mmio = ap->host->mmio_base; |
254950cd TH |
1422 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
1423 | void *mem; | |
1424 | dma_addr_t mem_dma; | |
1425 | int rc; | |
1426 | ||
1427 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
1428 | if (!pp) | |
1429 | return -ENOMEM; | |
1430 | memset(pp, 0, sizeof(*pp)); | |
1431 | ||
1432 | rc = ata_pad_alloc(ap, dev); | |
1433 | if (rc) { | |
1434 | kfree(pp); | |
1435 | return rc; | |
1436 | } | |
1437 | ||
1438 | mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL); | |
1439 | if (!mem) { | |
1440 | ata_pad_free(ap, dev); | |
1441 | kfree(pp); | |
1442 | return -ENOMEM; | |
1443 | } | |
1444 | memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ); | |
1445 | ||
1446 | /* | |
1447 | * First item in chunk of DMA memory: 32-slot command table, | |
1448 | * 32 bytes each in size | |
1449 | */ | |
1450 | pp->cmd_slot = mem; | |
1451 | pp->cmd_slot_dma = mem_dma; | |
1452 | ||
1453 | mem += AHCI_CMD_SLOT_SZ; | |
1454 | mem_dma += AHCI_CMD_SLOT_SZ; | |
1455 | ||
1456 | /* | |
1457 | * Second item: Received-FIS area | |
1458 | */ | |
1459 | pp->rx_fis = mem; | |
1460 | pp->rx_fis_dma = mem_dma; | |
1461 | ||
1462 | mem += AHCI_RX_FIS_SZ; | |
1463 | mem_dma += AHCI_RX_FIS_SZ; | |
1464 | ||
1465 | /* | |
1466 | * Third item: data area for storing a single command | |
1467 | * and its scatter-gather table | |
1468 | */ | |
1469 | pp->cmd_tbl = mem; | |
1470 | pp->cmd_tbl_dma = mem_dma; | |
1471 | ||
1472 | ap->private_data = pp; | |
1473 | ||
8e16f941 TH |
1474 | /* power up port */ |
1475 | ahci_power_up(port_mmio, hpriv->cap); | |
1476 | ||
0be0aa98 TH |
1477 | /* initialize port */ |
1478 | ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma); | |
254950cd TH |
1479 | |
1480 | return 0; | |
1481 | } | |
1482 | ||
1483 | static void ahci_port_stop(struct ata_port *ap) | |
1484 | { | |
cca3974e JG |
1485 | struct device *dev = ap->host->dev; |
1486 | struct ahci_host_priv *hpriv = ap->host->private_data; | |
254950cd | 1487 | struct ahci_port_priv *pp = ap->private_data; |
cca3974e | 1488 | void __iomem *mmio = ap->host->mmio_base; |
254950cd | 1489 | void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no); |
0be0aa98 TH |
1490 | const char *emsg = NULL; |
1491 | int rc; | |
254950cd | 1492 | |
0be0aa98 TH |
1493 | /* de-initialize port */ |
1494 | rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg); | |
1495 | if (rc) | |
1496 | ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc); | |
254950cd TH |
1497 | |
1498 | ap->private_data = NULL; | |
1499 | dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, | |
1500 | pp->cmd_slot, pp->cmd_slot_dma); | |
1501 | ata_pad_free(ap, dev); | |
1502 | kfree(pp); | |
1503 | } | |
1504 | ||
1da177e4 LT |
1505 | static void ahci_setup_port(struct ata_ioports *port, unsigned long base, |
1506 | unsigned int port_idx) | |
1507 | { | |
1508 | VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx); | |
1509 | base = ahci_port_base_ul(base, port_idx); | |
1510 | VPRINTK("base now==0x%lx\n", base); | |
1511 | ||
1512 | port->cmd_addr = base; | |
1513 | port->scr_addr = base + PORT_SCR; | |
1514 | ||
1515 | VPRINTK("EXIT\n"); | |
1516 | } | |
1517 | ||
1518 | static int ahci_host_init(struct ata_probe_ent *probe_ent) | |
1519 | { | |
1520 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1521 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
1522 | void __iomem *mmio = probe_ent->mmio_base; | |
648a88be | 1523 | unsigned int i, cap_n_ports, using_dac; |
1da177e4 | 1524 | int rc; |
1da177e4 | 1525 | |
d91542c1 TH |
1526 | rc = ahci_reset_controller(mmio, pdev); |
1527 | if (rc) | |
1528 | return rc; | |
1da177e4 LT |
1529 | |
1530 | hpriv->cap = readl(mmio + HOST_CAP); | |
1531 | hpriv->port_map = readl(mmio + HOST_PORTS_IMPL); | |
648a88be | 1532 | cap_n_ports = ahci_nr_ports(hpriv->cap); |
1da177e4 LT |
1533 | |
1534 | VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n", | |
648a88be TH |
1535 | hpriv->cap, hpriv->port_map, cap_n_ports); |
1536 | ||
1537 | if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) { | |
1538 | unsigned int n_ports = cap_n_ports; | |
1539 | u32 port_map = hpriv->port_map; | |
1540 | int max_port = 0; | |
1541 | ||
1542 | for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) { | |
1543 | if (port_map & (1 << i)) { | |
1544 | n_ports--; | |
1545 | port_map &= ~(1 << i); | |
1546 | max_port = i; | |
1547 | } else | |
1548 | probe_ent->dummy_port_mask |= 1 << i; | |
1549 | } | |
1550 | ||
1551 | if (n_ports || port_map) | |
1552 | dev_printk(KERN_WARNING, &pdev->dev, | |
1553 | "nr_ports (%u) and implemented port map " | |
1554 | "(0x%x) don't match\n", | |
1555 | cap_n_ports, hpriv->port_map); | |
1556 | ||
1557 | probe_ent->n_ports = max_port + 1; | |
1558 | } else | |
1559 | probe_ent->n_ports = cap_n_ports; | |
1da177e4 LT |
1560 | |
1561 | using_dac = hpriv->cap & HOST_CAP_64; | |
1562 | if (using_dac && | |
1563 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
1564 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1565 | if (rc) { | |
1566 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1567 | if (rc) { | |
a9524a76 JG |
1568 | dev_printk(KERN_ERR, &pdev->dev, |
1569 | "64-bit DMA enable failed\n"); | |
1da177e4 LT |
1570 | return rc; |
1571 | } | |
1572 | } | |
1da177e4 LT |
1573 | } else { |
1574 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1575 | if (rc) { | |
a9524a76 JG |
1576 | dev_printk(KERN_ERR, &pdev->dev, |
1577 | "32-bit DMA enable failed\n"); | |
1da177e4 LT |
1578 | return rc; |
1579 | } | |
1580 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1581 | if (rc) { | |
a9524a76 JG |
1582 | dev_printk(KERN_ERR, &pdev->dev, |
1583 | "32-bit consistent DMA enable failed\n"); | |
1da177e4 LT |
1584 | return rc; |
1585 | } | |
1586 | } | |
1587 | ||
d91542c1 TH |
1588 | for (i = 0; i < probe_ent->n_ports; i++) |
1589 | ahci_setup_port(&probe_ent->port[i], (unsigned long) mmio, i); | |
1da177e4 | 1590 | |
648a88be TH |
1591 | ahci_init_controller(mmio, pdev, probe_ent->n_ports, |
1592 | probe_ent->port_flags, hpriv); | |
1da177e4 LT |
1593 | |
1594 | pci_set_master(pdev); | |
1595 | ||
1596 | return 0; | |
1597 | } | |
1598 | ||
1da177e4 LT |
1599 | static void ahci_print_info(struct ata_probe_ent *probe_ent) |
1600 | { | |
1601 | struct ahci_host_priv *hpriv = probe_ent->private_data; | |
1602 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
ea6ba10b | 1603 | void __iomem *mmio = probe_ent->mmio_base; |
1da177e4 LT |
1604 | u32 vers, cap, impl, speed; |
1605 | const char *speed_s; | |
1606 | u16 cc; | |
1607 | const char *scc_s; | |
1608 | ||
1609 | vers = readl(mmio + HOST_VERSION); | |
1610 | cap = hpriv->cap; | |
1611 | impl = hpriv->port_map; | |
1612 | ||
1613 | speed = (cap >> 20) & 0xf; | |
1614 | if (speed == 1) | |
1615 | speed_s = "1.5"; | |
1616 | else if (speed == 2) | |
1617 | speed_s = "3"; | |
1618 | else | |
1619 | speed_s = "?"; | |
1620 | ||
1621 | pci_read_config_word(pdev, 0x0a, &cc); | |
1622 | if (cc == 0x0101) | |
1623 | scc_s = "IDE"; | |
1624 | else if (cc == 0x0106) | |
1625 | scc_s = "SATA"; | |
1626 | else if (cc == 0x0104) | |
1627 | scc_s = "RAID"; | |
1628 | else | |
1629 | scc_s = "unknown"; | |
1630 | ||
a9524a76 JG |
1631 | dev_printk(KERN_INFO, &pdev->dev, |
1632 | "AHCI %02x%02x.%02x%02x " | |
1da177e4 LT |
1633 | "%u slots %u ports %s Gbps 0x%x impl %s mode\n" |
1634 | , | |
1da177e4 LT |
1635 | |
1636 | (vers >> 24) & 0xff, | |
1637 | (vers >> 16) & 0xff, | |
1638 | (vers >> 8) & 0xff, | |
1639 | vers & 0xff, | |
1640 | ||
1641 | ((cap >> 8) & 0x1f) + 1, | |
1642 | (cap & 0x1f) + 1, | |
1643 | speed_s, | |
1644 | impl, | |
1645 | scc_s); | |
1646 | ||
a9524a76 JG |
1647 | dev_printk(KERN_INFO, &pdev->dev, |
1648 | "flags: " | |
1da177e4 LT |
1649 | "%s%s%s%s%s%s" |
1650 | "%s%s%s%s%s%s%s\n" | |
1651 | , | |
1da177e4 LT |
1652 | |
1653 | cap & (1 << 31) ? "64bit " : "", | |
1654 | cap & (1 << 30) ? "ncq " : "", | |
1655 | cap & (1 << 28) ? "ilck " : "", | |
1656 | cap & (1 << 27) ? "stag " : "", | |
1657 | cap & (1 << 26) ? "pm " : "", | |
1658 | cap & (1 << 25) ? "led " : "", | |
1659 | ||
1660 | cap & (1 << 24) ? "clo " : "", | |
1661 | cap & (1 << 19) ? "nz " : "", | |
1662 | cap & (1 << 18) ? "only " : "", | |
1663 | cap & (1 << 17) ? "pmp " : "", | |
1664 | cap & (1 << 15) ? "pio " : "", | |
1665 | cap & (1 << 14) ? "slum " : "", | |
1666 | cap & (1 << 13) ? "part " : "" | |
1667 | ); | |
1668 | } | |
1669 | ||
1670 | static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
1671 | { | |
1672 | static int printed_version; | |
1673 | struct ata_probe_ent *probe_ent = NULL; | |
1674 | struct ahci_host_priv *hpriv; | |
1675 | unsigned long base; | |
ea6ba10b | 1676 | void __iomem *mmio_base; |
1da177e4 | 1677 | unsigned int board_idx = (unsigned int) ent->driver_data; |
907f4678 | 1678 | int have_msi, pci_dev_busy = 0; |
1da177e4 LT |
1679 | int rc; |
1680 | ||
1681 | VPRINTK("ENTER\n"); | |
1682 | ||
12fad3f9 TH |
1683 | WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
1684 | ||
1da177e4 | 1685 | if (!printed_version++) |
a9524a76 | 1686 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1687 | |
9545b578 AC |
1688 | /* JMicron-specific fixup: make sure we're in AHCI mode */ |
1689 | /* This is protected from races with ata_jmicron by the pci probe | |
1690 | locking */ | |
1691 | if (pdev->vendor == PCI_VENDOR_ID_JMICRON) { | |
1692 | /* AHCI enable, AHCI on function 0 */ | |
1693 | pci_write_config_byte(pdev, 0x41, 0xa1); | |
1694 | /* Function 1 is the PATA controller */ | |
1695 | if (PCI_FUNC(pdev->devfn)) | |
1696 | return -ENODEV; | |
1697 | } | |
1698 | ||
1da177e4 LT |
1699 | rc = pci_enable_device(pdev); |
1700 | if (rc) | |
1701 | return rc; | |
1702 | ||
1703 | rc = pci_request_regions(pdev, DRV_NAME); | |
1704 | if (rc) { | |
1705 | pci_dev_busy = 1; | |
1706 | goto err_out; | |
1707 | } | |
1708 | ||
907f4678 JG |
1709 | if (pci_enable_msi(pdev) == 0) |
1710 | have_msi = 1; | |
1711 | else { | |
1712 | pci_intx(pdev, 1); | |
1713 | have_msi = 0; | |
1714 | } | |
1da177e4 LT |
1715 | |
1716 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
1717 | if (probe_ent == NULL) { | |
1718 | rc = -ENOMEM; | |
907f4678 | 1719 | goto err_out_msi; |
1da177e4 LT |
1720 | } |
1721 | ||
1722 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
1723 | probe_ent->dev = pci_dev_to_dev(pdev); | |
1724 | INIT_LIST_HEAD(&probe_ent->node); | |
1725 | ||
374b1873 | 1726 | mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0); |
1da177e4 LT |
1727 | if (mmio_base == NULL) { |
1728 | rc = -ENOMEM; | |
1729 | goto err_out_free_ent; | |
1730 | } | |
1731 | base = (unsigned long) mmio_base; | |
1732 | ||
1733 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
1734 | if (!hpriv) { | |
1735 | rc = -ENOMEM; | |
1736 | goto err_out_iounmap; | |
1737 | } | |
1738 | memset(hpriv, 0, sizeof(*hpriv)); | |
1739 | ||
1740 | probe_ent->sht = ahci_port_info[board_idx].sht; | |
cca3974e | 1741 | probe_ent->port_flags = ahci_port_info[board_idx].flags; |
1da177e4 LT |
1742 | probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask; |
1743 | probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask; | |
1744 | probe_ent->port_ops = ahci_port_info[board_idx].port_ops; | |
1745 | ||
1746 | probe_ent->irq = pdev->irq; | |
1d6f359a | 1747 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
1748 | probe_ent->mmio_base = mmio_base; |
1749 | probe_ent->private_data = hpriv; | |
1750 | ||
4b0060f4 JG |
1751 | if (have_msi) |
1752 | hpriv->flags |= AHCI_FLAG_MSI; | |
907f4678 | 1753 | |
1da177e4 LT |
1754 | /* initialize adapter */ |
1755 | rc = ahci_host_init(probe_ent); | |
1756 | if (rc) | |
1757 | goto err_out_hpriv; | |
1758 | ||
cca3974e | 1759 | if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) && |
71f0737b | 1760 | (hpriv->cap & HOST_CAP_NCQ)) |
cca3974e | 1761 | probe_ent->port_flags |= ATA_FLAG_NCQ; |
12fad3f9 | 1762 | |
1da177e4 LT |
1763 | ahci_print_info(probe_ent); |
1764 | ||
1765 | /* FIXME: check ata_device_add return value */ | |
1766 | ata_device_add(probe_ent); | |
1767 | kfree(probe_ent); | |
1768 | ||
1769 | return 0; | |
1770 | ||
1771 | err_out_hpriv: | |
1772 | kfree(hpriv); | |
1773 | err_out_iounmap: | |
374b1873 | 1774 | pci_iounmap(pdev, mmio_base); |
1da177e4 LT |
1775 | err_out_free_ent: |
1776 | kfree(probe_ent); | |
907f4678 JG |
1777 | err_out_msi: |
1778 | if (have_msi) | |
1779 | pci_disable_msi(pdev); | |
1780 | else | |
1781 | pci_intx(pdev, 0); | |
1da177e4 LT |
1782 | pci_release_regions(pdev); |
1783 | err_out: | |
1784 | if (!pci_dev_busy) | |
1785 | pci_disable_device(pdev); | |
1786 | return rc; | |
1787 | } | |
1788 | ||
907f4678 JG |
1789 | static void ahci_remove_one (struct pci_dev *pdev) |
1790 | { | |
1791 | struct device *dev = pci_dev_to_dev(pdev); | |
cca3974e JG |
1792 | struct ata_host *host = dev_get_drvdata(dev); |
1793 | struct ahci_host_priv *hpriv = host->private_data; | |
907f4678 JG |
1794 | unsigned int i; |
1795 | int have_msi; | |
1796 | ||
cca3974e JG |
1797 | for (i = 0; i < host->n_ports; i++) |
1798 | ata_port_detach(host->ports[i]); | |
907f4678 | 1799 | |
4b0060f4 | 1800 | have_msi = hpriv->flags & AHCI_FLAG_MSI; |
cca3974e | 1801 | free_irq(host->irq, host); |
907f4678 | 1802 | |
cca3974e JG |
1803 | for (i = 0; i < host->n_ports; i++) { |
1804 | struct ata_port *ap = host->ports[i]; | |
907f4678 | 1805 | |
cca3974e JG |
1806 | ata_scsi_release(ap->scsi_host); |
1807 | scsi_host_put(ap->scsi_host); | |
907f4678 JG |
1808 | } |
1809 | ||
e005f01d | 1810 | kfree(hpriv); |
cca3974e JG |
1811 | pci_iounmap(pdev, host->mmio_base); |
1812 | kfree(host); | |
ead5de99 | 1813 | |
907f4678 JG |
1814 | if (have_msi) |
1815 | pci_disable_msi(pdev); | |
1816 | else | |
1817 | pci_intx(pdev, 0); | |
1818 | pci_release_regions(pdev); | |
907f4678 JG |
1819 | pci_disable_device(pdev); |
1820 | dev_set_drvdata(dev, NULL); | |
1821 | } | |
1da177e4 LT |
1822 | |
1823 | static int __init ahci_init(void) | |
1824 | { | |
b7887196 | 1825 | return pci_register_driver(&ahci_pci_driver); |
1da177e4 LT |
1826 | } |
1827 | ||
1da177e4 LT |
1828 | static void __exit ahci_exit(void) |
1829 | { | |
1830 | pci_unregister_driver(&ahci_pci_driver); | |
1831 | } | |
1832 | ||
1833 | ||
1834 | MODULE_AUTHOR("Jeff Garzik"); | |
1835 | MODULE_DESCRIPTION("AHCI SATA low-level driver"); | |
1836 | MODULE_LICENSE("GPL"); | |
1837 | MODULE_DEVICE_TABLE(pci, ahci_pci_tbl); | |
6885433c | 1838 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
1839 | |
1840 | module_init(ahci_init); | |
1841 | module_exit(ahci_exit); |