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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
1da177e4 LT |
36 | #include <linux/acpi.h> |
37 | #include <linux/dmi.h> | |
38 | #include <linux/moduleparam.h> | |
4e57b681 | 39 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 40 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 41 | #include <linux/clockchips.h> |
4f86d3a8 | 42 | #include <linux/cpuidle.h> |
ba84be23 | 43 | #include <linux/irqflags.h> |
1da177e4 | 44 | |
3434933b TG |
45 | /* |
46 | * Include the apic definitions for x86 to have the APIC timer related defines | |
47 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
48 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
49 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
50 | */ | |
51 | #ifdef CONFIG_X86 | |
52 | #include <asm/apic.h> | |
53 | #endif | |
54 | ||
1da177e4 LT |
55 | #include <asm/io.h> |
56 | #include <asm/uaccess.h> | |
57 | ||
58 | #include <acpi/acpi_bus.h> | |
59 | #include <acpi/processor.h> | |
c1e3b377 | 60 | #include <asm/processor.h> |
1da177e4 | 61 | |
a192a958 LB |
62 | #define PREFIX "ACPI: " |
63 | ||
1da177e4 | 64 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 65 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 66 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 67 | #define ACPI_PROCESSOR_FILE_POWER "power" |
2aa44d05 | 68 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 LB |
69 | #define C2_OVERHEAD 1 /* 1us */ |
70 | #define C3_OVERHEAD 1 /* 1us */ | |
4f86d3a8 | 71 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
1da177e4 | 72 | |
4f86d3a8 LB |
73 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
74 | module_param(max_cstate, uint, 0000); | |
b6835052 | 75 | static unsigned int nocst __read_mostly; |
1da177e4 | 76 | module_param(nocst, uint, 0000); |
d3e7e99f LB |
77 | static int bm_check_disable __read_mostly; |
78 | module_param(bm_check_disable, uint, 0000); | |
1da177e4 | 79 | |
25de5718 | 80 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 81 | module_param(latency_factor, uint, 0644); |
1da177e4 LT |
82 | |
83 | /* | |
84 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
85 | * For now disable this. Probably a bug somewhere else. | |
86 | * | |
87 | * To skip this limit, boot/load with a large max_cstate limit. | |
88 | */ | |
1855256c | 89 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
90 | { |
91 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
92 | return 0; | |
93 | ||
3d35600a | 94 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
95 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
96 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 97 | |
3d35600a | 98 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
99 | |
100 | return 0; | |
101 | } | |
102 | ||
7ded5689 AR |
103 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
104 | callers to only run once -AK */ | |
105 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
876c184b TR |
106 | { set_max_cstate, "Clevo 5600D", { |
107 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
108 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 109 | (void *)2}, |
370d5cd8 AV |
110 | { set_max_cstate, "Pavilion zv5000", { |
111 | DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), | |
112 | DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, | |
113 | (void *)1}, | |
114 | { set_max_cstate, "Asus L8400B", { | |
115 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), | |
116 | DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, | |
117 | (void *)1}, | |
1da177e4 LT |
118 | {}, |
119 | }; | |
120 | ||
4f86d3a8 | 121 | |
2e906655 | 122 | /* |
123 | * Callers should disable interrupts before the call and enable | |
124 | * interrupts after return. | |
125 | */ | |
ddc081a1 VP |
126 | static void acpi_safe_halt(void) |
127 | { | |
128 | current_thread_info()->status &= ~TS_POLLING; | |
129 | /* | |
130 | * TS_POLLING-cleared state must be visible before we | |
131 | * test NEED_RESCHED: | |
132 | */ | |
133 | smp_mb(); | |
71e93d15 | 134 | if (!need_resched()) { |
ddc081a1 | 135 | safe_halt(); |
71e93d15 VP |
136 | local_irq_disable(); |
137 | } | |
ddc081a1 VP |
138 | current_thread_info()->status |= TS_POLLING; |
139 | } | |
140 | ||
169a0abb TG |
141 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
142 | ||
143 | /* | |
144 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
145 | * This seems to be a common problem on AMD boxen, but other vendors |
146 | * are affected too. We pick the most conservative approach: we assume | |
147 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 148 | */ |
7e275cc4 | 149 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
150 | struct acpi_processor_cx *cx) |
151 | { | |
152 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 153 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 154 | |
db954b58 VP |
155 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
156 | return; | |
157 | ||
87ad57ba SL |
158 | if (boot_cpu_has(X86_FEATURE_AMDC1E)) |
159 | type = ACPI_STATE_C1; | |
160 | ||
169a0abb TG |
161 | /* |
162 | * Check, if one of the previous states already marked the lapic | |
163 | * unstable | |
164 | */ | |
165 | if (pwr->timer_broadcast_on_state < state) | |
166 | return; | |
167 | ||
e585bef8 | 168 | if (cx->type >= type) |
296d93cd | 169 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
170 | } |
171 | ||
918aae42 | 172 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 173 | { |
f833bab8 | 174 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 TG |
175 | unsigned long reason; |
176 | ||
177 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
178 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
179 | ||
180 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
181 | } |
182 | ||
918aae42 HS |
183 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
184 | { | |
185 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
186 | (void *)pr, 1); | |
187 | } | |
188 | ||
e9e2cdb4 | 189 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 190 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
191 | struct acpi_processor_cx *cx, |
192 | int broadcast) | |
193 | { | |
e9e2cdb4 TG |
194 | int state = cx - pr->power.states; |
195 | ||
196 | if (state >= pr->power.timer_broadcast_on_state) { | |
197 | unsigned long reason; | |
198 | ||
199 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
200 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
201 | clockevents_notify(reason, &pr->id); | |
202 | } | |
169a0abb TG |
203 | } |
204 | ||
205 | #else | |
206 | ||
7e275cc4 | 207 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 208 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
209 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
210 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
211 | struct acpi_processor_cx *cx, |
212 | int broadcast) | |
213 | { | |
214 | } | |
169a0abb TG |
215 | |
216 | #endif | |
217 | ||
b04e7bdb TG |
218 | /* |
219 | * Suspend / resume control | |
220 | */ | |
221 | static int acpi_idle_suspend; | |
815ab0fd LB |
222 | static u32 saved_bm_rld; |
223 | ||
224 | static void acpi_idle_bm_rld_save(void) | |
225 | { | |
226 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
227 | } | |
228 | static void acpi_idle_bm_rld_restore(void) | |
229 | { | |
230 | u32 resumed_bm_rld; | |
231 | ||
232 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
233 | ||
234 | if (resumed_bm_rld != saved_bm_rld) | |
235 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); | |
236 | } | |
b04e7bdb TG |
237 | |
238 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
239 | { | |
815ab0fd LB |
240 | if (acpi_idle_suspend == 1) |
241 | return 0; | |
242 | ||
243 | acpi_idle_bm_rld_save(); | |
b04e7bdb TG |
244 | acpi_idle_suspend = 1; |
245 | return 0; | |
246 | } | |
247 | ||
248 | int acpi_processor_resume(struct acpi_device * device) | |
249 | { | |
815ab0fd LB |
250 | if (acpi_idle_suspend == 0) |
251 | return 0; | |
252 | ||
253 | acpi_idle_bm_rld_restore(); | |
b04e7bdb TG |
254 | acpi_idle_suspend = 0; |
255 | return 0; | |
256 | } | |
257 | ||
61331168 | 258 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
520daf72 | 259 | static void tsc_check_state(int state) |
ddb25f9a AK |
260 | { |
261 | switch (boot_cpu_data.x86_vendor) { | |
262 | case X86_VENDOR_AMD: | |
40fb1715 | 263 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
264 | /* |
265 | * AMD Fam10h TSC will tick in all | |
266 | * C/P/S0/S1 states when this bit is set. | |
267 | */ | |
40fb1715 | 268 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 269 | return; |
40fb1715 | 270 | |
ddb25f9a | 271 | /*FALL THROUGH*/ |
ddb25f9a | 272 | default: |
520daf72 LB |
273 | /* TSC could halt in idle, so notify users */ |
274 | if (state > ACPI_STATE_C1) | |
275 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
276 | } |
277 | } | |
520daf72 LB |
278 | #else |
279 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
280 | #endif |
281 | ||
4be44fcd | 282 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 283 | { |
1da177e4 LT |
284 | |
285 | if (!pr) | |
d550d98d | 286 | return -EINVAL; |
1da177e4 LT |
287 | |
288 | if (!pr->pblk) | |
d550d98d | 289 | return -ENODEV; |
1da177e4 | 290 | |
1da177e4 | 291 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
292 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
293 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
294 | ||
4c033552 VP |
295 | #ifndef CONFIG_HOTPLUG_CPU |
296 | /* | |
297 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 298 | * an SMP system. |
4c033552 | 299 | */ |
ad71860a | 300 | if ((num_online_cpus() > 1) && |
cee324b1 | 301 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 302 | return -ENODEV; |
4c033552 VP |
303 | #endif |
304 | ||
1da177e4 LT |
305 | /* determine C2 and C3 address from pblk */ |
306 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
307 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
308 | ||
309 | /* determine latencies from FADT */ | |
cee324b1 AS |
310 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
311 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 | 312 | |
5d76b6f6 LB |
313 | /* |
314 | * FADT specified C2 latency must be less than or equal to | |
315 | * 100 microseconds. | |
316 | */ | |
317 | if (acpi_gbl_FADT.C2latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
318 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
319 | "C2 latency too large [%d]\n", acpi_gbl_FADT.C2latency)); | |
320 | /* invalidate C2 */ | |
321 | pr->power.states[ACPI_STATE_C2].address = 0; | |
322 | } | |
323 | ||
a6d72c18 LB |
324 | /* |
325 | * FADT supplied C3 latency must be less than or equal to | |
326 | * 1000 microseconds. | |
327 | */ | |
328 | if (acpi_gbl_FADT.C3latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
329 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
330 | "C3 latency too large [%d]\n", acpi_gbl_FADT.C3latency)); | |
331 | /* invalidate C3 */ | |
332 | pr->power.states[ACPI_STATE_C3].address = 0; | |
333 | } | |
334 | ||
1da177e4 LT |
335 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
336 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
337 | pr->power.states[ACPI_STATE_C2].address, | |
338 | pr->power.states[ACPI_STATE_C3].address)); | |
339 | ||
d550d98d | 340 | return 0; |
1da177e4 LT |
341 | } |
342 | ||
991528d7 | 343 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 344 | { |
991528d7 VP |
345 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
346 | /* set the first C-State to C1 */ | |
347 | /* all processors need to support C1 */ | |
348 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
349 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 350 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
351 | } |
352 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 353 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 354 | return 0; |
acf05f4b VP |
355 | } |
356 | ||
4be44fcd | 357 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 358 | { |
4be44fcd | 359 | acpi_status status = 0; |
439913ff | 360 | u64 count; |
cf824788 | 361 | int current_count; |
4be44fcd LB |
362 | int i; |
363 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
364 | union acpi_object *cst; | |
1da177e4 | 365 | |
1da177e4 | 366 | |
1da177e4 | 367 | if (nocst) |
d550d98d | 368 | return -ENODEV; |
1da177e4 | 369 | |
991528d7 | 370 | current_count = 0; |
1da177e4 LT |
371 | |
372 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
373 | if (ACPI_FAILURE(status)) { | |
374 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 375 | return -ENODEV; |
4be44fcd | 376 | } |
1da177e4 | 377 | |
50dd0969 | 378 | cst = buffer.pointer; |
1da177e4 LT |
379 | |
380 | /* There must be at least 2 elements */ | |
381 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 382 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
383 | status = -EFAULT; |
384 | goto end; | |
385 | } | |
386 | ||
387 | count = cst->package.elements[0].integer.value; | |
388 | ||
389 | /* Validate number of power states. */ | |
390 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 391 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
392 | status = -EFAULT; |
393 | goto end; | |
394 | } | |
395 | ||
1da177e4 LT |
396 | /* Tell driver that at least _CST is supported. */ |
397 | pr->flags.has_cst = 1; | |
398 | ||
399 | for (i = 1; i <= count; i++) { | |
400 | union acpi_object *element; | |
401 | union acpi_object *obj; | |
402 | struct acpi_power_register *reg; | |
403 | struct acpi_processor_cx cx; | |
404 | ||
405 | memset(&cx, 0, sizeof(cx)); | |
406 | ||
50dd0969 | 407 | element = &(cst->package.elements[i]); |
1da177e4 LT |
408 | if (element->type != ACPI_TYPE_PACKAGE) |
409 | continue; | |
410 | ||
411 | if (element->package.count != 4) | |
412 | continue; | |
413 | ||
50dd0969 | 414 | obj = &(element->package.elements[0]); |
1da177e4 LT |
415 | |
416 | if (obj->type != ACPI_TYPE_BUFFER) | |
417 | continue; | |
418 | ||
4be44fcd | 419 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
420 | |
421 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 422 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
423 | continue; |
424 | ||
1da177e4 | 425 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 426 | obj = &(element->package.elements[1]); |
1da177e4 LT |
427 | if (obj->type != ACPI_TYPE_INTEGER) |
428 | continue; | |
429 | ||
430 | cx.type = obj->integer.value; | |
991528d7 VP |
431 | /* |
432 | * Some buggy BIOSes won't list C1 in _CST - | |
433 | * Let acpi_processor_get_power_info_default() handle them later | |
434 | */ | |
435 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
436 | current_count++; | |
437 | ||
438 | cx.address = reg->address; | |
439 | cx.index = current_count + 1; | |
440 | ||
bc71bec9 | 441 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
442 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
443 | if (acpi_processor_ffh_cstate_probe | |
444 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 445 | cx.entry_method = ACPI_CSTATE_FFH; |
446 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
447 | /* |
448 | * C1 is a special case where FIXED_HARDWARE | |
449 | * can be handled in non-MWAIT way as well. | |
450 | * In that case, save this _CST entry info. | |
991528d7 VP |
451 | * Otherwise, ignore this info and continue. |
452 | */ | |
bc71bec9 | 453 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 454 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 455 | } else { |
991528d7 VP |
456 | continue; |
457 | } | |
da5e09a1 ZY |
458 | if (cx.type == ACPI_STATE_C1 && |
459 | (idle_halt || idle_nomwait)) { | |
c1e3b377 ZY |
460 | /* |
461 | * In most cases the C1 space_id obtained from | |
462 | * _CST object is FIXED_HARDWARE access mode. | |
463 | * But when the option of idle=halt is added, | |
464 | * the entry_method type should be changed from | |
465 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
466 | * When the option of idle=nomwait is added, |
467 | * the C1 entry_method type should be | |
468 | * CSTATE_HALT. | |
c1e3b377 ZY |
469 | */ |
470 | cx.entry_method = ACPI_CSTATE_HALT; | |
471 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
472 | } | |
4fcb2fcd VP |
473 | } else { |
474 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
475 | cx.address); | |
991528d7 | 476 | } |
1da177e4 | 477 | |
0fda6b40 VP |
478 | if (cx.type == ACPI_STATE_C1) { |
479 | cx.valid = 1; | |
480 | } | |
4fcb2fcd | 481 | |
50dd0969 | 482 | obj = &(element->package.elements[2]); |
1da177e4 LT |
483 | if (obj->type != ACPI_TYPE_INTEGER) |
484 | continue; | |
485 | ||
486 | cx.latency = obj->integer.value; | |
487 | ||
50dd0969 | 488 | obj = &(element->package.elements[3]); |
1da177e4 LT |
489 | if (obj->type != ACPI_TYPE_INTEGER) |
490 | continue; | |
491 | ||
492 | cx.power = obj->integer.value; | |
493 | ||
cf824788 JM |
494 | current_count++; |
495 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
496 | ||
497 | /* | |
498 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
499 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
500 | */ | |
501 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
502 | printk(KERN_WARNING | |
503 | "Limiting number of power states to max (%d)\n", | |
504 | ACPI_PROCESSOR_MAX_POWER); | |
505 | printk(KERN_WARNING | |
506 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
507 | break; | |
508 | } | |
1da177e4 LT |
509 | } |
510 | ||
4be44fcd | 511 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 512 | current_count)); |
1da177e4 LT |
513 | |
514 | /* Validate number of power states discovered */ | |
cf824788 | 515 | if (current_count < 2) |
6d93c648 | 516 | status = -EFAULT; |
1da177e4 | 517 | |
4be44fcd | 518 | end: |
02438d87 | 519 | kfree(buffer.pointer); |
1da177e4 | 520 | |
d550d98d | 521 | return status; |
1da177e4 LT |
522 | } |
523 | ||
4be44fcd LB |
524 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
525 | struct acpi_processor_cx *cx) | |
1da177e4 | 526 | { |
ee1ca48f PV |
527 | static int bm_check_flag = -1; |
528 | static int bm_control_flag = -1; | |
02df8b93 | 529 | |
1da177e4 LT |
530 | |
531 | if (!cx->address) | |
d550d98d | 532 | return; |
1da177e4 | 533 | |
1da177e4 LT |
534 | /* |
535 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
536 | * DMA transfers are used by any ISA device to avoid livelock. | |
537 | * Note that we could disable Type-F DMA (as recommended by | |
538 | * the erratum), but this is known to disrupt certain ISA | |
539 | * devices thus we take the conservative approach. | |
540 | */ | |
541 | else if (errata.piix4.fdma) { | |
542 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 543 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 544 | return; |
1da177e4 LT |
545 | } |
546 | ||
02df8b93 | 547 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 548 | if (bm_check_flag == -1) { |
02df8b93 VP |
549 | /* Determine whether bm_check is needed based on CPU */ |
550 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
551 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 552 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
553 | } else { |
554 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 555 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
556 | } |
557 | ||
558 | if (pr->flags.bm_check) { | |
02df8b93 | 559 | if (!pr->flags.bm_control) { |
ed3110ef VP |
560 | if (pr->flags.has_cst != 1) { |
561 | /* bus mastering control is necessary */ | |
562 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
563 | "C3 support requires BM control\n")); | |
564 | return; | |
565 | } else { | |
566 | /* Here we enter C3 without bus mastering */ | |
567 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
568 | "C3 support without BM control\n")); | |
569 | } | |
02df8b93 VP |
570 | } |
571 | } else { | |
02df8b93 VP |
572 | /* |
573 | * WBINVD should be set in fadt, for C3 state to be | |
574 | * supported on when bm_check is not required. | |
575 | */ | |
cee324b1 | 576 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 577 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
578 | "Cache invalidation should work properly" |
579 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 580 | return; |
02df8b93 | 581 | } |
02df8b93 VP |
582 | } |
583 | ||
1da177e4 LT |
584 | /* |
585 | * Otherwise we've met all of our C3 requirements. | |
586 | * Normalize the C3 latency to expidite policy. Enable | |
587 | * checking of bus mastering status (bm_check) so we can | |
588 | * use this in our C3 policy | |
589 | */ | |
590 | cx->valid = 1; | |
4f86d3a8 | 591 | |
4f86d3a8 | 592 | cx->latency_ticks = cx->latency; |
31878dd8 LB |
593 | /* |
594 | * On older chipsets, BM_RLD needs to be set | |
595 | * in order for Bus Master activity to wake the | |
596 | * system from C3. Newer chipsets handle DMA | |
597 | * during C3 automatically and BM_RLD is a NOP. | |
598 | * In either case, the proper way to | |
599 | * handle BM_RLD is to set it and leave it set. | |
600 | */ | |
50ffba1b | 601 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 602 | |
d550d98d | 603 | return; |
1da177e4 LT |
604 | } |
605 | ||
1da177e4 LT |
606 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
607 | { | |
608 | unsigned int i; | |
609 | unsigned int working = 0; | |
6eb0a0fd | 610 | |
169a0abb | 611 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 612 | |
a0bf284b | 613 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
614 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
615 | ||
616 | switch (cx->type) { | |
617 | case ACPI_STATE_C1: | |
618 | cx->valid = 1; | |
619 | break; | |
620 | ||
621 | case ACPI_STATE_C2: | |
d22edd29 LB |
622 | if (!cx->address) |
623 | break; | |
624 | cx->valid = 1; | |
625 | cx->latency_ticks = cx->latency; /* Normalize latency */ | |
1da177e4 LT |
626 | break; |
627 | ||
628 | case ACPI_STATE_C3: | |
629 | acpi_processor_power_verify_c3(pr, cx); | |
630 | break; | |
631 | } | |
7e275cc4 LB |
632 | if (!cx->valid) |
633 | continue; | |
1da177e4 | 634 | |
7e275cc4 LB |
635 | lapic_timer_check_state(i, pr, cx); |
636 | tsc_check_state(cx->type); | |
637 | working++; | |
1da177e4 | 638 | } |
bd663347 | 639 | |
918aae42 | 640 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
641 | |
642 | return (working); | |
643 | } | |
644 | ||
4be44fcd | 645 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
646 | { |
647 | unsigned int i; | |
648 | int result; | |
649 | ||
1da177e4 LT |
650 | |
651 | /* NOTE: the idle thread may not be running while calling | |
652 | * this function */ | |
653 | ||
991528d7 VP |
654 | /* Zero initialize all the C-states info. */ |
655 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
656 | ||
1da177e4 | 657 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 658 | if (result == -ENODEV) |
c5a114f1 | 659 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 660 | |
991528d7 VP |
661 | if (result) |
662 | return result; | |
663 | ||
664 | acpi_processor_get_power_info_default(pr); | |
665 | ||
cf824788 | 666 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 667 | |
1da177e4 LT |
668 | /* |
669 | * if one state of type C2 or C3 is available, mark this | |
670 | * CPU as being "idle manageable" | |
671 | */ | |
672 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 673 | if (pr->power.states[i].valid) { |
1da177e4 | 674 | pr->power.count = i; |
2203d6ed LT |
675 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
676 | pr->flags.power = 1; | |
acf05f4b | 677 | } |
1da177e4 LT |
678 | } |
679 | ||
d550d98d | 680 | return 0; |
1da177e4 LT |
681 | } |
682 | ||
4f86d3a8 LB |
683 | /** |
684 | * acpi_idle_bm_check - checks if bus master activity was detected | |
685 | */ | |
686 | static int acpi_idle_bm_check(void) | |
687 | { | |
688 | u32 bm_status = 0; | |
689 | ||
d3e7e99f LB |
690 | if (bm_check_disable) |
691 | return 0; | |
692 | ||
50ffba1b | 693 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 694 | if (bm_status) |
50ffba1b | 695 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
696 | /* |
697 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
698 | * the true state of bus mastering activity; forcing us to | |
699 | * manually check the BMIDEA bit of each IDE channel. | |
700 | */ | |
701 | else if (errata.piix4.bmisx) { | |
702 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
703 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
704 | bm_status = 1; | |
705 | } | |
706 | return bm_status; | |
707 | } | |
708 | ||
4f86d3a8 LB |
709 | /** |
710 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
711 | * @cx: cstate data | |
bc71bec9 | 712 | * |
713 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
714 | */ |
715 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
716 | { | |
dcf30997 SR |
717 | /* Don't trace irqs off for idle */ |
718 | stop_critical_timings(); | |
bc71bec9 | 719 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
720 | /* Call into architectural FFH based C-state */ |
721 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 722 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
723 | acpi_safe_halt(); | |
4f86d3a8 | 724 | } else { |
4f86d3a8 LB |
725 | /* IO port based C-state */ |
726 | inb(cx->address); | |
727 | /* Dummy wait op - must do something useless after P_LVL2 read | |
728 | because chipsets cannot guarantee that STPCLK# signal | |
729 | gets asserted in time to freeze execution properly. */ | |
cfa806f0 | 730 | inl(acpi_gbl_FADT.xpm_timer_block.address); |
4f86d3a8 | 731 | } |
dcf30997 | 732 | start_critical_timings(); |
4f86d3a8 LB |
733 | } |
734 | ||
735 | /** | |
736 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
737 | * @dev: the target CPU | |
738 | * @state: the state data | |
739 | * | |
740 | * This is equivalent to the HALT instruction. | |
741 | */ | |
742 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
743 | struct cpuidle_state *state) | |
744 | { | |
ff69f2bb | 745 | ktime_t kt1, kt2; |
746 | s64 idle_time; | |
4f86d3a8 LB |
747 | struct acpi_processor *pr; |
748 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
9b12e18c | 749 | |
706546d0 | 750 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
751 | |
752 | if (unlikely(!pr)) | |
753 | return 0; | |
754 | ||
2e906655 | 755 | local_irq_disable(); |
b077fbad VP |
756 | |
757 | /* Do not access any ACPI IO ports in suspend path */ | |
758 | if (acpi_idle_suspend) { | |
b077fbad | 759 | local_irq_enable(); |
7d60e8ab | 760 | cpu_relax(); |
b077fbad VP |
761 | return 0; |
762 | } | |
763 | ||
7e275cc4 | 764 | lapic_timer_state_broadcast(pr, cx, 1); |
ff69f2bb | 765 | kt1 = ktime_get_real(); |
bc71bec9 | 766 | acpi_idle_do_entry(cx); |
ff69f2bb | 767 | kt2 = ktime_get_real(); |
768 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 769 | |
2e906655 | 770 | local_irq_enable(); |
4f86d3a8 | 771 | cx->usage++; |
7e275cc4 | 772 | lapic_timer_state_broadcast(pr, cx, 0); |
4f86d3a8 | 773 | |
ff69f2bb | 774 | return idle_time; |
4f86d3a8 LB |
775 | } |
776 | ||
777 | /** | |
778 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
779 | * @dev: the target CPU | |
780 | * @state: the state data | |
781 | */ | |
782 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
783 | struct cpuidle_state *state) | |
784 | { | |
785 | struct acpi_processor *pr; | |
786 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 787 | ktime_t kt1, kt2; |
2da513f5 | 788 | s64 idle_time_ns; |
ff69f2bb | 789 | s64 idle_time; |
50629118 | 790 | |
706546d0 | 791 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
792 | |
793 | if (unlikely(!pr)) | |
794 | return 0; | |
795 | ||
e196441b LB |
796 | if (acpi_idle_suspend) |
797 | return(acpi_idle_enter_c1(dev, state)); | |
798 | ||
4f86d3a8 | 799 | local_irq_disable(); |
02cf4f98 | 800 | |
d306ebc2 PV |
801 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
802 | current_thread_info()->status &= ~TS_POLLING; | |
803 | /* | |
804 | * TS_POLLING-cleared state must be visible before we test | |
805 | * NEED_RESCHED: | |
806 | */ | |
807 | smp_mb(); | |
4f86d3a8 | 808 | |
02cf4f98 LB |
809 | if (unlikely(need_resched())) { |
810 | current_thread_info()->status |= TS_POLLING; | |
811 | local_irq_enable(); | |
812 | return 0; | |
813 | } | |
4f86d3a8 LB |
814 | } |
815 | ||
e17bcb43 TG |
816 | /* |
817 | * Must be done before busmaster disable as we might need to | |
818 | * access HPET ! | |
819 | */ | |
7e275cc4 | 820 | lapic_timer_state_broadcast(pr, cx, 1); |
e17bcb43 | 821 | |
4f86d3a8 LB |
822 | if (cx->type == ACPI_STATE_C3) |
823 | ACPI_FLUSH_CPU_CACHE(); | |
824 | ||
ff69f2bb | 825 | kt1 = ktime_get_real(); |
50629118 VP |
826 | /* Tell the scheduler that we are going deep-idle: */ |
827 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 828 | acpi_idle_do_entry(cx); |
ff69f2bb | 829 | kt2 = ktime_get_real(); |
2da513f5 VP |
830 | idle_time_ns = ktime_to_ns(ktime_sub(kt2, kt1)); |
831 | idle_time = idle_time_ns; | |
832 | do_div(idle_time, NSEC_PER_USEC); | |
4f86d3a8 | 833 | |
50629118 | 834 | /* Tell the scheduler how much we idled: */ |
2da513f5 | 835 | sched_clock_idle_wakeup_event(idle_time_ns); |
4f86d3a8 LB |
836 | |
837 | local_irq_enable(); | |
02cf4f98 LB |
838 | if (cx->entry_method != ACPI_CSTATE_FFH) |
839 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 LB |
840 | |
841 | cx->usage++; | |
842 | ||
7e275cc4 | 843 | lapic_timer_state_broadcast(pr, cx, 0); |
bceefad5 | 844 | cx->time += idle_time; |
ff69f2bb | 845 | return idle_time; |
4f86d3a8 LB |
846 | } |
847 | ||
848 | static int c3_cpu_count; | |
849 | static DEFINE_SPINLOCK(c3_lock); | |
850 | ||
851 | /** | |
852 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
853 | * @dev: the target CPU | |
854 | * @state: the state data | |
855 | * | |
856 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
857 | */ | |
858 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
859 | struct cpuidle_state *state) | |
860 | { | |
861 | struct acpi_processor *pr; | |
862 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 863 | ktime_t kt1, kt2; |
2da513f5 | 864 | s64 idle_time_ns; |
ff69f2bb | 865 | s64 idle_time; |
ff69f2bb | 866 | |
50629118 | 867 | |
706546d0 | 868 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
869 | |
870 | if (unlikely(!pr)) | |
871 | return 0; | |
872 | ||
e196441b LB |
873 | if (acpi_idle_suspend) |
874 | return(acpi_idle_enter_c1(dev, state)); | |
875 | ||
718be4aa | 876 | if (!cx->bm_sts_skip && acpi_idle_bm_check()) { |
ddc081a1 | 877 | if (dev->safe_state) { |
addbad46 | 878 | dev->last_state = dev->safe_state; |
ddc081a1 VP |
879 | return dev->safe_state->enter(dev, dev->safe_state); |
880 | } else { | |
2e906655 | 881 | local_irq_disable(); |
ddc081a1 | 882 | acpi_safe_halt(); |
2e906655 | 883 | local_irq_enable(); |
ddc081a1 VP |
884 | return 0; |
885 | } | |
886 | } | |
887 | ||
4f86d3a8 | 888 | local_irq_disable(); |
02cf4f98 | 889 | |
d306ebc2 PV |
890 | if (cx->entry_method != ACPI_CSTATE_FFH) { |
891 | current_thread_info()->status &= ~TS_POLLING; | |
892 | /* | |
893 | * TS_POLLING-cleared state must be visible before we test | |
894 | * NEED_RESCHED: | |
895 | */ | |
896 | smp_mb(); | |
4f86d3a8 | 897 | |
02cf4f98 LB |
898 | if (unlikely(need_resched())) { |
899 | current_thread_info()->status |= TS_POLLING; | |
900 | local_irq_enable(); | |
901 | return 0; | |
902 | } | |
4f86d3a8 LB |
903 | } |
904 | ||
996520c1 VP |
905 | acpi_unlazy_tlb(smp_processor_id()); |
906 | ||
50629118 VP |
907 | /* Tell the scheduler that we are going deep-idle: */ |
908 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
909 | /* |
910 | * Must be done before busmaster disable as we might need to | |
911 | * access HPET ! | |
912 | */ | |
7e275cc4 | 913 | lapic_timer_state_broadcast(pr, cx, 1); |
4f86d3a8 | 914 | |
f461ddea | 915 | kt1 = ktime_get_real(); |
ddc081a1 VP |
916 | /* |
917 | * disable bus master | |
918 | * bm_check implies we need ARB_DIS | |
919 | * !bm_check implies we need cache flush | |
920 | * bm_control implies whether we can do ARB_DIS | |
921 | * | |
922 | * That leaves a case where bm_check is set and bm_control is | |
923 | * not set. In that case we cannot do much, we enter C3 | |
924 | * without doing anything. | |
925 | */ | |
926 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
927 | spin_lock(&c3_lock); |
928 | c3_cpu_count++; | |
929 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
930 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 931 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
4f86d3a8 | 932 | spin_unlock(&c3_lock); |
ddc081a1 VP |
933 | } else if (!pr->flags.bm_check) { |
934 | ACPI_FLUSH_CPU_CACHE(); | |
935 | } | |
4f86d3a8 | 936 | |
ddc081a1 | 937 | acpi_idle_do_entry(cx); |
4f86d3a8 | 938 | |
ddc081a1 VP |
939 | /* Re-enable bus master arbitration */ |
940 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 941 | spin_lock(&c3_lock); |
50ffba1b | 942 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
943 | c3_cpu_count--; |
944 | spin_unlock(&c3_lock); | |
945 | } | |
f461ddea | 946 | kt2 = ktime_get_real(); |
157317ba | 947 | idle_time_ns = ktime_to_ns(ktime_sub(kt2, kt1)); |
2da513f5 VP |
948 | idle_time = idle_time_ns; |
949 | do_div(idle_time, NSEC_PER_USEC); | |
4f86d3a8 | 950 | |
50629118 | 951 | /* Tell the scheduler how much we idled: */ |
2da513f5 | 952 | sched_clock_idle_wakeup_event(idle_time_ns); |
4f86d3a8 LB |
953 | |
954 | local_irq_enable(); | |
02cf4f98 LB |
955 | if (cx->entry_method != ACPI_CSTATE_FFH) |
956 | current_thread_info()->status |= TS_POLLING; | |
4f86d3a8 LB |
957 | |
958 | cx->usage++; | |
959 | ||
7e275cc4 | 960 | lapic_timer_state_broadcast(pr, cx, 0); |
bceefad5 | 961 | cx->time += idle_time; |
ff69f2bb | 962 | return idle_time; |
4f86d3a8 LB |
963 | } |
964 | ||
965 | struct cpuidle_driver acpi_idle_driver = { | |
966 | .name = "acpi_idle", | |
967 | .owner = THIS_MODULE, | |
968 | }; | |
969 | ||
970 | /** | |
971 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
972 | * @pr: the ACPI processor | |
973 | */ | |
974 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
975 | { | |
9a0b8415 | 976 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 LB |
977 | struct acpi_processor_cx *cx; |
978 | struct cpuidle_state *state; | |
979 | struct cpuidle_device *dev = &pr->power.dev; | |
980 | ||
981 | if (!pr->flags.power_setup_done) | |
982 | return -EINVAL; | |
983 | ||
984 | if (pr->flags.power == 0) { | |
985 | return -EINVAL; | |
986 | } | |
987 | ||
dcb84f33 | 988 | dev->cpu = pr->id; |
4fcb2fcd VP |
989 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
990 | dev->states[i].name[0] = '\0'; | |
991 | dev->states[i].desc[0] = '\0'; | |
992 | } | |
993 | ||
615dfd93 LB |
994 | if (max_cstate == 0) |
995 | max_cstate = 1; | |
996 | ||
4f86d3a8 LB |
997 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
998 | cx = &pr->power.states[i]; | |
999 | state = &dev->states[count]; | |
1000 | ||
1001 | if (!cx->valid) | |
1002 | continue; | |
1003 | ||
1004 | #ifdef CONFIG_HOTPLUG_CPU | |
1005 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1006 | !pr->flags.has_cst && | |
1007 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1008 | continue; | |
1fec74a9 | 1009 | #endif |
4f86d3a8 LB |
1010 | cpuidle_set_statedata(state, cx); |
1011 | ||
1012 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
4fcb2fcd | 1013 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1014 | state->exit_latency = cx->latency; |
4963f620 | 1015 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1016 | state->power_usage = cx->power; |
1017 | ||
1018 | state->flags = 0; | |
1019 | switch (cx->type) { | |
1020 | case ACPI_STATE_C1: | |
1021 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
8e92b660 VP |
1022 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1023 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1024 | ||
4f86d3a8 | 1025 | state->enter = acpi_idle_enter_c1; |
ddc081a1 | 1026 | dev->safe_state = state; |
4f86d3a8 LB |
1027 | break; |
1028 | ||
1029 | case ACPI_STATE_C2: | |
1030 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1031 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1032 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1033 | dev->safe_state = state; |
4f86d3a8 LB |
1034 | break; |
1035 | ||
1036 | case ACPI_STATE_C3: | |
1037 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1038 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1039 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1040 | state->enter = pr->flags.bm_check ? | |
1041 | acpi_idle_enter_bm : | |
1042 | acpi_idle_enter_simple; | |
1043 | break; | |
1044 | } | |
1045 | ||
1046 | count++; | |
9a0b8415 | 1047 | if (count == CPUIDLE_STATE_MAX) |
1048 | break; | |
4f86d3a8 LB |
1049 | } |
1050 | ||
1051 | dev->state_count = count; | |
1052 | ||
1053 | if (!count) | |
1054 | return -EINVAL; | |
1055 | ||
4f86d3a8 LB |
1056 | return 0; |
1057 | } | |
1058 | ||
1059 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1060 | { | |
dcb84f33 | 1061 | int ret = 0; |
4f86d3a8 | 1062 | |
36a91358 VP |
1063 | if (boot_option_idle_override) |
1064 | return 0; | |
1065 | ||
4f86d3a8 LB |
1066 | if (!pr) |
1067 | return -EINVAL; | |
1068 | ||
1069 | if (nocst) { | |
1070 | return -ENODEV; | |
1071 | } | |
1072 | ||
1073 | if (!pr->flags.power_setup_done) | |
1074 | return -ENODEV; | |
1075 | ||
1076 | cpuidle_pause_and_lock(); | |
1077 | cpuidle_disable_device(&pr->power.dev); | |
1078 | acpi_processor_get_power_info(pr); | |
dcb84f33 VP |
1079 | if (pr->flags.power) { |
1080 | acpi_processor_setup_cpuidle(pr); | |
1081 | ret = cpuidle_enable_device(&pr->power.dev); | |
1082 | } | |
4f86d3a8 LB |
1083 | cpuidle_resume_and_unlock(); |
1084 | ||
1085 | return ret; | |
1086 | } | |
1087 | ||
7af8b660 | 1088 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1089 | struct acpi_device *device) |
1da177e4 | 1090 | { |
4be44fcd | 1091 | acpi_status status = 0; |
b6835052 | 1092 | static int first_run; |
1da177e4 | 1093 | |
36a91358 VP |
1094 | if (boot_option_idle_override) |
1095 | return 0; | |
1da177e4 LT |
1096 | |
1097 | if (!first_run) { | |
c1e3b377 ZY |
1098 | if (idle_halt) { |
1099 | /* | |
1100 | * When the boot option of "idle=halt" is added, halt | |
1101 | * is used for CPU IDLE. | |
1102 | * In such case C2/C3 is meaningless. So the max_cstate | |
1103 | * is set to one. | |
1104 | */ | |
1105 | max_cstate = 1; | |
1106 | } | |
1da177e4 | 1107 | dmi_check_system(processor_power_dmi_table); |
c1c30634 | 1108 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1109 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1110 | printk(KERN_NOTICE |
1111 | "ACPI: processor limited to max C-state %d\n", | |
1112 | max_cstate); | |
1da177e4 LT |
1113 | first_run++; |
1114 | } | |
1115 | ||
02df8b93 | 1116 | if (!pr) |
d550d98d | 1117 | return -EINVAL; |
02df8b93 | 1118 | |
cee324b1 | 1119 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1120 | status = |
cee324b1 | 1121 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1122 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1123 | ACPI_EXCEPTION((AE_INFO, status, |
1124 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1125 | } |
1126 | } | |
1127 | ||
1128 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1129 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1130 | |
1131 | /* | |
1132 | * Install the idle handler if processor power management is supported. | |
1133 | * Note that we use previously set idle handler will be used on | |
1134 | * platforms that only support C1. | |
1135 | */ | |
36a91358 | 1136 | if (pr->flags.power) { |
4f86d3a8 | 1137 | acpi_processor_setup_cpuidle(pr); |
4f86d3a8 LB |
1138 | if (cpuidle_register_device(&pr->power.dev)) |
1139 | return -EIO; | |
1da177e4 | 1140 | } |
d550d98d | 1141 | return 0; |
1da177e4 LT |
1142 | } |
1143 | ||
4be44fcd LB |
1144 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1145 | struct acpi_device *device) | |
1da177e4 | 1146 | { |
36a91358 VP |
1147 | if (boot_option_idle_override) |
1148 | return 0; | |
1149 | ||
dcb84f33 | 1150 | cpuidle_unregister_device(&pr->power.dev); |
1da177e4 LT |
1151 | pr->flags.power_setup_done = 0; |
1152 | ||
d550d98d | 1153 | return 0; |
1da177e4 | 1154 | } |