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dmaengine, async_tx: support alignment checks
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CommitLineData
9bc89cd8
DW
1/*
2 * xor offload engine api
3 *
4 * Copyright © 2006, Intel Corporation.
5 *
6 * Dan Williams <dan.j.williams@intel.com>
7 *
8 * with architecture considerations by:
9 * Neil Brown <neilb@suse.de>
10 * Jeff Garzik <jeff@garzik.org>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
15 *
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc.,
23 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
24 *
25 */
26#include <linux/kernel.h>
27#include <linux/interrupt.h>
28#include <linux/mm.h>
29#include <linux/dma-mapping.h>
30#include <linux/raid/xor.h>
31#include <linux/async_tx.h>
32
06164f31
DW
33/* do_async_xor - dma map the pages and perform the xor with an engine */
34static __async_inline struct dma_async_tx_descriptor *
1e55db2d 35do_async_xor(struct dma_chan *chan, struct page *dest, struct page **src_list,
04ce9ab3 36 unsigned int offset, int src_cnt, size_t len, dma_addr_t *dma_src,
a08abd8c 37 struct async_submit_ctl *submit)
9bc89cd8 38{
1e55db2d 39 struct dma_device *dma = chan->device;
1e55db2d
DW
40 struct dma_async_tx_descriptor *tx = NULL;
41 int src_off = 0;
9bc89cd8 42 int i;
a08abd8c
DW
43 dma_async_tx_callback cb_fn_orig = submit->cb_fn;
44 void *cb_param_orig = submit->cb_param;
45 enum async_tx_flags flags_orig = submit->flags;
1e55db2d
DW
46 enum dma_ctrl_flags dma_flags;
47 int xor_src_cnt;
48 dma_addr_t dma_dest;
9bc89cd8 49
a06d568f
DW
50 /* map the dest bidrectional in case it is re-used as a source */
51 dma_dest = dma_map_page(dma->dev, dest, offset, len, DMA_BIDIRECTIONAL);
52 for (i = 0; i < src_cnt; i++) {
53 /* only map the dest once */
54 if (unlikely(src_list[i] == dest)) {
55 dma_src[i] = dma_dest;
56 continue;
57 }
1e55db2d 58 dma_src[i] = dma_map_page(dma->dev, src_list[i], offset,
0036731c 59 len, DMA_TO_DEVICE);
a06d568f 60 }
0036731c 61
1e55db2d 62 while (src_cnt) {
a08abd8c 63 submit->flags = flags_orig;
1e55db2d 64 dma_flags = 0;
b2f46fd8 65 xor_src_cnt = min(src_cnt, (int)dma->max_xor);
1e55db2d
DW
66 /* if we are submitting additional xors, leave the chain open,
67 * clear the callback parameters, and leave the destination
68 * buffer mapped
69 */
70 if (src_cnt > xor_src_cnt) {
a08abd8c 71 submit->flags &= ~ASYNC_TX_ACK;
0403e382 72 submit->flags |= ASYNC_TX_FENCE;
1e55db2d 73 dma_flags = DMA_COMPL_SKIP_DEST_UNMAP;
a08abd8c
DW
74 submit->cb_fn = NULL;
75 submit->cb_param = NULL;
1e55db2d 76 } else {
a08abd8c
DW
77 submit->cb_fn = cb_fn_orig;
78 submit->cb_param = cb_param_orig;
1e55db2d 79 }
a08abd8c 80 if (submit->cb_fn)
1e55db2d 81 dma_flags |= DMA_PREP_INTERRUPT;
0403e382
DW
82 if (submit->flags & ASYNC_TX_FENCE)
83 dma_flags |= DMA_PREP_FENCE;
1e55db2d
DW
84 /* Since we have clobbered the src_list we are committed
85 * to doing this asynchronously. Drivers force forward progress
86 * in case they can not provide a descriptor
87 */
88 tx = dma->device_prep_dma_xor(chan, dma_dest, &dma_src[src_off],
89 xor_src_cnt, len, dma_flags);
90
669ab0b2 91 if (unlikely(!tx))
a08abd8c 92 async_tx_quiesce(&submit->depend_tx);
0036731c 93
1e55db2d 94 /* spin wait for the preceeding transactions to complete */
669ab0b2
DW
95 while (unlikely(!tx)) {
96 dma_async_issue_pending(chan);
1e55db2d
DW
97 tx = dma->device_prep_dma_xor(chan, dma_dest,
98 &dma_src[src_off],
99 xor_src_cnt, len,
100 dma_flags);
669ab0b2 101 }
9bc89cd8 102
a08abd8c
DW
103 async_tx_submit(chan, tx, submit);
104 submit->depend_tx = tx;
1e55db2d
DW
105
106 if (src_cnt > xor_src_cnt) {
107 /* drop completed sources */
108 src_cnt -= xor_src_cnt;
109 src_off += xor_src_cnt;
110
111 /* use the intermediate result a source */
112 dma_src[--src_off] = dma_dest;
113 src_cnt++;
114 } else
115 break;
116 }
0036731c
DW
117
118 return tx;
9bc89cd8
DW
119}
120
121static void
122do_sync_xor(struct page *dest, struct page **src_list, unsigned int offset,
a08abd8c 123 int src_cnt, size_t len, struct async_submit_ctl *submit)
9bc89cd8 124{
9bc89cd8 125 int i;
1e55db2d
DW
126 int xor_src_cnt;
127 int src_off = 0;
128 void *dest_buf;
04ce9ab3 129 void **srcs;
9bc89cd8 130
04ce9ab3
DW
131 if (submit->scribble)
132 srcs = submit->scribble;
133 else
134 srcs = (void **) src_list;
135
136 /* convert to buffer pointers */
9bc89cd8 137 for (i = 0; i < src_cnt; i++)
1e55db2d 138 srcs[i] = page_address(src_list[i]) + offset;
9bc89cd8
DW
139
140 /* set destination address */
1e55db2d 141 dest_buf = page_address(dest) + offset;
9bc89cd8 142
a08abd8c 143 if (submit->flags & ASYNC_TX_XOR_ZERO_DST)
1e55db2d 144 memset(dest_buf, 0, len);
9bc89cd8 145
1e55db2d
DW
146 while (src_cnt > 0) {
147 /* process up to 'MAX_XOR_BLOCKS' sources */
148 xor_src_cnt = min(src_cnt, MAX_XOR_BLOCKS);
149 xor_blocks(xor_src_cnt, len, dest_buf, &srcs[src_off]);
150
151 /* drop completed sources */
152 src_cnt -= xor_src_cnt;
153 src_off += xor_src_cnt;
154 }
9bc89cd8 155
a08abd8c 156 async_tx_sync_epilog(submit);
9bc89cd8
DW
157}
158
159/**
160 * async_xor - attempt to xor a set of blocks with a dma engine.
9bc89cd8 161 * @dest: destination page
a08abd8c
DW
162 * @src_list: array of source pages
163 * @offset: common src/dst offset to start transaction
9bc89cd8
DW
164 * @src_cnt: number of source pages
165 * @len: length in bytes
a08abd8c
DW
166 * @submit: submission / completion modifiers
167 *
168 * honored flags: ASYNC_TX_ACK, ASYNC_TX_XOR_ZERO_DST, ASYNC_TX_XOR_DROP_DST
169 *
170 * xor_blocks always uses the dest as a source so the
171 * ASYNC_TX_XOR_ZERO_DST flag must be set to not include dest data in
172 * the calculation. The assumption with dma eninges is that they only
173 * use the destination buffer as a source when it is explicity specified
174 * in the source list.
175 *
176 * src_list note: if the dest is also a source it must be at index zero.
177 * The contents of this array will be overwritten if a scribble region
178 * is not specified.
9bc89cd8
DW
179 */
180struct dma_async_tx_descriptor *
181async_xor(struct page *dest, struct page **src_list, unsigned int offset,
a08abd8c 182 int src_cnt, size_t len, struct async_submit_ctl *submit)
9bc89cd8 183{
a08abd8c 184 struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR,
47437b2c
DW
185 &dest, 1, src_list,
186 src_cnt, len);
04ce9ab3
DW
187 dma_addr_t *dma_src = NULL;
188
9bc89cd8
DW
189 BUG_ON(src_cnt <= 1);
190
04ce9ab3
DW
191 if (submit->scribble)
192 dma_src = submit->scribble;
193 else if (sizeof(dma_addr_t) <= sizeof(struct page *))
194 dma_src = (dma_addr_t *) src_list;
195
83544ae9 196 if (dma_src && chan && is_dma_xor_aligned(chan->device, offset, 0, len)) {
1e55db2d
DW
197 /* run the xor asynchronously */
198 pr_debug("%s (async): len: %zu\n", __func__, len);
9bc89cd8 199
1e55db2d 200 return do_async_xor(chan, dest, src_list, offset, src_cnt, len,
04ce9ab3 201 dma_src, submit);
1e55db2d
DW
202 } else {
203 /* run the xor synchronously */
204 pr_debug("%s (sync): len: %zu\n", __func__, len);
04ce9ab3
DW
205 WARN_ONCE(chan, "%s: no space for dma address conversion\n",
206 __func__);
9bc89cd8 207
1e55db2d
DW
208 /* in the sync case the dest is an implied source
209 * (assumes the dest is the first source)
9bc89cd8 210 */
a08abd8c 211 if (submit->flags & ASYNC_TX_XOR_DROP_DST) {
1e55db2d
DW
212 src_cnt--;
213 src_list++;
214 }
9bc89cd8 215
1e55db2d 216 /* wait for any prerequisite operations */
a08abd8c 217 async_tx_quiesce(&submit->depend_tx);
9bc89cd8 218
a08abd8c 219 do_sync_xor(dest, src_list, offset, src_cnt, len, submit);
9bc89cd8 220
1e55db2d 221 return NULL;
9bc89cd8 222 }
9bc89cd8
DW
223}
224EXPORT_SYMBOL_GPL(async_xor);
225
226static int page_is_zero(struct page *p, unsigned int offset, size_t len)
227{
228 char *a = page_address(p) + offset;
229 return ((*(u32 *) a) == 0 &&
230 memcmp(a, a + 4, len - 4) == 0);
231}
232
233/**
099f53cb 234 * async_xor_val - attempt a xor parity check with a dma engine.
9bc89cd8 235 * @dest: destination page used if the xor is performed synchronously
a08abd8c 236 * @src_list: array of source pages
9bc89cd8
DW
237 * @offset: offset in pages to start transaction
238 * @src_cnt: number of source pages
239 * @len: length in bytes
240 * @result: 0 if sum == 0 else non-zero
a08abd8c
DW
241 * @submit: submission / completion modifiers
242 *
243 * honored flags: ASYNC_TX_ACK
244 *
245 * src_list note: if the dest is also a source it must be at index zero.
246 * The contents of this array will be overwritten if a scribble region
247 * is not specified.
9bc89cd8
DW
248 */
249struct dma_async_tx_descriptor *
a08abd8c 250async_xor_val(struct page *dest, struct page **src_list, unsigned int offset,
ad283ea4 251 int src_cnt, size_t len, enum sum_check_flags *result,
a08abd8c 252 struct async_submit_ctl *submit)
9bc89cd8 253{
a08abd8c 254 struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR_VAL,
47437b2c
DW
255 &dest, 1, src_list,
256 src_cnt, len);
9bc89cd8 257 struct dma_device *device = chan ? chan->device : NULL;
0036731c 258 struct dma_async_tx_descriptor *tx = NULL;
04ce9ab3 259 dma_addr_t *dma_src = NULL;
9bc89cd8
DW
260
261 BUG_ON(src_cnt <= 1);
262
04ce9ab3
DW
263 if (submit->scribble)
264 dma_src = submit->scribble;
265 else if (sizeof(dma_addr_t) <= sizeof(struct page *))
266 dma_src = (dma_addr_t *) src_list;
267
83544ae9
DW
268 if (dma_src && device && src_cnt <= device->max_xor &&
269 is_dma_xor_aligned(device, offset, 0, len)) {
0403e382 270 unsigned long dma_prep_flags = 0;
0036731c 271 int i;
9bc89cd8 272
3280ab3e 273 pr_debug("%s: (async) len: %zu\n", __func__, len);
9bc89cd8 274
0403e382
DW
275 if (submit->cb_fn)
276 dma_prep_flags |= DMA_PREP_INTERRUPT;
277 if (submit->flags & ASYNC_TX_FENCE)
278 dma_prep_flags |= DMA_PREP_FENCE;
0036731c
DW
279 for (i = 0; i < src_cnt; i++)
280 dma_src[i] = dma_map_page(device->dev, src_list[i],
281 offset, len, DMA_TO_DEVICE);
282
099f53cb
DW
283 tx = device->device_prep_dma_xor_val(chan, dma_src, src_cnt,
284 len, result,
285 dma_prep_flags);
669ab0b2 286 if (unlikely(!tx)) {
a08abd8c 287 async_tx_quiesce(&submit->depend_tx);
0036731c 288
e34a8ae7 289 while (!tx) {
669ab0b2 290 dma_async_issue_pending(chan);
099f53cb 291 tx = device->device_prep_dma_xor_val(chan,
0036731c 292 dma_src, src_cnt, len, result,
d4c56f97 293 dma_prep_flags);
e34a8ae7 294 }
9bc89cd8
DW
295 }
296
a08abd8c 297 async_tx_submit(chan, tx, submit);
9bc89cd8 298 } else {
a08abd8c 299 enum async_tx_flags flags_orig = submit->flags;
9bc89cd8 300
3280ab3e 301 pr_debug("%s: (sync) len: %zu\n", __func__, len);
04ce9ab3
DW
302 WARN_ONCE(device && src_cnt <= device->max_xor,
303 "%s: no space for dma address conversion\n",
304 __func__);
9bc89cd8 305
a08abd8c
DW
306 submit->flags |= ASYNC_TX_XOR_DROP_DST;
307 submit->flags &= ~ASYNC_TX_ACK;
9bc89cd8 308
a08abd8c 309 tx = async_xor(dest, src_list, offset, src_cnt, len, submit);
9bc89cd8 310
d2c52b79 311 async_tx_quiesce(&tx);
9bc89cd8 312
ad283ea4 313 *result = !page_is_zero(dest, offset, len) << SUM_CHECK_P;
9bc89cd8 314
a08abd8c
DW
315 async_tx_sync_epilog(submit);
316 submit->flags = flags_orig;
9bc89cd8
DW
317 }
318
319 return tx;
320}
099f53cb 321EXPORT_SYMBOL_GPL(async_xor_val);
9bc89cd8 322
9bc89cd8
DW
323MODULE_AUTHOR("Intel Corporation");
324MODULE_DESCRIPTION("asynchronous xor/xor-zero-sum api");
325MODULE_LICENSE("GPL");