[net-next-2.6.git] / arch / x86_64 / kernel / apic.c

/*
 *	Local APIC handling, local APIC timers
 *
 *	(c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
 *
 *	Fixes
 *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
 *					thanks to Eric Gilmore
 *					and Rolf G. Tews
 *					for testing these extensively.
 *	Maciej W. Rozycki	:	Various updates and fixes.
 *	Mikael Pettersson	:	Power Management for UP-APIC.
 *	Pavel Machek and
 *	Mikael Pettersson	:	PM converted to driver model.
 */

#include <linux/init.h>

#include <linux/mm.h>
#include <linux/delay.h>
#include <linux/bootmem.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/kernel_stat.h>
#include <linux/sysdev.h>
#include <linux/module.h>
#include <linux/ioport.h>

#include <asm/atomic.h>
#include <asm/smp.h>
#include <asm/mtrr.h>
#include <asm/mpspec.h>
#include <asm/pgalloc.h>
#include <asm/mach_apic.h>
#include <asm/nmi.h>
#include <asm/idle.h>
#include <asm/proto.h>
#include <asm/timex.h>
#include <asm/hpet.h>
#include <asm/apic.h>

int apic_mapped;
int apic_verbosity;
int apic_runs_main_timer;
int apic_calibrate_pmtmr __initdata;

int disable_apic_timer __initdata;

/* Local APIC timer works in C2? */
int local_apic_timer_c2_ok;
EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);

static struct resource *ioapic_resources;
static struct resource lapic_resource = {
	.name = "Local APIC",
	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
};

/*
 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
 * IPIs in place of local APIC timers
 */
static cpumask_t timer_interrupt_broadcast_ipi_mask;

/* Using APIC to generate smp_local_timer_interrupt? */
int using_apic_timer __read_mostly = 0;

static void apic_pm_activate(void);

void apic_wait_icr_idle(void)
{
	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
		cpu_relax();
}

unsigned int safe_apic_wait_icr_idle(void)
{
	unsigned int send_status;
	int timeout;

	timeout = 0;
	do {
		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
		if (!send_status)
			break;
		udelay(100);
	} while (timeout++ < 1000);

	return send_status;
}

void enable_NMI_through_LVT0 (void * dummy)
{
	unsigned int v;

	/* unmask and set to NMI */
	v = APIC_DM_NMI;
	apic_write(APIC_LVT0, v);
}

int get_maxlvt(void)
{
	unsigned int v, maxlvt;

	v = apic_read(APIC_LVR);
	maxlvt = GET_APIC_MAXLVT(v);
	return maxlvt;
}

/*
 * 'what should we do if we get a hw irq event on an illegal vector'.
 * each architecture has to answer this themselves.
 */
void ack_bad_irq(unsigned int irq)
{
	printk("unexpected IRQ trap at vector %02x\n", irq);
	/*
	 * Currently unexpected vectors happen only on SMP and APIC.
	 * We _must_ ack these because every local APIC has only N
	 * irq slots per priority level, and a 'hanging, unacked' IRQ
	 * holds up an irq slot - in excessive cases (when multiple
	 * unexpected vectors occur) that might lock up the APIC
	 * completely.
	 * But don't ack when the APIC is disabled. -AK
	 */
	if (!disable_apic)
		ack_APIC_irq();
}

void clear_local_APIC(void)
{
	int maxlvt;
	unsigned int v;

	maxlvt = get_maxlvt();

	/*
	 * Masking an LVT entry can trigger a local APIC error
	 * if the vector is zero. Mask LVTERR first to prevent this.
	 */
	if (maxlvt >= 3) {
		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
	}
	/*
	 * Careful: we have to set masks only first to deassert
	 * any level-triggered sources.
	 */
	v = apic_read(APIC_LVTT);
	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT0);
	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
	v = apic_read(APIC_LVT1);
	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
	if (maxlvt >= 4) {
		v = apic_read(APIC_LVTPC);
		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
	}

	/*
	 * Clean APIC state for other OSs:
	 */
	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	apic_write(APIC_LVT1, APIC_LVT_MASKED);
	if (maxlvt >= 3)
		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
	if (maxlvt >= 4)
		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
	apic_write(APIC_ESR, 0);
	apic_read(APIC_ESR);
}

void disconnect_bsp_APIC(int virt_wire_setup)
{
	/* Go back to Virtual Wire compatibility mode */
	unsigned long value;

	/* For the spurious interrupt use vector F, and enable it */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= 0xf;
	apic_write(APIC_SPIV, value);

	if (!virt_wire_setup) {
		/* For LVT0 make it edge triggered, active high, external and enabled */
		value = apic_read(APIC_LVT0);
		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
		apic_write(APIC_LVT0, value);
	} else {
		/* Disable LVT0 */
		apic_write(APIC_LVT0, APIC_LVT_MASKED);
	}

	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	value = apic_read(APIC_LVT1);
	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	apic_write(APIC_LVT1, value);
}

void disable_local_APIC(void)
{
	unsigned int value;

	clear_local_APIC();

	/*
	 * Disable APIC (implies clearing of registers
	 * for 82489DX!).
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_SPIV_APIC_ENABLED;
	apic_write(APIC_SPIV, value);
}

/*
 * This is to verify that we're looking at a real local APIC.
 * Check these against your board if the CPUs aren't getting
 * started for no apparent reason.
 */
int __init verify_local_APIC(void)
{
	unsigned int reg0, reg1;

	/*
	 * The version register is read-only in a real APIC.
	 */
	reg0 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	reg1 = apic_read(APIC_LVR);
	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);

	/*
	 * The two version reads above should print the same
	 * numbers.  If the second one is different, then we
	 * poke at a non-APIC.
	 */
	if (reg1 != reg0)
		return 0;

	/*
	 * Check if the version looks reasonably.
	 */
	reg1 = GET_APIC_VERSION(reg0);
	if (reg1 == 0x00 || reg1 == 0xff)
		return 0;
	reg1 = get_maxlvt();
	if (reg1 < 0x02 || reg1 == 0xff)
		return 0;

	/*
	 * The ID register is read/write in a real APIC.
	 */
	reg0 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	reg1 = apic_read(APIC_ID);
	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	apic_write(APIC_ID, reg0);
	if (reg1 != (reg0 ^ APIC_ID_MASK))
		return 0;

	/*
	 * The next two are just to see if we have sane values.
	 * They're only really relevant if we're in Virtual Wire
	 * compatibility mode, but most boxes are anymore.
	 */
	reg0 = apic_read(APIC_LVT0);
	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	reg1 = apic_read(APIC_LVT1);
	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);

	return 1;
}

void __init sync_Arb_IDs(void)
{
	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
	if (ver >= 0x14)	/* P4 or higher */
		return;

	/*
	 * Wait for idle.
	 */
	apic_wait_icr_idle();

	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
	apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
				| APIC_DM_INIT);
}

/*
 * An initial setup of the virtual wire mode.
 */
void __init init_bsp_APIC(void)
{
	unsigned int value;

	/*
	 * Don't do the setup now if we have a SMP BIOS as the
	 * through-I/O-APIC virtual wire mode might be active.
	 */
	if (smp_found_config || !cpu_has_apic)
		return;

	value = apic_read(APIC_LVR);

	/*
	 * Do not trust the local APIC being empty at bootup.
	 */
	clear_local_APIC();

	/*
	 * Enable APIC.
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	value |= APIC_SPIV_APIC_ENABLED;
	value |= APIC_SPIV_FOCUS_DISABLED;
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up the virtual wire mode.
	 */
	apic_write(APIC_LVT0, APIC_DM_EXTINT);
	value = APIC_DM_NMI;
	apic_write(APIC_LVT1, value);
}

void __cpuinit setup_local_APIC (void)
{
	unsigned int value, maxlvt;
	int i, j;

	value = apic_read(APIC_LVR);

	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);

	/*
	 * Double-check whether this APIC is really registered.
	 * This is meaningless in clustered apic mode, so we skip it.
	 */
	if (!apic_id_registered())
		BUG();

	/*
	 * Intel recommends to set DFR, LDR and TPR before enabling
	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
	 * document number 292116).  So here it goes...
	 */
	init_apic_ldr();

	/*
	 * Set Task Priority to 'accept all'. We never change this
	 * later on.
	 */
	value = apic_read(APIC_TASKPRI);
	value &= ~APIC_TPRI_MASK;
	apic_write(APIC_TASKPRI, value);

	/*
	 * After a crash, we no longer service the interrupts and a pending
	 * interrupt from previous kernel might still have ISR bit set.
	 *
	 * Most probably by now CPU has serviced that pending interrupt and
	 * it might not have done the ack_APIC_irq() because it thought,
	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	 * does not clear the ISR bit and cpu thinks it has already serivced
	 * the interrupt. Hence a vector might get locked. It was noticed
	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	 */
	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
		value = apic_read(APIC_ISR + i*0x10);
		for (j = 31; j >= 0; j--) {
			if (value & (1<<j))
				ack_APIC_irq();
		}
	}

	/*
	 * Now that we are all set up, enable the APIC
	 */
	value = apic_read(APIC_SPIV);
	value &= ~APIC_VECTOR_MASK;
	/*
	 * Enable APIC
	 */
	value |= APIC_SPIV_APIC_ENABLED;

	/* We always use processor focus */

	/*
	 * Set spurious IRQ vector
	 */
	value |= SPURIOUS_APIC_VECTOR;
	apic_write(APIC_SPIV, value);

	/*
	 * Set up LVT0, LVT1:
	 *
	 * set up through-local-APIC on the BP's LINT0. This is not
	 * strictly necessary in pure symmetric-IO mode, but sometimes
	 * we delegate interrupts to the 8259A.
	 */
	/*
	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
	 */
	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
	if (!smp_processor_id() && !value) {
		value = APIC_DM_EXTINT;
		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	} else {
		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	}
	apic_write(APIC_LVT0, value);

	/*
	 * only the BP should see the LINT1 NMI signal, obviously.
	 */
	if (!smp_processor_id())
		value = APIC_DM_NMI;
	else
		value = APIC_DM_NMI | APIC_LVT_MASKED;
	apic_write(APIC_LVT1, value);

	{
		unsigned oldvalue;
		maxlvt = get_maxlvt();
		oldvalue = apic_read(APIC_ESR);
		value = ERROR_APIC_VECTOR;      // enables sending errors
		apic_write(APIC_LVTERR, value);
		/*
		 * spec says clear errors after enabling vector.
		 */
		if (maxlvt > 3)
			apic_write(APIC_ESR, 0);
		value = apic_read(APIC_ESR);
		if (value != oldvalue)
			apic_printk(APIC_VERBOSE,
			"ESR value after enabling vector: %08x, after %08x\n",
			oldvalue, value);
	}

	nmi_watchdog_default();
	setup_apic_nmi_watchdog(NULL);
	apic_pm_activate();
}

#ifdef CONFIG_PM

static struct {
	/* 'active' is true if the local APIC was enabled by us and
	   not the BIOS; this signifies that we are also responsible
	   for disabling it before entering apm/acpi suspend */
	int active;
	/* r/w apic fields */
	unsigned int apic_id;
	unsigned int apic_taskpri;
	unsigned int apic_ldr;
	unsigned int apic_dfr;
	unsigned int apic_spiv;
	unsigned int apic_lvtt;
	unsigned int apic_lvtpc;
	unsigned int apic_lvt0;
	unsigned int apic_lvt1;
	unsigned int apic_lvterr;
	unsigned int apic_tmict;
	unsigned int apic_tdcr;
	unsigned int apic_thmr;
} apic_pm_state;

static int lapic_suspend(struct sys_device *dev, pm_message_t state)
{
	unsigned long flags;
	int maxlvt;

	if (!apic_pm_state.active)
		return 0;

	maxlvt = get_maxlvt();

	apic_pm_state.apic_id = apic_read(APIC_ID);
	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
	if (maxlvt >= 4)
		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
#ifdef CONFIG_X86_MCE_INTEL
	if (maxlvt >= 5)
		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Local APIC handling, local APIC timers
	3	*
	4	* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
	5	*
	6	* Fixes
	7	* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
	8	* thanks to Eric Gilmore
	9	* and Rolf G. Tews
	10	* for testing these extensively.
	11	* Maciej W. Rozycki : Various updates and fixes.
	12	* Mikael Pettersson : Power Management for UP-APIC.
	13	* Pavel Machek and
	14	* Mikael Pettersson : PM converted to driver model.
	15	*/
	16
1da177e4 LT	17	#include <linux/init.h>
	18
	19	#include <linux/mm.h>
1da177e4 LT	20	#include <linux/delay.h>
1da177e4 LT	21	#include <linux/bootmem.h>
1da177e4 LT	22	#include <linux/interrupt.h>
	23	#include <linux/mc146818rtc.h>
	24	#include <linux/kernel_stat.h>
	25	#include <linux/sysdev.h>
d25bf7e5	26	#include <linux/module.h>
39928722	27	#include <linux/ioport.h>
1da177e4 LT	28
	29	#include <asm/atomic.h>
	30	#include <asm/smp.h>
	31	#include <asm/mtrr.h>
	32	#include <asm/mpspec.h>
	33	#include <asm/pgalloc.h>
	34	#include <asm/mach_apic.h>
75152114	35	#include <asm/nmi.h>
95833c83	36	#include <asm/idle.h>
73dea47f AK	37	#include <asm/proto.h>
73dea47f AK	38	#include <asm/timex.h>
2d0c87c3	39	#include <asm/hpet.h>
2c8c0e6b	40	#include <asm/apic.h>
1da177e4	41
b7f5e3c7	42	int apic_mapped;
1da177e4	43	int apic_verbosity;
73dea47f	44	int apic_runs_main_timer;
0c3749c4	45	int apic_calibrate_pmtmr __initdata;
1da177e4 LT	46
	47	int disable_apic_timer __initdata;
	48
2e7c2838 LT	49	/* Local APIC timer works in C2? */
	50	int local_apic_timer_c2_ok;
	51	EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
	52
39928722 AD	53	static struct resource *ioapic_resources;
	54	static struct resource lapic_resource = {
	55	.name = "Local APIC",
	56	.flags = IORESOURCE_MEM \| IORESOURCE_BUSY,
	57	};
	58
d25bf7e5 VP	59	/*
	60	* cpu_mask that denotes the CPUs that needs timer interrupt coming in as
	61	* IPIs in place of local APIC timers
	62	*/
	63	static cpumask_t timer_interrupt_broadcast_ipi_mask;
	64
1da177e4	65	/* Using APIC to generate smp_local_timer_interrupt? */
acae9d32	66	int using_apic_timer __read_mostly = 0;
1da177e4	67
1da177e4 LT	68	static void apic_pm_activate(void);
1da177e4 LT	69
8339e9fb FLV	70	void apic_wait_icr_idle(void)
	71	{
	72	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
	73	cpu_relax();
	74	}
	75
	76	unsigned int safe_apic_wait_icr_idle(void)
	77	{
	78	unsigned int send_status;
	79	int timeout;
	80
	81	timeout = 0;
	82	do {
	83	send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
	84	if (!send_status)
	85	break;
	86	udelay(100);
	87	} while (timeout++ < 1000);
	88
	89	return send_status;
	90	}
	91
1da177e4 LT	92	void enable_NMI_through_LVT0 (void * dummy)
1da177e4 LT	93	{
11a8e778	94	unsigned int v;
6935d1f9 TG	95
	96	/* unmask and set to NMI */
	97	v = APIC_DM_NMI;
11a8e778	98	apic_write(APIC_LVT0, v);
1da177e4 LT	99	}
	100
	101	int get_maxlvt(void)
	102	{
11a8e778	103	unsigned int v, maxlvt;
1da177e4 LT	104
1da177e4 LT	105	v = apic_read(APIC_LVR);
1da177e4 LT	106	maxlvt = GET_APIC_MAXLVT(v);
	107	return maxlvt;
	108	}
	109
3777a959 AK	110	/*
	111	* 'what should we do if we get a hw irq event on an illegal vector'.
	112	* each architecture has to answer this themselves.
	113	*/
	114	void ack_bad_irq(unsigned int irq)
	115	{
	116	printk("unexpected IRQ trap at vector %02x\n", irq);
	117	/*
	118	* Currently unexpected vectors happen only on SMP and APIC.
	119	* We _must_ ack these because every local APIC has only N
	120	* irq slots per priority level, and a 'hanging, unacked' IRQ
	121	* holds up an irq slot - in excessive cases (when multiple
	122	* unexpected vectors occur) that might lock up the APIC
	123	* completely.
6935d1f9	124	* But don't ack when the APIC is disabled. -AK
3777a959 AK	125	*/
	126	if (!disable_apic)
	127	ack_APIC_irq();
	128	}
	129
1da177e4 LT	130	void clear_local_APIC(void)
	131	{
	132	int maxlvt;
	133	unsigned int v;
	134
	135	maxlvt = get_maxlvt();
	136
	137	/*
704fc59e	138	* Masking an LVT entry can trigger a local APIC error
1da177e4 LT	139	* if the vector is zero. Mask LVTERR first to prevent this.
	140	*/
	141	if (maxlvt >= 3) {
	142	v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
11a8e778	143	apic_write(APIC_LVTERR, v \| APIC_LVT_MASKED);
1da177e4 LT	144	}
	145	/*
	146	* Careful: we have to set masks only first to deassert
	147	* any level-triggered sources.
	148	*/
	149	v = apic_read(APIC_LVTT);
11a8e778	150	apic_write(APIC_LVTT, v \| APIC_LVT_MASKED);
1da177e4	151	v = apic_read(APIC_LVT0);
11a8e778	152	apic_write(APIC_LVT0, v \| APIC_LVT_MASKED);
1da177e4	153	v = apic_read(APIC_LVT1);
11a8e778	154	apic_write(APIC_LVT1, v \| APIC_LVT_MASKED);
1da177e4 LT	155	if (maxlvt >= 4) {
1da177e4 LT	156	v = apic_read(APIC_LVTPC);
11a8e778	157	apic_write(APIC_LVTPC, v \| APIC_LVT_MASKED);
1da177e4 LT	158	}
	159
	160	/*
	161	* Clean APIC state for other OSs:
	162	*/
11a8e778 AK	163	apic_write(APIC_LVTT, APIC_LVT_MASKED);
	164	apic_write(APIC_LVT0, APIC_LVT_MASKED);
	165	apic_write(APIC_LVT1, APIC_LVT_MASKED);
1da177e4	166	if (maxlvt >= 3)
11a8e778	167	apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1da177e4	168	if (maxlvt >= 4)
11a8e778	169	apic_write(APIC_LVTPC, APIC_LVT_MASKED);
5a40b7c2 AK	170	apic_write(APIC_ESR, 0);
5a40b7c2 AK	171	apic_read(APIC_ESR);
1da177e4 LT	172	}
1da177e4 LT	173
208fb931	174	void disconnect_bsp_APIC(int virt_wire_setup)
1da177e4	175	{
a8fcf1a2 AK	176	/* Go back to Virtual Wire compatibility mode */
a8fcf1a2 AK	177	unsigned long value;
208fb931	178
a8fcf1a2 AK	179	/* For the spurious interrupt use vector F, and enable it */
	180	value = apic_read(APIC_SPIV);
	181	value &= ~APIC_VECTOR_MASK;
	182	value \|= APIC_SPIV_APIC_ENABLED;
	183	value \|= 0xf;
	184	apic_write(APIC_SPIV, value);
	185
	186	if (!virt_wire_setup) {
	187	/* For LVT0 make it edge triggered, active high, external and enabled */
	188	value = apic_read(APIC_LVT0);
	189	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
208fb931	190	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
a8fcf1a2	191	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED );
208fb931	192	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
a8fcf1a2 AK	193	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
	194	apic_write(APIC_LVT0, value);
	195	} else {
	196	/* Disable LVT0 */
	197	apic_write(APIC_LVT0, APIC_LVT_MASKED);
208fb931	198	}
a8fcf1a2 AK	199
	200	/* For LVT1 make it edge triggered, active high, nmi and enabled */
	201	value = apic_read(APIC_LVT1);
	202	value &= ~(APIC_MODE_MASK \| APIC_SEND_PENDING \|
	203	APIC_INPUT_POLARITY \| APIC_LVT_REMOTE_IRR \|
	204	APIC_LVT_LEVEL_TRIGGER \| APIC_LVT_MASKED);
	205	value \|= APIC_LVT_REMOTE_IRR \| APIC_SEND_PENDING;
	206	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
	207	apic_write(APIC_LVT1, value);
1da177e4 LT	208	}
	209
	210	void disable_local_APIC(void)
	211	{
	212	unsigned int value;
	213
	214	clear_local_APIC();
	215
	216	/*
	217	* Disable APIC (implies clearing of registers
	218	* for 82489DX!).
	219	*/
	220	value = apic_read(APIC_SPIV);
	221	value &= ~APIC_SPIV_APIC_ENABLED;
11a8e778	222	apic_write(APIC_SPIV, value);
1da177e4 LT	223	}
	224
	225	/*
	226	* This is to verify that we're looking at a real local APIC.
	227	* Check these against your board if the CPUs aren't getting
	228	* started for no apparent reason.
	229	*/
	230	int __init verify_local_APIC(void)
	231	{
	232	unsigned int reg0, reg1;
	233
	234	/*
	235	* The version register is read-only in a real APIC.
	236	*/
	237	reg0 = apic_read(APIC_LVR);
	238	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
	239	apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
	240	reg1 = apic_read(APIC_LVR);
	241	apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
	242
	243	/*
	244	* The two version reads above should print the same
	245	* numbers. If the second one is different, then we
	246	* poke at a non-APIC.
	247	*/
	248	if (reg1 != reg0)
	249	return 0;
	250
	251	/*
	252	* Check if the version looks reasonably.
	253	*/
	254	reg1 = GET_APIC_VERSION(reg0);
	255	if (reg1 == 0x00 \|\| reg1 == 0xff)
	256	return 0;
	257	reg1 = get_maxlvt();
	258	if (reg1 < 0x02 \|\| reg1 == 0xff)
	259	return 0;
	260
	261	/*
	262	* The ID register is read/write in a real APIC.
	263	*/
	264	reg0 = apic_read(APIC_ID);
	265	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
	266	apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
	267	reg1 = apic_read(APIC_ID);
	268	apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
	269	apic_write(APIC_ID, reg0);
	270	if (reg1 != (reg0 ^ APIC_ID_MASK))
	271	return 0;
	272
	273	/*
	274	* The next two are just to see if we have sane values.
	275	* They're only really relevant if we're in Virtual Wire
	276	* compatibility mode, but most boxes are anymore.
	277	*/
	278	reg0 = apic_read(APIC_LVT0);
	279	apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
	280	reg1 = apic_read(APIC_LVT1);
	281	apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
	282
	283	return 1;
	284	}
	285
	286	void __init sync_Arb_IDs(void)
287	{
288	/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
289	unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
290	if (ver >= 0x14) /* P4 or higher */
291	return;
292
293	/*
294	* Wait for idle.
295	*/
296	apic_wait_icr_idle();
297
298	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
11a8e778	299	apic_write(APIC_ICR, APIC_DEST_ALLINC \| APIC_INT_LEVELTRIG
1da177e4 LT	300	\| APIC_DM_INIT);
	301	}
	302
1da177e4 LT	303	/*
	304	* An initial setup of the virtual wire mode.
	305	*/
	306	void __init init_bsp_APIC(void)
	307	{
11a8e778	308	unsigned int value;
1da177e4 LT	309
	310	/*
	311	* Don't do the setup now if we have a SMP BIOS as the
	312	* through-I/O-APIC virtual wire mode might be active.
	313	*/
	314	if (smp_found_config \|\| !cpu_has_apic)
	315	return;
	316
	317	value = apic_read(APIC_LVR);
1da177e4 LT	318
	319	/*
	320	* Do not trust the local APIC being empty at bootup.
	321	*/
	322	clear_local_APIC();
	323
	324	/*
	325	* Enable APIC.
	326	*/
	327	value = apic_read(APIC_SPIV);
	328	value &= ~APIC_VECTOR_MASK;
	329	value \|= APIC_SPIV_APIC_ENABLED;
	330	value \|= APIC_SPIV_FOCUS_DISABLED;
	331	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	332	apic_write(APIC_SPIV, value);
1da177e4 LT	333
	334	/*
	335	* Set up the virtual wire mode.
	336	*/
11a8e778	337	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1da177e4	338	value = APIC_DM_NMI;
11a8e778	339	apic_write(APIC_LVT1, value);
1da177e4 LT	340	}
1da177e4 LT	341
e6982c67	342	void __cpuinit setup_local_APIC (void)
1da177e4	343	{
11a8e778	344	unsigned int value, maxlvt;
da7ed9f9	345	int i, j;
1da177e4	346
1da177e4	347	value = apic_read(APIC_LVR);
1da177e4	348
fe7414a2	349	BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
1da177e4 LT	350
	351	/*
	352	* Double-check whether this APIC is really registered.
	353	* This is meaningless in clustered apic mode, so we skip it.
	354	*/
	355	if (!apic_id_registered())
	356	BUG();
	357
	358	/*
	359	* Intel recommends to set DFR, LDR and TPR before enabling
	360	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	361	* document number 292116). So here it goes...
	362	*/
	363	init_apic_ldr();
	364
	365	/*
	366	* Set Task Priority to 'accept all'. We never change this
	367	* later on.
	368	*/
	369	value = apic_read(APIC_TASKPRI);
	370	value &= ~APIC_TPRI_MASK;
11a8e778	371	apic_write(APIC_TASKPRI, value);
1da177e4	372
da7ed9f9 VG	373	/*
	374	* After a crash, we no longer service the interrupts and a pending
	375	* interrupt from previous kernel might still have ISR bit set.
	376	*
	377	* Most probably by now CPU has serviced that pending interrupt and
	378	* it might not have done the ack_APIC_irq() because it thought,
	379	* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
	380	* does not clear the ISR bit and cpu thinks it has already serivced
	381	* the interrupt. Hence a vector might get locked. It was noticed
	382	* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
	383	*/
	384	for (i = APIC_ISR_NR - 1; i >= 0; i--) {
	385	value = apic_read(APIC_ISR + i*0x10);
	386	for (j = 31; j >= 0; j--) {
	387	if (value & (1<<j))
	388	ack_APIC_irq();
	389	}
	390	}
	391
1da177e4 LT	392	/*
	393	* Now that we are all set up, enable the APIC
	394	*/
	395	value = apic_read(APIC_SPIV);
	396	value &= ~APIC_VECTOR_MASK;
	397	/*
	398	* Enable APIC
	399	*/
	400	value \|= APIC_SPIV_APIC_ENABLED;
	401
3f14c746 AK	402	/* We always use processor focus */
3f14c746 AK	403
1da177e4 LT	404	/*
	405	* Set spurious IRQ vector
	406	*/
	407	value \|= SPURIOUS_APIC_VECTOR;
11a8e778	408	apic_write(APIC_SPIV, value);
1da177e4 LT	409
	410	/*
	411	* Set up LVT0, LVT1:
	412	*
	413	* set up through-local-APIC on the BP's LINT0. This is not
	414	* strictly necessary in pure symmetric-IO mode, but sometimes
	415	* we delegate interrupts to the 8259A.
	416	*/
	417	/*
	418	* TODO: set up through-local-APIC from through-I/O-APIC? --macro
	419	*/
	420	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
a8fcf1a2	421	if (!smp_processor_id() && !value) {
1da177e4 LT	422	value = APIC_DM_EXTINT;
	423	apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
	424	} else {
	425	value = APIC_DM_EXTINT \| APIC_LVT_MASKED;
	426	apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
	427	}
11a8e778	428	apic_write(APIC_LVT0, value);
1da177e4 LT	429
	430	/*
	431	* only the BP should see the LINT1 NMI signal, obviously.
	432	*/
	433	if (!smp_processor_id())
	434	value = APIC_DM_NMI;
	435	else
	436	value = APIC_DM_NMI \| APIC_LVT_MASKED;
11a8e778	437	apic_write(APIC_LVT1, value);
1da177e4	438
61c11341	439	{
1da177e4 LT	440	unsigned oldvalue;
1da177e4 LT	441	maxlvt = get_maxlvt();
1da177e4 LT	442	oldvalue = apic_read(APIC_ESR);
1da177e4 LT	443	value = ERROR_APIC_VECTOR; // enables sending errors
11a8e778	444	apic_write(APIC_LVTERR, value);
1da177e4 LT	445	/*
	446	* spec says clear errors after enabling vector.
	447	*/
	448	if (maxlvt > 3)
	449	apic_write(APIC_ESR, 0);
	450	value = apic_read(APIC_ESR);
	451	if (value != oldvalue)
	452	apic_printk(APIC_VERBOSE,
	453	"ESR value after enabling vector: %08x, after %08x\n",
	454	oldvalue, value);
1da177e4 LT	455	}
	456
	457	nmi_watchdog_default();
f2802e7f	458	setup_apic_nmi_watchdog(NULL);
1da177e4 LT	459	apic_pm_activate();
	460	}
	461
	462	#ifdef CONFIG_PM
	463
	464	static struct {
	465	/* 'active' is true if the local APIC was enabled by us and
	466	not the BIOS; this signifies that we are also responsible
	467	for disabling it before entering apm/acpi suspend */
	468	int active;
	469	/* r/w apic fields */
	470	unsigned int apic_id;
	471	unsigned int apic_taskpri;
	472	unsigned int apic_ldr;
	473	unsigned int apic_dfr;
	474	unsigned int apic_spiv;
	475	unsigned int apic_lvtt;
	476	unsigned int apic_lvtpc;
	477	unsigned int apic_lvt0;
	478	unsigned int apic_lvt1;
	479	unsigned int apic_lvterr;
	480	unsigned int apic_tmict;
	481	unsigned int apic_tdcr;
	482	unsigned int apic_thmr;
	483	} apic_pm_state;
	484
0b9c33a7	485	static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1da177e4 LT	486	{
1da177e4 LT	487	unsigned long flags;
f990fff4	488	int maxlvt;
1da177e4 LT	489
	490	if (!apic_pm_state.active)
	491	return 0;
	492
f990fff4 KW	493	maxlvt = get_maxlvt();
f990fff4 KW	494
1da177e4 LT	495	apic_pm_state.apic_id = apic_read(APIC_ID);
	496	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
	497	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
	498	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
	499	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
	500	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
f990fff4 KW	501	if (maxlvt >= 4)
f990fff4 KW	502	apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1da177e4 LT	503	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
	504	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
	505	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
	506	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
	507	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
f990fff4 KW	508	#ifdef CONFIG_X86_MCE_INTEL
	509	if (maxlvt >= 5)
	510	apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
	511	#endif