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Commit | Line | Data |
---|---|---|
b7867394 OG |
1 | /* |
2 | * mmconfig-shared.c - Low-level direct PCI config space access via | |
3 | * MMCONFIG - common code between i386 and x86-64. | |
4 | * | |
5 | * This code does: | |
9358c693 | 6 | * - known chipset handling |
b7867394 OG |
7 | * - ACPI decoding and validation |
8 | * | |
9 | * Per-architecture code takes care of the mappings and accesses | |
10 | * themselves. | |
11 | */ | |
12 | ||
13 | #include <linux/pci.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/acpi.h> | |
5f0db7a2 | 16 | #include <linux/sfi_acpi.h> |
b7867394 | 17 | #include <linux/bitmap.h> |
9a08f7d3 | 18 | #include <linux/dmi.h> |
068258bc | 19 | #include <linux/sort.h> |
b7867394 | 20 | #include <asm/e820.h> |
82487711 | 21 | #include <asm/pci_x86.h> |
5f0db7a2 | 22 | #include <asm/acpi.h> |
b7867394 | 23 | |
f4a2d584 | 24 | #define PREFIX "PCI: " |
a192a958 | 25 | |
a5ba7971 AD |
26 | /* Indicate if the mmcfg resources have been placed into the resource table. */ |
27 | static int __initdata pci_mmcfg_resources_inserted; | |
28 | ||
7da7d360 BH |
29 | static __init void free_all_mmcfg(void) |
30 | { | |
31 | pci_mmcfg_arch_free(); | |
32 | pci_mmcfg_config_num = 0; | |
33 | kfree(pci_mmcfg_config); | |
34 | pci_mmcfg_config = NULL; | |
35 | } | |
36 | ||
d215a9c8 BH |
37 | static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, |
38 | int end, u64 addr) | |
068258bc | 39 | { |
d215a9c8 | 40 | struct pci_mmcfg_region *new; |
7da7d360 BH |
41 | int new_num = pci_mmcfg_config_num + 1; |
42 | int i = pci_mmcfg_config_num; | |
068258bc | 43 | |
f7ca6984 BH |
44 | if (addr == 0) |
45 | return NULL; | |
46 | ||
068258bc YL |
47 | new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL); |
48 | if (!new) | |
7da7d360 | 49 | return NULL; |
068258bc YL |
50 | |
51 | if (pci_mmcfg_config) { | |
52 | memcpy(new, pci_mmcfg_config, | |
53 | sizeof(pci_mmcfg_config[0]) * new_num); | |
54 | kfree(pci_mmcfg_config); | |
55 | } | |
56 | pci_mmcfg_config = new; | |
57 | ||
068258bc YL |
58 | pci_mmcfg_config_num++; |
59 | pci_mmcfg_config[i].address = addr; | |
60 | pci_mmcfg_config[i].pci_segment = segment; | |
61 | pci_mmcfg_config[i].start_bus_number = start; | |
62 | pci_mmcfg_config[i].end_bus_number = end; | |
7da7d360 BH |
63 | |
64 | return &pci_mmcfg_config[i]; | |
068258bc YL |
65 | } |
66 | ||
429d512e | 67 | static const char __init *pci_mmcfg_e7520(void) |
9358c693 OG |
68 | { |
69 | u32 win; | |
bb63b421 | 70 | raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win); |
9358c693 | 71 | |
b5229dbb | 72 | win = win & 0xf000; |
068258bc YL |
73 | if (win == 0x0000 || win == 0xf000) |
74 | return NULL; | |
75 | ||
7da7d360 | 76 | if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL) |
068258bc YL |
77 | return NULL; |
78 | ||
9358c693 OG |
79 | return "Intel Corporation E7520 Memory Controller Hub"; |
80 | } | |
81 | ||
429d512e | 82 | static const char __init *pci_mmcfg_intel_945(void) |
9358c693 OG |
83 | { |
84 | u32 pciexbar, mask = 0, len = 0; | |
85 | ||
bb63b421 | 86 | raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar); |
9358c693 OG |
87 | |
88 | /* Enable bit */ | |
89 | if (!(pciexbar & 1)) | |
068258bc | 90 | return NULL; |
9358c693 OG |
91 | |
92 | /* Size bits */ | |
93 | switch ((pciexbar >> 1) & 3) { | |
94 | case 0: | |
95 | mask = 0xf0000000U; | |
96 | len = 0x10000000U; | |
97 | break; | |
98 | case 1: | |
99 | mask = 0xf8000000U; | |
100 | len = 0x08000000U; | |
101 | break; | |
102 | case 2: | |
103 | mask = 0xfc000000U; | |
104 | len = 0x04000000U; | |
105 | break; | |
106 | default: | |
068258bc | 107 | return NULL; |
9358c693 OG |
108 | } |
109 | ||
110 | /* Errata #2, things break when not aligned on a 256Mb boundary */ | |
111 | /* Can only happen in 64M/128M mode */ | |
112 | ||
113 | if ((pciexbar & mask) & 0x0fffffffU) | |
068258bc | 114 | return NULL; |
9358c693 | 115 | |
b5229dbb OG |
116 | /* Don't hit the APIC registers and their friends */ |
117 | if ((pciexbar & mask) >= 0xf0000000U) | |
068258bc YL |
118 | return NULL; |
119 | ||
7da7d360 | 120 | if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL) |
068258bc YL |
121 | return NULL; |
122 | ||
9358c693 OG |
123 | return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub"; |
124 | } | |
125 | ||
7fd0da40 YL |
126 | static const char __init *pci_mmcfg_amd_fam10h(void) |
127 | { | |
128 | u32 low, high, address; | |
129 | u64 base, msr; | |
130 | int i; | |
7da7d360 | 131 | unsigned segnbits = 0, busnbits, end_bus; |
7fd0da40 | 132 | |
5f0b2976 YL |
133 | if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) |
134 | return NULL; | |
135 | ||
7fd0da40 YL |
136 | address = MSR_FAM10H_MMIO_CONF_BASE; |
137 | if (rdmsr_safe(address, &low, &high)) | |
138 | return NULL; | |
139 | ||
140 | msr = high; | |
141 | msr <<= 32; | |
142 | msr |= low; | |
143 | ||
144 | /* mmconfig is not enable */ | |
145 | if (!(msr & FAM10H_MMIO_CONF_ENABLE)) | |
146 | return NULL; | |
147 | ||
148 | base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT); | |
149 | ||
150 | busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) & | |
151 | FAM10H_MMIO_CONF_BUSRANGE_MASK; | |
152 | ||
153 | /* | |
154 | * only handle bus 0 ? | |
155 | * need to skip it | |
156 | */ | |
157 | if (!busnbits) | |
158 | return NULL; | |
159 | ||
160 | if (busnbits > 8) { | |
161 | segnbits = busnbits - 8; | |
162 | busnbits = 8; | |
163 | } | |
164 | ||
7da7d360 | 165 | end_bus = (1 << busnbits) - 1; |
068258bc | 166 | for (i = 0; i < (1 << segnbits); i++) |
7da7d360 BH |
167 | if (pci_mmconfig_add(i, 0, end_bus, |
168 | base + (1<<28) * i) == NULL) { | |
169 | free_all_mmcfg(); | |
170 | return NULL; | |
171 | } | |
7fd0da40 YL |
172 | |
173 | return "AMD Family 10h NB"; | |
174 | } | |
175 | ||
5546d6f5 ES |
176 | static bool __initdata mcp55_checked; |
177 | static const char __init *pci_mmcfg_nvidia_mcp55(void) | |
178 | { | |
179 | int bus; | |
180 | int mcp55_mmconf_found = 0; | |
181 | ||
182 | static const u32 extcfg_regnum = 0x90; | |
183 | static const u32 extcfg_regsize = 4; | |
184 | static const u32 extcfg_enable_mask = 1<<31; | |
185 | static const u32 extcfg_start_mask = 0xff<<16; | |
186 | static const int extcfg_start_shift = 16; | |
187 | static const u32 extcfg_size_mask = 0x3<<28; | |
188 | static const int extcfg_size_shift = 28; | |
189 | static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20}; | |
190 | static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff}; | |
191 | static const int extcfg_base_lshift = 25; | |
192 | ||
193 | /* | |
194 | * do check if amd fam10h already took over | |
195 | */ | |
196 | if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked) | |
197 | return NULL; | |
198 | ||
199 | mcp55_checked = true; | |
200 | for (bus = 0; bus < 256; bus++) { | |
201 | u64 base; | |
202 | u32 l, extcfg; | |
203 | u16 vendor, device; | |
204 | int start, size_index, end; | |
205 | ||
206 | raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l); | |
207 | vendor = l & 0xffff; | |
208 | device = (l >> 16) & 0xffff; | |
209 | ||
210 | if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device) | |
211 | continue; | |
212 | ||
213 | raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum, | |
214 | extcfg_regsize, &extcfg); | |
215 | ||
216 | if (!(extcfg & extcfg_enable_mask)) | |
217 | continue; | |
218 | ||
5546d6f5 ES |
219 | size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift; |
220 | base = extcfg & extcfg_base_mask[size_index]; | |
221 | /* base could > 4G */ | |
222 | base <<= extcfg_base_lshift; | |
223 | start = (extcfg & extcfg_start_mask) >> extcfg_start_shift; | |
224 | end = start + extcfg_sizebus[size_index] - 1; | |
7da7d360 BH |
225 | if (pci_mmconfig_add(0, start, end, base) == NULL) |
226 | continue; | |
5546d6f5 ES |
227 | mcp55_mmconf_found++; |
228 | } | |
229 | ||
230 | if (!mcp55_mmconf_found) | |
231 | return NULL; | |
232 | ||
233 | return "nVidia MCP55"; | |
234 | } | |
235 | ||
9358c693 | 236 | struct pci_mmcfg_hostbridge_probe { |
7fd0da40 YL |
237 | u32 bus; |
238 | u32 devfn; | |
9358c693 OG |
239 | u32 vendor; |
240 | u32 device; | |
241 | const char *(*probe)(void); | |
242 | }; | |
243 | ||
429d512e | 244 | static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = { |
7fd0da40 YL |
245 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, |
246 | PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 }, | |
247 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL, | |
248 | PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 }, | |
249 | { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD, | |
250 | 0x1200, pci_mmcfg_amd_fam10h }, | |
251 | { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD, | |
252 | 0x1200, pci_mmcfg_amd_fam10h }, | |
5546d6f5 ES |
253 | { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA, |
254 | 0x0369, pci_mmcfg_nvidia_mcp55 }, | |
9358c693 OG |
255 | }; |
256 | ||
068258bc YL |
257 | static int __init cmp_mmcfg(const void *x1, const void *x2) |
258 | { | |
259 | const typeof(pci_mmcfg_config[0]) *m1 = x1; | |
260 | const typeof(pci_mmcfg_config[0]) *m2 = x2; | |
261 | int start1, start2; | |
262 | ||
263 | start1 = m1->start_bus_number; | |
264 | start2 = m2->start_bus_number; | |
265 | ||
266 | return start1 - start2; | |
267 | } | |
268 | ||
269 | static void __init pci_mmcfg_check_end_bus_number(void) | |
270 | { | |
271 | int i; | |
272 | typeof(pci_mmcfg_config[0]) *cfg, *cfgx; | |
273 | ||
274 | /* sort them at first */ | |
275 | sort(pci_mmcfg_config, pci_mmcfg_config_num, | |
276 | sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL); | |
277 | ||
278 | /* last one*/ | |
279 | if (pci_mmcfg_config_num > 0) { | |
280 | i = pci_mmcfg_config_num - 1; | |
281 | cfg = &pci_mmcfg_config[i]; | |
282 | if (cfg->end_bus_number < cfg->start_bus_number) | |
283 | cfg->end_bus_number = 255; | |
284 | } | |
285 | ||
286 | /* don't overlap please */ | |
287 | for (i = 0; i < pci_mmcfg_config_num - 1; i++) { | |
288 | cfg = &pci_mmcfg_config[i]; | |
289 | cfgx = &pci_mmcfg_config[i+1]; | |
290 | ||
291 | if (cfg->end_bus_number < cfg->start_bus_number) | |
292 | cfg->end_bus_number = 255; | |
293 | ||
294 | if (cfg->end_bus_number >= cfgx->start_bus_number) | |
295 | cfg->end_bus_number = cfgx->start_bus_number - 1; | |
296 | } | |
297 | } | |
298 | ||
9358c693 OG |
299 | static int __init pci_mmcfg_check_hostbridge(void) |
300 | { | |
301 | u32 l; | |
7fd0da40 | 302 | u32 bus, devfn; |
9358c693 OG |
303 | u16 vendor, device; |
304 | int i; | |
305 | const char *name; | |
306 | ||
bb63b421 YL |
307 | if (!raw_pci_ops) |
308 | return 0; | |
309 | ||
7da7d360 | 310 | free_all_mmcfg(); |
9358c693 | 311 | |
068258bc | 312 | for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) { |
7fd0da40 YL |
313 | bus = pci_mmcfg_probes[i].bus; |
314 | devfn = pci_mmcfg_probes[i].devfn; | |
bb63b421 | 315 | raw_pci_ops->read(0, bus, devfn, 0, 4, &l); |
7fd0da40 YL |
316 | vendor = l & 0xffff; |
317 | device = (l >> 16) & 0xffff; | |
318 | ||
068258bc | 319 | name = NULL; |
429d512e OH |
320 | if (pci_mmcfg_probes[i].vendor == vendor && |
321 | pci_mmcfg_probes[i].device == device) | |
9358c693 OG |
322 | name = pci_mmcfg_probes[i].probe(); |
323 | ||
068258bc YL |
324 | if (name) |
325 | printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n", | |
326 | name); | |
9358c693 OG |
327 | } |
328 | ||
068258bc YL |
329 | /* some end_bus_number is crazy, fix it */ |
330 | pci_mmcfg_check_end_bus_number(); | |
331 | ||
332 | return pci_mmcfg_config_num != 0; | |
9358c693 OG |
333 | } |
334 | ||
ebd60cd6 | 335 | static void __init pci_mmcfg_insert_resources(void) |
6a0668fc | 336 | { |
068258bc | 337 | #define PCI_MMCFG_RESOURCE_NAME_LEN 24 |
6a0668fc OG |
338 | int i; |
339 | struct resource *res; | |
340 | char *names; | |
341 | unsigned num_buses; | |
342 | ||
343 | res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res), | |
344 | pci_mmcfg_config_num, GFP_KERNEL); | |
6a0668fc OG |
345 | if (!res) { |
346 | printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n"); | |
347 | return; | |
348 | } | |
349 | ||
350 | names = (void *)&res[pci_mmcfg_config_num]; | |
351 | for (i = 0; i < pci_mmcfg_config_num; i++, res++) { | |
d215a9c8 | 352 | struct pci_mmcfg_region *cfg = &pci_mmcfg_config[i]; |
429d512e | 353 | num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; |
6a0668fc | 354 | res->name = names; |
068258bc YL |
355 | snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, |
356 | "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment, | |
357 | cfg->start_bus_number, cfg->end_bus_number); | |
df5eb1d6 BH |
358 | res->start = cfg->address + |
359 | PCI_MMCFG_BUS_OFFSET(cfg->start_bus_number); | |
360 | res->end = res->start + PCI_MMCFG_BUS_OFFSET(num_buses) - 1; | |
ebd60cd6 | 361 | res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
6a0668fc OG |
362 | insert_resource(&iomem_resource, res); |
363 | names += PCI_MMCFG_RESOURCE_NAME_LEN; | |
364 | } | |
a5ba7971 AD |
365 | |
366 | /* Mark that the resources have been inserted. */ | |
367 | pci_mmcfg_resources_inserted = 1; | |
6a0668fc OG |
368 | } |
369 | ||
7752d5cf RH |
370 | static acpi_status __init check_mcfg_resource(struct acpi_resource *res, |
371 | void *data) | |
372 | { | |
373 | struct resource *mcfg_res = data; | |
374 | struct acpi_resource_address64 address; | |
375 | acpi_status status; | |
376 | ||
377 | if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) { | |
378 | struct acpi_resource_fixed_memory32 *fixmem32 = | |
379 | &res->data.fixed_memory32; | |
380 | if (!fixmem32) | |
381 | return AE_OK; | |
382 | if ((mcfg_res->start >= fixmem32->address) && | |
75e613cd | 383 | (mcfg_res->end < (fixmem32->address + |
7752d5cf RH |
384 | fixmem32->address_length))) { |
385 | mcfg_res->flags = 1; | |
386 | return AE_CTRL_TERMINATE; | |
387 | } | |
388 | } | |
389 | if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) && | |
390 | (res->type != ACPI_RESOURCE_TYPE_ADDRESS64)) | |
391 | return AE_OK; | |
392 | ||
393 | status = acpi_resource_to_address64(res, &address); | |
394 | if (ACPI_FAILURE(status) || | |
395 | (address.address_length <= 0) || | |
396 | (address.resource_type != ACPI_MEMORY_RANGE)) | |
397 | return AE_OK; | |
398 | ||
399 | if ((mcfg_res->start >= address.minimum) && | |
75e613cd | 400 | (mcfg_res->end < (address.minimum + address.address_length))) { |
7752d5cf RH |
401 | mcfg_res->flags = 1; |
402 | return AE_CTRL_TERMINATE; | |
403 | } | |
404 | return AE_OK; | |
405 | } | |
406 | ||
407 | static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl, | |
408 | void *context, void **rv) | |
409 | { | |
410 | struct resource *mcfg_res = context; | |
411 | ||
412 | acpi_walk_resources(handle, METHOD_NAME__CRS, | |
413 | check_mcfg_resource, context); | |
414 | ||
415 | if (mcfg_res->flags) | |
416 | return AE_CTRL_TERMINATE; | |
417 | ||
418 | return AE_OK; | |
419 | } | |
420 | ||
a83fe32f | 421 | static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used) |
7752d5cf RH |
422 | { |
423 | struct resource mcfg_res; | |
424 | ||
425 | mcfg_res.start = start; | |
75e613cd | 426 | mcfg_res.end = end - 1; |
7752d5cf RH |
427 | mcfg_res.flags = 0; |
428 | ||
429 | acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL); | |
430 | ||
431 | if (!mcfg_res.flags) | |
432 | acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res, | |
433 | NULL); | |
434 | ||
435 | return mcfg_res.flags; | |
436 | } | |
437 | ||
a83fe32f YL |
438 | typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type); |
439 | ||
440 | static int __init is_mmconf_reserved(check_reserved_t is_reserved, | |
441 | u64 addr, u64 size, int i, | |
442 | typeof(pci_mmcfg_config[0]) *cfg, int with_e820) | |
443 | { | |
444 | u64 old_size = size; | |
445 | int valid = 0; | |
446 | ||
044cd809 | 447 | while (!is_reserved(addr, addr + size, E820_RESERVED)) { |
a83fe32f YL |
448 | size >>= 1; |
449 | if (size < (16UL<<20)) | |
450 | break; | |
451 | } | |
452 | ||
453 | if (size >= (16UL<<20) || size == old_size) { | |
454 | printk(KERN_NOTICE | |
455 | "PCI: MCFG area at %Lx reserved in %s\n", | |
456 | addr, with_e820?"E820":"ACPI motherboard resources"); | |
457 | valid = 1; | |
458 | ||
459 | if (old_size != size) { | |
460 | /* update end_bus_number */ | |
461 | cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1); | |
462 | printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx " | |
463 | "segment %hu buses %u - %u\n", | |
464 | i, (unsigned long)cfg->address, cfg->pci_segment, | |
465 | (unsigned int)cfg->start_bus_number, | |
466 | (unsigned int)cfg->end_bus_number); | |
467 | } | |
468 | } | |
469 | ||
470 | return valid; | |
471 | } | |
472 | ||
bb63b421 | 473 | static void __init pci_mmcfg_reject_broken(int early) |
44de0203 | 474 | { |
26054ed0 | 475 | typeof(pci_mmcfg_config[0]) *cfg; |
7752d5cf | 476 | int i; |
26054ed0 | 477 | |
f7ca6984 | 478 | if (pci_mmcfg_config_num == 0) |
26054ed0 OH |
479 | return; |
480 | ||
7752d5cf | 481 | for (i = 0; i < pci_mmcfg_config_num; i++) { |
df5eb1d6 | 482 | int num_buses, valid = 0; |
a83fe32f YL |
483 | u64 addr, size; |
484 | ||
7752d5cf | 485 | cfg = &pci_mmcfg_config[i]; |
df5eb1d6 BH |
486 | addr = cfg->address + |
487 | PCI_MMCFG_BUS_OFFSET(cfg->start_bus_number); | |
488 | num_buses = cfg->end_bus_number - cfg->start_bus_number + 1; | |
489 | size = PCI_MMCFG_BUS_OFFSET(num_buses); | |
05c58b8a | 490 | printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx " |
7752d5cf RH |
491 | "segment %hu buses %u - %u\n", |
492 | i, (unsigned long)cfg->address, cfg->pci_segment, | |
493 | (unsigned int)cfg->start_bus_number, | |
494 | (unsigned int)cfg->end_bus_number); | |
05c58b8a | 495 | |
5f0db7a2 | 496 | if (!early && !acpi_disabled) |
a83fe32f | 497 | valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0); |
05c58b8a YL |
498 | |
499 | if (valid) | |
500 | continue; | |
501 | ||
502 | if (!early) | |
7752d5cf RH |
503 | printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not" |
504 | " reserved in ACPI motherboard resources\n", | |
505 | cfg->address); | |
a83fe32f | 506 | |
05c58b8a | 507 | /* Don't try to do this check unless configuration |
bb63b421 | 508 | type 1 is available. how about type 2 ?*/ |
a83fe32f YL |
509 | if (raw_pci_ops) |
510 | valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1); | |
05c58b8a YL |
511 | |
512 | if (!valid) | |
513 | goto reject; | |
44de0203 | 514 | } |
7752d5cf | 515 | |
26054ed0 OH |
516 | return; |
517 | ||
518 | reject: | |
ef310237 | 519 | printk(KERN_INFO "PCI: Not using MMCONFIG.\n"); |
7da7d360 | 520 | free_all_mmcfg(); |
44de0203 OH |
521 | } |
522 | ||
05c58b8a | 523 | static int __initdata known_bridge; |
7752d5cf | 524 | |
c4bf2f37 | 525 | /* The physical address of the MMCONFIG aperture. Set from ACPI tables. */ |
d215a9c8 | 526 | struct pci_mmcfg_region *pci_mmcfg_config; |
c4bf2f37 LB |
527 | int pci_mmcfg_config_num; |
528 | ||
9a08f7d3 BH |
529 | static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, |
530 | struct acpi_mcfg_allocation *cfg) | |
c4bf2f37 | 531 | { |
9a08f7d3 BH |
532 | int year; |
533 | ||
534 | if (cfg->address < 0xFFFFFFFF) | |
535 | return 0; | |
536 | ||
c4bf2f37 | 537 | if (!strcmp(mcfg->header.oem_id, "SGI")) |
9a08f7d3 | 538 | return 0; |
c4bf2f37 | 539 | |
9a08f7d3 BH |
540 | if (mcfg->header.revision >= 1) { |
541 | if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && | |
542 | year >= 2010) | |
543 | return 0; | |
544 | } | |
545 | ||
546 | printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx " | |
547 | "is above 4GB, ignored\n", cfg->pci_segment, | |
548 | cfg->start_bus_number, cfg->end_bus_number, cfg->address); | |
549 | return -EINVAL; | |
c4bf2f37 LB |
550 | } |
551 | ||
552 | static int __init pci_parse_mcfg(struct acpi_table_header *header) | |
553 | { | |
554 | struct acpi_table_mcfg *mcfg; | |
d3578ef7 | 555 | struct acpi_mcfg_allocation *cfg_table, *cfg; |
c4bf2f37 | 556 | unsigned long i; |
7da7d360 | 557 | int entries; |
c4bf2f37 LB |
558 | |
559 | if (!header) | |
560 | return -EINVAL; | |
561 | ||
562 | mcfg = (struct acpi_table_mcfg *)header; | |
563 | ||
564 | /* how many config structures do we have */ | |
7da7d360 | 565 | free_all_mmcfg(); |
e823d6ff | 566 | entries = 0; |
c4bf2f37 LB |
567 | i = header->length - sizeof(struct acpi_table_mcfg); |
568 | while (i >= sizeof(struct acpi_mcfg_allocation)) { | |
e823d6ff | 569 | entries++; |
c4bf2f37 LB |
570 | i -= sizeof(struct acpi_mcfg_allocation); |
571 | }; | |
e823d6ff | 572 | if (entries == 0) { |
c4bf2f37 LB |
573 | printk(KERN_ERR PREFIX "MMCONFIG has no entries\n"); |
574 | return -ENODEV; | |
575 | } | |
576 | ||
d3578ef7 | 577 | cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; |
e823d6ff | 578 | for (i = 0; i < entries; i++) { |
d3578ef7 BH |
579 | cfg = &cfg_table[i]; |
580 | if (acpi_mcfg_check_entry(mcfg, cfg)) { | |
7da7d360 | 581 | free_all_mmcfg(); |
c4bf2f37 LB |
582 | return -ENODEV; |
583 | } | |
7da7d360 BH |
584 | |
585 | if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, | |
586 | cfg->end_bus_number, cfg->address) == NULL) { | |
587 | printk(KERN_WARNING PREFIX | |
588 | "no memory for MCFG entries\n"); | |
589 | free_all_mmcfg(); | |
590 | return -ENOMEM; | |
591 | } | |
c4bf2f37 LB |
592 | } |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
968cbfad | 597 | static void __init __pci_mmcfg_init(int early) |
b7867394 | 598 | { |
7752d5cf | 599 | /* MMCONFIG disabled */ |
b7867394 OG |
600 | if ((pci_probe & PCI_PROBE_MMCONF) == 0) |
601 | return; | |
602 | ||
7752d5cf | 603 | /* MMCONFIG already enabled */ |
05c58b8a | 604 | if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF)) |
7752d5cf | 605 | return; |
9358c693 | 606 | |
05c58b8a YL |
607 | /* for late to exit */ |
608 | if (known_bridge) | |
609 | return; | |
7752d5cf | 610 | |
bb63b421 | 611 | if (early) { |
05c58b8a YL |
612 | if (pci_mmcfg_check_hostbridge()) |
613 | known_bridge = 1; | |
614 | } | |
615 | ||
068258bc | 616 | if (!known_bridge) |
5f0db7a2 | 617 | acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); |
068258bc YL |
618 | |
619 | pci_mmcfg_reject_broken(early); | |
b7867394 | 620 | |
f7ca6984 | 621 | if (pci_mmcfg_config_num == 0) |
b7867394 OG |
622 | return; |
623 | ||
ebd60cd6 | 624 | if (pci_mmcfg_arch_init()) |
b7867394 | 625 | pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; |
ebd60cd6 | 626 | else { |
a5ba7971 AD |
627 | /* |
628 | * Signal not to attempt to insert mmcfg resources because | |
629 | * the architecture mmcfg setup could not initialize. | |
630 | */ | |
631 | pci_mmcfg_resources_inserted = 1; | |
b7867394 OG |
632 | } |
633 | } | |
a5ba7971 | 634 | |
bb63b421 | 635 | void __init pci_mmcfg_early_init(void) |
05c58b8a | 636 | { |
bb63b421 | 637 | __pci_mmcfg_init(1); |
05c58b8a YL |
638 | } |
639 | ||
640 | void __init pci_mmcfg_late_init(void) | |
641 | { | |
bb63b421 | 642 | __pci_mmcfg_init(0); |
05c58b8a YL |
643 | } |
644 | ||
a5ba7971 AD |
645 | static int __init pci_mmcfg_late_insert_resources(void) |
646 | { | |
647 | /* | |
648 | * If resources are already inserted or we are not using MMCONFIG, | |
649 | * don't insert the resources. | |
650 | */ | |
651 | if ((pci_mmcfg_resources_inserted == 1) || | |
652 | (pci_probe & PCI_PROBE_MMCONF) == 0 || | |
f7ca6984 | 653 | (pci_mmcfg_config_num == 0)) |
a5ba7971 AD |
654 | return 1; |
655 | ||
656 | /* | |
657 | * Attempt to insert the mmcfg resources but not with the busy flag | |
658 | * marked so it won't cause request errors when __request_region is | |
659 | * called. | |
660 | */ | |
ebd60cd6 | 661 | pci_mmcfg_insert_resources(); |
a5ba7971 AD |
662 | |
663 | return 0; | |
664 | } | |
665 | ||
666 | /* | |
667 | * Perform MMCONFIG resource insertion after PCI initialization to allow for | |
668 | * misprogrammed MCFG tables that state larger sizes but actually conflict | |
669 | * with other system resources. | |
670 | */ | |
671 | late_initcall(pci_mmcfg_late_insert_resources); |