[net-next-2.6.git] / arch / x86 / pci / mmconfig-shared.c

/*
 * mmconfig-shared.c - Low-level direct PCI config space access via
 *                     MMCONFIG - common code between i386 and x86-64.
 *
 * This code does:
 * - known chipset handling
 * - ACPI decoding and validation
 *
 * Per-architecture code takes care of the mappings and accesses
 * themselves.
 */

#include <linux/pci.h>
#include <linux/init.h>
#include <linux/acpi.h>
#include <linux/sfi_acpi.h>
#include <linux/bitmap.h>
#include <linux/dmi.h>
#include <linux/sort.h>
#include <asm/e820.h>
#include <asm/pci_x86.h>
#include <asm/acpi.h>

#define PREFIX "PCI: "

/* Indicate if the mmcfg resources have been placed into the resource table. */
static int __initdata pci_mmcfg_resources_inserted;

static __init int extend_mmcfg(int num)
{
	struct acpi_mcfg_allocation *new;
	int new_num = pci_mmcfg_config_num + num;

	new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
	if (!new)
		return -1;

	if (pci_mmcfg_config) {
		memcpy(new, pci_mmcfg_config,
			 sizeof(pci_mmcfg_config[0]) * new_num);
		kfree(pci_mmcfg_config);
	}
	pci_mmcfg_config = new;

	return 0;
}

static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
{
	int i = pci_mmcfg_config_num;

	pci_mmcfg_config_num++;
	pci_mmcfg_config[i].address = addr;
	pci_mmcfg_config[i].pci_segment = segment;
	pci_mmcfg_config[i].start_bus_number = start;
	pci_mmcfg_config[i].end_bus_number = end;
}

static const char __init *pci_mmcfg_e7520(void)
{
	u32 win;
	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);

	win = win & 0xf000;
	if (win == 0x0000 || win == 0xf000)
		return NULL;

	if (extend_mmcfg(1) == -1)
		return NULL;

	fill_one_mmcfg(win << 16, 0, 0, 255);

	return "Intel Corporation E7520 Memory Controller Hub";
}

static const char __init *pci_mmcfg_intel_945(void)
{
	u32 pciexbar, mask = 0, len = 0;

	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);

	/* Enable bit */
	if (!(pciexbar & 1))
		return NULL;

	/* Size bits */
	switch ((pciexbar >> 1) & 3) {
	case 0:
		mask = 0xf0000000U;
		len  = 0x10000000U;
		break;
	case 1:
		mask = 0xf8000000U;
		len  = 0x08000000U;
		break;
	case 2:
		mask = 0xfc000000U;
		len  = 0x04000000U;
		break;
	default:
		return NULL;
	}

	/* Errata #2, things break when not aligned on a 256Mb boundary */
	/* Can only happen in 64M/128M mode */

	if ((pciexbar & mask) & 0x0fffffffU)
		return NULL;

	/* Don't hit the APIC registers and their friends */
	if ((pciexbar & mask) >= 0xf0000000U)
		return NULL;

	if (extend_mmcfg(1) == -1)
		return NULL;

	fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);

	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
}

static const char __init *pci_mmcfg_amd_fam10h(void)
{
	u32 low, high, address;
	u64 base, msr;
	int i;
	unsigned segnbits = 0, busnbits;

	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
		return NULL;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	if (rdmsr_safe(address, &low, &high))
		return NULL;

	msr = high;
	msr <<= 32;
	msr |= low;

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return NULL;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	/*
	 * only handle bus 0 ?
	 * need to skip it
	 */
	if (!busnbits)
		return NULL;

	if (busnbits > 8) {
		segnbits = busnbits - 8;
		busnbits = 8;
	}

	if (extend_mmcfg(1 << segnbits) == -1)
		return NULL;

	for (i = 0; i < (1 << segnbits); i++)
		fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);

	return "AMD Family 10h NB";
}

static bool __initdata mcp55_checked;
static const char __init *pci_mmcfg_nvidia_mcp55(void)
{
	int bus;
	int mcp55_mmconf_found = 0;

	static const u32 extcfg_regnum		= 0x90;
	static const u32 extcfg_regsize		= 4;
	static const u32 extcfg_enable_mask	= 1<<31;
	static const u32 extcfg_start_mask	= 0xff<<16;
	static const int extcfg_start_shift	= 16;
	static const u32 extcfg_size_mask	= 0x3<<28;
	static const int extcfg_size_shift	= 28;
	static const int extcfg_sizebus[]	= {0x100, 0x80, 0x40, 0x20};
	static const u32 extcfg_base_mask[]	= {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
	static const int extcfg_base_lshift	= 25;

	/*
	 * do check if amd fam10h already took over
	 */
	if (!acpi_disabled || pci_mmcfg_config_num || mcp55_checked)
		return NULL;

	mcp55_checked = true;
	for (bus = 0; bus < 256; bus++) {
		u64 base;
		u32 l, extcfg;
		u16 vendor, device;
		int start, size_index, end;

		raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
		vendor = l & 0xffff;
		device = (l >> 16) & 0xffff;

		if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
			continue;

		raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
				  extcfg_regsize, &extcfg);

		if (!(extcfg & extcfg_enable_mask))
			continue;

		if (extend_mmcfg(1) == -1)
			continue;

		size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
		base = extcfg & extcfg_base_mask[size_index];
		/* base could > 4G */
		base <<= extcfg_base_lshift;
		start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
		end = start + extcfg_sizebus[size_index] - 1;
		fill_one_mmcfg(base, 0, start, end);
		mcp55_mmconf_found++;
	}

	if (!mcp55_mmconf_found)
		return NULL;

	return "nVidia MCP55";
}

struct pci_mmcfg_hostbridge_probe {
	u32 bus;
	u32 devfn;
	u32 vendor;
	u32 device;
	const char *(*probe)(void);
};

static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	  PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	  0x1200, pci_mmcfg_amd_fam10h },
	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
	  0x0369, pci_mmcfg_nvidia_mcp55 },
};

static int __init cmp_mmcfg(const void *x1, const void *x2)
{
	const typeof(pci_mmcfg_config[0]) *m1 = x1;
	const typeof(pci_mmcfg_config[0]) *m2 = x2;
	int start1, start2;

	start1 = m1->start_bus_number;
	start2 = m2->start_bus_number;

	return start1 - start2;
}

static void __init pci_mmcfg_check_end_bus_number(void)
{
	int i;
	typeof(pci_mmcfg_config[0]) *cfg, *cfgx;

	/* sort them at first */
	sort(pci_mmcfg_config, pci_mmcfg_config_num,
		 sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);

	/* last one*/
	if (pci_mmcfg_config_num > 0) {
		i = pci_mmcfg_config_num - 1;
		cfg = &pci_mmcfg_config[i];
		if (cfg->end_bus_number < cfg->start_bus_number)
			cfg->end_bus_number = 255;
	}

	/* don't overlap please */
	for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
		cfg = &pci_mmcfg_config[i];
		cfgx = &pci_mmcfg_config[i+1];

		if (cfg->end_bus_number < cfg->start_bus_number)
			cfg->end_bus_number = 255;

		if (cfg->end_bus_number >= cfgx->start_bus_number)
			cfg->end_bus_number = cfgx->start_bus_number - 1;
	}
}

static int __init pci_mmcfg_check_hostbridge(void)
{
	u32 l;
	u32 bus, devfn;
	u16 vendor, device;
	int i;
	const char *name;

	if (!raw_pci_ops)
		return 0;

	pci_mmcfg_config_num = 0;
	pci_mmcfg_config = NULL;

	for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
		bus =  pci_mmcfg_probes[i].bus;
		devfn = pci_mmcfg_probes[i].devfn;
		raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
		vendor = l & 0xffff;
		device = (l >> 16) & 0xffff;

		name = NULL;
		if (pci_mmcfg_probes[i].vendor == vendor &&
		    pci_mmcfg_probes[i].device == device)
			name = pci_mmcfg_probes[i].probe();

		if (name)
			printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
			       name);
	}

	/* some end_bus_number is crazy, fix it */
	pci_mmcfg_check_end_bus_number();

	return pci_mmcfg_config_num != 0;
}

static void __init pci_mmcfg_insert_resources(void)
{
#define PCI_MMCFG_RESOURCE_NAME_LEN 24
	int i;
	struct resource *res;
	char *names;
	unsigned num_buses;

	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
			pci_mmcfg_config_num, GFP_KERNEL);
	if (!res) {
		printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
		return;
	}

	names = (void *)&res[pci_mmcfg_config_num];
	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
		struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
		num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
		res->name = names;
		snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
			 "PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
			 cfg->start_bus_number, cfg->end_bus_number);
		res->start = cfg->address + (cfg->start_bus_number << 20);
		res->end = res->start + (num_buses << 20) - 1;
		res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
		insert_resource(&iomem_resource, res);
		names += PCI_MMCFG_RESOURCE_NAME_LEN;
	}

	/* Mark that the resources have been inserted. */
	pci_mmcfg_resources_inserted = 1;
}

static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
					      void *data)
{
	struct resource *mcfg_res = data;
	struct acpi_resource_address64 address;
	acpi_status status;

	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
		struct acpi_resource_fixed_memory32 *fixmem32 =
			&res->data.fixed_memory32;
		if (!fixmem32)
			return AE_OK;
		if ((mcfg_res->start >= fixmem32->address) &&
		    (mcfg_res->end < (fixmem32->address +
				      fixmem32->address_length))) {
			mcfg_res->flags = 1;
			return AE_CTRL_TERMINATE;
		}
	}
	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	    (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
		return AE_OK;

	status = acpi_resource_to_address64(res, &address);
	if (ACPI_FAILURE(status) ||
	   (address.address_length <= 0) ||
	   (address.resource_type != ACPI_MEMORY_RANGE))
		return AE_OK;

	if ((mcfg_res->start >= address.minimum) &&
	    (mcfg_res->end < (address.minimum + address.address_length))) {
		mcfg_res->flags = 1;
		return AE_CTRL_TERMINATE;
	}
	return AE_OK;
}

static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
		void *context, void **rv)
{
	struct resource *mcfg_res = context;

	acpi_walk_resources(handle, METHOD_NAME__CRS,
			    check_mcfg_resource, context);

	if (mcfg_res->flags)
		return AE_CTRL_TERMINATE;

	return AE_OK;
}

static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
{
	struct resource mcfg_res;

	mcfg_res.start = start;
	mcfg_res.end = end - 1;
	mcfg_res.flags = 0;

	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);

	if (!mcfg_res.flags)
		acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
				 NULL);

	return mcfg_res.flags;
}

typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);

static int __init is_mmconf_reserved(check_reserved_t is_reserved,
		u64 addr, u64 size, int i,
		typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
{
	u64 old_size = size;
	int valid = 0;

	while (!is_reserved(addr, addr + size, E820_RESERVED)) {
		size >>= 1;
		if (size < (16UL<<20))
			break;
	}

	if (size >= (16UL<<20) || size == old_size) {
		printk(KERN_NOTICE
		       "PCI: MCFG area at %Lx reserved in %s\n",
			addr, with_e820?"E820":"ACPI motherboard resources");
		valid = 1;

		if (old_size != size) {
			/* update end_bus_number */
			cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
			printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
			       "segment %hu buses %u - %u\n",
			       i, (unsigned long)cfg->address, cfg->pci_segment,
			       (unsigned int)cfg->start_bus_number,
			       (unsigned int)cfg->end_bus_number);
		}
	}

	return valid;
}

static void __init pci_mmcfg_reject_broken(int early)
{
	typeof(pci_mmcfg_config[0]) *cfg;
	int i;

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	for (i = 0; i < pci_mmcfg_config_num; i++) {
		int valid = 0;
		u64 addr, size;

		cfg = &pci_mmcfg_config[i];
		addr = cfg->start_bus_number;
		addr <<= 20;
		addr += cfg->address;
		size = cfg->end_bus_number + 1 - cfg->start_bus_number;
		size <<= 20;
		printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
		       "segment %hu buses %u - %u\n",
		       i, (unsigned long)cfg->address, cfg->pci_segment,
		       (unsigned int)cfg->start_bus_number,
		       (unsigned int)cfg->end_bus_number);

		if (!early && !acpi_disabled)
			valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);

		if (valid)
			continue;

		if (!early)
			printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
			       " reserved in ACPI motherboard resources\n",
			       cfg->address);

		/* Don't try to do this check unless configuration
		   type 1 is available. how about type 2 ?*/
		if (raw_pci_ops)
			valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);

		if (!valid)
			goto reject;
	}

	return;

reject:
	printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
	pci_mmcfg_arch_free();
	kfree(pci_mmcfg_config);
	pci_mmcfg_config = NULL;
	pci_mmcfg_config_num = 0;
}

static int __initdata known_bridge;

/* The physical address of the MMCONFIG aperture.  Set from ACPI tables. */
struct acpi_mcfg_allocation *pci_mmcfg_config;
int pci_mmcfg_config_num;

static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
					struct acpi_mcfg_allocation *cfg)
{
	int year;

	if (cfg->address < 0xFFFFFFFF)
		return 0;

	if (!strcmp(mcfg->header.oem_id, "SGI"))
		return 0;

	if (mcfg->header.revision >= 1) {
		if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
		    year >= 2010)
			return 0;
	}

	printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx "
	       "is above 4GB, ignored\n", cfg->pci_segment,
	       cfg->start_bus_number, cfg->end_bus_number, cfg->address);
	return -EINVAL;
}

static int __init pci_parse_mcfg(struct acpi_table_header *header)
{
	struct acpi_table_mcfg *mcfg;
	unsigned long i;
	int config_size;

	if (!header)
		return -EINVAL;

	mcfg = (struct acpi_table_mcfg *)header;

	/* how many config structures do we have */
	pci_mmcfg_config_num = 0;
	i = header->length - sizeof(struct acpi_table_mcfg);
	while (i >= sizeof(struct acpi_mcfg_allocation)) {
		++pci_mmcfg_config_num;
		i -= sizeof(struct acpi_mcfg_allocation);
	};
	if (pci_mmcfg_config_num == 0) {
		printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
		return -ENODEV;
	}

	config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
	pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
	if (!pci_mmcfg_config) {
		printk(KERN_WARNING PREFIX
		       "No memory for MCFG config tables\n");
		return -ENOMEM;
	}

	memcpy(pci_mmcfg_config, &mcfg[1], config_size);

	for (i = 0; i < pci_mmcfg_config_num; ++i) {
		if (acpi_mcfg_check_entry(mcfg, &pci_mmcfg_config[i])) {
			kfree(pci_mmcfg_config);
			pci_mmcfg_config_num = 0;
			return -ENODEV;
		}
	}

	return 0;
}

static void __init __pci_mmcfg_init(int early)
{
	/* MMCONFIG disabled */
	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
		return;

	/* MMCONFIG already enabled */
	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
		return;

	/* for late to exit */
	if (known_bridge)
		return;

	if (early) {
		if (pci_mmcfg_check_hostbridge())
			known_bridge = 1;
	}

	if (!known_bridge)
		acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);

	pci_mmcfg_reject_broken(early);

	if ((pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return;

	if (pci_mmcfg_arch_init())
		pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
	else {
		/*
		 * Signal not to attempt to insert mmcfg resources because
		 * the architecture mmcfg setup could not initialize.
		 */
		pci_mmcfg_resources_inserted = 1;
	}
}

void __init pci_mmcfg_early_init(void)
{
	__pci_mmcfg_init(1);
}

void __init pci_mmcfg_late_init(void)
{
	__pci_mmcfg_init(0);
}

static int __init pci_mmcfg_late_insert_resources(void)
{
	/*
	 * If resources are already inserted or we are not using MMCONFIG,
	 * don't insert the resources.
	 */
	if ((pci_mmcfg_resources_inserted == 1) ||
	    (pci_probe & PCI_PROBE_MMCONF) == 0 ||
	    (pci_mmcfg_config_num == 0) ||
	    (pci_mmcfg_config == NULL) ||
	    (pci_mmcfg_config[0].address == 0))
		return 1;

	/*
	 * Attempt to insert the mmcfg resources but not with the busy flag
	 * marked so it won't cause request errors when __request_region is
	 * called.
	 */
	pci_mmcfg_insert_resources();

	return 0;
}

/*
 * Perform MMCONFIG resource insertion after PCI initialization to allow for
 * misprogrammed MCFG tables that state larger sizes but actually conflict
 * with other system resources.
 */
late_initcall(pci_mmcfg_late_insert_resources);
Commit	Line	Data
b7867394 OG	1	/*
	2	* mmconfig-shared.c - Low-level direct PCI config space access via
	3	* MMCONFIG - common code between i386 and x86-64.
	4	*
	5	* This code does:
9358c693	6	* - known chipset handling
b7867394 OG	7	* - ACPI decoding and validation
	8	*
	9	* Per-architecture code takes care of the mappings and accesses
	10	* themselves.
	11	*/
	12
	13	#include <linux/pci.h>
	14	#include <linux/init.h>
	15	#include <linux/acpi.h>
5f0db7a2	16	#include <linux/sfi_acpi.h>
b7867394	17	#include <linux/bitmap.h>
9a08f7d3	18	#include <linux/dmi.h>
068258bc	19	#include <linux/sort.h>
b7867394	20	#include <asm/e820.h>
82487711	21	#include <asm/pci_x86.h>
5f0db7a2	22	#include <asm/acpi.h>
b7867394	23
f4a2d584	24	#define PREFIX "PCI: "
a192a958	25
a5ba7971 AD	26	/* Indicate if the mmcfg resources have been placed into the resource table. */
	27	static int __initdata pci_mmcfg_resources_inserted;
	28
068258bc YL	29	static __init int extend_mmcfg(int num)
	30	{
	31	struct acpi_mcfg_allocation *new;
	32	int new_num = pci_mmcfg_config_num + num;
	33
	34	new = kzalloc(sizeof(pci_mmcfg_config[0]) * new_num, GFP_KERNEL);
	35	if (!new)
	36	return -1;
	37
	38	if (pci_mmcfg_config) {
	39	memcpy(new, pci_mmcfg_config,
	40	sizeof(pci_mmcfg_config[0]) * new_num);
	41	kfree(pci_mmcfg_config);
	42	}
	43	pci_mmcfg_config = new;
	44
	45	return 0;
	46	}
	47
	48	static __init void fill_one_mmcfg(u64 addr, int segment, int start, int end)
	49	{
	50	int i = pci_mmcfg_config_num;
	51
	52	pci_mmcfg_config_num++;
	53	pci_mmcfg_config[i].address = addr;
	54	pci_mmcfg_config[i].pci_segment = segment;
	55	pci_mmcfg_config[i].start_bus_number = start;
	56	pci_mmcfg_config[i].end_bus_number = end;
	57	}
	58
429d512e	59	static const char __init *pci_mmcfg_e7520(void)
9358c693 OG	60	{
9358c693 OG	61	u32 win;
bb63b421	62	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
9358c693	63
b5229dbb	64	win = win & 0xf000;
068258bc YL	65	if (win == 0x0000 \|\| win == 0xf000)
	66	return NULL;
	67
	68	if (extend_mmcfg(1) == -1)
	69	return NULL;
	70
	71	fill_one_mmcfg(win << 16, 0, 0, 255);
9358c693 OG	72
	73	return "Intel Corporation E7520 Memory Controller Hub";
	74	}
	75
429d512e	76	static const char __init *pci_mmcfg_intel_945(void)
9358c693 OG	77	{
	78	u32 pciexbar, mask = 0, len = 0;
	79
bb63b421	80	raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
9358c693 OG	81
	82	/* Enable bit */
	83	if (!(pciexbar & 1))
068258bc	84	return NULL;
9358c693 OG	85
	86	/* Size bits */
	87	switch ((pciexbar >> 1) & 3) {
	88	case 0:
	89	mask = 0xf0000000U;
	90	len = 0x10000000U;
	91	break;
	92	case 1:
	93	mask = 0xf8000000U;
	94	len = 0x08000000U;
	95	break;
	96	case 2:
	97	mask = 0xfc000000U;
	98	len = 0x04000000U;
	99	break;
	100	default:
068258bc	101	return NULL;
9358c693 OG	102	}
	103
	104	/* Errata #2, things break when not aligned on a 256Mb boundary */
	105	/* Can only happen in 64M/128M mode */
	106
	107	if ((pciexbar & mask) & 0x0fffffffU)
068258bc	108	return NULL;
9358c693	109
b5229dbb OG	110	/* Don't hit the APIC registers and their friends */
b5229dbb OG	111	if ((pciexbar & mask) >= 0xf0000000U)
068258bc YL	112	return NULL;
	113
	114	if (extend_mmcfg(1) == -1)
	115	return NULL;
	116
	117	fill_one_mmcfg(pciexbar & mask, 0, 0, (len >> 20) - 1);
9358c693 OG	118
	119	return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
	120	}
	121
7fd0da40 YL	122	static const char __init *pci_mmcfg_amd_fam10h(void)
	123	{
	124	u32 low, high, address;
	125	u64 base, msr;
	126	int i;
	127	unsigned segnbits = 0, busnbits;
	128
5f0b2976 YL	129	if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
	130	return NULL;
	131
7fd0da40 YL	132	address = MSR_FAM10H_MMIO_CONF_BASE;
	133	if (rdmsr_safe(address, &low, &high))
	134	return NULL;
	135
	136	msr = high;
	137	msr <<= 32;
	138	msr \|= low;
	139
	140	/* mmconfig is not enable */
	141	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	142	return NULL;
	143
	144	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	145
	146	busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	147	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	148
	149	/*
	150	* only handle bus 0 ?
	151	* need to skip it
	152	*/
	153	if (!busnbits)
	154	return NULL;
	155
	156	if (busnbits > 8) {
	157	segnbits = busnbits - 8;
	158	busnbits = 8;
	159	}
	160
068258bc	161	if (extend_mmcfg(1 << segnbits) == -1)
7fd0da40 YL	162	return NULL;
7fd0da40 YL	163
068258bc YL	164	for (i = 0; i < (1 << segnbits); i++)
068258bc YL	165	fill_one_mmcfg(base + (1<<28) * i, i, 0, (1 << busnbits) - 1);
7fd0da40 YL	166
	167	return "AMD Family 10h NB";
	168	}
	169
5546d6f5 ES	170	static bool __initdata mcp55_checked;
	171	static const char __init *pci_mmcfg_nvidia_mcp55(void)
	172	{
	173	int bus;
	174	int mcp55_mmconf_found = 0;
	175
	176	static const u32 extcfg_regnum = 0x90;
	177	static const u32 extcfg_regsize = 4;
	178	static const u32 extcfg_enable_mask = 1<<31;
	179	static const u32 extcfg_start_mask = 0xff<<16;
	180	static const int extcfg_start_shift = 16;
	181	static const u32 extcfg_size_mask = 0x3<<28;
	182	static const int extcfg_size_shift = 28;
	183	static const int extcfg_sizebus[] = {0x100, 0x80, 0x40, 0x20};
	184	static const u32 extcfg_base_mask[] = {0x7ff8, 0x7ffc, 0x7ffe, 0x7fff};
	185	static const int extcfg_base_lshift = 25;
	186
	187	/*
	188	* do check if amd fam10h already took over
	189	*/
	190	if (!acpi_disabled \|\| pci_mmcfg_config_num \|\| mcp55_checked)
	191	return NULL;
	192
	193	mcp55_checked = true;
	194	for (bus = 0; bus < 256; bus++) {
	195	u64 base;
	196	u32 l, extcfg;
	197	u16 vendor, device;
	198	int start, size_index, end;
	199
	200	raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
	201	vendor = l & 0xffff;
	202	device = (l >> 16) & 0xffff;
	203
	204	if (PCI_VENDOR_ID_NVIDIA != vendor \|\| 0x0369 != device)
	205	continue;
	206
	207	raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
	208	extcfg_regsize, &extcfg);
	209
	210	if (!(extcfg & extcfg_enable_mask))
	211	continue;
	212
	213	if (extend_mmcfg(1) == -1)
	214	continue;
	215
	216	size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
	217	base = extcfg & extcfg_base_mask[size_index];
	218	/* base could > 4G */
	219	base <<= extcfg_base_lshift;
	220	start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
	221	end = start + extcfg_sizebus[size_index] - 1;
	222	fill_one_mmcfg(base, 0, start, end);
	223	mcp55_mmconf_found++;
	224	}
	225
	226	if (!mcp55_mmconf_found)
	227	return NULL;
	228
	229	return "nVidia MCP55";
	230	}
	231
9358c693	232	struct pci_mmcfg_hostbridge_probe {
7fd0da40 YL	233	u32 bus;
7fd0da40 YL	234	u32 devfn;
9358c693 OG	235	u32 vendor;
	236	u32 device;
	237	const char (probe)(void);
	238	};
	239
429d512e	240	static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
7fd0da40 YL	241	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	242	PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
	243	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
	244	PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
	245	{ 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
	246	0x1200, pci_mmcfg_amd_fam10h },
	247	{ 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
	248	0x1200, pci_mmcfg_amd_fam10h },
5546d6f5 ES	249	{ 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
5546d6f5 ES	250	0x0369, pci_mmcfg_nvidia_mcp55 },
9358c693 OG	251	};
9358c693 OG	252
068258bc YL	253	static int __init cmp_mmcfg(const void x1, const void x2)
	254	{
	255	const typeof(pci_mmcfg_config[0]) *m1 = x1;
	256	const typeof(pci_mmcfg_config[0]) *m2 = x2;
	257	int start1, start2;
	258
	259	start1 = m1->start_bus_number;
	260	start2 = m2->start_bus_number;
	261
	262	return start1 - start2;
	263	}
	264
	265	static void __init pci_mmcfg_check_end_bus_number(void)
	266	{
	267	int i;
	268	typeof(pci_mmcfg_config[0]) cfg, cfgx;
	269
	270	/* sort them at first */
	271	sort(pci_mmcfg_config, pci_mmcfg_config_num,
	272	sizeof(pci_mmcfg_config[0]), cmp_mmcfg, NULL);
	273
	274	/* last one*/
	275	if (pci_mmcfg_config_num > 0) {
	276	i = pci_mmcfg_config_num - 1;
	277	cfg = &pci_mmcfg_config[i];
	278	if (cfg->end_bus_number < cfg->start_bus_number)
	279	cfg->end_bus_number = 255;
	280	}
	281
	282	/* don't overlap please */
	283	for (i = 0; i < pci_mmcfg_config_num - 1; i++) {
	284	cfg = &pci_mmcfg_config[i];
	285	cfgx = &pci_mmcfg_config[i+1];
	286
	287	if (cfg->end_bus_number < cfg->start_bus_number)
	288	cfg->end_bus_number = 255;
	289
	290	if (cfg->end_bus_number >= cfgx->start_bus_number)
	291	cfg->end_bus_number = cfgx->start_bus_number - 1;
	292	}
	293	}
	294
9358c693 OG	295	static int __init pci_mmcfg_check_hostbridge(void)
	296	{
	297	u32 l;
7fd0da40	298	u32 bus, devfn;
9358c693 OG	299	u16 vendor, device;
	300	int i;
	301	const char *name;
	302
bb63b421 YL	303	if (!raw_pci_ops)
	304	return 0;
	305
9358c693 OG	306	pci_mmcfg_config_num = 0;
9358c693 OG	307	pci_mmcfg_config = NULL;
9358c693	308
068258bc	309	for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
7fd0da40 YL	310	bus = pci_mmcfg_probes[i].bus;
7fd0da40 YL	311	devfn = pci_mmcfg_probes[i].devfn;
bb63b421	312	raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
7fd0da40 YL	313	vendor = l & 0xffff;
	314	device = (l >> 16) & 0xffff;
	315
068258bc	316	name = NULL;
429d512e OH	317	if (pci_mmcfg_probes[i].vendor == vendor &&
429d512e OH	318	pci_mmcfg_probes[i].device == device)
9358c693 OG	319	name = pci_mmcfg_probes[i].probe();
9358c693 OG	320
068258bc YL	321	if (name)
	322	printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n",
	323	name);
9358c693 OG	324	}
9358c693 OG	325
068258bc YL	326	/* some end_bus_number is crazy, fix it */
	327	pci_mmcfg_check_end_bus_number();
	328
	329	return pci_mmcfg_config_num != 0;
9358c693 OG	330	}
9358c693 OG	331
ebd60cd6	332	static void __init pci_mmcfg_insert_resources(void)
6a0668fc	333	{
068258bc	334	#define PCI_MMCFG_RESOURCE_NAME_LEN 24
6a0668fc OG	335	int i;
	336	struct resource *res;
	337	char *names;
	338	unsigned num_buses;
	339
	340	res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
	341	pci_mmcfg_config_num, GFP_KERNEL);
6a0668fc OG	342	if (!res) {
	343	printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
	344	return;
	345	}
	346
	347	names = (void *)&res[pci_mmcfg_config_num];
	348	for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
429d512e OH	349	struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
429d512e OH	350	num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
6a0668fc	351	res->name = names;
068258bc YL	352	snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN,
	353	"PCI MMCONFIG %u [%02x-%02x]", cfg->pci_segment,
	354	cfg->start_bus_number, cfg->end_bus_number);
	355	res->start = cfg->address + (cfg->start_bus_number << 20);
6a0668fc	356	res->end = res->start + (num_buses << 20) - 1;
ebd60cd6	357	res->flags = IORESOURCE_MEM \| IORESOURCE_BUSY;
6a0668fc OG	358	insert_resource(&iomem_resource, res);
	359	names += PCI_MMCFG_RESOURCE_NAME_LEN;
	360	}
a5ba7971 AD	361
	362	/* Mark that the resources have been inserted. */
	363	pci_mmcfg_resources_inserted = 1;
6a0668fc OG	364	}
6a0668fc OG	365
7752d5cf RH	366	static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
	367	void *data)
	368	{
	369	struct resource *mcfg_res = data;
	370	struct acpi_resource_address64 address;
	371	acpi_status status;
	372
	373	if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
	374	struct acpi_resource_fixed_memory32 *fixmem32 =
	375	&res->data.fixed_memory32;
	376	if (!fixmem32)
	377	return AE_OK;
	378	if ((mcfg_res->start >= fixmem32->address) &&
75e613cd	379	(mcfg_res->end < (fixmem32->address +
7752d5cf RH	380	fixmem32->address_length))) {
	381	mcfg_res->flags = 1;
	382	return AE_CTRL_TERMINATE;
	383	}
	384	}
	385	if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
	386	(res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
	387	return AE_OK;
	388
	389	status = acpi_resource_to_address64(res, &address);
	390	if (ACPI_FAILURE(status) \|\|
	391	(address.address_length <= 0) \|\|
	392	(address.resource_type != ACPI_MEMORY_RANGE))
	393	return AE_OK;
	394
	395	if ((mcfg_res->start >= address.minimum) &&
75e613cd	396	(mcfg_res->end < (address.minimum + address.address_length))) {
7752d5cf RH	397	mcfg_res->flags = 1;
	398	return AE_CTRL_TERMINATE;
	399	}
	400	return AE_OK;
	401	}
	402
	403	static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
	404	void context, void *rv)
	405	{
	406	struct resource *mcfg_res = context;
	407
	408	acpi_walk_resources(handle, METHOD_NAME__CRS,
	409	check_mcfg_resource, context);
	410
	411	if (mcfg_res->flags)
	412	return AE_CTRL_TERMINATE;
	413
	414	return AE_OK;
	415	}
	416
a83fe32f	417	static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
7752d5cf RH	418	{
	419	struct resource mcfg_res;
	420
	421	mcfg_res.start = start;
75e613cd	422	mcfg_res.end = end - 1;
7752d5cf RH	423	mcfg_res.flags = 0;
	424
	425	acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
	426
	427	if (!mcfg_res.flags)
	428	acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
	429	NULL);
	430
	431	return mcfg_res.flags;
	432	}
	433
a83fe32f YL	434	typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
	435
	436	static int __init is_mmconf_reserved(check_reserved_t is_reserved,
	437	u64 addr, u64 size, int i,
	438	typeof(pci_mmcfg_config[0]) *cfg, int with_e820)
	439	{
	440	u64 old_size = size;
	441	int valid = 0;
	442
044cd809	443	while (!is_reserved(addr, addr + size, E820_RESERVED)) {
a83fe32f YL	444	size >>= 1;
	445	if (size < (16UL<<20))
	446	break;
	447	}
	448
	449	if (size >= (16UL<<20) \|\| size == old_size) {
	450	printk(KERN_NOTICE
	451	"PCI: MCFG area at %Lx reserved in %s\n",
	452	addr, with_e820?"E820":"ACPI motherboard resources");
	453	valid = 1;
	454
	455	if (old_size != size) {
	456	/* update end_bus_number */
	457	cfg->end_bus_number = cfg->start_bus_number + ((size>>20) - 1);
	458	printk(KERN_NOTICE "PCI: updated MCFG configuration %d: base %lx "
	459	"segment %hu buses %u - %u\n",
	460	i, (unsigned long)cfg->address, cfg->pci_segment,
	461	(unsigned int)cfg->start_bus_number,
	462	(unsigned int)cfg->end_bus_number);
	463	}
	464	}
	465
	466	return valid;
	467	}
	468
bb63b421	469	static void __init pci_mmcfg_reject_broken(int early)
44de0203	470	{
26054ed0	471	typeof(pci_mmcfg_config[0]) *cfg;
7752d5cf	472	int i;
26054ed0 OH	473
	474	if ((pci_mmcfg_config_num == 0) \|\|
	475	(pci_mmcfg_config == NULL) \|\|
	476	(pci_mmcfg_config[0].address == 0))
	477	return;
	478
7752d5cf	479	for (i = 0; i < pci_mmcfg_config_num; i++) {
05c58b8a	480	int valid = 0;
a83fe32f YL	481	u64 addr, size;
a83fe32f YL	482
7752d5cf	483	cfg = &pci_mmcfg_config[i];
a83fe32f YL	484	addr = cfg->start_bus_number;
	485	addr <<= 20;
	486	addr += cfg->address;
	487	size = cfg->end_bus_number + 1 - cfg->start_bus_number;
	488	size <<= 20;
05c58b8a	489	printk(KERN_NOTICE "PCI: MCFG configuration %d: base %lx "
7752d5cf RH	490	"segment %hu buses %u - %u\n",
	491	i, (unsigned long)cfg->address, cfg->pci_segment,
	492	(unsigned int)cfg->start_bus_number,
	493	(unsigned int)cfg->end_bus_number);
05c58b8a	494
5f0db7a2	495	if (!early && !acpi_disabled)
a83fe32f	496	valid = is_mmconf_reserved(is_acpi_reserved, addr, size, i, cfg, 0);
05c58b8a YL	497
	498	if (valid)
	499	continue;
	500
	501	if (!early)
7752d5cf RH	502	printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
	503	" reserved in ACPI motherboard resources\n",
	504	cfg->address);
a83fe32f	505
05c58b8a	506	/* Don't try to do this check unless configuration
bb63b421	507	type 1 is available. how about type 2 ?*/
a83fe32f YL	508	if (raw_pci_ops)
a83fe32f YL	509	valid = is_mmconf_reserved(e820_all_mapped, addr, size, i, cfg, 1);
05c58b8a YL	510
	511	if (!valid)
	512	goto reject;
44de0203	513	}
7752d5cf	514
26054ed0 OH	515	return;
	516
	517	reject:
ef310237	518	printk(KERN_INFO "PCI: Not using MMCONFIG.\n");
0b64ad71	519	pci_mmcfg_arch_free();
26054ed0 OH	520	kfree(pci_mmcfg_config);
	521	pci_mmcfg_config = NULL;
	522	pci_mmcfg_config_num = 0;
44de0203 OH	523	}
44de0203 OH	524
05c58b8a	525	static int __initdata known_bridge;
7752d5cf	526
c4bf2f37 LB	527	/* The physical address of the MMCONFIG aperture. Set from ACPI tables. */
	528	struct acpi_mcfg_allocation *pci_mmcfg_config;
	529	int pci_mmcfg_config_num;
	530
9a08f7d3 BH	531	static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
9a08f7d3 BH	532	struct acpi_mcfg_allocation *cfg)
c4bf2f37	533	{
9a08f7d3 BH	534	int year;
	535
	536	if (cfg->address < 0xFFFFFFFF)
	537	return 0;
	538
c4bf2f37	539	if (!strcmp(mcfg->header.oem_id, "SGI"))
9a08f7d3	540	return 0;
c4bf2f37	541
9a08f7d3 BH	542	if (mcfg->header.revision >= 1) {
	543	if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
	544	year >= 2010)
	545	return 0;
	546	}
	547
	548	printk(KERN_ERR PREFIX "MCFG region for %04x:%02x-%02x at %#llx "
	549	"is above 4GB, ignored\n", cfg->pci_segment,
	550	cfg->start_bus_number, cfg->end_bus_number, cfg->address);
	551	return -EINVAL;
c4bf2f37 LB	552	}
	553
	554	static int __init pci_parse_mcfg(struct acpi_table_header *header)
	555	{
	556	struct acpi_table_mcfg *mcfg;
	557	unsigned long i;
	558	int config_size;
	559
	560	if (!header)
	561	return -EINVAL;
	562
	563	mcfg = (struct acpi_table_mcfg *)header;
	564
	565	/* how many config structures do we have */
	566	pci_mmcfg_config_num = 0;
	567	i = header->length - sizeof(struct acpi_table_mcfg);
	568	while (i >= sizeof(struct acpi_mcfg_allocation)) {
	569	++pci_mmcfg_config_num;
	570	i -= sizeof(struct acpi_mcfg_allocation);
	571	};
	572	if (pci_mmcfg_config_num == 0) {
	573	printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
	574	return -ENODEV;
	575	}
	576
	577	config_size = pci_mmcfg_config_num * sizeof(*pci_mmcfg_config);
	578	pci_mmcfg_config = kmalloc(config_size, GFP_KERNEL);
	579	if (!pci_mmcfg_config) {
	580	printk(KERN_WARNING PREFIX
	581	"No memory for MCFG config tables\n");
	582	return -ENOMEM;
	583	}
	584
	585	memcpy(pci_mmcfg_config, &mcfg[1], config_size);
	586
c4bf2f37	587	for (i = 0; i < pci_mmcfg_config_num; ++i) {
9a08f7d3	588	if (acpi_mcfg_check_entry(mcfg, &pci_mmcfg_config[i])) {
c4bf2f37 LB	589	kfree(pci_mmcfg_config);
	590	pci_mmcfg_config_num = 0;
	591	return -ENODEV;
	592	}
	593	}
	594
	595	return 0;
	596	}
	597
968cbfad	598	static void __init __pci_mmcfg_init(int early)
b7867394	599	{
7752d5cf	600	/* MMCONFIG disabled */
b7867394 OG	601	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
	602	return;
	603
7752d5cf	604	/* MMCONFIG already enabled */
05c58b8a	605	if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
7752d5cf	606	return;
9358c693	607
05c58b8a YL	608	/* for late to exit */
	609	if (known_bridge)
	610	return;
7752d5cf	611
bb63b421	612	if (early) {
05c58b8a YL	613	if (pci_mmcfg_check_hostbridge())
	614	known_bridge = 1;
	615	}
	616
068258bc	617	if (!known_bridge)
5f0db7a2	618	acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
068258bc YL	619
068258bc YL	620	pci_mmcfg_reject_broken(early);
b7867394 OG	621
	622	if ((pci_mmcfg_config_num == 0) \|\|
	623	(pci_mmcfg_config == NULL) \|\|
	624	(pci_mmcfg_config[0].address == 0))
	625	return;
	626
ebd60cd6	627	if (pci_mmcfg_arch_init())
b7867394	628	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
ebd60cd6	629	else {
a5ba7971 AD	630	/*
	631	* Signal not to attempt to insert mmcfg resources because
	632	* the architecture mmcfg setup could not initialize.
	633	*/
	634	pci_mmcfg_resources_inserted = 1;
b7867394 OG	635	}
b7867394 OG	636	}
a5ba7971	637
bb63b421	638	void __init pci_mmcfg_early_init(void)
05c58b8a	639	{
bb63b421	640	__pci_mmcfg_init(1);
05c58b8a YL	641	}
	642
	643	void __init pci_mmcfg_late_init(void)
	644	{
bb63b421	645	__pci_mmcfg_init(0);
05c58b8a YL	646	}
05c58b8a YL	647
a5ba7971 AD	648	static int __init pci_mmcfg_late_insert_resources(void)
	649	{
	650	/*
	651	* If resources are already inserted or we are not using MMCONFIG,
	652	* don't insert the resources.
	653	*/
	654	if ((pci_mmcfg_resources_inserted == 1) \|\|
	655	(pci_probe & PCI_PROBE_MMCONF) == 0 \|\|
	656	(pci_mmcfg_config_num == 0) \|\|
	657	(pci_mmcfg_config == NULL) \|\|
	658	(pci_mmcfg_config[0].address == 0))
	659	return 1;
	660
	661	/*
	662	* Attempt to insert the mmcfg resources but not with the busy flag
	663	* marked so it won't cause request errors when __request_region is
	664	* called.
	665	*/
ebd60cd6	666	pci_mmcfg_insert_resources();
a5ba7971 AD	667
	668	return 0;
	669	}
	670
	671	/*
	672	* Perform MMCONFIG resource insertion after PCI initialization to allow for
	673	* misprogrammed MCFG tables that state larger sizes but actually conflict
	674	* with other system resources.
	675	*/
	676	late_initcall(pci_mmcfg_late_insert_resources);