[net-next-2.6.git] / arch / x86 / pci / i386.c

/*
 *	Low-Level PCI Access for i386 machines
 *
 * Copyright 1993, 1994 Drew Eckhardt
 *      Visionary Computing
 *      (Unix and Linux consulting and custom programming)
 *      Drew@Colorado.EDU
 *      +1 (303) 786-7975
 *
 * Drew's work was sponsored by:
 *	iX Multiuser Multitasking Magazine
 *	Hannover, Germany
 *	hm@ix.de
 *
 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
 *
 * For more information, please consult the following manuals (look at
 * http://www.pcisig.com/ for how to get them):
 *
 * PCI BIOS Specification
 * PCI Local Bus Specification
 * PCI to PCI Bridge Specification
 * PCI System Design Guide
 *
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/bootmem.h>
#include <linux/acpi.h>

#include <asm/pat.h>
#include <asm/hpet.h>
#include <asm/io_apic.h>
#include <asm/e820.h>

#include "pci.h"

static int
skip_isa_ioresource_align(struct pci_dev *dev) {

	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
	    !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
		return 1;
	return 0;
}

/*
 * We need to avoid collisions with `mirrored' VGA ports
 * and other strange ISA hardware, so we always want the
 * addresses to be allocated in the 0x000-0x0ff region
 * modulo 0x400.
 *
 * Why? Because some silly external IO cards only decode
 * the low 10 bits of the IO address. The 0x00-0xff region
 * is reserved for motherboard devices that decode all 16
 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
 * but we want to try to avoid allocating at 0x2900-0x2bff
 * which might have be mirrored at 0x0100-0x03ff..
 */
void
pcibios_align_resource(void *data, struct resource *res,
			resource_size_t size, resource_size_t align)
{
	struct pci_dev *dev = data;

	if (res->flags & IORESOURCE_IO) {
		resource_size_t start = res->start;

		if (skip_isa_ioresource_align(dev))
			return;
		if (start & 0x300) {
			start = (start + 0x3ff) & ~0x3ff;
			res->start = start;
		}
	}
}
EXPORT_SYMBOL(pcibios_align_resource);

static int check_res_with_valid(struct pci_dev *dev, struct resource *res)
{
	unsigned long base;
	unsigned long size;
	int i;

	base = res->start;
	size = (res->start == 0 && res->end == res->start) ? 0 :
		 (res->end - res->start + 1);

	if (!base || !size)
		return 0;

#ifdef CONFIG_HPET_TIMER
	/* for hpet */
	if (base == hpet_address && (res->flags & IORESOURCE_MEM)) {
		dev_info(&dev->dev, "BAR has HPET at %08lx-%08lx\n",
				 base, base + size - 1);
		return 1;
	}
#endif

#ifdef CONFIG_X86_IO_APIC
	for (i = 0; i < nr_ioapics; i++) {
		unsigned long ioapic_phys = mp_ioapics[i].mp_apicaddr;

		if (base == ioapic_phys && (res->flags & IORESOURCE_MEM)) {
			dev_info(&dev->dev, "BAR has ioapic at %08lx-%08lx\n",
					 base, base + size - 1);
			return 1;
		}
	}
#endif

#ifdef CONFIG_PCI_MMCONFIG
	for (i = 0; i < pci_mmcfg_config_num; i++) {
		unsigned long addr;

		addr = pci_mmcfg_config[i].address;
		if (base == addr && (res->flags & IORESOURCE_MEM)) {
			dev_info(&dev->dev, "BAR has MMCONFIG at %08lx-%08lx\n",
					 base, base + size - 1);
			return 1;
		}
	}
#endif

	return 0;
}

static int check_platform(struct pci_dev *dev, struct resource *res)
{
	struct resource *root = NULL;

	/*
	 * forcibly insert it into the
	 * resource tree
	 */
	if (res->flags & IORESOURCE_MEM)
		root = &iomem_resource;
	else if (res->flags & IORESOURCE_IO)
		root = &ioport_resource;

	if (root && check_res_with_valid(dev, res)) {
		insert_resource(root, res);

		return 1;
	}

	return 0;
}
/*
 *  Handle resources of PCI devices.  If the world were perfect, we could
 *  just allocate all the resource regions and do nothing more.  It isn't.
 *  On the other hand, we cannot just re-allocate all devices, as it would
 *  require us to know lots of host bridge internals.  So we attempt to
 *  keep as much of the original configuration as possible, but tweak it
 *  when it's found to be wrong.
 *
 *  Known BIOS problems we have to work around:
 *	- I/O or memory regions not configured
 *	- regions configured, but not enabled in the command register
 *	- bogus I/O addresses above 64K used
 *	- expansion ROMs left enabled (this may sound harmless, but given
 *	  the fact the PCI specs explicitly allow address decoders to be
 *	  shared between expansion ROMs and other resource regions, it's
 *	  at least dangerous)
 *
 *  Our solution:
 *	(1) Allocate resources for all buses behind PCI-to-PCI bridges.
 *	    This gives us fixed barriers on where we can allocate.
 *	(2) Allocate resources for all enabled devices.  If there is
 *	    a collision, just mark the resource as unallocated. Also
 *	    disable expansion ROMs during this step.
 *	(3) Try to allocate resources for disabled devices.  If the
 *	    resources were assigned correctly, everything goes well,
 *	    if they weren't, they won't disturb allocation of other
 *	    resources.
 *	(4) Assign new addresses to resources which were either
 *	    not configured at all or misconfigured.  If explicitly
 *	    requested by the user, configure expansion ROM address
 *	    as well.
 */

static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
{
	struct pci_bus *bus;
	struct pci_dev *dev;
	int idx;
	struct resource *r, *pr;

	/* Depth-First Search on bus tree */
	list_for_each_entry(bus, bus_list, node) {
		if ((dev = bus->self)) {
			for (idx = PCI_BRIDGE_RESOURCES;
			    idx < PCI_NUM_RESOURCES; idx++) {
				r = &dev->resource[idx];
				if (!r->flags)
					continue;
				pr = pci_find_parent_resource(dev, r);
				if (!r->start || !pr ||
				    request_resource(pr, r) < 0) {
					if (check_platform(dev, r))
						continue;
					dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx);
					/*
					 * Something is wrong with the region.
					 * Invalidate the resource to prevent
					 * child resource allocations in this
					 * range.
					 */
					r->flags = 0;
				}
			}
		}
		pcibios_allocate_bus_resources(&bus->children);
	}
}

static void __init pcibios_allocate_resources(int pass)
{
	struct pci_dev *dev = NULL;
	int idx, disabled;
	u16 command;
	struct resource *r, *pr;

	for_each_pci_dev(dev) {
		pci_read_config_word(dev, PCI_COMMAND, &command);
		for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
			r = &dev->resource[idx];
			if (r->parent)		/* Already allocated */
				continue;
			if (!r->start)		/* Address not assigned at all */
				continue;
			if (r->flags & IORESOURCE_IO)
				disabled = !(command & PCI_COMMAND_IO);
			else
				disabled = !(command & PCI_COMMAND_MEMORY);
			if (pass == disabled) {
				dev_dbg(&dev->dev, "resource %#08llx-%#08llx (f=%lx, d=%d, p=%d)\n",
					(unsigned long long) r->start,
					(unsigned long long) r->end,
					r->flags, disabled, pass);
				pr = pci_find_parent_resource(dev, r);
				if (!pr || request_resource(pr, r) < 0) {
					if (check_platform(dev, r))
						continue;
					dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx);
					/* We'll assign a new address later */
					r->end -= r->start;
					r->start = 0;
				}
			}
		}
		if (!pass) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (r->flags & IORESOURCE_ROM_ENABLE) {
				/* Turn the ROM off, leave the resource region,
				 * but keep it unregistered. */
				u32 reg;
				dev_dbg(&dev->dev, "disabling ROM\n");
				r->flags &= ~IORESOURCE_ROM_ENABLE;
				pci_read_config_dword(dev,
						dev->rom_base_reg, &reg);
				pci_write_config_dword(dev, dev->rom_base_reg,
						reg & ~PCI_ROM_ADDRESS_ENABLE);
			}
		}
	}
}

static int __init pcibios_assign_resources(void)
{
	struct pci_dev *dev = NULL;
	struct resource *r, *pr;

	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
		/*
		 * Try to use BIOS settings for ROMs, otherwise let
		 * pci_assign_unassigned_resources() allocate the new
		 * addresses.
		 */
		for_each_pci_dev(dev) {
			r = &dev->resource[PCI_ROM_RESOURCE];
			if (!r->flags || !r->start)
				continue;
			pr = pci_find_parent_resource(dev, r);
			if (!pr || request_resource(pr, r) < 0) {
				r->end -= r->start;
				r->start = 0;
			}
		}
	}

	pci_assign_unassigned_resources();

	return 0;
}

void __init pcibios_resource_survey(void)
{
	DBG("PCI: Allocating resources\n");
	pcibios_allocate_bus_resources(&pci_root_buses);
	pcibios_allocate_resources(0);
	pcibios_allocate_resources(1);
}

/**
 * called in fs_initcall (one below subsys_initcall),
 * give a chance for motherboard reserve resources
 */
fs_initcall(pcibios_assign_resources);

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain crappy BIOSes forget to set it properly.
 */
unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}

static void pci_unmap_page_range(struct vm_area_struct *vma)
{
	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	free_memtype(addr, addr + vma->vm_end - vma->vm_start);
}

static void pci_track_mmap_page_range(struct vm_area_struct *vma)
{
	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	unsigned long flags = pgprot_val(vma->vm_page_prot)
						& _PAGE_CACHE_MASK;

	reserve_memtype(addr, addr + vma->vm_end - vma->vm_start, flags, NULL);
}

static struct vm_operations_struct pci_mmap_ops = {
	.open  = pci_track_mmap_page_range,
	.close = pci_unmap_page_range,
	.access = generic_access_phys,
};

int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine)
{
	unsigned long prot;
	u64 addr = vma->vm_pgoff << PAGE_SHIFT;
	unsigned long len = vma->vm_end - vma->vm_start;
	unsigned long flags;
	unsigned long new_flags;
	int retval;

	/* I/O space cannot be accessed via normal processor loads and
	 * stores on this platform.
	 */
	if (mmap_state == pci_mmap_io)
		return -EINVAL;

	prot = pgprot_val(vma->vm_page_prot);
	if (pat_enabled && write_combine)
		prot |= _PAGE_CACHE_WC;
	else if (pat_enabled || boot_cpu_data.x86 > 3)
		/*
		 * ioremap() and ioremap_nocache() defaults to UC MINUS for now.
		 * To avoid attribute conflicts, request UC MINUS here
		 * aswell.
		 */
		prot |= _PAGE_CACHE_UC_MINUS;

	vma->vm_page_prot = __pgprot(prot);

	flags = pgprot_val(vma->vm_page_prot) & _PAGE_CACHE_MASK;
	retval = reserve_memtype(addr, addr + len, flags, &new_flags);
	if (retval)
		return retval;

	if (flags != new_flags) {
		/*
		 * Do not fallback to certain memory types with certain
		 * requested type:
		 * - request is uncached, return cannot be write-back
		 * - request is uncached, return cannot be write-combine
		 * - request is write-combine, return cannot be write-back
		 */
		if ((flags == _PAGE_CACHE_UC_MINUS &&
		     (new_flags == _PAGE_CACHE_WB)) ||
		    (flags == _PAGE_CACHE_WC &&
		     new_flags == _PAGE_CACHE_WB)) {
			free_memtype(addr, addr+len);
			return -EINVAL;
		}
		flags = new_flags;
	}

	if (((vma->vm_pgoff < max_low_pfn_mapped) ||
	     (vma->vm_pgoff >= (1UL<<(32 - PAGE_SHIFT)) &&
	      vma->vm_pgoff < max_pfn_mapped)) &&
	    ioremap_change_attr((unsigned long)__va(addr), len, flags)) {
		free_memtype(addr, addr + len);
		return -EINVAL;
	}

	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			       vma->vm_end - vma->vm_start,
			       vma->vm_page_prot))
		return -EAGAIN;

	vma->vm_ops = &pci_mmap_ops;

	return 0;
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Low-Level PCI Access for i386 machines
	3	*
	4	* Copyright 1993, 1994 Drew Eckhardt
	5	* Visionary Computing
	6	* (Unix and Linux consulting and custom programming)
	7	* Drew@Colorado.EDU
	8	* +1 (303) 786-7975
	9	*
	10	* Drew's work was sponsored by:
	11	* iX Multiuser Multitasking Magazine
	12	* Hannover, Germany
	13	* hm@ix.de
	14	*
	15	* Copyright 1997--2000 Martin Mares <mj@ucw.cz>
	16	*
	17	* For more information, please consult the following manuals (look at
	18	* http://www.pcisig.com/ for how to get them):
	19	*
	20	* PCI BIOS Specification
	21	* PCI Local Bus Specification
	22	* PCI to PCI Bridge Specification
	23	* PCI System Design Guide
	24	*
	25	*/
	26
	27	#include <linux/types.h>
	28	#include <linux/kernel.h>
	29	#include <linux/pci.h>
	30	#include <linux/init.h>
	31	#include <linux/ioport.h>
	32	#include <linux/errno.h>
03d72aa1	33	#include <linux/bootmem.h>
58f7c988	34	#include <linux/acpi.h>
03d72aa1	35
03d72aa1	36	#include <asm/pat.h>
58f7c988 YL	37	#include <asm/hpet.h>
	38	#include <asm/io_apic.h>
	39	#include <asm/e820.h>
1da177e4 LT	40
	41	#include "pci.h"
	42
036fff4c GH	43	static int
	44	skip_isa_ioresource_align(struct pci_dev *dev) {
	45
	46	if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
11949255	47	!(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
036fff4c GH	48	return 1;
	49	return 0;
	50	}
	51
1da177e4 LT	52	/*
	53	* We need to avoid collisions with `mirrored' VGA ports
	54	* and other strange ISA hardware, so we always want the
	55	* addresses to be allocated in the 0x000-0x0ff region
	56	* modulo 0x400.
	57	*
	58	* Why? Because some silly external IO cards only decode
	59	* the low 10 bits of the IO address. The 0x00-0xff region
	60	* is reserved for motherboard devices that decode all 16
	61	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
	62	* but we want to try to avoid allocating at 0x2900-0x2bff
	63	* which might have be mirrored at 0x0100-0x03ff..
	64	*/
	65	void
	66	pcibios_align_resource(void data, struct resource res,
e31dd6e4	67	resource_size_t size, resource_size_t align)
1da177e4	68	{
036fff4c GH	69	struct pci_dev *dev = data;
036fff4c GH	70
1da177e4	71	if (res->flags & IORESOURCE_IO) {
e31dd6e4	72	resource_size_t start = res->start;
1da177e4	73
036fff4c GH	74	if (skip_isa_ioresource_align(dev))
036fff4c GH	75	return;
1da177e4 LT	76	if (start & 0x300) {
	77	start = (start + 0x3ff) & ~0x3ff;
	78	res->start = start;
	79	}
	80	}
	81	}
6c00a61e	82	EXPORT_SYMBOL(pcibios_align_resource);
1da177e4	83
58f7c988 YL	84	static int check_res_with_valid(struct pci_dev dev, struct resource res)
	85	{
	86	unsigned long base;
	87	unsigned long size;
	88	int i;
	89
	90	base = res->start;
	91	size = (res->start == 0 && res->end == res->start) ? 0 :
	92	(res->end - res->start + 1);
	93
	94	if (!base \|\| !size)
	95	return 0;
	96
	97	#ifdef CONFIG_HPET_TIMER
	98	/* for hpet */
	99	if (base == hpet_address && (res->flags & IORESOURCE_MEM)) {
	100	dev_info(&dev->dev, "BAR has HPET at %08lx-%08lx\n",
	101	base, base + size - 1);
	102	return 1;
	103	}
	104	#endif
	105
	106	#ifdef CONFIG_X86_IO_APIC
	107	for (i = 0; i < nr_ioapics; i++) {
	108	unsigned long ioapic_phys = mp_ioapics[i].mp_apicaddr;
	109
	110	if (base == ioapic_phys && (res->flags & IORESOURCE_MEM)) {
	111	dev_info(&dev->dev, "BAR has ioapic at %08lx-%08lx\n",
	112	base, base + size - 1);
	113	return 1;
	114	}
	115	}
	116	#endif
	117
	118	#ifdef CONFIG_PCI_MMCONFIG
	119	for (i = 0; i < pci_mmcfg_config_num; i++) {
	120	unsigned long addr;
	121
	122	addr = pci_mmcfg_config[i].address;
	123	if (base == addr && (res->flags & IORESOURCE_MEM)) {
	124	dev_info(&dev->dev, "BAR has MMCONFIG at %08lx-%08lx\n",
	125	base, base + size - 1);
	126	return 1;
	127	}
	128	}
	129	#endif
	130
	131	return 0;
	132	}
	133
	134	static int check_platform(struct pci_dev dev, struct resource res)
	135	{
	136	struct resource *root = NULL;
	137
	138	/*
	139	* forcibly insert it into the
	140	* resource tree
	141	*/
	142	if (res->flags & IORESOURCE_MEM)
	143	root = &iomem_resource;
	144	else if (res->flags & IORESOURCE_IO)
	145	root = &ioport_resource;
	146
	147	if (root && check_res_with_valid(dev, res)) {
148	insert_resource(root, res);
149
150	return 1;
151	}
152
153	return 0;
154	}
1da177e4 LT	155	/*
	156	* Handle resources of PCI devices. If the world were perfect, we could
	157	* just allocate all the resource regions and do nothing more. It isn't.
	158	* On the other hand, we cannot just re-allocate all devices, as it would
	159	* require us to know lots of host bridge internals. So we attempt to
	160	* keep as much of the original configuration as possible, but tweak it
	161	* when it's found to be wrong.
	162	*
	163	* Known BIOS problems we have to work around:
	164	* - I/O or memory regions not configured
	165	* - regions configured, but not enabled in the command register
	166	* - bogus I/O addresses above 64K used
	167	* - expansion ROMs left enabled (this may sound harmless, but given
	168	* the fact the PCI specs explicitly allow address decoders to be
	169	* shared between expansion ROMs and other resource regions, it's
	170	* at least dangerous)
	171	*
	172	* Our solution:
	173	* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
	174	* This gives us fixed barriers on where we can allocate.
	175	* (2) Allocate resources for all enabled devices. If there is
	176	* a collision, just mark the resource as unallocated. Also
	177	* disable expansion ROMs during this step.
	178	* (3) Try to allocate resources for disabled devices. If the
	179	* resources were assigned correctly, everything goes well,
	180	* if they weren't, they won't disturb allocation of other
	181	* resources.
	182	* (4) Assign new addresses to resources which were either
	183	* not configured at all or misconfigured. If explicitly
	184	* requested by the user, configure expansion ROM address
	185	* as well.
	186	*/
	187
	188	static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
	189	{
	190	struct pci_bus *bus;
	191	struct pci_dev *dev;
	192	int idx;
	193	struct resource r, pr;
	194
	195	/* Depth-First Search on bus tree */
	196	list_for_each_entry(bus, bus_list, node) {
	197	if ((dev = bus->self)) {
7edab2f0 RD	198	for (idx = PCI_BRIDGE_RESOURCES;
7edab2f0 RD	199	idx < PCI_NUM_RESOURCES; idx++) {
1da177e4	200	r = &dev->resource[idx];
299de034	201	if (!r->flags)
1da177e4 LT	202	continue;
1da177e4 LT	203	pr = pci_find_parent_resource(dev, r);
7edab2f0 RD	204	if (!r->start \|\| !pr \|\|
7edab2f0 RD	205	request_resource(pr, r) < 0) {
58f7c988 YL	206	if (check_platform(dev, r))
58f7c988 YL	207	continue;
011fec74	208	dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx);
7edab2f0 RD	209	/*
	210	* Something is wrong with the region.
	211	* Invalidate the resource to prevent
	212	* child resource allocations in this
	213	* range.
	214	*/
299de034 IK	215	r->flags = 0;
299de034 IK	216	}
1da177e4 LT	217	}
	218	}
	219	pcibios_allocate_bus_resources(&bus->children);
	220	}
	221	}
	222
	223	static void __init pcibios_allocate_resources(int pass)
	224	{
	225	struct pci_dev *dev = NULL;
	226	int idx, disabled;
	227	u16 command;
	228	struct resource r, pr;
	229
	230	for_each_pci_dev(dev) {
	231	pci_read_config_word(dev, PCI_COMMAND, &command);
7edab2f0	232	for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
1da177e4 LT	233	r = &dev->resource[idx];
	234	if (r->parent) /* Already allocated */
	235	continue;
	236	if (!r->start) /* Address not assigned at all */
	237	continue;
	238	if (r->flags & IORESOURCE_IO)
	239	disabled = !(command & PCI_COMMAND_IO);
	240	else
	241	disabled = !(command & PCI_COMMAND_MEMORY);
	242	if (pass == disabled) {
011fec74	243	dev_dbg(&dev->dev, "resource %#08llx-%#08llx (f=%lx, d=%d, p=%d)\n",
12c0b20f BH	244	(unsigned long long) r->start,
	245	(unsigned long long) r->end,
	246	r->flags, disabled, pass);
1da177e4 LT	247	pr = pci_find_parent_resource(dev, r);
1da177e4 LT	248	if (!pr \|\| request_resource(pr, r) < 0) {
58f7c988 YL	249	if (check_platform(dev, r))
58f7c988 YL	250	continue;
011fec74	251	dev_err(&dev->dev, "BAR %d: can't allocate resource\n", idx);
1da177e4 LT	252	/* We'll assign a new address later */
	253	r->end -= r->start;
	254	r->start = 0;
	255	}
	256	}
	257	}
	258	if (!pass) {
	259	r = &dev->resource[PCI_ROM_RESOURCE];
	260	if (r->flags & IORESOURCE_ROM_ENABLE) {
7edab2f0 RD	261	/* Turn the ROM off, leave the resource region,
7edab2f0 RD	262	* but keep it unregistered. */
1da177e4	263	u32 reg;
12c0b20f	264	dev_dbg(&dev->dev, "disabling ROM\n");
1da177e4	265	r->flags &= ~IORESOURCE_ROM_ENABLE;
7edab2f0 RD	266	pci_read_config_dword(dev,
	267	dev->rom_base_reg, &reg);
	268	pci_write_config_dword(dev, dev->rom_base_reg,
	269	reg & ~PCI_ROM_ADDRESS_ENABLE);
1da177e4 LT	270	}
	271	}
	272	}
	273	}
	274
	275	static int __init pcibios_assign_resources(void)
	276	{
	277	struct pci_dev *dev = NULL;
81d4af13	278	struct resource r, pr;
1da177e4	279
81d4af13	280	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
7edab2f0 RD	281	/*
	282	* Try to use BIOS settings for ROMs, otherwise let
	283	* pci_assign_unassigned_resources() allocate the new
	284	* addresses.
	285	*/
81d4af13	286	for_each_pci_dev(dev) {
1da177e4	287	r = &dev->resource[PCI_ROM_RESOURCE];
81d4af13 IK	288	if (!r->flags \|\| !r->start)
	289	continue;
	290	pr = pci_find_parent_resource(dev, r);
	291	if (!pr \|\| request_resource(pr, r) < 0) {
	292	r->end -= r->start;
	293	r->start = 0;
	294	}
1da177e4 LT	295	}
1da177e4 LT	296	}
81d4af13 IK	297
	298	pci_assign_unassigned_resources();
	299
1da177e4 LT	300	return 0;
	301	}
	302
	303	void __init pcibios_resource_survey(void)
	304	{
	305	DBG("PCI: Allocating resources\n");
	306	pcibios_allocate_bus_resources(&pci_root_buses);
	307	pcibios_allocate_resources(0);
	308	pcibios_allocate_resources(1);
	309	}
	310
	311	/**
	312	* called in fs_initcall (one below subsys_initcall),
	313	* give a chance for motherboard reserve resources
	314	*/
	315	fs_initcall(pcibios_assign_resources);
	316
1da177e4 LT	317	/*
	318	* If we set up a device for bus mastering, we need to check the latency
	319	* timer as certain crappy BIOSes forget to set it properly.
	320	*/
	321	unsigned int pcibios_max_latency = 255;
	322
	323	void pcibios_set_master(struct pci_dev *dev)
	324	{
	325	u8 lat;
	326	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	327	if (lat < 16)
	328	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	329	else if (lat > pcibios_max_latency)
	330	lat = pcibios_max_latency;
	331	else
	332	return;
12c0b20f	333	dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
1da177e4 LT	334	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
	335	}
	336
03d72aa1	337	static void pci_unmap_page_range(struct vm_area_struct *vma)
	338	{
	339	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	340	free_memtype(addr, addr + vma->vm_end - vma->vm_start);
	341	}
	342
	343	static void pci_track_mmap_page_range(struct vm_area_struct *vma)
	344	{
	345	u64 addr = (u64)vma->vm_pgoff << PAGE_SHIFT;
	346	unsigned long flags = pgprot_val(vma->vm_page_prot)
	347	& _PAGE_CACHE_MASK;
	348
	349	reserve_memtype(addr, addr + vma->vm_end - vma->vm_start, flags, NULL);
	350	}
	351
	352	static struct vm_operations_struct pci_mmap_ops = {
	353	.open = pci_track_mmap_page_range,
	354	.close = pci_unmap_page_range,
7ae8ed50	355	.access = generic_access_phys,
03d72aa1	356	};
03d72aa1	357
1da177e4 LT	358	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
	359	enum pci_mmap_state mmap_state, int write_combine)
	360	{
	361	unsigned long prot;
03d72aa1	362	u64 addr = vma->vm_pgoff << PAGE_SHIFT;
	363	unsigned long len = vma->vm_end - vma->vm_start;
	364	unsigned long flags;
	365	unsigned long new_flags;
dee7cbb2	366	int retval;
1da177e4 LT	367
	368	/* I/O space cannot be accessed via normal processor loads and
	369	* stores on this platform.
	370	*/
	371	if (mmap_state == pci_mmap_io)
	372	return -EINVAL;
	373
1da177e4	374	prot = pgprot_val(vma->vm_page_prot);
499f8f84	375	if (pat_enabled && write_combine)
03d72aa1	376	prot \|= _PAGE_CACHE_WC;
499f8f84	377	else if (pat_enabled \|\| boot_cpu_data.x86 > 3)
de33c442 SS	378	/*
	379	* ioremap() and ioremap_nocache() defaults to UC MINUS for now.
	380	* To avoid attribute conflicts, request UC MINUS here
	381	* aswell.
	382	*/
	383	prot \|= _PAGE_CACHE_UC_MINUS;
03d72aa1	384
1da177e4 LT	385	vma->vm_page_prot = __pgprot(prot);
1da177e4 LT	386
03d72aa1	387	flags = pgprot_val(vma->vm_page_prot) & _PAGE_CACHE_MASK;
dee7cbb2 VP	388	retval = reserve_memtype(addr, addr + len, flags, &new_flags);
	389	if (retval)
	390	return retval;
	391
	392	if (flags != new_flags) {
03d72aa1	393	/*
	394	* Do not fallback to certain memory types with certain
	395	* requested type:
	396	* - request is uncached, return cannot be write-back
	397	* - request is uncached, return cannot be write-combine
	398	* - request is write-combine, return cannot be write-back
	399	*/
de33c442 SS	400	if ((flags == _PAGE_CACHE_UC_MINUS &&
de33c442 SS	401	(new_flags == _PAGE_CACHE_WB)) \|\|
03d72aa1	402	(flags == _PAGE_CACHE_WC &&
	403	new_flags == _PAGE_CACHE_WB)) {
	404	free_memtype(addr, addr+len);
	405	return -EINVAL;
	406	}
	407	flags = new_flags;
	408	}
	409
965194c1	410	if (((vma->vm_pgoff < max_low_pfn_mapped) \|\|
f361a450	411	(vma->vm_pgoff >= (1UL<<(32 - PAGE_SHIFT)) &&
965194c1	412	vma->vm_pgoff < max_pfn_mapped)) &&
03d72aa1	413	ioremap_change_attr((unsigned long)__va(addr), len, flags)) {
	414	free_memtype(addr, addr + len);
	415	return -EINVAL;
	416	}
	417
346d3882 MT	418	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
	419	vma->vm_end - vma->vm_start,
	420	vma->vm_page_prot))
1da177e4 LT	421	return -EAGAIN;
1da177e4 LT	422
03d72aa1	423	vma->vm_ops = &pci_mmap_ops;
03d72aa1	424
1da177e4 LT	425	return 0;
1da177e4 LT	426	}