[net-next-2.6.git] / arch / x86 / pci / amd_bus.c

#include <linux/init.h>
#include <linux/pci.h>
#include <linux/topology.h>
#include <linux/cpu.h>
#include <asm/pci_x86.h>

#ifdef CONFIG_X86_64
#include <asm/pci-direct.h>
#endif

#include "bus_numa.h"

/*
 * This discovers the pcibus <-> node mapping on AMD K8.
 * also get peer root bus resource for io,mmio
 */

#ifdef CONFIG_X86_64

#define RANGE_NUM 16

struct res_range {
	size_t start;
	size_t end;
};

static void __init update_range(struct res_range *range, size_t start,
				size_t end)
{
	int i;
	int j;

	for (j = 0; j < RANGE_NUM; j++) {
		if (!range[j].end)
			continue;

		if (start <= range[j].start && end >= range[j].end) {
			range[j].start = 0;
			range[j].end = 0;
			continue;
		}

		if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
			range[j].start = end + 1;
			continue;
		}


		if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
			range[j].end = start - 1;
			continue;
		}

		if (start > range[j].start && end < range[j].end) {
			/* find the new spare */
			for (i = 0; i < RANGE_NUM; i++) {
				if (range[i].end == 0)
					break;
			}
			if (i < RANGE_NUM) {
				range[i].end = range[j].end;
				range[i].start = end + 1;
			} else {
				printk(KERN_ERR "run of slot in ranges\n");
			}
			range[j].end = start - 1;
			continue;
		}
	}
}

struct pci_hostbridge_probe {
	u32 bus;
	u32 slot;
	u32 vendor;
	u32 device;
};

static struct pci_hostbridge_probe pci_probes[] __initdata = {
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
};

static u64 __initdata fam10h_mmconf_start;
static u64 __initdata fam10h_mmconf_end;
static void __init get_pci_mmcfg_amd_fam10h_range(void)
{
	u32 address;
	u64 base, msr;
	unsigned segn_busn_bits;

	/* assume all cpus from fam10h have mmconf */
        if (boot_cpu_data.x86 < 0x10)
		return;

	address = MSR_FAM10H_MMIO_CONF_BASE;
	rdmsrl(address, msr);

	/* mmconfig is not enable */
	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
		return;

	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);

	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
			 FAM10H_MMIO_CONF_BUSRANGE_MASK;

	fam10h_mmconf_start = base;
	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
}

/**
 * early_fill_mp_bus_to_node()
 * called before pcibios_scan_root and pci_scan_bus
 * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
 * Registers found in the K8 northbridge
 */
static int __init early_fill_mp_bus_info(void)
{
	int i;
	int j;
	unsigned bus;
	unsigned slot;
	int node;
	int link;
	int def_node;
	int def_link;
	struct pci_root_info *info;
	u32 reg;
	struct resource *res;
	size_t start;
	size_t end;
	struct res_range range[RANGE_NUM];
	u64 val;
	u32 address;

	if (!early_pci_allowed())
		return -1;

	found_all_numa_early = 0;
	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
		u32 id;
		u16 device;
		u16 vendor;

		bus = pci_probes[i].bus;
		slot = pci_probes[i].slot;
		id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);

		vendor = id & 0xffff;
		device = (id>>16) & 0xffff;
		if (pci_probes[i].vendor == vendor &&
		    pci_probes[i].device == device) {
			found_all_numa_early = 1;
			break;
		}
	}

	if (!found_all_numa_early)
		return 0;

	pci_root_num = 0;
	for (i = 0; i < 4; i++) {
		int min_bus;
		int max_bus;
		reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));

		/* Check if that register is enabled for bus range */
		if ((reg & 7) != 3)
			continue;

		min_bus = (reg >> 16) & 0xff;
		max_bus = (reg >> 24) & 0xff;
		node = (reg >> 4) & 0x07;
#ifdef CONFIG_NUMA
		for (j = min_bus; j <= max_bus; j++)
			set_mp_bus_to_node(j, node);
#endif
		link = (reg >> 8) & 0x03;

		info = &pci_root_info[pci_root_num];
		info->bus_min = min_bus;
		info->bus_max = max_bus;
		info->node = node;
		info->link = link;
		sprintf(info->name, "PCI Bus #%02x", min_bus);
		pci_root_num++;
	}

	/* get the default node and link for left over res */
	reg = read_pci_config(bus, slot, 0, 0x60);
	def_node = (reg >> 8) & 0x07;
	reg = read_pci_config(bus, slot, 0, 0x64);
	def_link = (reg >> 8) & 0x03;

	memset(range, 0, sizeof(range));
	range[0].end = 0xffff;
	/* io port resource */
	for (i = 0; i < 4; i++) {
		reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xfff000;
		reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xfff000) | 0xfff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];
		printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
		       node, link, (u64)start, (u64)end);

		/* kernel only handle 16 bit only */
		if (end > 0xffff)
			end = 0xffff;
		update_res(info, start, end, IORESOURCE_IO, 1);
		update_range(range, start, end);
	}
	/* add left over io port range to def node/link, [0, 0xffff] */
	/* find the position */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];
		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_IO, 1);
		}
	}

	memset(range, 0, sizeof(range));
	/* 0xfd00000000-0xffffffffff for HT */
	range[0].end = (0xfdULL<<32) - 1;

	/* need to take out [0, TOM) for RAM*/
	address = MSR_K8_TOP_MEM1;
	rdmsrl(address, val);
	end = (val & 0xffffff800000ULL);
	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
	if (end < (1ULL<<32))
		update_range(range, 0, end - 1);

	/* get mmconfig */
	get_pci_mmcfg_amd_fam10h_range();
	/* need to take out mmconf range */
	if (fam10h_mmconf_end) {
		printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
		update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
	}

	/* mmio resource */
	for (i = 0; i < 8; i++) {
		reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
		if (!(reg & 3))
			continue;

		start = reg & 0xffffff00; /* 39:16 on 31:8*/
		start <<= 8;
		reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
		node = reg & 0x07;
		link = (reg >> 4) & 0x03;
		end = (reg & 0xffffff00);
		end <<= 8;
		end |= 0xffff;

		/* find the position */
		for (j = 0; j < pci_root_num; j++) {
			info = &pci_root_info[j];
			if (info->node == node && info->link == link)
				break;
		}
		if (j == pci_root_num)
			continue; /* not found */

		info = &pci_root_info[j];

		printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
		       node, link, (u64)start, (u64)end);
		/*
		 * some sick allocation would have range overlap with fam10h
		 * mmconf range, so need to update start and end.
		 */
		if (fam10h_mmconf_end) {
			int changed = 0;
			u64 endx = 0;
			if (start >= fam10h_mmconf_start &&
			    start <= fam10h_mmconf_end) {
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}

			if (end >= fam10h_mmconf_start &&
			    end <= fam10h_mmconf_end) {
				end = fam10h_mmconf_start - 1;
				changed = 1;
			}

			if (start < fam10h_mmconf_start &&
			    end > fam10h_mmconf_end) {
				/* we got a hole */
				endx = fam10h_mmconf_start - 1;
				update_res(info, start, endx, IORESOURCE_MEM, 0);
				update_range(range, start, endx);
				printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
				start = fam10h_mmconf_end + 1;
				changed = 1;
			}
			if (changed) {
				if (start <= end) {
					printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
				} else {
					printk(KERN_CONT "%s\n", endx?"":" ==> none");
					continue;
				}
			}
		}

		update_res(info, start, end, IORESOURCE_MEM, 1);
		update_range(range, start, end);
		printk(KERN_CONT "\n");
	}

	/* need to take out [4G, TOM2) for RAM*/
	/* SYS_CFG */
	address = MSR_K8_SYSCFG;
	rdmsrl(address, val);
	/* TOP_MEM2 is enabled? */
	if (val & (1<<21)) {
		/* TOP_MEM2 */
		address = MSR_K8_TOP_MEM2;
		rdmsrl(address, val);
		end = (val & 0xffffff800000ULL);
		printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
		update_range(range, 1ULL<<32, end - 1);
	}

	/*
	 * add left over mmio range to def node/link ?
	 * that is tricky, just record range in from start_min to 4G
	 */
	for (j = 0; j < pci_root_num; j++) {
		info = &pci_root_info[j];
		if (info->node == def_node && info->link == def_link)
			break;
	}
	if (j < pci_root_num) {
		info = &pci_root_info[j];

		for (i = 0; i < RANGE_NUM; i++) {
			if (!range[i].end)
				continue;

			update_res(info, range[i].start, range[i].end,
				   IORESOURCE_MEM, 1);
		}
	}

	for (i = 0; i < pci_root_num; i++) {
		int res_num;
		int busnum;

		info = &pci_root_info[i];
		res_num = info->res_num;
		busnum = info->bus_min;
		printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
		       info->bus_min, info->bus_max, info->node, info->link);
		for (j = 0; j < res_num; j++) {
			res = &info->res[j];
			printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
			       busnum, j,
			       (res->flags & IORESOURCE_IO)?"io port":"mmio",
			       res->start, res->end);
		}
	}

	return 0;
}

#else  /* !CONFIG_X86_64 */

static int __init early_fill_mp_bus_info(void) { return 0; }

#endif /* !CONFIG_X86_64 */

/* common 32/64 bit code */

#define ENABLE_CF8_EXT_CFG      (1ULL << 46)

static void enable_pci_io_ecs(void *unused)
{
	u64 reg;
	rdmsrl(MSR_AMD64_NB_CFG, reg);
	if (!(reg & ENABLE_CF8_EXT_CFG)) {
		reg |= ENABLE_CF8_EXT_CFG;
		wrmsrl(MSR_AMD64_NB_CFG, reg);
	}
}

static int __cpuinit amd_cpu_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	int cpu = (long)hcpu;
	switch (action) {
	case CPU_ONLINE:
	case CPU_ONLINE_FROZEN:
		smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
		break;
	default:
		break;
	}
	return NOTIFY_OK;
}

static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	.notifier_call	= amd_cpu_notify,
};

static int __init pci_io_ecs_init(void)
{
	int cpu;

	/* assume all cpus from fam10h have IO ECS */
        if (boot_cpu_data.x86 < 0x10)
		return 0;

	register_cpu_notifier(&amd_cpu_notifier);
	for_each_online_cpu(cpu)
		amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
			       (void *)(long)cpu);
	pci_probe |= PCI_HAS_IO_ECS;

	return 0;
}

static int __init amd_postcore_init(void)
{
	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
		return 0;

	early_fill_mp_bus_info();
	pci_io_ecs_init();

	return 0;
}

postcore_initcall(amd_postcore_init);
Commit	Line	Data
1da177e4 LT	1	#include <linux/init.h>
1da177e4 LT	2	#include <linux/pci.h>
d199a048	3	#include <linux/topology.h>
91ede005	4	#include <linux/cpu.h>
82487711	5	#include <asm/pci_x86.h>
3a27dd1c RR	6
3a27dd1c RR	7	#ifdef CONFIG_X86_64
871d5f8d	8	#include <asm/pci-direct.h>
d199a048	9	#endif
1da177e4	10
99935a7a YL	11	#include "bus_numa.h"
99935a7a YL	12
1da177e4 LT	13	/*
1da177e4 LT	14	* This discovers the pcibus <-> node mapping on AMD K8.
30a18d6c	15	* also get peer root bus resource for io,mmio
1da177e4 LT	16	*/
1da177e4 LT	17
d199a048	18	#ifdef CONFIG_X86_64
871d5f8d	19
30a18d6c YL	20	#define RANGE_NUM 16
	21
	22	struct res_range {
	23	size_t start;
	24	size_t end;
	25	};
	26
	27	static void __init update_range(struct res_range *range, size_t start,
	28	size_t end)
	29	{
	30	int i;
	31	int j;
	32
	33	for (j = 0; j < RANGE_NUM; j++) {
	34	if (!range[j].end)
	35	continue;
e8ee6f0a YL	36
e8ee6f0a YL	37	if (start <= range[j].start && end >= range[j].end) {
30a18d6c YL	38	range[j].start = 0;
30a18d6c YL	39	range[j].end = 0;
e8ee6f0a YL	40	continue;
	41	}
	42
	43	if (start <= range[j].start && end < range[j].end && range[j].start < end + 1) {
	44	range[j].start = end + 1;
	45	continue;
	46	}
	47
	48
	49	if (start > range[j].start && end >= range[j].end && range[j].end > start - 1) {
30a18d6c	50	range[j].end = start - 1;
e8ee6f0a YL	51	continue;
	52	}
	53
	54	if (start > range[j].start && end < range[j].end) {
30a18d6c YL	55	/* find the new spare */
	56	for (i = 0; i < RANGE_NUM; i++) {
	57	if (range[i].end == 0)
	58	break;
	59	}
	60	if (i < RANGE_NUM) {
	61	range[i].end = range[j].end;
	62	range[i].start = end + 1;
	63	} else {
	64	printk(KERN_ERR "run of slot in ranges\n");
	65	}
	66	range[j].end = start - 1;
e8ee6f0a	67	continue;
30a18d6c YL	68	}
	69	}
	70	}
	71
30a18d6c YL	72	struct pci_hostbridge_probe {
	73	u32 bus;
	74	u32 slot;
	75	u32 vendor;
	76	u32 device;
	77	};
	78
	79	static struct pci_hostbridge_probe pci_probes[] __initdata = {
	80	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1100 },
	81	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
	82	{ 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
	83	{ 0, 0x18, PCI_VENDOR_ID_AMD, 0x1300 },
	84	};
	85
6e184f29 YL	86	static u64 __initdata fam10h_mmconf_start;
	87	static u64 __initdata fam10h_mmconf_end;
	88	static void __init get_pci_mmcfg_amd_fam10h_range(void)
	89	{
	90	u32 address;
	91	u64 base, msr;
	92	unsigned segn_busn_bits;
	93
	94	/* assume all cpus from fam10h have mmconf */
	95	if (boot_cpu_data.x86 < 0x10)
	96	return;
	97
	98	address = MSR_FAM10H_MMIO_CONF_BASE;
	99	rdmsrl(address, msr);
	100
	101	/* mmconfig is not enable */
	102	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
	103	return;
	104
	105	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
	106
	107	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
	108	FAM10H_MMIO_CONF_BUSRANGE_MASK;
	109
	110	fam10h_mmconf_start = base;
	111	fam10h_mmconf_end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
	112	}
	113
1da177e4	114	/**
871d5f8d YL	115	* early_fill_mp_bus_to_node()
871d5f8d YL	116	* called before pcibios_scan_root and pci_scan_bus
1da177e4 LT	117	* fills the mp_bus_to_cpumask array based according to the LDT Bus Number
	118	* Registers found in the K8 northbridge
	119	*/
30a18d6c	120	static int __init early_fill_mp_bus_info(void)
1da177e4	121	{
30a18d6c YL	122	int i;
	123	int j;
	124	unsigned bus;
871d5f8d	125	unsigned slot;
35ddd068	126	int node;
30a18d6c YL	127	int link;
	128	int def_node;
	129	int def_link;
	130	struct pci_root_info *info;
	131	u32 reg;
	132	struct resource *res;
	133	size_t start;
	134	size_t end;
	135	struct res_range range[RANGE_NUM];
	136	u64 val;
	137	u32 address;
1da177e4	138
871d5f8d YL	139	if (!early_pci_allowed())
	140	return -1;
	141
99935a7a	142	found_all_numa_early = 0;
30a18d6c YL	143	for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
	144	u32 id;
	145	u16 device;
	146	u16 vendor;
35ddd068	147
30a18d6c YL	148	bus = pci_probes[i].bus;
	149	slot = pci_probes[i].slot;
	150	id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
35ddd068	151
30a18d6c YL	152	vendor = id & 0xffff;
	153	device = (id>>16) & 0xffff;
	154	if (pci_probes[i].vendor == vendor &&
	155	pci_probes[i].device == device) {
99935a7a	156	found_all_numa_early = 1;
30a18d6c YL	157	break;
	158	}
	159	}
	160
99935a7a	161	if (!found_all_numa_early)
30a18d6c	162	return 0;
35ddd068	163
30a18d6c YL	164	pci_root_num = 0;
	165	for (i = 0; i < 4; i++) {
	166	int min_bus;
	167	int max_bus;
	168	reg = read_pci_config(bus, slot, 1, 0xe0 + (i << 2));
35ddd068 YL	169
35ddd068 YL	170	/* Check if that register is enabled for bus range */
30a18d6c	171	if ((reg & 7) != 3)
35ddd068 YL	172	continue;
35ddd068 YL	173
30a18d6c YL	174	min_bus = (reg >> 16) & 0xff;
	175	max_bus = (reg >> 24) & 0xff;
	176	node = (reg >> 4) & 0x07;
	177	#ifdef CONFIG_NUMA
35ddd068	178	for (j = min_bus; j <= max_bus; j++)
2547089c	179	set_mp_bus_to_node(j, node);
30a18d6c YL	180	#endif
	181	link = (reg >> 8) & 0x03;
	182
	183	info = &pci_root_info[pci_root_num];
	184	info->bus_min = min_bus;
	185	info->bus_max = max_bus;
	186	info->node = node;
	187	info->link = link;
	188	sprintf(info->name, "PCI Bus #%02x", min_bus);
	189	pci_root_num++;
1da177e4 LT	190	}
1da177e4 LT	191
30a18d6c YL	192	/* get the default node and link for left over res */
	193	reg = read_pci_config(bus, slot, 0, 0x60);
	194	def_node = (reg >> 8) & 0x07;
	195	reg = read_pci_config(bus, slot, 0, 0x64);
	196	def_link = (reg >> 8) & 0x03;
	197
	198	memset(range, 0, sizeof(range));
	199	range[0].end = 0xffff;
	200	/* io port resource */
	201	for (i = 0; i < 4; i++) {
	202	reg = read_pci_config(bus, slot, 1, 0xc0 + (i << 3));
	203	if (!(reg & 3))
	204	continue;
	205
	206	start = reg & 0xfff000;
	207	reg = read_pci_config(bus, slot, 1, 0xc4 + (i << 3));
	208	node = reg & 0x07;
	209	link = (reg >> 4) & 0x03;
	210	end = (reg & 0xfff000) \| 0xfff;
	211
	212	/* find the position */
	213	for (j = 0; j < pci_root_num; j++) {
	214	info = &pci_root_info[j];
	215	if (info->node == node && info->link == link)
	216	break;
	217	}
	218	if (j == pci_root_num)
	219	continue; /* not found */
	220
	221	info = &pci_root_info[j];
6e184f29 YL	222	printk(KERN_DEBUG "node %d link %d: io port [%llx, %llx]\n",
6e184f29 YL	223	node, link, (u64)start, (u64)end);
e8ee6f0a YL	224
	225	/* kernel only handle 16 bit only */
	226	if (end > 0xffff)
	227	end = 0xffff;
	228	update_res(info, start, end, IORESOURCE_IO, 1);
30a18d6c YL	229	update_range(range, start, end);
	230	}
	231	/* add left over io port range to def node/link, [0, 0xffff] */
	232	/* find the position */
	233	for (j = 0; j < pci_root_num; j++) {
	234	info = &pci_root_info[j];
	235	if (info->node == def_node && info->link == def_link)
	236	break;
	237	}
	238	if (j < pci_root_num) {
	239	info = &pci_root_info[j];
	240	for (i = 0; i < RANGE_NUM; i++) {
	241	if (!range[i].end)
	242	continue;
	243
	244	update_res(info, range[i].start, range[i].end,
	245	IORESOURCE_IO, 1);
	246	}
	247	}
	248
	249	memset(range, 0, sizeof(range));
	250	/* 0xfd00000000-0xffffffffff for HT */
6e184f29	251	range[0].end = (0xfdULL<<32) - 1;
30a18d6c YL	252
	253	/* need to take out [0, TOM) for RAM*/
	254	address = MSR_K8_TOP_MEM1;
	255	rdmsrl(address, val);
8004dd96	256	end = (val & 0xffffff800000ULL);
30a18d6c YL	257	printk(KERN_INFO "TOM: %016lx aka %ldM\n", end, end>>20);
	258	if (end < (1ULL<<32))
	259	update_range(range, 0, end - 1);
	260
6e184f29 YL	261	/* get mmconfig */
	262	get_pci_mmcfg_amd_fam10h_range();
	263	/* need to take out mmconf range */
	264	if (fam10h_mmconf_end) {
	265	printk(KERN_DEBUG "Fam 10h mmconf [%llx, %llx]\n", fam10h_mmconf_start, fam10h_mmconf_end);
	266	update_range(range, fam10h_mmconf_start, fam10h_mmconf_end);
	267	}
	268
30a18d6c YL	269	/* mmio resource */
	270	for (i = 0; i < 8; i++) {
	271	reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
	272	if (!(reg & 3))
	273	continue;
	274
	275	start = reg & 0xffffff00; /* 39:16 on 31:8*/
	276	start <<= 8;
	277	reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
	278	node = reg & 0x07;
	279	link = (reg >> 4) & 0x03;
	280	end = (reg & 0xffffff00);
	281	end <<= 8;
	282	end \|= 0xffff;
	283
	284	/* find the position */
	285	for (j = 0; j < pci_root_num; j++) {
	286	info = &pci_root_info[j];
	287	if (info->node == node && info->link == link)
	288	break;
	289	}
	290	if (j == pci_root_num)
	291	continue; /* not found */
	292
	293	info = &pci_root_info[j];
6e184f29 YL	294
	295	printk(KERN_DEBUG "node %d link %d: mmio [%llx, %llx]",
	296	node, link, (u64)start, (u64)end);
	297	/*
	298	* some sick allocation would have range overlap with fam10h
	299	* mmconf range, so need to update start and end.
	300	*/
	301	if (fam10h_mmconf_end) {
	302	int changed = 0;
	303	u64 endx = 0;
	304	if (start >= fam10h_mmconf_start &&
	305	start <= fam10h_mmconf_end) {
	306	start = fam10h_mmconf_end + 1;
	307	changed = 1;
	308	}
	309
	310	if (end >= fam10h_mmconf_start &&
	311	end <= fam10h_mmconf_end) {
	312	end = fam10h_mmconf_start - 1;
	313	changed = 1;
	314	}
	315
	316	if (start < fam10h_mmconf_start &&
	317	end > fam10h_mmconf_end) {
	318	/* we got a hole */
	319	endx = fam10h_mmconf_start - 1;
	320	update_res(info, start, endx, IORESOURCE_MEM, 0);
	321	update_range(range, start, endx);
	322	printk(KERN_CONT " ==> [%llx, %llx]", (u64)start, endx);
	323	start = fam10h_mmconf_end + 1;
	324	changed = 1;
	325	}
	326	if (changed) {
	327	if (start <= end) {
	328	printk(KERN_CONT " %s [%llx, %llx]", endx?"and":"==>", (u64)start, (u64)end);
	329	} else {
	330	printk(KERN_CONT "%s\n", endx?"":" ==> none");
	331	continue;
	332	}
	333	}
	334	}
	335
e8ee6f0a	336	update_res(info, start, end, IORESOURCE_MEM, 1);
30a18d6c	337	update_range(range, start, end);
6e184f29	338	printk(KERN_CONT "\n");
30a18d6c YL	339	}
	340
	341	/* need to take out [4G, TOM2) for RAM*/
	342	/* SYS_CFG */
	343	address = MSR_K8_SYSCFG;
	344	rdmsrl(address, val);
	345	/* TOP_MEM2 is enabled? */
	346	if (val & (1<<21)) {
	347	/* TOP_MEM2 */
	348	address = MSR_K8_TOP_MEM2;
	349	rdmsrl(address, val);
8004dd96	350	end = (val & 0xffffff800000ULL);
30a18d6c YL	351	printk(KERN_INFO "TOM2: %016lx aka %ldM\n", end, end>>20);
	352	update_range(range, 1ULL<<32, end - 1);
	353	}
	354
	355	/*
	356	* add left over mmio range to def node/link ?
	357	* that is tricky, just record range in from start_min to 4G
	358	*/
	359	for (j = 0; j < pci_root_num; j++) {
	360	info = &pci_root_info[j];
	361	if (info->node == def_node && info->link == def_link)
	362	break;
	363	}
	364	if (j < pci_root_num) {
	365	info = &pci_root_info[j];
	366
	367	for (i = 0; i < RANGE_NUM; i++) {
	368	if (!range[i].end)
	369	continue;
	370
	371	update_res(info, range[i].start, range[i].end,
	372	IORESOURCE_MEM, 1);
	373	}
	374	}
	375
30a18d6c YL	376	for (i = 0; i < pci_root_num; i++) {
	377	int res_num;
	378	int busnum;
	379
	380	info = &pci_root_info[i];
	381	res_num = info->res_num;
	382	busnum = info->bus_min;
99935a7a	383	printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
30a18d6c YL	384	info->bus_min, info->bus_max, info->node, info->link);
	385	for (j = 0; j < res_num; j++) {
	386	res = &info->res[j];
	387	printk(KERN_DEBUG "bus: %02x index %x %s: [%llx, %llx]\n",
	388	busnum, j,
	389	(res->flags & IORESOURCE_IO)?"io port":"mmio",
	390	res->start, res->end);
	391	}
	392	}
	393
1da177e4 LT	394	return 0;
	395	}
	396
9b4e27b5	397	#else /* !CONFIG_X86_64 */
3a27dd1c	398
9b4e27b5 RR	399	static int __init early_fill_mp_bus_info(void) { return 0; }
	400
	401	#endif /* !CONFIG_X86_64 */
3a27dd1c RR	402
	403	/* common 32/64 bit code */
	404
	405	#define ENABLE_CF8_EXT_CFG (1ULL << 46)
	406
91ede005	407	static void enable_pci_io_ecs(void *unused)
3a27dd1c RR	408	{
	409	u64 reg;
	410	rdmsrl(MSR_AMD64_NB_CFG, reg);
	411	if (!(reg & ENABLE_CF8_EXT_CFG)) {
	412	reg \|= ENABLE_CF8_EXT_CFG;
	413	wrmsrl(MSR_AMD64_NB_CFG, reg);
	414	}
	415	}
	416
91ede005 RR	417	static int __cpuinit amd_cpu_notify(struct notifier_block *self,
91ede005 RR	418	unsigned long action, void *hcpu)
3a27dd1c	419	{
91ede005	420	int cpu = (long)hcpu;
ed21763e	421	switch (action) {
91ede005 RR	422	case CPU_ONLINE:
	423	case CPU_ONLINE_FROZEN:
	424	smp_call_function_single(cpu, enable_pci_io_ecs, NULL, 0);
	425	break;
	426	default:
	427	break;
	428	}
	429	return NOTIFY_OK;
	430	}
	431
	432	static struct notifier_block __cpuinitdata amd_cpu_notifier = {
	433	.notifier_call = amd_cpu_notify,
	434	};
	435
	436	static int __init pci_io_ecs_init(void)
	437	{
	438	int cpu;
	439
3a27dd1c RR	440	/* assume all cpus from fam10h have IO ECS */
	441	if (boot_cpu_data.x86 < 0x10)
	442	return 0;
91ede005 RR	443
	444	register_cpu_notifier(&amd_cpu_notifier);
	445	for_each_online_cpu(cpu)
	446	amd_cpu_notify(&amd_cpu_notifier, (unsigned long)CPU_ONLINE,
	447	(void *)(long)cpu);
3a27dd1c	448	pci_probe \|= PCI_HAS_IO_ECS;
91ede005	449
3a27dd1c RR	450	return 0;
	451	}
	452
9b4e27b5 RR	453	static int __init amd_postcore_init(void)
	454	{
	455	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
	456	return 0;
	457
	458	early_fill_mp_bus_info();
91ede005	459	pci_io_ecs_init();
9b4e27b5 RR	460
	461	return 0;
	462	}
	463
	464	postcore_initcall(amd_postcore_init);