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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
9f4c815c | 14 | |
950f9d95 | 15 | #include <asm/e820.h> |
1da177e4 LT |
16 | #include <asm/processor.h> |
17 | #include <asm/tlbflush.h> | |
f8af095d | 18 | #include <asm/sections.h> |
93dbda7c | 19 | #include <asm/setup.h> |
9f4c815c IM |
20 | #include <asm/uaccess.h> |
21 | #include <asm/pgalloc.h> | |
c31c7d48 | 22 | #include <asm/proto.h> |
1219333d | 23 | #include <asm/pat.h> |
1da177e4 | 24 | |
9df84993 IM |
25 | /* |
26 | * The current flushing context - we pass it instead of 5 arguments: | |
27 | */ | |
72e458df | 28 | struct cpa_data { |
d75586ad | 29 | unsigned long *vaddr; |
72e458df TG |
30 | pgprot_t mask_set; |
31 | pgprot_t mask_clr; | |
65e074df | 32 | int numpages; |
d75586ad | 33 | int flags; |
c31c7d48 | 34 | unsigned long pfn; |
c9caa02c | 35 | unsigned force_split : 1; |
d75586ad | 36 | int curpage; |
9ae28475 | 37 | struct page **pages; |
72e458df TG |
38 | }; |
39 | ||
ad5ca55f SS |
40 | /* |
41 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
42 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
43 | * entries change the page attribute in parallel to some other cpu | |
44 | * splitting a large page entry along with changing the attribute. | |
45 | */ | |
46 | static DEFINE_SPINLOCK(cpa_lock); | |
47 | ||
d75586ad SL |
48 | #define CPA_FLUSHTLB 1 |
49 | #define CPA_ARRAY 2 | |
9ae28475 | 50 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 51 | |
65280e61 | 52 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
53 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
54 | ||
65280e61 | 55 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 56 | { |
ce0c0e50 | 57 | unsigned long flags; |
65280e61 | 58 | |
ce0c0e50 AK |
59 | /* Protect against CPA */ |
60 | spin_lock_irqsave(&pgd_lock, flags); | |
61 | direct_pages_count[level] += pages; | |
62 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
63 | } |
64 | ||
65 | static void split_page_count(int level) | |
66 | { | |
67 | direct_pages_count[level]--; | |
68 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
69 | } | |
70 | ||
e1759c21 | 71 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 72 | { |
b9c3bfc2 | 73 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
74 | direct_pages_count[PG_LEVEL_4K] << 2); |
75 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 76 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
77 | direct_pages_count[PG_LEVEL_2M] << 11); |
78 | #else | |
b9c3bfc2 | 79 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
80 | direct_pages_count[PG_LEVEL_2M] << 12); |
81 | #endif | |
65280e61 | 82 | #ifdef CONFIG_X86_64 |
a06de630 | 83 | if (direct_gbpages) |
b9c3bfc2 | 84 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 85 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
86 | #endif |
87 | } | |
65280e61 TG |
88 | #else |
89 | static inline void split_page_count(int level) { } | |
90 | #endif | |
ce0c0e50 | 91 | |
c31c7d48 TG |
92 | #ifdef CONFIG_X86_64 |
93 | ||
94 | static inline unsigned long highmap_start_pfn(void) | |
95 | { | |
96 | return __pa(_text) >> PAGE_SHIFT; | |
97 | } | |
98 | ||
99 | static inline unsigned long highmap_end_pfn(void) | |
100 | { | |
93dbda7c | 101 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
102 | } |
103 | ||
104 | #endif | |
105 | ||
92cb54a3 IM |
106 | #ifdef CONFIG_DEBUG_PAGEALLOC |
107 | # define debug_pagealloc 1 | |
108 | #else | |
109 | # define debug_pagealloc 0 | |
110 | #endif | |
111 | ||
ed724be6 AV |
112 | static inline int |
113 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 114 | { |
ed724be6 AV |
115 | return addr >= start && addr < end; |
116 | } | |
117 | ||
d7c8f21a TG |
118 | /* |
119 | * Flushing functions | |
120 | */ | |
cd8ddf1a | 121 | |
cd8ddf1a TG |
122 | /** |
123 | * clflush_cache_range - flush a cache range with clflush | |
124 | * @addr: virtual start address | |
125 | * @size: number of bytes to flush | |
126 | * | |
127 | * clflush is an unordered instruction which needs fencing with mfence | |
128 | * to avoid ordering issues. | |
129 | */ | |
4c61afcd | 130 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 131 | { |
4c61afcd | 132 | void *vend = vaddr + size - 1; |
d7c8f21a | 133 | |
cd8ddf1a | 134 | mb(); |
4c61afcd IM |
135 | |
136 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
137 | clflush(vaddr); | |
138 | /* | |
139 | * Flush any possible final partial cacheline: | |
140 | */ | |
141 | clflush(vend); | |
142 | ||
cd8ddf1a | 143 | mb(); |
d7c8f21a TG |
144 | } |
145 | ||
af1e6844 | 146 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 147 | { |
6bb8383b AK |
148 | unsigned long cache = (unsigned long)arg; |
149 | ||
d7c8f21a TG |
150 | /* |
151 | * Flush all to work around Errata in early athlons regarding | |
152 | * large page flushing. | |
153 | */ | |
154 | __flush_tlb_all(); | |
155 | ||
6bb8383b | 156 | if (cache && boot_cpu_data.x86_model >= 4) |
d7c8f21a TG |
157 | wbinvd(); |
158 | } | |
159 | ||
6bb8383b | 160 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
161 | { |
162 | BUG_ON(irqs_disabled()); | |
163 | ||
15c8b6c1 | 164 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
165 | } |
166 | ||
57a6a46a TG |
167 | static void __cpa_flush_range(void *arg) |
168 | { | |
57a6a46a TG |
169 | /* |
170 | * We could optimize that further and do individual per page | |
171 | * tlb invalidates for a low number of pages. Caveat: we must | |
172 | * flush the high aliases on 64bit as well. | |
173 | */ | |
174 | __flush_tlb_all(); | |
57a6a46a TG |
175 | } |
176 | ||
6bb8383b | 177 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 178 | { |
4c61afcd IM |
179 | unsigned int i, level; |
180 | unsigned long addr; | |
181 | ||
57a6a46a | 182 | BUG_ON(irqs_disabled()); |
4c61afcd | 183 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 184 | |
15c8b6c1 | 185 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 186 | |
6bb8383b AK |
187 | if (!cache) |
188 | return; | |
189 | ||
3b233e52 TG |
190 | /* |
191 | * We only need to flush on one CPU, | |
192 | * clflush is a MESI-coherent instruction that | |
193 | * will cause all other CPUs to flush the same | |
194 | * cachelines: | |
195 | */ | |
4c61afcd IM |
196 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
197 | pte_t *pte = lookup_address(addr, &level); | |
198 | ||
199 | /* | |
200 | * Only flush present addresses: | |
201 | */ | |
7bfb72e8 | 202 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
203 | clflush_cache_range((void *) addr, PAGE_SIZE); |
204 | } | |
57a6a46a TG |
205 | } |
206 | ||
9ae28475 | 207 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
208 | int in_flags, struct page **pages) | |
d75586ad SL |
209 | { |
210 | unsigned int i, level; | |
d75586ad SL |
211 | |
212 | BUG_ON(irqs_disabled()); | |
213 | ||
214 | on_each_cpu(__cpa_flush_range, NULL, 1); | |
215 | ||
216 | if (!cache) | |
217 | return; | |
218 | ||
219 | /* 4M threshold */ | |
220 | if (numpages >= 1024) { | |
221 | if (boot_cpu_data.x86_model >= 4) | |
222 | wbinvd(); | |
223 | return; | |
224 | } | |
225 | /* | |
226 | * We only need to flush on one CPU, | |
227 | * clflush is a MESI-coherent instruction that | |
228 | * will cause all other CPUs to flush the same | |
229 | * cachelines: | |
230 | */ | |
9ae28475 | 231 | for (i = 0; i < numpages; i++) { |
232 | unsigned long addr; | |
233 | pte_t *pte; | |
234 | ||
235 | if (in_flags & CPA_PAGES_ARRAY) | |
236 | addr = (unsigned long)page_address(pages[i]); | |
237 | else | |
238 | addr = start[i]; | |
239 | ||
240 | pte = lookup_address(addr, &level); | |
d75586ad SL |
241 | |
242 | /* | |
243 | * Only flush present addresses: | |
244 | */ | |
245 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 246 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
247 | } |
248 | } | |
249 | ||
ed724be6 AV |
250 | /* |
251 | * Certain areas of memory on x86 require very specific protection flags, | |
252 | * for example the BIOS area or kernel text. Callers don't always get this | |
253 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
254 | * checks and fixes these known static required protection bits. | |
255 | */ | |
c31c7d48 TG |
256 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
257 | unsigned long pfn) | |
ed724be6 AV |
258 | { |
259 | pgprot_t forbidden = __pgprot(0); | |
260 | ||
687c4825 | 261 | /* |
ed724be6 AV |
262 | * The BIOS area between 640k and 1Mb needs to be executable for |
263 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 264 | */ |
c31c7d48 | 265 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
266 | pgprot_val(forbidden) |= _PAGE_NX; |
267 | ||
268 | /* | |
269 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
270 | * Does not cover __inittext since that is gone later on. On |
271 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
272 | */ |
273 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
274 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 275 | |
cc0f21bb | 276 | /* |
c31c7d48 TG |
277 | * The .rodata section needs to be read-only. Using the pfn |
278 | * catches all aliases. | |
cc0f21bb | 279 | */ |
c31c7d48 TG |
280 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
281 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 282 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 AV |
283 | |
284 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); | |
687c4825 IM |
285 | |
286 | return prot; | |
287 | } | |
288 | ||
9a14aefc TG |
289 | /* |
290 | * Lookup the page table entry for a virtual address. Return a pointer | |
291 | * to the entry and the level of the mapping. | |
292 | * | |
293 | * Note: We return pud and pmd either when the entry is marked large | |
294 | * or when the present bit is not set. Otherwise we would return a | |
295 | * pointer to a nonexisting mapping. | |
296 | */ | |
da7bfc50 | 297 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 298 | { |
1da177e4 LT |
299 | pgd_t *pgd = pgd_offset_k(address); |
300 | pud_t *pud; | |
301 | pmd_t *pmd; | |
9f4c815c | 302 | |
30551bb3 TG |
303 | *level = PG_LEVEL_NONE; |
304 | ||
1da177e4 LT |
305 | if (pgd_none(*pgd)) |
306 | return NULL; | |
9df84993 | 307 | |
1da177e4 LT |
308 | pud = pud_offset(pgd, address); |
309 | if (pud_none(*pud)) | |
310 | return NULL; | |
c2f71ee2 AK |
311 | |
312 | *level = PG_LEVEL_1G; | |
313 | if (pud_large(*pud) || !pud_present(*pud)) | |
314 | return (pte_t *)pud; | |
315 | ||
1da177e4 LT |
316 | pmd = pmd_offset(pud, address); |
317 | if (pmd_none(*pmd)) | |
318 | return NULL; | |
30551bb3 TG |
319 | |
320 | *level = PG_LEVEL_2M; | |
9a14aefc | 321 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 322 | return (pte_t *)pmd; |
1da177e4 | 323 | |
30551bb3 | 324 | *level = PG_LEVEL_4K; |
9df84993 | 325 | |
9f4c815c IM |
326 | return pte_offset_kernel(pmd, address); |
327 | } | |
75bb8835 | 328 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 329 | |
9df84993 IM |
330 | /* |
331 | * Set the new pmd in all the pgds we know about: | |
332 | */ | |
9a3dc780 | 333 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 334 | { |
9f4c815c IM |
335 | /* change init_mm */ |
336 | set_pte_atomic(kpte, pte); | |
44af6c41 | 337 | #ifdef CONFIG_X86_32 |
e4b71dcf | 338 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
339 | struct page *page; |
340 | ||
e3ed910d | 341 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
342 | pgd_t *pgd; |
343 | pud_t *pud; | |
344 | pmd_t *pmd; | |
345 | ||
346 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
347 | pud = pud_offset(pgd, address); | |
348 | pmd = pmd_offset(pud, address); | |
349 | set_pte_atomic((pte_t *)pmd, pte); | |
350 | } | |
1da177e4 | 351 | } |
44af6c41 | 352 | #endif |
1da177e4 LT |
353 | } |
354 | ||
9df84993 IM |
355 | static int |
356 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
357 | struct cpa_data *cpa) | |
65e074df | 358 | { |
c31c7d48 | 359 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
360 | pte_t new_pte, old_pte, *tmp; |
361 | pgprot_t old_prot, new_prot; | |
fac84939 | 362 | int i, do_split = 1; |
da7bfc50 | 363 | unsigned int level; |
65e074df | 364 | |
c9caa02c AK |
365 | if (cpa->force_split) |
366 | return 1; | |
367 | ||
65e074df TG |
368 | spin_lock_irqsave(&pgd_lock, flags); |
369 | /* | |
370 | * Check for races, another CPU might have split this page | |
371 | * up already: | |
372 | */ | |
373 | tmp = lookup_address(address, &level); | |
374 | if (tmp != kpte) | |
375 | goto out_unlock; | |
376 | ||
377 | switch (level) { | |
378 | case PG_LEVEL_2M: | |
31422c51 AK |
379 | psize = PMD_PAGE_SIZE; |
380 | pmask = PMD_PAGE_MASK; | |
65e074df | 381 | break; |
f07333fd | 382 | #ifdef CONFIG_X86_64 |
65e074df | 383 | case PG_LEVEL_1G: |
5d3c8b21 AK |
384 | psize = PUD_PAGE_SIZE; |
385 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
386 | break; |
387 | #endif | |
65e074df | 388 | default: |
beaff633 | 389 | do_split = -EINVAL; |
65e074df TG |
390 | goto out_unlock; |
391 | } | |
392 | ||
393 | /* | |
394 | * Calculate the number of pages, which fit into this large | |
395 | * page starting at address: | |
396 | */ | |
397 | nextpage_addr = (address + psize) & pmask; | |
398 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
399 | if (numpages < cpa->numpages) |
400 | cpa->numpages = numpages; | |
65e074df TG |
401 | |
402 | /* | |
403 | * We are safe now. Check whether the new pgprot is the same: | |
404 | */ | |
405 | old_pte = *kpte; | |
406 | old_prot = new_prot = pte_pgprot(old_pte); | |
407 | ||
408 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
409 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
410 | |
411 | /* | |
412 | * old_pte points to the large page base address. So we need | |
413 | * to add the offset of the virtual address: | |
414 | */ | |
415 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
416 | cpa->pfn = pfn; | |
417 | ||
418 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 419 | |
fac84939 TG |
420 | /* |
421 | * We need to check the full range, whether | |
422 | * static_protection() requires a different pgprot for one of | |
423 | * the pages in the range we try to preserve: | |
424 | */ | |
425 | addr = address + PAGE_SIZE; | |
c31c7d48 | 426 | pfn++; |
9b5cf48b | 427 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 428 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
429 | |
430 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
431 | goto out_unlock; | |
432 | } | |
433 | ||
65e074df TG |
434 | /* |
435 | * If there are no changes, return. maxpages has been updated | |
436 | * above: | |
437 | */ | |
438 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 439 | do_split = 0; |
65e074df TG |
440 | goto out_unlock; |
441 | } | |
442 | ||
443 | /* | |
444 | * We need to change the attributes. Check, whether we can | |
445 | * change the large page in one go. We request a split, when | |
446 | * the address is not aligned and the number of pages is | |
447 | * smaller than the number of pages in the large page. Note | |
448 | * that we limited the number of possible pages already to | |
449 | * the number of pages in the large page. | |
450 | */ | |
9b5cf48b | 451 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
452 | /* |
453 | * The address is aligned and the number of pages | |
454 | * covers the full page. | |
455 | */ | |
456 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
457 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 458 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 459 | do_split = 0; |
65e074df TG |
460 | } |
461 | ||
462 | out_unlock: | |
463 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 464 | |
beaff633 | 465 | return do_split; |
65e074df TG |
466 | } |
467 | ||
7afe15b9 | 468 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 469 | { |
7b610eec | 470 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 471 | unsigned int i, level; |
bb5c2dbd | 472 | pte_t *pbase, *tmp; |
9df84993 | 473 | pgprot_t ref_prot; |
ad5ca55f SS |
474 | struct page *base; |
475 | ||
476 | if (!debug_pagealloc) | |
477 | spin_unlock(&cpa_lock); | |
478 | base = alloc_pages(GFP_KERNEL, 0); | |
479 | if (!debug_pagealloc) | |
480 | spin_lock(&cpa_lock); | |
8311eb84 SS |
481 | if (!base) |
482 | return -ENOMEM; | |
bb5c2dbd | 483 | |
eb5b5f02 | 484 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
485 | /* |
486 | * Check for races, another CPU might have split this page | |
487 | * up for us already: | |
488 | */ | |
489 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 490 | if (tmp != kpte) |
bb5c2dbd IM |
491 | goto out_unlock; |
492 | ||
bb5c2dbd | 493 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 494 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 495 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
496 | /* |
497 | * If we ever want to utilize the PAT bit, we need to | |
498 | * update this function to make sure it's converted from | |
499 | * bit 12 to bit 7 when we cross from the 2MB level to | |
500 | * the 4K level: | |
501 | */ | |
502 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 503 | |
f07333fd AK |
504 | #ifdef CONFIG_X86_64 |
505 | if (level == PG_LEVEL_1G) { | |
506 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
507 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
508 | } |
509 | #endif | |
510 | ||
63c1dcf4 TG |
511 | /* |
512 | * Get the target pfn from the original entry: | |
513 | */ | |
514 | pfn = pte_pfn(*kpte); | |
f07333fd | 515 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 516 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 517 | |
ce0c0e50 | 518 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
519 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
520 | split_page_count(level); | |
521 | ||
522 | #ifdef CONFIG_X86_64 | |
523 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
524 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
525 | split_page_count(level); | |
f361a450 | 526 | #endif |
ce0c0e50 | 527 | |
bb5c2dbd | 528 | /* |
07a66d7c | 529 | * Install the new, split up pagetable. |
4c881ca1 | 530 | * |
07a66d7c IM |
531 | * We use the standard kernel pagetable protections for the new |
532 | * pagetable protections, the actual ptes set above control the | |
533 | * primary protection behavior: | |
bb5c2dbd | 534 | */ |
07a66d7c | 535 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
536 | |
537 | /* | |
538 | * Intel Atom errata AAH41 workaround. | |
539 | * | |
540 | * The real fix should be in hw or in a microcode update, but | |
541 | * we also probabilistically try to reduce the window of having | |
542 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
543 | * going on. | |
544 | */ | |
545 | __flush_tlb_all(); | |
546 | ||
bb5c2dbd IM |
547 | base = NULL; |
548 | ||
549 | out_unlock: | |
eb5b5f02 TG |
550 | /* |
551 | * If we dropped out via the lookup_address check under | |
552 | * pgd_lock then stick the page back into the pool: | |
553 | */ | |
8311eb84 SS |
554 | if (base) |
555 | __free_page(base); | |
9a3dc780 | 556 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 557 | |
bb5c2dbd IM |
558 | return 0; |
559 | } | |
560 | ||
a1e46212 SS |
561 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
562 | int primary) | |
563 | { | |
564 | /* | |
565 | * Ignore all non primary paths. | |
566 | */ | |
567 | if (!primary) | |
568 | return 0; | |
569 | ||
570 | /* | |
571 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
572 | * to have holes. | |
573 | * Also set numpages to '1' indicating that we processed cpa req for | |
574 | * one virtual address page and its pfn. TBD: numpages can be set based | |
575 | * on the initial value and the level returned by lookup_address(). | |
576 | */ | |
577 | if (within(vaddr, PAGE_OFFSET, | |
578 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
579 | cpa->numpages = 1; | |
580 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
581 | return 0; | |
582 | } else { | |
583 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
584 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
585 | *cpa->vaddr); | |
586 | ||
587 | return -EFAULT; | |
588 | } | |
589 | } | |
590 | ||
c31c7d48 | 591 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 592 | { |
d75586ad | 593 | unsigned long address; |
da7bfc50 HH |
594 | int do_split, err; |
595 | unsigned int level; | |
c31c7d48 | 596 | pte_t *kpte, old_pte; |
1da177e4 | 597 | |
9ae28475 | 598 | if (cpa->flags & CPA_PAGES_ARRAY) |
599 | address = (unsigned long)page_address(cpa->pages[cpa->curpage]); | |
600 | else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
601 | address = cpa->vaddr[cpa->curpage]; |
602 | else | |
603 | address = *cpa->vaddr; | |
97f99fed | 604 | repeat: |
f0646e43 | 605 | kpte = lookup_address(address, &level); |
1da177e4 | 606 | if (!kpte) |
a1e46212 | 607 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
608 | |
609 | old_pte = *kpte; | |
a1e46212 SS |
610 | if (!pte_val(old_pte)) |
611 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 612 | |
30551bb3 | 613 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 614 | pte_t new_pte; |
626c2c9d | 615 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 616 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 617 | |
72e458df TG |
618 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
619 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 620 | |
c31c7d48 | 621 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 622 | |
626c2c9d AV |
623 | /* |
624 | * We need to keep the pfn from the existing PTE, | |
625 | * after all we're only going to change it's attributes | |
626 | * not the memory it points to | |
627 | */ | |
c31c7d48 TG |
628 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
629 | cpa->pfn = pfn; | |
f4ae5da0 TG |
630 | /* |
631 | * Do we really change anything ? | |
632 | */ | |
633 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
634 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 635 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 636 | } |
9b5cf48b | 637 | cpa->numpages = 1; |
65e074df | 638 | return 0; |
1da177e4 | 639 | } |
65e074df TG |
640 | |
641 | /* | |
642 | * Check, whether we can keep the large page intact | |
643 | * and just change the pte: | |
644 | */ | |
beaff633 | 645 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
646 | /* |
647 | * When the range fits into the existing large page, | |
9b5cf48b | 648 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
649 | * try_large_page: |
650 | */ | |
87f7f8fe IM |
651 | if (do_split <= 0) |
652 | return do_split; | |
65e074df TG |
653 | |
654 | /* | |
655 | * We have to split the large page: | |
656 | */ | |
87f7f8fe IM |
657 | err = split_large_page(kpte, address); |
658 | if (!err) { | |
ad5ca55f SS |
659 | /* |
660 | * Do a global flush tlb after splitting the large page | |
661 | * and before we do the actual change page attribute in the PTE. | |
662 | * | |
663 | * With out this, we violate the TLB application note, that says | |
664 | * "The TLBs may contain both ordinary and large-page | |
665 | * translations for a 4-KByte range of linear addresses. This | |
666 | * may occur if software modifies the paging structures so that | |
667 | * the page size used for the address range changes. If the two | |
668 | * translations differ with respect to page frame or attributes | |
669 | * (e.g., permissions), processor behavior is undefined and may | |
670 | * be implementation-specific." | |
671 | * | |
672 | * We do this global tlb flush inside the cpa_lock, so that we | |
673 | * don't allow any other cpu, with stale tlb entries change the | |
674 | * page attribute in parallel, that also falls into the | |
675 | * just split large page entry. | |
676 | */ | |
677 | flush_tlb_all(); | |
87f7f8fe IM |
678 | goto repeat; |
679 | } | |
beaff633 | 680 | |
87f7f8fe | 681 | return err; |
9f4c815c | 682 | } |
1da177e4 | 683 | |
c31c7d48 TG |
684 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
685 | ||
686 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 687 | { |
c31c7d48 | 688 | struct cpa_data alias_cpa; |
f34b439f | 689 | int ret = 0; |
d75586ad | 690 | unsigned long temp_cpa_vaddr, vaddr; |
44af6c41 | 691 | |
965194c1 | 692 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 693 | return 0; |
626c2c9d | 694 | |
f361a450 | 695 | #ifdef CONFIG_X86_64 |
965194c1 | 696 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
697 | return 0; |
698 | #endif | |
f34b439f TG |
699 | /* |
700 | * No need to redo, when the primary call touched the direct | |
701 | * mapping already: | |
702 | */ | |
9ae28475 | 703 | if (cpa->flags & CPA_PAGES_ARRAY) |
704 | vaddr = (unsigned long)page_address(cpa->pages[cpa->curpage]); | |
705 | else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
706 | vaddr = cpa->vaddr[cpa->curpage]; |
707 | else | |
708 | vaddr = *cpa->vaddr; | |
709 | ||
710 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 711 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 712 | |
f34b439f | 713 | alias_cpa = *cpa; |
d75586ad SL |
714 | temp_cpa_vaddr = (unsigned long) __va(cpa->pfn << PAGE_SHIFT); |
715 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
9ae28475 | 716 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 717 | |
f34b439f TG |
718 | |
719 | ret = __change_page_attr_set_clr(&alias_cpa, 0); | |
720 | } | |
44af6c41 | 721 | |
44af6c41 | 722 | #ifdef CONFIG_X86_64 |
c31c7d48 TG |
723 | if (ret) |
724 | return ret; | |
f34b439f TG |
725 | /* |
726 | * No need to redo, when the primary call touched the high | |
727 | * mapping already: | |
728 | */ | |
93dbda7c | 729 | if (within(vaddr, (unsigned long) _text, _brk_end)) |
f34b439f TG |
730 | return 0; |
731 | ||
488fd995 | 732 | /* |
0879750f TG |
733 | * If the physical address is inside the kernel map, we need |
734 | * to touch the high mapped kernel as well: | |
488fd995 | 735 | */ |
c31c7d48 TG |
736 | if (!within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) |
737 | return 0; | |
0879750f | 738 | |
c31c7d48 | 739 | alias_cpa = *cpa; |
d75586ad SL |
740 | temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + __START_KERNEL_map - phys_base; |
741 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
9ae28475 | 742 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
c31c7d48 TG |
743 | |
744 | /* | |
745 | * The high mapping range is imprecise, so ignore the return value. | |
746 | */ | |
747 | __change_page_attr_set_clr(&alias_cpa, 0); | |
488fd995 | 748 | #endif |
c31c7d48 | 749 | return ret; |
1da177e4 LT |
750 | } |
751 | ||
c31c7d48 | 752 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 753 | { |
65e074df | 754 | int ret, numpages = cpa->numpages; |
ff31452b | 755 | |
65e074df TG |
756 | while (numpages) { |
757 | /* | |
758 | * Store the remaining nr of pages for the large page | |
759 | * preservation check. | |
760 | */ | |
9b5cf48b | 761 | cpa->numpages = numpages; |
d75586ad | 762 | /* for array changes, we can't use large page */ |
9ae28475 | 763 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 764 | cpa->numpages = 1; |
c31c7d48 | 765 | |
ad5ca55f SS |
766 | if (!debug_pagealloc) |
767 | spin_lock(&cpa_lock); | |
c31c7d48 | 768 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
769 | if (!debug_pagealloc) |
770 | spin_unlock(&cpa_lock); | |
ff31452b TG |
771 | if (ret) |
772 | return ret; | |
ff31452b | 773 | |
c31c7d48 TG |
774 | if (checkalias) { |
775 | ret = cpa_process_alias(cpa); | |
776 | if (ret) | |
777 | return ret; | |
778 | } | |
779 | ||
65e074df TG |
780 | /* |
781 | * Adjust the number of pages with the result of the | |
782 | * CPA operation. Either a large page has been | |
783 | * preserved or a single page update happened. | |
784 | */ | |
9b5cf48b RW |
785 | BUG_ON(cpa->numpages > numpages); |
786 | numpages -= cpa->numpages; | |
9ae28475 | 787 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
788 | cpa->curpage++; |
789 | else | |
790 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
791 | ||
65e074df | 792 | } |
ff31452b TG |
793 | return 0; |
794 | } | |
795 | ||
6bb8383b AK |
796 | static inline int cache_attr(pgprot_t attr) |
797 | { | |
798 | return pgprot_val(attr) & | |
799 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
800 | } | |
801 | ||
d75586ad | 802 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 803 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 804 | int force_split, int in_flag, |
805 | struct page **pages) | |
ff31452b | 806 | { |
72e458df | 807 | struct cpa_data cpa; |
cacf8906 | 808 | int ret, cache, checkalias; |
331e4065 TG |
809 | |
810 | /* | |
811 | * Check, if we are requested to change a not supported | |
812 | * feature: | |
813 | */ | |
814 | mask_set = canon_pgprot(mask_set); | |
815 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 816 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
817 | return 0; |
818 | ||
69b1415e | 819 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 820 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
821 | int i; |
822 | for (i = 0; i < numpages; i++) { | |
823 | if (addr[i] & ~PAGE_MASK) { | |
824 | addr[i] &= PAGE_MASK; | |
825 | WARN_ON_ONCE(1); | |
826 | } | |
827 | } | |
9ae28475 | 828 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
829 | /* | |
830 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
831 | * No need to cehck in that case | |
832 | */ | |
833 | if (*addr & ~PAGE_MASK) { | |
834 | *addr &= PAGE_MASK; | |
835 | /* | |
836 | * People should not be passing in unaligned addresses: | |
837 | */ | |
838 | WARN_ON_ONCE(1); | |
839 | } | |
69b1415e TG |
840 | } |
841 | ||
5843d9a4 NP |
842 | /* Must avoid aliasing mappings in the highmem code */ |
843 | kmap_flush_unused(); | |
844 | ||
db64fe02 NP |
845 | vm_unmap_aliases(); |
846 | ||
7ad9de6a TG |
847 | /* |
848 | * If we're called with lazy mmu updates enabled, the | |
849 | * in-memory pte state may be stale. Flush pending updates to | |
850 | * bring them up to date. | |
851 | */ | |
852 | arch_flush_lazy_mmu_mode(); | |
853 | ||
72e458df | 854 | cpa.vaddr = addr; |
9ae28475 | 855 | cpa.pages = pages; |
72e458df TG |
856 | cpa.numpages = numpages; |
857 | cpa.mask_set = mask_set; | |
858 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
859 | cpa.flags = 0; |
860 | cpa.curpage = 0; | |
c9caa02c | 861 | cpa.force_split = force_split; |
72e458df | 862 | |
9ae28475 | 863 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
864 | cpa.flags |= in_flag; | |
d75586ad | 865 | |
af96e443 TG |
866 | /* No alias checking for _NX bit modifications */ |
867 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
868 | ||
869 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 870 | |
f4ae5da0 TG |
871 | /* |
872 | * Check whether we really changed something: | |
873 | */ | |
d75586ad | 874 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 875 | goto out; |
cacf8906 | 876 | |
6bb8383b AK |
877 | /* |
878 | * No need to flush, when we did not set any of the caching | |
879 | * attributes: | |
880 | */ | |
881 | cache = cache_attr(mask_set); | |
882 | ||
57a6a46a TG |
883 | /* |
884 | * On success we use clflush, when the CPU supports it to | |
885 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 886 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
887 | * wbindv): |
888 | */ | |
d75586ad | 889 | if (!ret && cpu_has_clflush) { |
9ae28475 | 890 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
891 | cpa_flush_array(addr, numpages, cache, | |
892 | cpa.flags, pages); | |
893 | } else | |
d75586ad SL |
894 | cpa_flush_range(*addr, numpages, cache); |
895 | } else | |
6bb8383b | 896 | cpa_flush_all(cache); |
cacf8906 | 897 | |
4f06b043 JF |
898 | /* |
899 | * If we've been called with lazy mmu updates enabled, then | |
900 | * make sure that everything gets flushed out before we | |
901 | * return. | |
902 | */ | |
903 | arch_flush_lazy_mmu_mode(); | |
904 | ||
76ebd054 | 905 | out: |
ff31452b TG |
906 | return ret; |
907 | } | |
908 | ||
d75586ad SL |
909 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
910 | pgprot_t mask, int array) | |
75cbade8 | 911 | { |
d75586ad | 912 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 913 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
914 | } |
915 | ||
d75586ad SL |
916 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
917 | pgprot_t mask, int array) | |
72932c7a | 918 | { |
d75586ad | 919 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 920 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
921 | } |
922 | ||
1219333d | 923 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 924 | { |
de33c442 SS |
925 | /* |
926 | * for now UC MINUS. see comments in ioremap_nocache() | |
927 | */ | |
d75586ad SL |
928 | return change_page_attr_set(&addr, numpages, |
929 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 930 | } |
1219333d | 931 | |
932 | int set_memory_uc(unsigned long addr, int numpages) | |
933 | { | |
de33c442 SS |
934 | /* |
935 | * for now UC MINUS. see comments in ioremap_nocache() | |
936 | */ | |
c15238df | 937 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
de33c442 | 938 | _PAGE_CACHE_UC_MINUS, NULL)) |
1219333d | 939 | return -EINVAL; |
940 | ||
941 | return _set_memory_uc(addr, numpages); | |
942 | } | |
75cbade8 AV |
943 | EXPORT_SYMBOL(set_memory_uc); |
944 | ||
d75586ad SL |
945 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
946 | { | |
c5e147cf RH |
947 | unsigned long start; |
948 | unsigned long end; | |
d75586ad SL |
949 | int i; |
950 | /* | |
951 | * for now UC MINUS. see comments in ioremap_nocache() | |
952 | */ | |
953 | for (i = 0; i < addrinarray; i++) { | |
c5e147cf RH |
954 | start = __pa(addr[i]); |
955 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
956 | if (end != __pa(addr[i + 1])) | |
957 | break; | |
958 | i++; | |
959 | } | |
960 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
d75586ad SL |
961 | goto out; |
962 | } | |
963 | ||
964 | return change_page_attr_set(addr, addrinarray, | |
965 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); | |
966 | out: | |
c5e147cf RH |
967 | for (i = 0; i < addrinarray; i++) { |
968 | unsigned long tmp = __pa(addr[i]); | |
969 | ||
970 | if (tmp == start) | |
971 | break; | |
01de05af | 972 | for (end = tmp + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { |
c5e147cf RH |
973 | if (end != __pa(addr[i + 1])) |
974 | break; | |
975 | i++; | |
976 | } | |
977 | free_memtype(tmp, end); | |
978 | } | |
d75586ad SL |
979 | return -EINVAL; |
980 | } | |
981 | EXPORT_SYMBOL(set_memory_array_uc); | |
982 | ||
ef354af4 | 983 | int _set_memory_wc(unsigned long addr, int numpages) |
984 | { | |
d75586ad SL |
985 | return change_page_attr_set(&addr, numpages, |
986 | __pgprot(_PAGE_CACHE_WC), 0); | |
ef354af4 | 987 | } |
988 | ||
989 | int set_memory_wc(unsigned long addr, int numpages) | |
990 | { | |
499f8f84 | 991 | if (!pat_enabled) |
ef354af4 | 992 | return set_memory_uc(addr, numpages); |
993 | ||
c15238df | 994 | if (reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
ef354af4 | 995 | _PAGE_CACHE_WC, NULL)) |
996 | return -EINVAL; | |
997 | ||
998 | return _set_memory_wc(addr, numpages); | |
999 | } | |
1000 | EXPORT_SYMBOL(set_memory_wc); | |
1001 | ||
1219333d | 1002 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1003 | { |
d75586ad SL |
1004 | return change_page_attr_clear(&addr, numpages, |
1005 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1006 | } |
1219333d | 1007 | |
1008 | int set_memory_wb(unsigned long addr, int numpages) | |
1009 | { | |
c15238df | 1010 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
1219333d | 1011 | |
1012 | return _set_memory_wb(addr, numpages); | |
1013 | } | |
75cbade8 AV |
1014 | EXPORT_SYMBOL(set_memory_wb); |
1015 | ||
d75586ad SL |
1016 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1017 | { | |
1018 | int i; | |
d75586ad | 1019 | |
c5e147cf RH |
1020 | for (i = 0; i < addrinarray; i++) { |
1021 | unsigned long start = __pa(addr[i]); | |
1022 | unsigned long end; | |
1023 | ||
1024 | for (end = start + PAGE_SIZE; i < addrinarray - 1; end += PAGE_SIZE) { | |
1025 | if (end != __pa(addr[i + 1])) | |
1026 | break; | |
1027 | i++; | |
1028 | } | |
1029 | free_memtype(start, end); | |
1030 | } | |
d75586ad SL |
1031 | return change_page_attr_clear(addr, addrinarray, |
1032 | __pgprot(_PAGE_CACHE_MASK), 1); | |
1033 | } | |
1034 | EXPORT_SYMBOL(set_memory_array_wb); | |
1035 | ||
75cbade8 AV |
1036 | int set_memory_x(unsigned long addr, int numpages) |
1037 | { | |
d75586ad | 1038 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1039 | } |
1040 | EXPORT_SYMBOL(set_memory_x); | |
1041 | ||
1042 | int set_memory_nx(unsigned long addr, int numpages) | |
1043 | { | |
d75586ad | 1044 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1045 | } |
1046 | EXPORT_SYMBOL(set_memory_nx); | |
1047 | ||
1048 | int set_memory_ro(unsigned long addr, int numpages) | |
1049 | { | |
d75586ad | 1050 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1051 | } |
a03352d2 | 1052 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1053 | |
1054 | int set_memory_rw(unsigned long addr, int numpages) | |
1055 | { | |
d75586ad | 1056 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1057 | } |
a03352d2 | 1058 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1059 | |
1060 | int set_memory_np(unsigned long addr, int numpages) | |
1061 | { | |
d75586ad | 1062 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1063 | } |
75cbade8 | 1064 | |
c9caa02c AK |
1065 | int set_memory_4k(unsigned long addr, int numpages) |
1066 | { | |
d75586ad | 1067 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1068 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1069 | } |
1070 | ||
75cbade8 AV |
1071 | int set_pages_uc(struct page *page, int numpages) |
1072 | { | |
1073 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1074 | |
d7c8f21a | 1075 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1076 | } |
1077 | EXPORT_SYMBOL(set_pages_uc); | |
1078 | ||
1079 | int set_pages_wb(struct page *page, int numpages) | |
1080 | { | |
1081 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1082 | |
d7c8f21a | 1083 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1084 | } |
1085 | EXPORT_SYMBOL(set_pages_wb); | |
1086 | ||
1087 | int set_pages_x(struct page *page, int numpages) | |
1088 | { | |
1089 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1090 | |
d7c8f21a | 1091 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1092 | } |
1093 | EXPORT_SYMBOL(set_pages_x); | |
1094 | ||
1095 | int set_pages_nx(struct page *page, int numpages) | |
1096 | { | |
1097 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1098 | |
d7c8f21a | 1099 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1100 | } |
1101 | EXPORT_SYMBOL(set_pages_nx); | |
1102 | ||
1103 | int set_pages_ro(struct page *page, int numpages) | |
1104 | { | |
1105 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1106 | |
d7c8f21a | 1107 | return set_memory_ro(addr, numpages); |
75cbade8 | 1108 | } |
75cbade8 AV |
1109 | |
1110 | int set_pages_rw(struct page *page, int numpages) | |
1111 | { | |
1112 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1113 | |
d7c8f21a | 1114 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1115 | } |
1116 | ||
1da177e4 | 1117 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1118 | |
1119 | static int __set_pages_p(struct page *page, int numpages) | |
1120 | { | |
d75586ad SL |
1121 | unsigned long tempaddr = (unsigned long) page_address(page); |
1122 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1123 | .numpages = numpages, |
1124 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1125 | .mask_clr = __pgprot(0), |
1126 | .flags = 0}; | |
72932c7a | 1127 | |
55121b43 SS |
1128 | /* |
1129 | * No alias checking needed for setting present flag. otherwise, | |
1130 | * we may need to break large pages for 64-bit kernel text | |
1131 | * mappings (this adds to complexity if we want to do this from | |
1132 | * atomic context especially). Let's keep it simple! | |
1133 | */ | |
1134 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1135 | } |
1136 | ||
1137 | static int __set_pages_np(struct page *page, int numpages) | |
1138 | { | |
d75586ad SL |
1139 | unsigned long tempaddr = (unsigned long) page_address(page); |
1140 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1141 | .numpages = numpages, |
1142 | .mask_set = __pgprot(0), | |
d75586ad SL |
1143 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1144 | .flags = 0}; | |
72932c7a | 1145 | |
55121b43 SS |
1146 | /* |
1147 | * No alias checking needed for setting not present flag. otherwise, | |
1148 | * we may need to break large pages for 64-bit kernel text | |
1149 | * mappings (this adds to complexity if we want to do this from | |
1150 | * atomic context especially). Let's keep it simple! | |
1151 | */ | |
1152 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1153 | } |
1154 | ||
1da177e4 LT |
1155 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1156 | { | |
1157 | if (PageHighMem(page)) | |
1158 | return; | |
9f4c815c | 1159 | if (!enable) { |
f9b8404c IM |
1160 | debug_check_no_locks_freed(page_address(page), |
1161 | numpages * PAGE_SIZE); | |
9f4c815c | 1162 | } |
de5097c2 | 1163 | |
12d6f21e IM |
1164 | /* |
1165 | * If page allocator is not up yet then do not call c_p_a(): | |
1166 | */ | |
1167 | if (!debug_pagealloc_enabled) | |
1168 | return; | |
1169 | ||
9f4c815c | 1170 | /* |
f8d8406b | 1171 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1172 | * Large pages for identity mappings are not used at boot time |
1173 | * and hence no memory allocations during large page split. | |
1da177e4 | 1174 | */ |
f62d0f00 IM |
1175 | if (enable) |
1176 | __set_pages_p(page, numpages); | |
1177 | else | |
1178 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1179 | |
1180 | /* | |
e4b71dcf IM |
1181 | * We should perform an IPI and flush all tlbs, |
1182 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1183 | */ |
1184 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1185 | } |
1186 | ||
8a235efa RW |
1187 | #ifdef CONFIG_HIBERNATION |
1188 | ||
1189 | bool kernel_page_present(struct page *page) | |
1190 | { | |
1191 | unsigned int level; | |
1192 | pte_t *pte; | |
1193 | ||
1194 | if (PageHighMem(page)) | |
1195 | return false; | |
1196 | ||
1197 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1198 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1199 | } | |
1200 | ||
1201 | #endif /* CONFIG_HIBERNATION */ | |
1202 | ||
1203 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1204 | |
1205 | /* | |
1206 | * The testcases use internal knowledge of the implementation that shouldn't | |
1207 | * be exposed to the rest of the kernel. Include these directly here. | |
1208 | */ | |
1209 | #ifdef CONFIG_CPA_DEBUG | |
1210 | #include "pageattr-test.c" | |
1211 | #endif |