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Commit | Line | Data |
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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | #include <linux/highmem.h> |
8192206d | 6 | #include <linux/bootmem.h> |
1da177e4 | 7 | #include <linux/module.h> |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c | 10 | #include <linux/mm.h> |
76ebd054 | 11 | #include <linux/interrupt.h> |
ee7ae7a1 TG |
12 | #include <linux/seq_file.h> |
13 | #include <linux/debugfs.h> | |
e59a1bb2 | 14 | #include <linux/pfn.h> |
8c4bfc6e | 15 | #include <linux/percpu.h> |
9f4c815c | 16 | |
950f9d95 | 17 | #include <asm/e820.h> |
1da177e4 LT |
18 | #include <asm/processor.h> |
19 | #include <asm/tlbflush.h> | |
f8af095d | 20 | #include <asm/sections.h> |
93dbda7c | 21 | #include <asm/setup.h> |
9f4c815c IM |
22 | #include <asm/uaccess.h> |
23 | #include <asm/pgalloc.h> | |
c31c7d48 | 24 | #include <asm/proto.h> |
1219333d | 25 | #include <asm/pat.h> |
1da177e4 | 26 | |
9df84993 IM |
27 | /* |
28 | * The current flushing context - we pass it instead of 5 arguments: | |
29 | */ | |
72e458df | 30 | struct cpa_data { |
d75586ad | 31 | unsigned long *vaddr; |
72e458df TG |
32 | pgprot_t mask_set; |
33 | pgprot_t mask_clr; | |
65e074df | 34 | int numpages; |
d75586ad | 35 | int flags; |
c31c7d48 | 36 | unsigned long pfn; |
c9caa02c | 37 | unsigned force_split : 1; |
d75586ad | 38 | int curpage; |
9ae28475 | 39 | struct page **pages; |
72e458df TG |
40 | }; |
41 | ||
ad5ca55f SS |
42 | /* |
43 | * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) | |
44 | * using cpa_lock. So that we don't allow any other cpu, with stale large tlb | |
45 | * entries change the page attribute in parallel to some other cpu | |
46 | * splitting a large page entry along with changing the attribute. | |
47 | */ | |
48 | static DEFINE_SPINLOCK(cpa_lock); | |
49 | ||
d75586ad SL |
50 | #define CPA_FLUSHTLB 1 |
51 | #define CPA_ARRAY 2 | |
9ae28475 | 52 | #define CPA_PAGES_ARRAY 4 |
d75586ad | 53 | |
65280e61 | 54 | #ifdef CONFIG_PROC_FS |
ce0c0e50 AK |
55 | static unsigned long direct_pages_count[PG_LEVEL_NUM]; |
56 | ||
65280e61 | 57 | void update_page_count(int level, unsigned long pages) |
ce0c0e50 | 58 | { |
ce0c0e50 | 59 | unsigned long flags; |
65280e61 | 60 | |
ce0c0e50 AK |
61 | /* Protect against CPA */ |
62 | spin_lock_irqsave(&pgd_lock, flags); | |
63 | direct_pages_count[level] += pages; | |
64 | spin_unlock_irqrestore(&pgd_lock, flags); | |
65280e61 TG |
65 | } |
66 | ||
67 | static void split_page_count(int level) | |
68 | { | |
69 | direct_pages_count[level]--; | |
70 | direct_pages_count[level - 1] += PTRS_PER_PTE; | |
71 | } | |
72 | ||
e1759c21 | 73 | void arch_report_meminfo(struct seq_file *m) |
65280e61 | 74 | { |
b9c3bfc2 | 75 | seq_printf(m, "DirectMap4k: %8lu kB\n", |
a06de630 HD |
76 | direct_pages_count[PG_LEVEL_4K] << 2); |
77 | #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) | |
b9c3bfc2 | 78 | seq_printf(m, "DirectMap2M: %8lu kB\n", |
a06de630 HD |
79 | direct_pages_count[PG_LEVEL_2M] << 11); |
80 | #else | |
b9c3bfc2 | 81 | seq_printf(m, "DirectMap4M: %8lu kB\n", |
a06de630 HD |
82 | direct_pages_count[PG_LEVEL_2M] << 12); |
83 | #endif | |
65280e61 | 84 | #ifdef CONFIG_X86_64 |
a06de630 | 85 | if (direct_gbpages) |
b9c3bfc2 | 86 | seq_printf(m, "DirectMap1G: %8lu kB\n", |
a06de630 | 87 | direct_pages_count[PG_LEVEL_1G] << 20); |
ce0c0e50 AK |
88 | #endif |
89 | } | |
65280e61 TG |
90 | #else |
91 | static inline void split_page_count(int level) { } | |
92 | #endif | |
ce0c0e50 | 93 | |
c31c7d48 TG |
94 | #ifdef CONFIG_X86_64 |
95 | ||
96 | static inline unsigned long highmap_start_pfn(void) | |
97 | { | |
98 | return __pa(_text) >> PAGE_SHIFT; | |
99 | } | |
100 | ||
101 | static inline unsigned long highmap_end_pfn(void) | |
102 | { | |
93dbda7c | 103 | return __pa(roundup(_brk_end, PMD_SIZE)) >> PAGE_SHIFT; |
c31c7d48 TG |
104 | } |
105 | ||
106 | #endif | |
107 | ||
92cb54a3 IM |
108 | #ifdef CONFIG_DEBUG_PAGEALLOC |
109 | # define debug_pagealloc 1 | |
110 | #else | |
111 | # define debug_pagealloc 0 | |
112 | #endif | |
113 | ||
ed724be6 AV |
114 | static inline int |
115 | within(unsigned long addr, unsigned long start, unsigned long end) | |
687c4825 | 116 | { |
ed724be6 AV |
117 | return addr >= start && addr < end; |
118 | } | |
119 | ||
d7c8f21a TG |
120 | /* |
121 | * Flushing functions | |
122 | */ | |
cd8ddf1a | 123 | |
cd8ddf1a TG |
124 | /** |
125 | * clflush_cache_range - flush a cache range with clflush | |
126 | * @addr: virtual start address | |
127 | * @size: number of bytes to flush | |
128 | * | |
129 | * clflush is an unordered instruction which needs fencing with mfence | |
130 | * to avoid ordering issues. | |
131 | */ | |
4c61afcd | 132 | void clflush_cache_range(void *vaddr, unsigned int size) |
d7c8f21a | 133 | { |
4c61afcd | 134 | void *vend = vaddr + size - 1; |
d7c8f21a | 135 | |
cd8ddf1a | 136 | mb(); |
4c61afcd IM |
137 | |
138 | for (; vaddr < vend; vaddr += boot_cpu_data.x86_clflush_size) | |
139 | clflush(vaddr); | |
140 | /* | |
141 | * Flush any possible final partial cacheline: | |
142 | */ | |
143 | clflush(vend); | |
144 | ||
cd8ddf1a | 145 | mb(); |
d7c8f21a | 146 | } |
e517a5e9 | 147 | EXPORT_SYMBOL_GPL(clflush_cache_range); |
d7c8f21a | 148 | |
af1e6844 | 149 | static void __cpa_flush_all(void *arg) |
d7c8f21a | 150 | { |
6bb8383b AK |
151 | unsigned long cache = (unsigned long)arg; |
152 | ||
d7c8f21a TG |
153 | /* |
154 | * Flush all to work around Errata in early athlons regarding | |
155 | * large page flushing. | |
156 | */ | |
157 | __flush_tlb_all(); | |
158 | ||
0b827537 | 159 | if (cache && boot_cpu_data.x86 >= 4) |
d7c8f21a TG |
160 | wbinvd(); |
161 | } | |
162 | ||
6bb8383b | 163 | static void cpa_flush_all(unsigned long cache) |
d7c8f21a TG |
164 | { |
165 | BUG_ON(irqs_disabled()); | |
166 | ||
15c8b6c1 | 167 | on_each_cpu(__cpa_flush_all, (void *) cache, 1); |
d7c8f21a TG |
168 | } |
169 | ||
57a6a46a TG |
170 | static void __cpa_flush_range(void *arg) |
171 | { | |
57a6a46a TG |
172 | /* |
173 | * We could optimize that further and do individual per page | |
174 | * tlb invalidates for a low number of pages. Caveat: we must | |
175 | * flush the high aliases on 64bit as well. | |
176 | */ | |
177 | __flush_tlb_all(); | |
57a6a46a TG |
178 | } |
179 | ||
6bb8383b | 180 | static void cpa_flush_range(unsigned long start, int numpages, int cache) |
57a6a46a | 181 | { |
4c61afcd IM |
182 | unsigned int i, level; |
183 | unsigned long addr; | |
184 | ||
57a6a46a | 185 | BUG_ON(irqs_disabled()); |
4c61afcd | 186 | WARN_ON(PAGE_ALIGN(start) != start); |
57a6a46a | 187 | |
15c8b6c1 | 188 | on_each_cpu(__cpa_flush_range, NULL, 1); |
57a6a46a | 189 | |
6bb8383b AK |
190 | if (!cache) |
191 | return; | |
192 | ||
3b233e52 TG |
193 | /* |
194 | * We only need to flush on one CPU, | |
195 | * clflush is a MESI-coherent instruction that | |
196 | * will cause all other CPUs to flush the same | |
197 | * cachelines: | |
198 | */ | |
4c61afcd IM |
199 | for (i = 0, addr = start; i < numpages; i++, addr += PAGE_SIZE) { |
200 | pte_t *pte = lookup_address(addr, &level); | |
201 | ||
202 | /* | |
203 | * Only flush present addresses: | |
204 | */ | |
7bfb72e8 | 205 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) |
4c61afcd IM |
206 | clflush_cache_range((void *) addr, PAGE_SIZE); |
207 | } | |
57a6a46a TG |
208 | } |
209 | ||
9ae28475 | 210 | static void cpa_flush_array(unsigned long *start, int numpages, int cache, |
211 | int in_flags, struct page **pages) | |
d75586ad SL |
212 | { |
213 | unsigned int i, level; | |
2171787b | 214 | unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ |
d75586ad SL |
215 | |
216 | BUG_ON(irqs_disabled()); | |
217 | ||
2171787b | 218 | on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); |
d75586ad | 219 | |
2171787b | 220 | if (!cache || do_wbinvd) |
d75586ad SL |
221 | return; |
222 | ||
d75586ad SL |
223 | /* |
224 | * We only need to flush on one CPU, | |
225 | * clflush is a MESI-coherent instruction that | |
226 | * will cause all other CPUs to flush the same | |
227 | * cachelines: | |
228 | */ | |
9ae28475 | 229 | for (i = 0; i < numpages; i++) { |
230 | unsigned long addr; | |
231 | pte_t *pte; | |
232 | ||
233 | if (in_flags & CPA_PAGES_ARRAY) | |
234 | addr = (unsigned long)page_address(pages[i]); | |
235 | else | |
236 | addr = start[i]; | |
237 | ||
238 | pte = lookup_address(addr, &level); | |
d75586ad SL |
239 | |
240 | /* | |
241 | * Only flush present addresses: | |
242 | */ | |
243 | if (pte && (pte_val(*pte) & _PAGE_PRESENT)) | |
9ae28475 | 244 | clflush_cache_range((void *)addr, PAGE_SIZE); |
d75586ad SL |
245 | } |
246 | } | |
247 | ||
ed724be6 AV |
248 | /* |
249 | * Certain areas of memory on x86 require very specific protection flags, | |
250 | * for example the BIOS area or kernel text. Callers don't always get this | |
251 | * right (again, ioremap() on BIOS memory is not uncommon) so this function | |
252 | * checks and fixes these known static required protection bits. | |
253 | */ | |
c31c7d48 TG |
254 | static inline pgprot_t static_protections(pgprot_t prot, unsigned long address, |
255 | unsigned long pfn) | |
ed724be6 AV |
256 | { |
257 | pgprot_t forbidden = __pgprot(0); | |
258 | ||
687c4825 | 259 | /* |
ed724be6 AV |
260 | * The BIOS area between 640k and 1Mb needs to be executable for |
261 | * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support. | |
687c4825 | 262 | */ |
c31c7d48 | 263 | if (within(pfn, BIOS_BEGIN >> PAGE_SHIFT, BIOS_END >> PAGE_SHIFT)) |
ed724be6 AV |
264 | pgprot_val(forbidden) |= _PAGE_NX; |
265 | ||
266 | /* | |
267 | * The kernel text needs to be executable for obvious reasons | |
c31c7d48 TG |
268 | * Does not cover __inittext since that is gone later on. On |
269 | * 64bit we do not enforce !NX on the low mapping | |
ed724be6 AV |
270 | */ |
271 | if (within(address, (unsigned long)_text, (unsigned long)_etext)) | |
272 | pgprot_val(forbidden) |= _PAGE_NX; | |
cc0f21bb | 273 | |
cc0f21bb | 274 | /* |
c31c7d48 TG |
275 | * The .rodata section needs to be read-only. Using the pfn |
276 | * catches all aliases. | |
cc0f21bb | 277 | */ |
c31c7d48 TG |
278 | if (within(pfn, __pa((unsigned long)__start_rodata) >> PAGE_SHIFT, |
279 | __pa((unsigned long)__end_rodata) >> PAGE_SHIFT)) | |
cc0f21bb | 280 | pgprot_val(forbidden) |= _PAGE_RW; |
ed724be6 | 281 | |
883242dd SR |
282 | #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA) && \ |
283 | !defined(CONFIG_DYNAMIC_FTRACE) | |
74e08179 SS |
284 | /* |
285 | * Kernel text mappings for the large page aligned .rodata section | |
286 | * will be read-only. For the kernel identity mappings covering | |
287 | * the holes caused by this alignment can be anything. | |
288 | * | |
289 | * This will preserve the large page mappings for kernel text/data | |
290 | * at no extra cost. | |
291 | */ | |
292 | if (within(address, (unsigned long)_text, | |
293 | (unsigned long)__end_rodata_hpage_align)) | |
294 | pgprot_val(forbidden) |= _PAGE_RW; | |
295 | #endif | |
296 | ||
ed724be6 | 297 | prot = __pgprot(pgprot_val(prot) & ~pgprot_val(forbidden)); |
687c4825 IM |
298 | |
299 | return prot; | |
300 | } | |
301 | ||
9a14aefc TG |
302 | /* |
303 | * Lookup the page table entry for a virtual address. Return a pointer | |
304 | * to the entry and the level of the mapping. | |
305 | * | |
306 | * Note: We return pud and pmd either when the entry is marked large | |
307 | * or when the present bit is not set. Otherwise we would return a | |
308 | * pointer to a nonexisting mapping. | |
309 | */ | |
da7bfc50 | 310 | pte_t *lookup_address(unsigned long address, unsigned int *level) |
9f4c815c | 311 | { |
1da177e4 LT |
312 | pgd_t *pgd = pgd_offset_k(address); |
313 | pud_t *pud; | |
314 | pmd_t *pmd; | |
9f4c815c | 315 | |
30551bb3 TG |
316 | *level = PG_LEVEL_NONE; |
317 | ||
1da177e4 LT |
318 | if (pgd_none(*pgd)) |
319 | return NULL; | |
9df84993 | 320 | |
1da177e4 LT |
321 | pud = pud_offset(pgd, address); |
322 | if (pud_none(*pud)) | |
323 | return NULL; | |
c2f71ee2 AK |
324 | |
325 | *level = PG_LEVEL_1G; | |
326 | if (pud_large(*pud) || !pud_present(*pud)) | |
327 | return (pte_t *)pud; | |
328 | ||
1da177e4 LT |
329 | pmd = pmd_offset(pud, address); |
330 | if (pmd_none(*pmd)) | |
331 | return NULL; | |
30551bb3 TG |
332 | |
333 | *level = PG_LEVEL_2M; | |
9a14aefc | 334 | if (pmd_large(*pmd) || !pmd_present(*pmd)) |
1da177e4 | 335 | return (pte_t *)pmd; |
1da177e4 | 336 | |
30551bb3 | 337 | *level = PG_LEVEL_4K; |
9df84993 | 338 | |
9f4c815c IM |
339 | return pte_offset_kernel(pmd, address); |
340 | } | |
75bb8835 | 341 | EXPORT_SYMBOL_GPL(lookup_address); |
9f4c815c | 342 | |
9df84993 IM |
343 | /* |
344 | * Set the new pmd in all the pgds we know about: | |
345 | */ | |
9a3dc780 | 346 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 347 | { |
9f4c815c IM |
348 | /* change init_mm */ |
349 | set_pte_atomic(kpte, pte); | |
44af6c41 | 350 | #ifdef CONFIG_X86_32 |
e4b71dcf | 351 | if (!SHARED_KERNEL_PMD) { |
44af6c41 IM |
352 | struct page *page; |
353 | ||
e3ed910d | 354 | list_for_each_entry(page, &pgd_list, lru) { |
44af6c41 IM |
355 | pgd_t *pgd; |
356 | pud_t *pud; | |
357 | pmd_t *pmd; | |
358 | ||
359 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
360 | pud = pud_offset(pgd, address); | |
361 | pmd = pmd_offset(pud, address); | |
362 | set_pte_atomic((pte_t *)pmd, pte); | |
363 | } | |
1da177e4 | 364 | } |
44af6c41 | 365 | #endif |
1da177e4 LT |
366 | } |
367 | ||
9df84993 IM |
368 | static int |
369 | try_preserve_large_page(pte_t *kpte, unsigned long address, | |
370 | struct cpa_data *cpa) | |
65e074df | 371 | { |
c31c7d48 | 372 | unsigned long nextpage_addr, numpages, pmask, psize, flags, addr, pfn; |
65e074df TG |
373 | pte_t new_pte, old_pte, *tmp; |
374 | pgprot_t old_prot, new_prot; | |
fac84939 | 375 | int i, do_split = 1; |
da7bfc50 | 376 | unsigned int level; |
65e074df | 377 | |
c9caa02c AK |
378 | if (cpa->force_split) |
379 | return 1; | |
380 | ||
65e074df TG |
381 | spin_lock_irqsave(&pgd_lock, flags); |
382 | /* | |
383 | * Check for races, another CPU might have split this page | |
384 | * up already: | |
385 | */ | |
386 | tmp = lookup_address(address, &level); | |
387 | if (tmp != kpte) | |
388 | goto out_unlock; | |
389 | ||
390 | switch (level) { | |
391 | case PG_LEVEL_2M: | |
31422c51 AK |
392 | psize = PMD_PAGE_SIZE; |
393 | pmask = PMD_PAGE_MASK; | |
65e074df | 394 | break; |
f07333fd | 395 | #ifdef CONFIG_X86_64 |
65e074df | 396 | case PG_LEVEL_1G: |
5d3c8b21 AK |
397 | psize = PUD_PAGE_SIZE; |
398 | pmask = PUD_PAGE_MASK; | |
f07333fd AK |
399 | break; |
400 | #endif | |
65e074df | 401 | default: |
beaff633 | 402 | do_split = -EINVAL; |
65e074df TG |
403 | goto out_unlock; |
404 | } | |
405 | ||
406 | /* | |
407 | * Calculate the number of pages, which fit into this large | |
408 | * page starting at address: | |
409 | */ | |
410 | nextpage_addr = (address + psize) & pmask; | |
411 | numpages = (nextpage_addr - address) >> PAGE_SHIFT; | |
9b5cf48b RW |
412 | if (numpages < cpa->numpages) |
413 | cpa->numpages = numpages; | |
65e074df TG |
414 | |
415 | /* | |
416 | * We are safe now. Check whether the new pgprot is the same: | |
417 | */ | |
418 | old_pte = *kpte; | |
419 | old_prot = new_prot = pte_pgprot(old_pte); | |
420 | ||
421 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); | |
422 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
c31c7d48 TG |
423 | |
424 | /* | |
425 | * old_pte points to the large page base address. So we need | |
426 | * to add the offset of the virtual address: | |
427 | */ | |
428 | pfn = pte_pfn(old_pte) + ((address & (psize - 1)) >> PAGE_SHIFT); | |
429 | cpa->pfn = pfn; | |
430 | ||
431 | new_prot = static_protections(new_prot, address, pfn); | |
65e074df | 432 | |
fac84939 TG |
433 | /* |
434 | * We need to check the full range, whether | |
435 | * static_protection() requires a different pgprot for one of | |
436 | * the pages in the range we try to preserve: | |
437 | */ | |
438 | addr = address + PAGE_SIZE; | |
c31c7d48 | 439 | pfn++; |
9b5cf48b | 440 | for (i = 1; i < cpa->numpages; i++, addr += PAGE_SIZE, pfn++) { |
c31c7d48 | 441 | pgprot_t chk_prot = static_protections(new_prot, addr, pfn); |
fac84939 TG |
442 | |
443 | if (pgprot_val(chk_prot) != pgprot_val(new_prot)) | |
444 | goto out_unlock; | |
445 | } | |
446 | ||
65e074df TG |
447 | /* |
448 | * If there are no changes, return. maxpages has been updated | |
449 | * above: | |
450 | */ | |
451 | if (pgprot_val(new_prot) == pgprot_val(old_prot)) { | |
beaff633 | 452 | do_split = 0; |
65e074df TG |
453 | goto out_unlock; |
454 | } | |
455 | ||
456 | /* | |
457 | * We need to change the attributes. Check, whether we can | |
458 | * change the large page in one go. We request a split, when | |
459 | * the address is not aligned and the number of pages is | |
460 | * smaller than the number of pages in the large page. Note | |
461 | * that we limited the number of possible pages already to | |
462 | * the number of pages in the large page. | |
463 | */ | |
9b5cf48b | 464 | if (address == (nextpage_addr - psize) && cpa->numpages == numpages) { |
65e074df TG |
465 | /* |
466 | * The address is aligned and the number of pages | |
467 | * covers the full page. | |
468 | */ | |
469 | new_pte = pfn_pte(pte_pfn(old_pte), canon_pgprot(new_prot)); | |
470 | __set_pmd_pte(kpte, address, new_pte); | |
d75586ad | 471 | cpa->flags |= CPA_FLUSHTLB; |
beaff633 | 472 | do_split = 0; |
65e074df TG |
473 | } |
474 | ||
475 | out_unlock: | |
476 | spin_unlock_irqrestore(&pgd_lock, flags); | |
9df84993 | 477 | |
beaff633 | 478 | return do_split; |
65e074df TG |
479 | } |
480 | ||
7afe15b9 | 481 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 482 | { |
7b610eec | 483 | unsigned long flags, pfn, pfninc = 1; |
9df84993 | 484 | unsigned int i, level; |
bb5c2dbd | 485 | pte_t *pbase, *tmp; |
9df84993 | 486 | pgprot_t ref_prot; |
ad5ca55f SS |
487 | struct page *base; |
488 | ||
489 | if (!debug_pagealloc) | |
490 | spin_unlock(&cpa_lock); | |
9e730237 | 491 | base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0); |
ad5ca55f SS |
492 | if (!debug_pagealloc) |
493 | spin_lock(&cpa_lock); | |
8311eb84 SS |
494 | if (!base) |
495 | return -ENOMEM; | |
bb5c2dbd | 496 | |
eb5b5f02 | 497 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
498 | /* |
499 | * Check for races, another CPU might have split this page | |
500 | * up for us already: | |
501 | */ | |
502 | tmp = lookup_address(address, &level); | |
6ce9fc17 | 503 | if (tmp != kpte) |
bb5c2dbd IM |
504 | goto out_unlock; |
505 | ||
bb5c2dbd | 506 | pbase = (pte_t *)page_address(base); |
6944a9c8 | 507 | paravirt_alloc_pte(&init_mm, page_to_pfn(base)); |
07cf89c0 | 508 | ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
7a5714e0 IM |
509 | /* |
510 | * If we ever want to utilize the PAT bit, we need to | |
511 | * update this function to make sure it's converted from | |
512 | * bit 12 to bit 7 when we cross from the 2MB level to | |
513 | * the 4K level: | |
514 | */ | |
515 | WARN_ON_ONCE(pgprot_val(ref_prot) & _PAGE_PAT_LARGE); | |
bb5c2dbd | 516 | |
f07333fd AK |
517 | #ifdef CONFIG_X86_64 |
518 | if (level == PG_LEVEL_1G) { | |
519 | pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT; | |
520 | pgprot_val(ref_prot) |= _PAGE_PSE; | |
f07333fd AK |
521 | } |
522 | #endif | |
523 | ||
63c1dcf4 TG |
524 | /* |
525 | * Get the target pfn from the original entry: | |
526 | */ | |
527 | pfn = pte_pfn(*kpte); | |
f07333fd | 528 | for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc) |
63c1dcf4 | 529 | set_pte(&pbase[i], pfn_pte(pfn, ref_prot)); |
bb5c2dbd | 530 | |
ce0c0e50 | 531 | if (address >= (unsigned long)__va(0) && |
f361a450 YL |
532 | address < (unsigned long)__va(max_low_pfn_mapped << PAGE_SHIFT)) |
533 | split_page_count(level); | |
534 | ||
535 | #ifdef CONFIG_X86_64 | |
536 | if (address >= (unsigned long)__va(1UL<<32) && | |
65280e61 TG |
537 | address < (unsigned long)__va(max_pfn_mapped << PAGE_SHIFT)) |
538 | split_page_count(level); | |
f361a450 | 539 | #endif |
ce0c0e50 | 540 | |
bb5c2dbd | 541 | /* |
07a66d7c | 542 | * Install the new, split up pagetable. |
4c881ca1 | 543 | * |
07a66d7c IM |
544 | * We use the standard kernel pagetable protections for the new |
545 | * pagetable protections, the actual ptes set above control the | |
546 | * primary protection behavior: | |
bb5c2dbd | 547 | */ |
07a66d7c | 548 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
211b3d03 IM |
549 | |
550 | /* | |
551 | * Intel Atom errata AAH41 workaround. | |
552 | * | |
553 | * The real fix should be in hw or in a microcode update, but | |
554 | * we also probabilistically try to reduce the window of having | |
555 | * a large TLB mixed with 4K TLBs while instruction fetches are | |
556 | * going on. | |
557 | */ | |
558 | __flush_tlb_all(); | |
559 | ||
bb5c2dbd IM |
560 | base = NULL; |
561 | ||
562 | out_unlock: | |
eb5b5f02 TG |
563 | /* |
564 | * If we dropped out via the lookup_address check under | |
565 | * pgd_lock then stick the page back into the pool: | |
566 | */ | |
8311eb84 SS |
567 | if (base) |
568 | __free_page(base); | |
9a3dc780 | 569 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd | 570 | |
bb5c2dbd IM |
571 | return 0; |
572 | } | |
573 | ||
a1e46212 SS |
574 | static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr, |
575 | int primary) | |
576 | { | |
577 | /* | |
578 | * Ignore all non primary paths. | |
579 | */ | |
580 | if (!primary) | |
581 | return 0; | |
582 | ||
583 | /* | |
584 | * Ignore the NULL PTE for kernel identity mapping, as it is expected | |
585 | * to have holes. | |
586 | * Also set numpages to '1' indicating that we processed cpa req for | |
587 | * one virtual address page and its pfn. TBD: numpages can be set based | |
588 | * on the initial value and the level returned by lookup_address(). | |
589 | */ | |
590 | if (within(vaddr, PAGE_OFFSET, | |
591 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) { | |
592 | cpa->numpages = 1; | |
593 | cpa->pfn = __pa(vaddr) >> PAGE_SHIFT; | |
594 | return 0; | |
595 | } else { | |
596 | WARN(1, KERN_WARNING "CPA: called for zero pte. " | |
597 | "vaddr = %lx cpa->vaddr = %lx\n", vaddr, | |
598 | *cpa->vaddr); | |
599 | ||
600 | return -EFAULT; | |
601 | } | |
602 | } | |
603 | ||
c31c7d48 | 604 | static int __change_page_attr(struct cpa_data *cpa, int primary) |
9f4c815c | 605 | { |
d75586ad | 606 | unsigned long address; |
da7bfc50 HH |
607 | int do_split, err; |
608 | unsigned int level; | |
c31c7d48 | 609 | pte_t *kpte, old_pte; |
1da177e4 | 610 | |
8523acfe TH |
611 | if (cpa->flags & CPA_PAGES_ARRAY) { |
612 | struct page *page = cpa->pages[cpa->curpage]; | |
613 | if (unlikely(PageHighMem(page))) | |
614 | return 0; | |
615 | address = (unsigned long)page_address(page); | |
616 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
617 | address = cpa->vaddr[cpa->curpage]; |
618 | else | |
619 | address = *cpa->vaddr; | |
97f99fed | 620 | repeat: |
f0646e43 | 621 | kpte = lookup_address(address, &level); |
1da177e4 | 622 | if (!kpte) |
a1e46212 | 623 | return __cpa_process_fault(cpa, address, primary); |
c31c7d48 TG |
624 | |
625 | old_pte = *kpte; | |
a1e46212 SS |
626 | if (!pte_val(old_pte)) |
627 | return __cpa_process_fault(cpa, address, primary); | |
9f4c815c | 628 | |
30551bb3 | 629 | if (level == PG_LEVEL_4K) { |
c31c7d48 | 630 | pte_t new_pte; |
626c2c9d | 631 | pgprot_t new_prot = pte_pgprot(old_pte); |
c31c7d48 | 632 | unsigned long pfn = pte_pfn(old_pte); |
86f03989 | 633 | |
72e458df TG |
634 | pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr); |
635 | pgprot_val(new_prot) |= pgprot_val(cpa->mask_set); | |
86f03989 | 636 | |
c31c7d48 | 637 | new_prot = static_protections(new_prot, address, pfn); |
86f03989 | 638 | |
626c2c9d AV |
639 | /* |
640 | * We need to keep the pfn from the existing PTE, | |
641 | * after all we're only going to change it's attributes | |
642 | * not the memory it points to | |
643 | */ | |
c31c7d48 TG |
644 | new_pte = pfn_pte(pfn, canon_pgprot(new_prot)); |
645 | cpa->pfn = pfn; | |
f4ae5da0 TG |
646 | /* |
647 | * Do we really change anything ? | |
648 | */ | |
649 | if (pte_val(old_pte) != pte_val(new_pte)) { | |
650 | set_pte_atomic(kpte, new_pte); | |
d75586ad | 651 | cpa->flags |= CPA_FLUSHTLB; |
f4ae5da0 | 652 | } |
9b5cf48b | 653 | cpa->numpages = 1; |
65e074df | 654 | return 0; |
1da177e4 | 655 | } |
65e074df TG |
656 | |
657 | /* | |
658 | * Check, whether we can keep the large page intact | |
659 | * and just change the pte: | |
660 | */ | |
beaff633 | 661 | do_split = try_preserve_large_page(kpte, address, cpa); |
65e074df TG |
662 | /* |
663 | * When the range fits into the existing large page, | |
9b5cf48b | 664 | * return. cp->numpages and cpa->tlbflush have been updated in |
65e074df TG |
665 | * try_large_page: |
666 | */ | |
87f7f8fe IM |
667 | if (do_split <= 0) |
668 | return do_split; | |
65e074df TG |
669 | |
670 | /* | |
671 | * We have to split the large page: | |
672 | */ | |
87f7f8fe IM |
673 | err = split_large_page(kpte, address); |
674 | if (!err) { | |
ad5ca55f SS |
675 | /* |
676 | * Do a global flush tlb after splitting the large page | |
677 | * and before we do the actual change page attribute in the PTE. | |
678 | * | |
679 | * With out this, we violate the TLB application note, that says | |
680 | * "The TLBs may contain both ordinary and large-page | |
681 | * translations for a 4-KByte range of linear addresses. This | |
682 | * may occur if software modifies the paging structures so that | |
683 | * the page size used for the address range changes. If the two | |
684 | * translations differ with respect to page frame or attributes | |
685 | * (e.g., permissions), processor behavior is undefined and may | |
686 | * be implementation-specific." | |
687 | * | |
688 | * We do this global tlb flush inside the cpa_lock, so that we | |
689 | * don't allow any other cpu, with stale tlb entries change the | |
690 | * page attribute in parallel, that also falls into the | |
691 | * just split large page entry. | |
692 | */ | |
693 | flush_tlb_all(); | |
87f7f8fe IM |
694 | goto repeat; |
695 | } | |
beaff633 | 696 | |
87f7f8fe | 697 | return err; |
9f4c815c | 698 | } |
1da177e4 | 699 | |
c31c7d48 TG |
700 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias); |
701 | ||
702 | static int cpa_process_alias(struct cpa_data *cpa) | |
1da177e4 | 703 | { |
c31c7d48 | 704 | struct cpa_data alias_cpa; |
992f4c1c | 705 | unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT); |
e933a73f | 706 | unsigned long vaddr; |
992f4c1c | 707 | int ret; |
44af6c41 | 708 | |
965194c1 | 709 | if (cpa->pfn >= max_pfn_mapped) |
c31c7d48 | 710 | return 0; |
626c2c9d | 711 | |
f361a450 | 712 | #ifdef CONFIG_X86_64 |
965194c1 | 713 | if (cpa->pfn >= max_low_pfn_mapped && cpa->pfn < (1UL<<(32-PAGE_SHIFT))) |
f361a450 YL |
714 | return 0; |
715 | #endif | |
f34b439f TG |
716 | /* |
717 | * No need to redo, when the primary call touched the direct | |
718 | * mapping already: | |
719 | */ | |
8523acfe TH |
720 | if (cpa->flags & CPA_PAGES_ARRAY) { |
721 | struct page *page = cpa->pages[cpa->curpage]; | |
722 | if (unlikely(PageHighMem(page))) | |
723 | return 0; | |
724 | vaddr = (unsigned long)page_address(page); | |
725 | } else if (cpa->flags & CPA_ARRAY) | |
d75586ad SL |
726 | vaddr = cpa->vaddr[cpa->curpage]; |
727 | else | |
728 | vaddr = *cpa->vaddr; | |
729 | ||
730 | if (!(within(vaddr, PAGE_OFFSET, | |
a1e46212 | 731 | PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) { |
44af6c41 | 732 | |
f34b439f | 733 | alias_cpa = *cpa; |
992f4c1c | 734 | alias_cpa.vaddr = &laddr; |
9ae28475 | 735 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); |
d75586ad | 736 | |
f34b439f | 737 | ret = __change_page_attr_set_clr(&alias_cpa, 0); |
992f4c1c TH |
738 | if (ret) |
739 | return ret; | |
f34b439f | 740 | } |
44af6c41 | 741 | |
44af6c41 | 742 | #ifdef CONFIG_X86_64 |
488fd995 | 743 | /* |
992f4c1c TH |
744 | * If the primary call didn't touch the high mapping already |
745 | * and the physical address is inside the kernel map, we need | |
0879750f | 746 | * to touch the high mapped kernel as well: |
488fd995 | 747 | */ |
992f4c1c TH |
748 | if (!within(vaddr, (unsigned long)_text, _brk_end) && |
749 | within(cpa->pfn, highmap_start_pfn(), highmap_end_pfn())) { | |
750 | unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) + | |
751 | __START_KERNEL_map - phys_base; | |
752 | alias_cpa = *cpa; | |
753 | alias_cpa.vaddr = &temp_cpa_vaddr; | |
754 | alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY); | |
c31c7d48 | 755 | |
992f4c1c TH |
756 | /* |
757 | * The high mapping range is imprecise, so ignore the | |
758 | * return value. | |
759 | */ | |
760 | __change_page_attr_set_clr(&alias_cpa, 0); | |
761 | } | |
488fd995 | 762 | #endif |
992f4c1c TH |
763 | |
764 | return 0; | |
1da177e4 LT |
765 | } |
766 | ||
c31c7d48 | 767 | static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias) |
ff31452b | 768 | { |
65e074df | 769 | int ret, numpages = cpa->numpages; |
ff31452b | 770 | |
65e074df TG |
771 | while (numpages) { |
772 | /* | |
773 | * Store the remaining nr of pages for the large page | |
774 | * preservation check. | |
775 | */ | |
9b5cf48b | 776 | cpa->numpages = numpages; |
d75586ad | 777 | /* for array changes, we can't use large page */ |
9ae28475 | 778 | if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
d75586ad | 779 | cpa->numpages = 1; |
c31c7d48 | 780 | |
ad5ca55f SS |
781 | if (!debug_pagealloc) |
782 | spin_lock(&cpa_lock); | |
c31c7d48 | 783 | ret = __change_page_attr(cpa, checkalias); |
ad5ca55f SS |
784 | if (!debug_pagealloc) |
785 | spin_unlock(&cpa_lock); | |
ff31452b TG |
786 | if (ret) |
787 | return ret; | |
ff31452b | 788 | |
c31c7d48 TG |
789 | if (checkalias) { |
790 | ret = cpa_process_alias(cpa); | |
791 | if (ret) | |
792 | return ret; | |
793 | } | |
794 | ||
65e074df TG |
795 | /* |
796 | * Adjust the number of pages with the result of the | |
797 | * CPA operation. Either a large page has been | |
798 | * preserved or a single page update happened. | |
799 | */ | |
9b5cf48b RW |
800 | BUG_ON(cpa->numpages > numpages); |
801 | numpages -= cpa->numpages; | |
9ae28475 | 802 | if (cpa->flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) |
d75586ad SL |
803 | cpa->curpage++; |
804 | else | |
805 | *cpa->vaddr += cpa->numpages * PAGE_SIZE; | |
806 | ||
65e074df | 807 | } |
ff31452b TG |
808 | return 0; |
809 | } | |
810 | ||
6bb8383b AK |
811 | static inline int cache_attr(pgprot_t attr) |
812 | { | |
813 | return pgprot_val(attr) & | |
814 | (_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD); | |
815 | } | |
816 | ||
d75586ad | 817 | static int change_page_attr_set_clr(unsigned long *addr, int numpages, |
c9caa02c | 818 | pgprot_t mask_set, pgprot_t mask_clr, |
9ae28475 | 819 | int force_split, int in_flag, |
820 | struct page **pages) | |
ff31452b | 821 | { |
72e458df | 822 | struct cpa_data cpa; |
cacf8906 | 823 | int ret, cache, checkalias; |
fa526d0d | 824 | unsigned long baddr = 0; |
331e4065 TG |
825 | |
826 | /* | |
827 | * Check, if we are requested to change a not supported | |
828 | * feature: | |
829 | */ | |
830 | mask_set = canon_pgprot(mask_set); | |
831 | mask_clr = canon_pgprot(mask_clr); | |
c9caa02c | 832 | if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split) |
331e4065 TG |
833 | return 0; |
834 | ||
69b1415e | 835 | /* Ensure we are PAGE_SIZE aligned */ |
9ae28475 | 836 | if (in_flag & CPA_ARRAY) { |
d75586ad SL |
837 | int i; |
838 | for (i = 0; i < numpages; i++) { | |
839 | if (addr[i] & ~PAGE_MASK) { | |
840 | addr[i] &= PAGE_MASK; | |
841 | WARN_ON_ONCE(1); | |
842 | } | |
843 | } | |
9ae28475 | 844 | } else if (!(in_flag & CPA_PAGES_ARRAY)) { |
845 | /* | |
846 | * in_flag of CPA_PAGES_ARRAY implies it is aligned. | |
847 | * No need to cehck in that case | |
848 | */ | |
849 | if (*addr & ~PAGE_MASK) { | |
850 | *addr &= PAGE_MASK; | |
851 | /* | |
852 | * People should not be passing in unaligned addresses: | |
853 | */ | |
854 | WARN_ON_ONCE(1); | |
855 | } | |
fa526d0d JS |
856 | /* |
857 | * Save address for cache flush. *addr is modified in the call | |
858 | * to __change_page_attr_set_clr() below. | |
859 | */ | |
860 | baddr = *addr; | |
69b1415e TG |
861 | } |
862 | ||
5843d9a4 NP |
863 | /* Must avoid aliasing mappings in the highmem code */ |
864 | kmap_flush_unused(); | |
865 | ||
db64fe02 NP |
866 | vm_unmap_aliases(); |
867 | ||
72e458df | 868 | cpa.vaddr = addr; |
9ae28475 | 869 | cpa.pages = pages; |
72e458df TG |
870 | cpa.numpages = numpages; |
871 | cpa.mask_set = mask_set; | |
872 | cpa.mask_clr = mask_clr; | |
d75586ad SL |
873 | cpa.flags = 0; |
874 | cpa.curpage = 0; | |
c9caa02c | 875 | cpa.force_split = force_split; |
72e458df | 876 | |
9ae28475 | 877 | if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY)) |
878 | cpa.flags |= in_flag; | |
d75586ad | 879 | |
af96e443 TG |
880 | /* No alias checking for _NX bit modifications */ |
881 | checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX; | |
882 | ||
883 | ret = __change_page_attr_set_clr(&cpa, checkalias); | |
ff31452b | 884 | |
f4ae5da0 TG |
885 | /* |
886 | * Check whether we really changed something: | |
887 | */ | |
d75586ad | 888 | if (!(cpa.flags & CPA_FLUSHTLB)) |
1ac2f7d5 | 889 | goto out; |
cacf8906 | 890 | |
6bb8383b AK |
891 | /* |
892 | * No need to flush, when we did not set any of the caching | |
893 | * attributes: | |
894 | */ | |
895 | cache = cache_attr(mask_set); | |
896 | ||
57a6a46a TG |
897 | /* |
898 | * On success we use clflush, when the CPU supports it to | |
899 | * avoid the wbindv. If the CPU does not support it and in the | |
af1e6844 | 900 | * error case we fall back to cpa_flush_all (which uses |
57a6a46a TG |
901 | * wbindv): |
902 | */ | |
d75586ad | 903 | if (!ret && cpu_has_clflush) { |
9ae28475 | 904 | if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) { |
905 | cpa_flush_array(addr, numpages, cache, | |
906 | cpa.flags, pages); | |
907 | } else | |
fa526d0d | 908 | cpa_flush_range(baddr, numpages, cache); |
d75586ad | 909 | } else |
6bb8383b | 910 | cpa_flush_all(cache); |
cacf8906 | 911 | |
76ebd054 | 912 | out: |
ff31452b TG |
913 | return ret; |
914 | } | |
915 | ||
d75586ad SL |
916 | static inline int change_page_attr_set(unsigned long *addr, int numpages, |
917 | pgprot_t mask, int array) | |
75cbade8 | 918 | { |
d75586ad | 919 | return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0, |
9ae28475 | 920 | (array ? CPA_ARRAY : 0), NULL); |
75cbade8 AV |
921 | } |
922 | ||
d75586ad SL |
923 | static inline int change_page_attr_clear(unsigned long *addr, int numpages, |
924 | pgprot_t mask, int array) | |
72932c7a | 925 | { |
d75586ad | 926 | return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0, |
9ae28475 | 927 | (array ? CPA_ARRAY : 0), NULL); |
72932c7a TG |
928 | } |
929 | ||
0f350755 | 930 | static inline int cpa_set_pages_array(struct page **pages, int numpages, |
931 | pgprot_t mask) | |
932 | { | |
933 | return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0, | |
934 | CPA_PAGES_ARRAY, pages); | |
935 | } | |
936 | ||
937 | static inline int cpa_clear_pages_array(struct page **pages, int numpages, | |
938 | pgprot_t mask) | |
939 | { | |
940 | return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0, | |
941 | CPA_PAGES_ARRAY, pages); | |
942 | } | |
943 | ||
1219333d | 944 | int _set_memory_uc(unsigned long addr, int numpages) |
72932c7a | 945 | { |
de33c442 SS |
946 | /* |
947 | * for now UC MINUS. see comments in ioremap_nocache() | |
948 | */ | |
d75586ad SL |
949 | return change_page_attr_set(&addr, numpages, |
950 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
75cbade8 | 951 | } |
1219333d | 952 | |
953 | int set_memory_uc(unsigned long addr, int numpages) | |
954 | { | |
9fa3ab39 | 955 | int ret; |
956 | ||
de33c442 SS |
957 | /* |
958 | * for now UC MINUS. see comments in ioremap_nocache() | |
959 | */ | |
9fa3ab39 | 960 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
961 | _PAGE_CACHE_UC_MINUS, NULL); | |
962 | if (ret) | |
963 | goto out_err; | |
964 | ||
965 | ret = _set_memory_uc(addr, numpages); | |
966 | if (ret) | |
967 | goto out_free; | |
968 | ||
969 | return 0; | |
1219333d | 970 | |
9fa3ab39 | 971 | out_free: |
972 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
973 | out_err: | |
974 | return ret; | |
1219333d | 975 | } |
75cbade8 AV |
976 | EXPORT_SYMBOL(set_memory_uc); |
977 | ||
d75586ad SL |
978 | int set_memory_array_uc(unsigned long *addr, int addrinarray) |
979 | { | |
9fa3ab39 | 980 | int i, j; |
981 | int ret; | |
982 | ||
d75586ad SL |
983 | /* |
984 | * for now UC MINUS. see comments in ioremap_nocache() | |
985 | */ | |
986 | for (i = 0; i < addrinarray; i++) { | |
9fa3ab39 | 987 | ret = reserve_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE, |
988 | _PAGE_CACHE_UC_MINUS, NULL); | |
989 | if (ret) | |
990 | goto out_free; | |
d75586ad SL |
991 | } |
992 | ||
9fa3ab39 | 993 | ret = change_page_attr_set(addr, addrinarray, |
d75586ad | 994 | __pgprot(_PAGE_CACHE_UC_MINUS), 1); |
9fa3ab39 | 995 | if (ret) |
996 | goto out_free; | |
997 | ||
998 | return 0; | |
999 | ||
1000 | out_free: | |
1001 | for (j = 0; j < i; j++) | |
1002 | free_memtype(__pa(addr[j]), __pa(addr[j]) + PAGE_SIZE); | |
1003 | ||
1004 | return ret; | |
d75586ad SL |
1005 | } |
1006 | EXPORT_SYMBOL(set_memory_array_uc); | |
1007 | ||
ef354af4 | 1008 | int _set_memory_wc(unsigned long addr, int numpages) |
1009 | { | |
3869c4aa | 1010 | int ret; |
bdc6340f PV |
1011 | unsigned long addr_copy = addr; |
1012 | ||
3869c4aa | 1013 | ret = change_page_attr_set(&addr, numpages, |
1014 | __pgprot(_PAGE_CACHE_UC_MINUS), 0); | |
3869c4aa | 1015 | if (!ret) { |
bdc6340f PV |
1016 | ret = change_page_attr_set_clr(&addr_copy, numpages, |
1017 | __pgprot(_PAGE_CACHE_WC), | |
1018 | __pgprot(_PAGE_CACHE_MASK), | |
1019 | 0, 0, NULL); | |
3869c4aa | 1020 | } |
1021 | return ret; | |
ef354af4 | 1022 | } |
1023 | ||
1024 | int set_memory_wc(unsigned long addr, int numpages) | |
1025 | { | |
9fa3ab39 | 1026 | int ret; |
1027 | ||
499f8f84 | 1028 | if (!pat_enabled) |
ef354af4 | 1029 | return set_memory_uc(addr, numpages); |
1030 | ||
9fa3ab39 | 1031 | ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE, |
1032 | _PAGE_CACHE_WC, NULL); | |
1033 | if (ret) | |
1034 | goto out_err; | |
ef354af4 | 1035 | |
9fa3ab39 | 1036 | ret = _set_memory_wc(addr, numpages); |
1037 | if (ret) | |
1038 | goto out_free; | |
1039 | ||
1040 | return 0; | |
1041 | ||
1042 | out_free: | |
1043 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); | |
1044 | out_err: | |
1045 | return ret; | |
ef354af4 | 1046 | } |
1047 | EXPORT_SYMBOL(set_memory_wc); | |
1048 | ||
1219333d | 1049 | int _set_memory_wb(unsigned long addr, int numpages) |
75cbade8 | 1050 | { |
d75586ad SL |
1051 | return change_page_attr_clear(&addr, numpages, |
1052 | __pgprot(_PAGE_CACHE_MASK), 0); | |
75cbade8 | 1053 | } |
1219333d | 1054 | |
1055 | int set_memory_wb(unsigned long addr, int numpages) | |
1056 | { | |
9fa3ab39 | 1057 | int ret; |
1058 | ||
1059 | ret = _set_memory_wb(addr, numpages); | |
1060 | if (ret) | |
1061 | return ret; | |
1062 | ||
c15238df | 1063 | free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE); |
9fa3ab39 | 1064 | return 0; |
1219333d | 1065 | } |
75cbade8 AV |
1066 | EXPORT_SYMBOL(set_memory_wb); |
1067 | ||
d75586ad SL |
1068 | int set_memory_array_wb(unsigned long *addr, int addrinarray) |
1069 | { | |
1070 | int i; | |
a5593e0b | 1071 | int ret; |
1072 | ||
1073 | ret = change_page_attr_clear(addr, addrinarray, | |
1074 | __pgprot(_PAGE_CACHE_MASK), 1); | |
9fa3ab39 | 1075 | if (ret) |
1076 | return ret; | |
d75586ad | 1077 | |
9fa3ab39 | 1078 | for (i = 0; i < addrinarray; i++) |
1079 | free_memtype(__pa(addr[i]), __pa(addr[i]) + PAGE_SIZE); | |
c5e147cf | 1080 | |
9fa3ab39 | 1081 | return 0; |
d75586ad SL |
1082 | } |
1083 | EXPORT_SYMBOL(set_memory_array_wb); | |
1084 | ||
75cbade8 AV |
1085 | int set_memory_x(unsigned long addr, int numpages) |
1086 | { | |
d75586ad | 1087 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1088 | } |
1089 | EXPORT_SYMBOL(set_memory_x); | |
1090 | ||
1091 | int set_memory_nx(unsigned long addr, int numpages) | |
1092 | { | |
d75586ad | 1093 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0); |
75cbade8 AV |
1094 | } |
1095 | EXPORT_SYMBOL(set_memory_nx); | |
1096 | ||
1097 | int set_memory_ro(unsigned long addr, int numpages) | |
1098 | { | |
d75586ad | 1099 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1100 | } |
a03352d2 | 1101 | EXPORT_SYMBOL_GPL(set_memory_ro); |
75cbade8 AV |
1102 | |
1103 | int set_memory_rw(unsigned long addr, int numpages) | |
1104 | { | |
d75586ad | 1105 | return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0); |
75cbade8 | 1106 | } |
a03352d2 | 1107 | EXPORT_SYMBOL_GPL(set_memory_rw); |
f62d0f00 IM |
1108 | |
1109 | int set_memory_np(unsigned long addr, int numpages) | |
1110 | { | |
d75586ad | 1111 | return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0); |
f62d0f00 | 1112 | } |
75cbade8 | 1113 | |
c9caa02c AK |
1114 | int set_memory_4k(unsigned long addr, int numpages) |
1115 | { | |
d75586ad | 1116 | return change_page_attr_set_clr(&addr, numpages, __pgprot(0), |
9ae28475 | 1117 | __pgprot(0), 1, 0, NULL); |
c9caa02c AK |
1118 | } |
1119 | ||
75cbade8 AV |
1120 | int set_pages_uc(struct page *page, int numpages) |
1121 | { | |
1122 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1123 | |
d7c8f21a | 1124 | return set_memory_uc(addr, numpages); |
75cbade8 AV |
1125 | } |
1126 | EXPORT_SYMBOL(set_pages_uc); | |
1127 | ||
0f350755 | 1128 | int set_pages_array_uc(struct page **pages, int addrinarray) |
1129 | { | |
1130 | unsigned long start; | |
1131 | unsigned long end; | |
1132 | int i; | |
1133 | int free_idx; | |
1134 | ||
1135 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1136 | if (PageHighMem(pages[i])) |
1137 | continue; | |
1138 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1139 | end = start + PAGE_SIZE; |
1140 | if (reserve_memtype(start, end, _PAGE_CACHE_UC_MINUS, NULL)) | |
1141 | goto err_out; | |
1142 | } | |
1143 | ||
1144 | if (cpa_set_pages_array(pages, addrinarray, | |
1145 | __pgprot(_PAGE_CACHE_UC_MINUS)) == 0) { | |
1146 | return 0; /* Success */ | |
1147 | } | |
1148 | err_out: | |
1149 | free_idx = i; | |
1150 | for (i = 0; i < free_idx; i++) { | |
8523acfe TH |
1151 | if (PageHighMem(pages[i])) |
1152 | continue; | |
1153 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1154 | end = start + PAGE_SIZE; |
1155 | free_memtype(start, end); | |
1156 | } | |
1157 | return -EINVAL; | |
1158 | } | |
1159 | EXPORT_SYMBOL(set_pages_array_uc); | |
1160 | ||
75cbade8 AV |
1161 | int set_pages_wb(struct page *page, int numpages) |
1162 | { | |
1163 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1164 | |
d7c8f21a | 1165 | return set_memory_wb(addr, numpages); |
75cbade8 AV |
1166 | } |
1167 | EXPORT_SYMBOL(set_pages_wb); | |
1168 | ||
0f350755 | 1169 | int set_pages_array_wb(struct page **pages, int addrinarray) |
1170 | { | |
1171 | int retval; | |
1172 | unsigned long start; | |
1173 | unsigned long end; | |
1174 | int i; | |
1175 | ||
1176 | retval = cpa_clear_pages_array(pages, addrinarray, | |
1177 | __pgprot(_PAGE_CACHE_MASK)); | |
9fa3ab39 | 1178 | if (retval) |
1179 | return retval; | |
0f350755 | 1180 | |
1181 | for (i = 0; i < addrinarray; i++) { | |
8523acfe TH |
1182 | if (PageHighMem(pages[i])) |
1183 | continue; | |
1184 | start = page_to_pfn(pages[i]) << PAGE_SHIFT; | |
0f350755 | 1185 | end = start + PAGE_SIZE; |
1186 | free_memtype(start, end); | |
1187 | } | |
1188 | ||
9fa3ab39 | 1189 | return 0; |
0f350755 | 1190 | } |
1191 | EXPORT_SYMBOL(set_pages_array_wb); | |
1192 | ||
75cbade8 AV |
1193 | int set_pages_x(struct page *page, int numpages) |
1194 | { | |
1195 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1196 | |
d7c8f21a | 1197 | return set_memory_x(addr, numpages); |
75cbade8 AV |
1198 | } |
1199 | EXPORT_SYMBOL(set_pages_x); | |
1200 | ||
1201 | int set_pages_nx(struct page *page, int numpages) | |
1202 | { | |
1203 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1204 | |
d7c8f21a | 1205 | return set_memory_nx(addr, numpages); |
75cbade8 AV |
1206 | } |
1207 | EXPORT_SYMBOL(set_pages_nx); | |
1208 | ||
1209 | int set_pages_ro(struct page *page, int numpages) | |
1210 | { | |
1211 | unsigned long addr = (unsigned long)page_address(page); | |
75cbade8 | 1212 | |
d7c8f21a | 1213 | return set_memory_ro(addr, numpages); |
75cbade8 | 1214 | } |
75cbade8 AV |
1215 | |
1216 | int set_pages_rw(struct page *page, int numpages) | |
1217 | { | |
1218 | unsigned long addr = (unsigned long)page_address(page); | |
e81d5dc4 | 1219 | |
d7c8f21a | 1220 | return set_memory_rw(addr, numpages); |
78c94aba IM |
1221 | } |
1222 | ||
1da177e4 | 1223 | #ifdef CONFIG_DEBUG_PAGEALLOC |
f62d0f00 IM |
1224 | |
1225 | static int __set_pages_p(struct page *page, int numpages) | |
1226 | { | |
d75586ad SL |
1227 | unsigned long tempaddr = (unsigned long) page_address(page); |
1228 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1229 | .numpages = numpages, |
1230 | .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW), | |
d75586ad SL |
1231 | .mask_clr = __pgprot(0), |
1232 | .flags = 0}; | |
72932c7a | 1233 | |
55121b43 SS |
1234 | /* |
1235 | * No alias checking needed for setting present flag. otherwise, | |
1236 | * we may need to break large pages for 64-bit kernel text | |
1237 | * mappings (this adds to complexity if we want to do this from | |
1238 | * atomic context especially). Let's keep it simple! | |
1239 | */ | |
1240 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1241 | } |
1242 | ||
1243 | static int __set_pages_np(struct page *page, int numpages) | |
1244 | { | |
d75586ad SL |
1245 | unsigned long tempaddr = (unsigned long) page_address(page); |
1246 | struct cpa_data cpa = { .vaddr = &tempaddr, | |
72e458df TG |
1247 | .numpages = numpages, |
1248 | .mask_set = __pgprot(0), | |
d75586ad SL |
1249 | .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW), |
1250 | .flags = 0}; | |
72932c7a | 1251 | |
55121b43 SS |
1252 | /* |
1253 | * No alias checking needed for setting not present flag. otherwise, | |
1254 | * we may need to break large pages for 64-bit kernel text | |
1255 | * mappings (this adds to complexity if we want to do this from | |
1256 | * atomic context especially). Let's keep it simple! | |
1257 | */ | |
1258 | return __change_page_attr_set_clr(&cpa, 0); | |
f62d0f00 IM |
1259 | } |
1260 | ||
1da177e4 LT |
1261 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1262 | { | |
1263 | if (PageHighMem(page)) | |
1264 | return; | |
9f4c815c | 1265 | if (!enable) { |
f9b8404c IM |
1266 | debug_check_no_locks_freed(page_address(page), |
1267 | numpages * PAGE_SIZE); | |
9f4c815c | 1268 | } |
de5097c2 | 1269 | |
12d6f21e IM |
1270 | /* |
1271 | * If page allocator is not up yet then do not call c_p_a(): | |
1272 | */ | |
1273 | if (!debug_pagealloc_enabled) | |
1274 | return; | |
1275 | ||
9f4c815c | 1276 | /* |
f8d8406b | 1277 | * The return value is ignored as the calls cannot fail. |
55121b43 SS |
1278 | * Large pages for identity mappings are not used at boot time |
1279 | * and hence no memory allocations during large page split. | |
1da177e4 | 1280 | */ |
f62d0f00 IM |
1281 | if (enable) |
1282 | __set_pages_p(page, numpages); | |
1283 | else | |
1284 | __set_pages_np(page, numpages); | |
9f4c815c IM |
1285 | |
1286 | /* | |
e4b71dcf IM |
1287 | * We should perform an IPI and flush all tlbs, |
1288 | * but that can deadlock->flush only current cpu: | |
1da177e4 LT |
1289 | */ |
1290 | __flush_tlb_all(); | |
ee7ae7a1 TG |
1291 | } |
1292 | ||
8a235efa RW |
1293 | #ifdef CONFIG_HIBERNATION |
1294 | ||
1295 | bool kernel_page_present(struct page *page) | |
1296 | { | |
1297 | unsigned int level; | |
1298 | pte_t *pte; | |
1299 | ||
1300 | if (PageHighMem(page)) | |
1301 | return false; | |
1302 | ||
1303 | pte = lookup_address((unsigned long)page_address(page), &level); | |
1304 | return (pte_val(*pte) & _PAGE_PRESENT); | |
1305 | } | |
1306 | ||
1307 | #endif /* CONFIG_HIBERNATION */ | |
1308 | ||
1309 | #endif /* CONFIG_DEBUG_PAGEALLOC */ | |
d1028a15 AV |
1310 | |
1311 | /* | |
1312 | * The testcases use internal knowledge of the implementation that shouldn't | |
1313 | * be exposed to the rest of the kernel. Include these directly here. | |
1314 | */ | |
1315 | #ifdef CONFIG_CPA_DEBUG | |
1316 | #include "pageattr-test.c" | |
1317 | #endif |