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9f4c815c IM |
1 | /* |
2 | * Copyright 2002 Andi Kleen, SuSE Labs. | |
1da177e4 | 3 | * Thanks to Ben LaHaise for precious feedback. |
9f4c815c | 4 | */ |
1da177e4 | 5 | |
1da177e4 LT |
6 | #include <linux/highmem.h> |
7 | #include <linux/module.h> | |
9f4c815c | 8 | #include <linux/sched.h> |
1da177e4 | 9 | #include <linux/slab.h> |
9f4c815c IM |
10 | #include <linux/mm.h> |
11 | ||
4554ab95 IM |
12 | void clflush_cache_range(void *addr, int size) |
13 | { | |
14 | int i; | |
15 | ||
16 | for (i = 0; i < size; i += boot_cpu_data.x86_clflush_size) | |
17 | clflush(addr+i); | |
18 | } | |
19 | ||
1da177e4 LT |
20 | #include <asm/processor.h> |
21 | #include <asm/tlbflush.h> | |
f8af095d | 22 | #include <asm/sections.h> |
9f4c815c IM |
23 | #include <asm/uaccess.h> |
24 | #include <asm/pgalloc.h> | |
1da177e4 | 25 | |
f0646e43 | 26 | pte_t *lookup_address(unsigned long address, int *level) |
9f4c815c | 27 | { |
1da177e4 LT |
28 | pgd_t *pgd = pgd_offset_k(address); |
29 | pud_t *pud; | |
30 | pmd_t *pmd; | |
9f4c815c | 31 | |
1da177e4 LT |
32 | if (pgd_none(*pgd)) |
33 | return NULL; | |
34 | pud = pud_offset(pgd, address); | |
35 | if (pud_none(*pud)) | |
36 | return NULL; | |
37 | pmd = pmd_offset(pud, address); | |
38 | if (pmd_none(*pmd)) | |
39 | return NULL; | |
bbb09f5c | 40 | *level = 3; |
1da177e4 LT |
41 | if (pmd_large(*pmd)) |
42 | return (pte_t *)pmd; | |
bbb09f5c | 43 | *level = 4; |
1da177e4 | 44 | |
9f4c815c IM |
45 | return pte_offset_kernel(pmd, address); |
46 | } | |
47 | ||
9a3dc780 | 48 | static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte) |
9f4c815c | 49 | { |
9f4c815c IM |
50 | /* change init_mm */ |
51 | set_pte_atomic(kpte, pte); | |
44af6c41 | 52 | #ifdef CONFIG_X86_32 |
5311ab62 | 53 | if (SHARED_KERNEL_PMD) |
1da177e4 | 54 | return; |
44af6c41 IM |
55 | { |
56 | struct page *page; | |
57 | ||
58 | for (page = pgd_list; page; page = (struct page *)page->index) { | |
59 | pgd_t *pgd; | |
60 | pud_t *pud; | |
61 | pmd_t *pmd; | |
62 | ||
63 | pgd = (pgd_t *)page_address(page) + pgd_index(address); | |
64 | pud = pud_offset(pgd, address); | |
65 | pmd = pmd_offset(pud, address); | |
66 | set_pte_atomic((pte_t *)pmd, pte); | |
67 | } | |
1da177e4 | 68 | } |
44af6c41 | 69 | #endif |
1da177e4 LT |
70 | } |
71 | ||
7afe15b9 | 72 | static int split_large_page(pte_t *kpte, unsigned long address) |
bb5c2dbd | 73 | { |
7afe15b9 | 74 | pgprot_t ref_prot = pte_pgprot(pte_clrhuge(*kpte)); |
12d6f21e | 75 | gfp_t gfp_flags = GFP_KERNEL; |
9a3dc780 | 76 | unsigned long flags; |
bb5c2dbd IM |
77 | unsigned long addr; |
78 | pte_t *pbase, *tmp; | |
79 | struct page *base; | |
7afe15b9 | 80 | int i, level; |
bb5c2dbd | 81 | |
12d6f21e IM |
82 | #ifdef CONFIG_DEBUG_PAGEALLOC |
83 | gfp_flags = GFP_ATOMIC; | |
84 | #endif | |
85 | base = alloc_pages(gfp_flags, 0); | |
bb5c2dbd IM |
86 | if (!base) |
87 | return -ENOMEM; | |
88 | ||
9a3dc780 | 89 | spin_lock_irqsave(&pgd_lock, flags); |
bb5c2dbd IM |
90 | /* |
91 | * Check for races, another CPU might have split this page | |
92 | * up for us already: | |
93 | */ | |
94 | tmp = lookup_address(address, &level); | |
5508a748 IM |
95 | if (tmp != kpte) { |
96 | WARN_ON_ONCE(1); | |
bb5c2dbd | 97 | goto out_unlock; |
5508a748 | 98 | } |
bb5c2dbd IM |
99 | |
100 | address = __pa(address); | |
101 | addr = address & LARGE_PAGE_MASK; | |
102 | pbase = (pte_t *)page_address(base); | |
44af6c41 | 103 | #ifdef CONFIG_X86_32 |
bb5c2dbd | 104 | paravirt_alloc_pt(&init_mm, page_to_pfn(base)); |
44af6c41 | 105 | #endif |
bb5c2dbd IM |
106 | |
107 | for (i = 0; i < PTRS_PER_PTE; i++, addr += PAGE_SIZE) | |
108 | set_pte(&pbase[i], pfn_pte(addr >> PAGE_SHIFT, ref_prot)); | |
109 | ||
110 | /* | |
111 | * Install the new, split up pagetable: | |
112 | */ | |
9a3dc780 | 113 | __set_pmd_pte(kpte, address, mk_pte(base, ref_prot)); |
bb5c2dbd IM |
114 | base = NULL; |
115 | ||
116 | out_unlock: | |
9a3dc780 | 117 | spin_unlock_irqrestore(&pgd_lock, flags); |
bb5c2dbd IM |
118 | |
119 | if (base) | |
120 | __free_pages(base, 0); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
44af6c41 IM |
125 | static int |
126 | __change_page_attr(unsigned long address, struct page *page, pgprot_t prot) | |
9f4c815c | 127 | { |
1da177e4 | 128 | struct page *kpte_page; |
bb5c2dbd | 129 | int level, err = 0; |
9f4c815c | 130 | pte_t *kpte; |
1da177e4 LT |
131 | |
132 | BUG_ON(PageHighMem(page)); | |
1da177e4 | 133 | |
97f99fed | 134 | repeat: |
f0646e43 | 135 | kpte = lookup_address(address, &level); |
1da177e4 LT |
136 | if (!kpte) |
137 | return -EINVAL; | |
9f4c815c | 138 | |
1da177e4 | 139 | kpte_page = virt_to_page(kpte); |
65d2f0bc AK |
140 | BUG_ON(PageLRU(kpte_page)); |
141 | BUG_ON(PageCompound(kpte_page)); | |
142 | ||
1da177e4 | 143 | /* |
78c94aba IM |
144 | * Better fail early if someone sets the kernel text to NX. |
145 | * Does not cover __inittext | |
1da177e4 | 146 | */ |
78c94aba IM |
147 | BUG_ON(address >= (unsigned long)&_text && |
148 | address < (unsigned long)&_etext && | |
149 | (pgprot_val(prot) & _PAGE_NX)); | |
65d2f0bc | 150 | |
bbb09f5c | 151 | if (level == 4) { |
7afe15b9 | 152 | set_pte_atomic(kpte, mk_pte(page, canon_pgprot(prot))); |
78c94aba | 153 | } else { |
7afe15b9 | 154 | err = split_large_page(kpte, address); |
bb5c2dbd IM |
155 | if (!err) |
156 | goto repeat; | |
1da177e4 | 157 | } |
bb5c2dbd | 158 | return err; |
9f4c815c | 159 | } |
1da177e4 | 160 | |
44af6c41 IM |
161 | /** |
162 | * change_page_attr_addr - Change page table attributes in linear mapping | |
163 | * @address: Virtual address in linear mapping. | |
164 | * @numpages: Number of pages to change | |
165 | * @prot: New page table attribute (PAGE_*) | |
1da177e4 | 166 | * |
44af6c41 IM |
167 | * Change page attributes of a page in the direct mapping. This is a variant |
168 | * of change_page_attr() that also works on memory holes that do not have | |
169 | * mem_map entry (pfn_valid() is false). | |
9f4c815c | 170 | * |
44af6c41 | 171 | * See change_page_attr() documentation for more details. |
1da177e4 | 172 | */ |
44af6c41 IM |
173 | |
174 | int change_page_attr_addr(unsigned long address, int numpages, pgprot_t prot) | |
1da177e4 | 175 | { |
44af6c41 IM |
176 | int err = 0, kernel_map = 0, i; |
177 | ||
178 | #ifdef CONFIG_X86_64 | |
179 | if (address >= __START_KERNEL_map && | |
180 | address < __START_KERNEL_map + KERNEL_TEXT_SIZE) { | |
1da177e4 | 181 | |
44af6c41 IM |
182 | address = (unsigned long)__va(__pa(address)); |
183 | kernel_map = 1; | |
184 | } | |
185 | #endif | |
186 | ||
187 | for (i = 0; i < numpages; i++, address += PAGE_SIZE) { | |
188 | unsigned long pfn = __pa(address) >> PAGE_SHIFT; | |
189 | ||
190 | if (!kernel_map || pte_present(pfn_pte(0, prot))) { | |
191 | err = __change_page_attr(address, pfn_to_page(pfn), prot); | |
192 | if (err) | |
193 | break; | |
194 | } | |
195 | #ifdef CONFIG_X86_64 | |
196 | /* | |
197 | * Handle kernel mapping too which aliases part of | |
198 | * lowmem: | |
199 | */ | |
200 | if (__pa(address) < KERNEL_TEXT_SIZE) { | |
201 | unsigned long addr2; | |
202 | pgprot_t prot2; | |
203 | ||
204 | addr2 = __START_KERNEL_map + __pa(address); | |
205 | /* Make sure the kernel mappings stay executable */ | |
206 | prot2 = pte_pgprot(pte_mkexec(pfn_pte(0, prot))); | |
207 | err = __change_page_attr(addr2, pfn_to_page(pfn), prot2); | |
208 | } | |
209 | #endif | |
9f4c815c | 210 | } |
9f4c815c | 211 | |
1da177e4 LT |
212 | return err; |
213 | } | |
214 | ||
44af6c41 IM |
215 | /** |
216 | * change_page_attr - Change page table attributes in the linear mapping. | |
217 | * @page: First page to change | |
218 | * @numpages: Number of pages to change | |
219 | * @prot: New protection/caching type (PAGE_*) | |
220 | * | |
221 | * Returns 0 on success, otherwise a negated errno. | |
222 | * | |
223 | * This should be used when a page is mapped with a different caching policy | |
224 | * than write-back somewhere - some CPUs do not like it when mappings with | |
225 | * different caching policies exist. This changes the page attributes of the | |
226 | * in kernel linear mapping too. | |
227 | * | |
228 | * Caller must call global_flush_tlb() later to make the changes active. | |
229 | * | |
230 | * The caller needs to ensure that there are no conflicting mappings elsewhere | |
231 | * (e.g. in user space) * This function only deals with the kernel linear map. | |
232 | * | |
233 | * For MMIO areas without mem_map use change_page_attr_addr() instead. | |
234 | */ | |
235 | int change_page_attr(struct page *page, int numpages, pgprot_t prot) | |
626ab0e6 | 236 | { |
44af6c41 | 237 | unsigned long addr = (unsigned long)page_address(page); |
5508a748 | 238 | |
44af6c41 | 239 | return change_page_attr_addr(addr, numpages, prot); |
78c94aba | 240 | } |
44af6c41 | 241 | EXPORT_SYMBOL(change_page_attr); |
78c94aba IM |
242 | |
243 | static void flush_kernel_map(void *arg) | |
244 | { | |
245 | /* | |
246 | * Flush all to work around Errata in early athlons regarding | |
247 | * large page flushing. | |
248 | */ | |
249 | __flush_tlb_all(); | |
250 | ||
251 | if (boot_cpu_data.x86_model >= 4) | |
252 | wbinvd(); | |
253 | } | |
254 | ||
255 | void global_flush_tlb(void) | |
256 | { | |
1da177e4 LT |
257 | BUG_ON(irqs_disabled()); |
258 | ||
78c94aba | 259 | on_each_cpu(flush_kernel_map, NULL, 1, 1); |
626ab0e6 | 260 | } |
9f4c815c | 261 | EXPORT_SYMBOL(global_flush_tlb); |
1da177e4 LT |
262 | |
263 | #ifdef CONFIG_DEBUG_PAGEALLOC | |
264 | void kernel_map_pages(struct page *page, int numpages, int enable) | |
265 | { | |
266 | if (PageHighMem(page)) | |
267 | return; | |
9f4c815c | 268 | if (!enable) { |
f9b8404c IM |
269 | debug_check_no_locks_freed(page_address(page), |
270 | numpages * PAGE_SIZE); | |
9f4c815c | 271 | } |
de5097c2 | 272 | |
12d6f21e IM |
273 | /* |
274 | * If page allocator is not up yet then do not call c_p_a(): | |
275 | */ | |
276 | if (!debug_pagealloc_enabled) | |
277 | return; | |
278 | ||
9f4c815c IM |
279 | /* |
280 | * the return value is ignored - the calls cannot fail, | |
1da177e4 LT |
281 | * large pages are disabled at boot time. |
282 | */ | |
283 | change_page_attr(page, numpages, enable ? PAGE_KERNEL : __pgprot(0)); | |
9f4c815c IM |
284 | |
285 | /* | |
286 | * we should perform an IPI and flush all tlbs, | |
1da177e4 LT |
287 | * but that can deadlock->flush only current cpu. |
288 | */ | |
289 | __flush_tlb_all(); | |
290 | } | |
291 | #endif |