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perf & kvm: Clean up some of the guest profiling callback API details
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
ff9d07a0 43#include <linux/perf_event.h>
aec51dc4
AK		 44#include <trace/events/kvm.h>
45#undef TRACE_INCLUDE_FILE
229456fc
MT		 46#define CREATE_TRACE_POINTS
47#include "trace.h"
043405e1 48
24f1e32c 49#include <asm/debugreg.h>
043405e1 50#include <asm/uaccess.h>
d825ed0a 51#include <asm/msr.h>
a5f61300 52#include <asm/desc.h>
0bed3b56 53#include <asm/mtrr.h>
890ca9ae 54#include <asm/mce.h>
043405e1 55
313a3dc7 56#define MAX_IO_MSRS 256
a03490ed
CO		 57#define CR0_RESERVED_BITS \
58 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
59 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
60 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
61#define CR4_RESERVED_BITS \
62 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
63 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
64 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
65 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
66
67#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 68
69#define KVM_MAX_MCE_BANKS 32
70#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
77static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
78#else
79static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 86static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
87 struct kvm_cpuid_entry2 __user *entries);
88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
ed85c068
AP		 92int ignore_msrs = 0;
93module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
18863bdd
AK		 150static void kvm_on_user_return(struct user_return_notifier *urn)
151{
152 unsigned slot;
18863bdd
AK		 153 struct kvm_shared_msrs *locals
154 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 155 struct kvm_shared_msr_values *values;
18863bdd
AK		 156
157 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 158 values = &locals->values[slot];
159 if (values->host != values->curr) {
160 wrmsrl(shared_msrs_global.msrs[slot], values->host);
161 values->curr = values->host;
18863bdd
AK		 162 }
163 }
164 locals->registered = false;
165 user_return_notifier_unregister(urn);
166}
167
2bf78fa7 168static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 169{
2bf78fa7 170 struct kvm_shared_msrs *smsr;
18863bdd
AK		 171 u64 value;
172
2bf78fa7
SY		 173 smsr = &__get_cpu_var(shared_msrs);
174 /* only read, and nobody should modify it at this time,
175 * so don't need lock */
176 if (slot >= shared_msrs_global.nr) {
177 printk(KERN_ERR "kvm: invalid MSR slot!");
178 return;
179 }
180 rdmsrl_safe(msr, &value);
181 smsr->values[slot].host = value;
182 smsr->values[slot].curr = value;
183}
184
185void kvm_define_shared_msr(unsigned slot, u32 msr)
186{
18863bdd
AK		 187 if (slot >= shared_msrs_global.nr)
188 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 189 shared_msrs_global.msrs[slot] = msr;
190 /* we need ensured the shared_msr_global have been updated */
191 smp_wmb();
18863bdd
AK		 192}
193EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
194
195static void kvm_shared_msr_cpu_online(void)
196{
197 unsigned i;
18863bdd
AK		 198
199 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 200 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 201}
202
d5696725 203void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 204{
205 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
206
2bf78fa7 207 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 208 return;
2bf78fa7
SY		 209 smsr->values[slot].curr = value;
210 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 211 if (!smsr->registered) {
212 smsr->urn.on_user_return = kvm_on_user_return;
213 user_return_notifier_register(&smsr->urn);
214 smsr->registered = true;
215 }
216}
217EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
218
3548bab5
AK		 219static void drop_user_return_notifiers(void *ignore)
220{
221 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
222
223 if (smsr->registered)
224 kvm_on_user_return(&smsr->urn);
225}
226
5fb76f9b
CO		 227unsigned long segment_base(u16 selector)
228{
229 struct descriptor_table gdt;
a5f61300 230 struct desc_struct *d;
5fb76f9b
CO		 231 unsigned long table_base;
232 unsigned long v;
233
234 if (selector == 0)
235 return 0;
236
b792c344 237 kvm_get_gdt(&gdt);
5fb76f9b
CO		 238 table_base = gdt.base;
239
240 if (selector & 4) { /* from ldt */
b792c344 241 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 242
5fb76f9b
CO		 243 table_base = segment_base(ldt_selector);
244 }
a5f61300 245 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 246 v = get_desc_base(d);
5fb76f9b 247#ifdef CONFIG_X86_64
a5f61300
AK		 248 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
249 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 250#endif
251 return v;
252}
253EXPORT_SYMBOL_GPL(segment_base);
254
6866b83e
CO		 255u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
256{
257 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 258 return vcpu->arch.apic_base;
6866b83e 259 else
ad312c7c 260 return vcpu->arch.apic_base;
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_get_apic_base);
263
264void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
265{
266 /* TODO: reserve bits check */
267 if (irqchip_in_kernel(vcpu->kvm))
268 kvm_lapic_set_base(vcpu, data);
269 else
ad312c7c 270 vcpu->arch.apic_base = data;
6866b83e
CO		 271}
272EXPORT_SYMBOL_GPL(kvm_set_apic_base);
273
3fd28fce
ED		 274#define EXCPT_BENIGN 0
275#define EXCPT_CONTRIBUTORY 1
276#define EXCPT_PF 2
277
278static int exception_class(int vector)
279{
280 switch (vector) {
281 case PF_VECTOR:
282 return EXCPT_PF;
283 case DE_VECTOR:
284 case TS_VECTOR:
285 case NP_VECTOR:
286 case SS_VECTOR:
287 case GP_VECTOR:
288 return EXCPT_CONTRIBUTORY;
289 default:
290 break;
291 }
292 return EXCPT_BENIGN;
293}
294
295static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
296 unsigned nr, bool has_error, u32 error_code)
297{
298 u32 prev_nr;
299 int class1, class2;
300
301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
307 return;
308 }
309
310 /* to check exception */
311 prev_nr = vcpu->arch.exception.nr;
312 if (prev_nr == DF_VECTOR) {
313 /* triple fault -> shutdown */
314 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
315 return;
316 }
317 class1 = exception_class(prev_nr);
318 class2 = exception_class(nr);
319 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
320 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
321 /* generate double fault per SDM Table 5-5 */
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = true;
324 vcpu->arch.exception.nr = DF_VECTOR;
325 vcpu->arch.exception.error_code = 0;
326 } else
327 /* replace previous exception with a new one in a hope
328 that instruction re-execution will regenerate lost
329 exception */
330 goto queue;
331}
332
298101da
AK		 333void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
334{
3fd28fce 335 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 336}
337EXPORT_SYMBOL_GPL(kvm_queue_exception);
338
c3c91fee
AK		 339void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
340 u32 error_code)
341{
342 ++vcpu->stat.pf_guest;
ad312c7c 343 vcpu->arch.cr2 = addr;
c3c91fee
AK		 344 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
345}
346
3419ffc8
SY		 347void kvm_inject_nmi(struct kvm_vcpu *vcpu)
348{
349 vcpu->arch.nmi_pending = 1;
350}
351EXPORT_SYMBOL_GPL(kvm_inject_nmi);
352
298101da
AK		 353void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
354{
3fd28fce 355 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
358
0a79b009
AK		 359/*
360 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
361 * a #GP and return false.
362 */
363bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 364{
0a79b009
AK		 365 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
366 return true;
367 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
368 return false;
298101da 369}
0a79b009 370EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 371
a03490ed
CO		 372/*
373 * Load the pae pdptrs. Return true is they are all valid.
374 */
375int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
376{
377 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
378 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
379 int i;
380 int ret;
ad312c7c 381 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 382
a03490ed
CO		 383 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
384 offset * sizeof(u64), sizeof(pdpte));
385 if (ret < 0) {
386 ret = 0;
387 goto out;
388 }
389 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 390 if (is_present_gpte(pdpte[i]) &&
20c466b5 391 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 392 ret = 0;
393 goto out;
394 }
395 }
396 ret = 1;
397
ad312c7c 398 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 399 __set_bit(VCPU_EXREG_PDPTR,
400 (unsigned long *)&vcpu->arch.regs_avail);
401 __set_bit(VCPU_EXREG_PDPTR,
402 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 403out:
a03490ed
CO		 404
405 return ret;
406}
cc4b6871 407EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 408
d835dfec
AK		 409static bool pdptrs_changed(struct kvm_vcpu *vcpu)
410{
ad312c7c 411 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 412 bool changed = true;
413 int r;
414
415 if (is_long_mode(vcpu) || !is_pae(vcpu))
416 return false;
417
6de4f3ad
AK		 418 if (!test_bit(VCPU_EXREG_PDPTR,
419 (unsigned long *)&vcpu->arch.regs_avail))
420 return true;
421
ad312c7c 422 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 423 if (r < 0)
424 goto out;
ad312c7c 425 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 426out:
d835dfec
AK		 427
428 return changed;
429}
430
2d3ad1f4 431void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 432{
f9a48e6a
AK		 433 cr0 |= X86_CR0_ET;
434
ab344828
GN		 435#ifdef CONFIG_X86_64
436 if (cr0 & 0xffffffff00000000UL) {
a03490ed 437 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
4d4ec087 438 cr0, kvm_read_cr0(vcpu));
c1a5d4f9 439 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 440 return;
441 }
ab344828
GN		 442#endif
443
444 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 445
446 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
447 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 448 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 449 return;
450 }
451
452 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
453 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
454 "and a clear PE flag\n");
c1a5d4f9 455 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 456 return;
457 }
458
459 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
460#ifdef CONFIG_X86_64
f6801dff 461 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 462 int cs_db, cs_l;
463
464 if (!is_pae(vcpu)) {
465 printk(KERN_DEBUG "set_cr0: #GP, start paging "
466 "in long mode while PAE is disabled\n");
c1a5d4f9 467 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 468 return;
469 }
470 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
471 if (cs_l) {
472 printk(KERN_DEBUG "set_cr0: #GP, start paging "
473 "in long mode while CS.L == 1\n");
c1a5d4f9 474 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 475 return;
476
477 }
478 } else
479#endif
ad312c7c 480 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 481 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
482 "reserved bits\n");
c1a5d4f9 483 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 484 return;
485 }
486
487 }
488
489 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 490 vcpu->arch.cr0 = cr0;
a03490ed 491
a03490ed 492 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 493 return;
494}
2d3ad1f4 495EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 496
2d3ad1f4 497void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 498{
4d4ec087 499 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 500}
2d3ad1f4 501EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 502
2d3ad1f4 503void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 504{
fc78f519 505 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 506 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
507
a03490ed
CO		 508 if (cr4 & CR4_RESERVED_BITS) {
509 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 510 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 511 return;
512 }
513
514 if (is_long_mode(vcpu)) {
515 if (!(cr4 & X86_CR4_PAE)) {
516 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
517 "in long mode\n");
c1a5d4f9 518 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 519 return;
520 }
a2edf57f
AK		 521 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
522 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 523 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 524 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 525 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 526 return;
527 }
528
529 if (cr4 & X86_CR4_VMXE) {
530 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 531 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 532 return;
533 }
534 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 535 vcpu->arch.cr4 = cr4;
5a41accd 536 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 537 kvm_mmu_reset_context(vcpu);
a03490ed 538}
2d3ad1f4 539EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 540
2d3ad1f4 541void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 542{
ad312c7c 543 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 544 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 545 kvm_mmu_flush_tlb(vcpu);
546 return;
547 }
548
a03490ed
CO		 549 if (is_long_mode(vcpu)) {
550 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
551 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 552 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 553 return;
554 }
555 } else {
556 if (is_pae(vcpu)) {
557 if (cr3 & CR3_PAE_RESERVED_BITS) {
558 printk(KERN_DEBUG
559 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 560 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 561 return;
562 }
563 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
564 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
565 "reserved bits\n");
c1a5d4f9 566 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 567 return;
568 }
569 }
570 /*
571 * We don't check reserved bits in nonpae mode, because
572 * this isn't enforced, and VMware depends on this.
573 */
574 }
575
a03490ed
CO		 576 /*
577 * Does the new cr3 value map to physical memory? (Note, we
578 * catch an invalid cr3 even in real-mode, because it would
579 * cause trouble later on when we turn on paging anyway.)
580 *
581 * A real CPU would silently accept an invalid cr3 and would
582 * attempt to use it - with largely undefined (and often hard
583 * to debug) behavior on the guest side.
584 */
585 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 586 kvm_inject_gp(vcpu, 0);
a03490ed 587 else {
ad312c7c
ZX		 588 vcpu->arch.cr3 = cr3;
589 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 590 }
a03490ed 591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 593
2d3ad1f4 594void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 595{
596 if (cr8 & CR8_RESERVED_BITS) {
597 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 598 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 599 return;
600 }
601 if (irqchip_in_kernel(vcpu->kvm))
602 kvm_lapic_set_tpr(vcpu, cr8);
603 else
ad312c7c 604 vcpu->arch.cr8 = cr8;
a03490ed 605}
2d3ad1f4 606EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 607
2d3ad1f4 608unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 609{
610 if (irqchip_in_kernel(vcpu->kvm))
611 return kvm_lapic_get_cr8(vcpu);
612 else
ad312c7c 613 return vcpu->arch.cr8;
a03490ed 614}
2d3ad1f4 615EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 616
d8017474
AG		 617static inline u32 bit(int bitno)
618{
619 return 1 << (bitno & 31);
620}
621
043405e1
CO		 622/*
623 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
624 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
625 *
626 * This list is modified at module load time to reflect the
e3267cbb
GC		 627 * capabilities of the host cpu. This capabilities test skips MSRs that are
628 * kvm-specific. Those are put in the beginning of the list.
043405e1 629 */
e3267cbb 630
10388a07 631#define KVM_SAVE_MSRS_BEGIN 5
043405e1 632static u32 msrs_to_save[] = {
e3267cbb 633 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 634 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 635 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 636 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
637 MSR_K6_STAR,
638#ifdef CONFIG_X86_64
639 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
640#endif
e3267cbb 641 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 642};
643
644static unsigned num_msrs_to_save;
645
646static u32 emulated_msrs[] = {
647 MSR_IA32_MISC_ENABLE,
648};
649
15c4a640
CO		 650static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
651{
f2b4b7dd 652 if (efer & efer_reserved_bits) {
15c4a640
CO		 653 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
654 efer);
c1a5d4f9 655 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 656 return;
657 }
658
659 if (is_paging(vcpu)
f6801dff 660 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 661 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 662 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 663 return;
664 }
665
1b2fd70c
AG		 666 if (efer & EFER_FFXSR) {
667 struct kvm_cpuid_entry2 *feat;
668
669 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
670 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
671 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
672 kvm_inject_gp(vcpu, 0);
673 return;
674 }
675 }
676
d8017474
AG		 677 if (efer & EFER_SVME) {
678 struct kvm_cpuid_entry2 *feat;
679
680 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
681 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
682 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
683 kvm_inject_gp(vcpu, 0);
684 return;
685 }
686 }
687
15c4a640
CO		 688 kvm_x86_ops->set_efer(vcpu, efer);
689
690 efer &= ~EFER_LMA;
f6801dff 691 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 692
f6801dff 693 vcpu->arch.efer = efer;
9645bb56
AK		 694
695 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
696 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 697}
698
f2b4b7dd
JR		 699void kvm_enable_efer_bits(u64 mask)
700{
701 efer_reserved_bits &= ~mask;
702}
703EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
704
705
15c4a640
CO		 706/*
707 * Writes msr value into into the appropriate "register".
708 * Returns 0 on success, non-0 otherwise.
709 * Assumes vcpu_load() was already called.
710 */
711int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
712{
713 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
714}
715
313a3dc7
CO		 716/*
717 * Adapt set_msr() to msr_io()'s calling convention
718 */
719static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
720{
721 return kvm_set_msr(vcpu, index, *data);
722}
723
18068523
GOC		 724static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
725{
726 static int version;
50d0a0f9 727 struct pvclock_wall_clock wc;
923de3cf 728 struct timespec boot;
18068523
GOC		 729
730 if (!wall_clock)
731 return;
732
733 version++;
734
18068523
GOC		 735 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
736
50d0a0f9
GH		 737 /*
738 * The guest calculates current wall clock time by adding
739 * system time (updated by kvm_write_guest_time below) to the
740 * wall clock specified here. guest system time equals host
741 * system time for us, thus we must fill in host boot time here.
742 */
923de3cf 743 getboottime(&boot);
50d0a0f9
GH		 744
745 wc.sec = boot.tv_sec;
746 wc.nsec = boot.tv_nsec;
747 wc.version = version;
18068523
GOC		 748
749 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
750
751 version++;
752 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 753}
754
50d0a0f9
GH		 755static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
756{
757 uint32_t quotient, remainder;
758
759 /* Don't try to replace with do_div(), this one calculates
760 * "(dividend << 32) / divisor" */
761 __asm__ ( "divl %4"
762 : "=a" (quotient), "=d" (remainder)
763 : "0" (0), "1" (dividend), "r" (divisor) );
764 return quotient;
765}
766
767static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
768{
769 uint64_t nsecs = 1000000000LL;
770 int32_t shift = 0;
771 uint64_t tps64;
772 uint32_t tps32;
773
774 tps64 = tsc_khz * 1000LL;
775 while (tps64 > nsecs*2) {
776 tps64 >>= 1;
777 shift--;
778 }
779
780 tps32 = (uint32_t)tps64;
781 while (tps32 <= (uint32_t)nsecs) {
782 tps32 <<= 1;
783 shift++;
784 }
785
786 hv_clock->tsc_shift = shift;
787 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
788
789 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 790 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 791 hv_clock->tsc_to_system_mul);
792}
793
c8076604
GH		 794static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
795
18068523
GOC		 796static void kvm_write_guest_time(struct kvm_vcpu *v)
797{
798 struct timespec ts;
799 unsigned long flags;
800 struct kvm_vcpu_arch *vcpu = &v->arch;
801 void *shared_kaddr;
463656c0 802 unsigned long this_tsc_khz;
18068523
GOC		 803
804 if ((!vcpu->time_page))
805 return;
806
463656c0
AK		 807 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
808 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
809 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
810 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 811 }
463656c0 812 put_cpu_var(cpu_tsc_khz);
50d0a0f9 813
18068523
GOC		 814 /* Keep irq disabled to prevent changes to the clock */
815 local_irq_save(flags);
af24a4e4 816 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 817 ktime_get_ts(&ts);
923de3cf 818 monotonic_to_bootbased(&ts);
18068523
GOC		 819 local_irq_restore(flags);
820
821 /* With all the info we got, fill in the values */
822
823 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 824 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
825
18068523
GOC		 826 /*
827 * The interface expects us to write an even number signaling that the
828 * update is finished. Since the guest won't see the intermediate
50d0a0f9 829 * state, we just increase by 2 at the end.
18068523 830 */
50d0a0f9 831 vcpu->hv_clock.version += 2;
18068523
GOC		 832
833 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
834
835 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 836 sizeof(vcpu->hv_clock));
18068523
GOC		 837
838 kunmap_atomic(shared_kaddr, KM_USER0);
839
840 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
841}
842
c8076604
GH		 843static int kvm_request_guest_time_update(struct kvm_vcpu *v)
844{
845 struct kvm_vcpu_arch *vcpu = &v->arch;
846
847 if (!vcpu->time_page)
848 return 0;
849 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
850 return 1;
851}
852
9ba075a6
AK		 853static bool msr_mtrr_valid(unsigned msr)
854{
855 switch (msr) {
856 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
857 case MSR_MTRRfix64K_00000:
858 case MSR_MTRRfix16K_80000:
859 case MSR_MTRRfix16K_A0000:
860 case MSR_MTRRfix4K_C0000:
861 case MSR_MTRRfix4K_C8000:
862 case MSR_MTRRfix4K_D0000:
863 case MSR_MTRRfix4K_D8000:
864 case MSR_MTRRfix4K_E0000:
865 case MSR_MTRRfix4K_E8000:
866 case MSR_MTRRfix4K_F0000:
867 case MSR_MTRRfix4K_F8000:
868 case MSR_MTRRdefType:
869 case MSR_IA32_CR_PAT:
870 return true;
871 case 0x2f8:
872 return true;
873 }
874 return false;
875}
876
d6289b93
MT		 877static bool valid_pat_type(unsigned t)
878{
879 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
880}
881
882static bool valid_mtrr_type(unsigned t)
883{
884 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
885}
886
887static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
888{
889 int i;
890
891 if (!msr_mtrr_valid(msr))
892 return false;
893
894 if (msr == MSR_IA32_CR_PAT) {
895 for (i = 0; i < 8; i++)
896 if (!valid_pat_type((data >> (i * 8)) & 0xff))
897 return false;
898 return true;
899 } else if (msr == MSR_MTRRdefType) {
900 if (data & ~0xcff)
901 return false;
902 return valid_mtrr_type(data & 0xff);
903 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
904 for (i = 0; i < 8 ; i++)
905 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
906 return false;
907 return true;
908 }
909
910 /* variable MTRRs */
911 return valid_mtrr_type(data & 0xff);
912}
913
9ba075a6
AK		 914static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
915{
0bed3b56
SY		 916 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
917
d6289b93 918 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 919 return 1;
920
0bed3b56
SY		 921 if (msr == MSR_MTRRdefType) {
922 vcpu->arch.mtrr_state.def_type = data;
923 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
924 } else if (msr == MSR_MTRRfix64K_00000)
925 p[0] = data;
926 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
927 p[1 + msr - MSR_MTRRfix16K_80000] = data;
928 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
929 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
930 else if (msr == MSR_IA32_CR_PAT)
931 vcpu->arch.pat = data;
932 else { /* Variable MTRRs */
933 int idx, is_mtrr_mask;
934 u64 *pt;
935
936 idx = (msr - 0x200) / 2;
937 is_mtrr_mask = msr - 0x200 - 2 * idx;
938 if (!is_mtrr_mask)
939 pt =
940 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
941 else
942 pt =
943 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
944 *pt = data;
945 }
946
947 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 948 return 0;
949}
15c4a640 950
890ca9ae 951static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 952{
890ca9ae
HY		 953 u64 mcg_cap = vcpu->arch.mcg_cap;
954 unsigned bank_num = mcg_cap & 0xff;
955
15c4a640 956 switch (msr) {
15c4a640 957 case MSR_IA32_MCG_STATUS:
890ca9ae 958 vcpu->arch.mcg_status = data;
15c4a640 959 break;
c7ac679c 960 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 961 if (!(mcg_cap & MCG_CTL_P))
962 return 1;
963 if (data != 0 && data != ~(u64)0)
964 return -1;
965 vcpu->arch.mcg_ctl = data;
966 break;
967 default:
968 if (msr >= MSR_IA32_MC0_CTL &&
969 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
970 u32 offset = msr - MSR_IA32_MC0_CTL;
971 /* only 0 or all 1s can be written to IA32_MCi_CTL */
972 if ((offset & 0x3) == 0 &&
973 data != 0 && data != ~(u64)0)
974 return -1;
975 vcpu->arch.mce_banks[offset] = data;
976 break;
977 }
978 return 1;
979 }
980 return 0;
981}
982
ffde22ac
ES		 983static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
984{
985 struct kvm *kvm = vcpu->kvm;
986 int lm = is_long_mode(vcpu);
987 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
988 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
989 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
990 : kvm->arch.xen_hvm_config.blob_size_32;
991 u32 page_num = data & ~PAGE_MASK;
992 u64 page_addr = data & PAGE_MASK;
993 u8 *page;
994 int r;
995
996 r = -E2BIG;
997 if (page_num >= blob_size)
998 goto out;
999 r = -ENOMEM;
1000 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1001 if (!page)
1002 goto out;
1003 r = -EFAULT;
1004 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1005 goto out_free;
1006 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1007 goto out_free;
1008 r = 0;
1009out_free:
1010 kfree(page);
1011out:
1012 return r;
1013}
1014
55cd8e5a
GN		 1015static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1016{
1017 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1018}
1019
1020static bool kvm_hv_msr_partition_wide(u32 msr)
1021{
1022 bool r = false;
1023 switch (msr) {
1024 case HV_X64_MSR_GUEST_OS_ID:
1025 case HV_X64_MSR_HYPERCALL:
1026 r = true;
1027 break;
1028 }
1029
1030 return r;
1031}
1032
1033static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1034{
1035 struct kvm *kvm = vcpu->kvm;
1036
1037 switch (msr) {
1038 case HV_X64_MSR_GUEST_OS_ID:
1039 kvm->arch.hv_guest_os_id = data;
1040 /* setting guest os id to zero disables hypercall page */
1041 if (!kvm->arch.hv_guest_os_id)
1042 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1043 break;
1044 case HV_X64_MSR_HYPERCALL: {
1045 u64 gfn;
1046 unsigned long addr;
1047 u8 instructions[4];
1048
1049 /* if guest os id is not set hypercall should remain disabled */
1050 if (!kvm->arch.hv_guest_os_id)
1051 break;
1052 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1053 kvm->arch.hv_hypercall = data;
1054 break;
1055 }
1056 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1057 addr = gfn_to_hva(kvm, gfn);
1058 if (kvm_is_error_hva(addr))
1059 return 1;
1060 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1061 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1062 if (copy_to_user((void __user *)addr, instructions, 4))
1063 return 1;
1064 kvm->arch.hv_hypercall = data;
1065 break;
1066 }
1067 default:
1068 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1069 "data 0x%llx\n", msr, data);
1070 return 1;
1071 }
1072 return 0;
1073}
1074
1075static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1076{
10388a07
GN		 1077 switch (msr) {
1078 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1079 unsigned long addr;
55cd8e5a 1080
10388a07
GN		 1081 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1082 vcpu->arch.hv_vapic = data;
1083 break;
1084 }
1085 addr = gfn_to_hva(vcpu->kvm, data >>
1086 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1087 if (kvm_is_error_hva(addr))
1088 return 1;
1089 if (clear_user((void __user *)addr, PAGE_SIZE))
1090 return 1;
1091 vcpu->arch.hv_vapic = data;
1092 break;
1093 }
1094 case HV_X64_MSR_EOI:
1095 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1096 case HV_X64_MSR_ICR:
1097 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1098 case HV_X64_MSR_TPR:
1099 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1100 default:
1101 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1102 "data 0x%llx\n", msr, data);
1103 return 1;
1104 }
1105
1106 return 0;
55cd8e5a
GN		 1107}
1108
15c4a640
CO		 1109int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1110{
1111 switch (msr) {
15c4a640
CO		 1112 case MSR_EFER:
1113 set_efer(vcpu, data);
1114 break;
8f1589d9
AP		 1115 case MSR_K7_HWCR:
1116 data &= ~(u64)0x40; /* ignore flush filter disable */
1117 if (data != 0) {
1118 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1119 data);
1120 return 1;
1121 }
15c4a640 1122 break;
f7c6d140
AP		 1123 case MSR_FAM10H_MMIO_CONF_BASE:
1124 if (data != 0) {
1125 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1126 "0x%llx\n", data);
1127 return 1;
1128 }
15c4a640 1129 break;
c323c0e5 1130 case MSR_AMD64_NB_CFG:
c7ac679c 1131 break;
b5e2fec0
AG		 1132 case MSR_IA32_DEBUGCTLMSR:
1133 if (!data) {
1134 /* We support the non-activated case already */
1135 break;
1136 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1137 /* Values other than LBR and BTF are vendor-specific,
1138 thus reserved and should throw a #GP */
1139 return 1;
1140 }
1141 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1142 __func__, data);
1143 break;
15c4a640
CO		 1144 case MSR_IA32_UCODE_REV:
1145 case MSR_IA32_UCODE_WRITE:
61a6bd67 1146 case MSR_VM_HSAVE_PA:
6098ca93 1147 case MSR_AMD64_PATCH_LOADER:
15c4a640 1148 break;
9ba075a6
AK		 1149 case 0x200 ... 0x2ff:
1150 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1151 case MSR_IA32_APICBASE:
1152 kvm_set_apic_base(vcpu, data);
1153 break;
0105d1a5
GN		 1154 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1155 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1156 case MSR_IA32_MISC_ENABLE:
ad312c7c 1157 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1158 break;
18068523
GOC		 1159 case MSR_KVM_WALL_CLOCK:
1160 vcpu->kvm->arch.wall_clock = data;
1161 kvm_write_wall_clock(vcpu->kvm, data);
1162 break;
1163 case MSR_KVM_SYSTEM_TIME: {
1164 if (vcpu->arch.time_page) {
1165 kvm_release_page_dirty(vcpu->arch.time_page);
1166 vcpu->arch.time_page = NULL;
1167 }
1168
1169 vcpu->arch.time = data;
1170
1171 /* we verify if the enable bit is set... */
1172 if (!(data & 1))
1173 break;
1174
1175 /* ...but clean it before doing the actual write */
1176 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1177
18068523
GOC		 1178 vcpu->arch.time_page =
1179 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1180
1181 if (is_error_page(vcpu->arch.time_page)) {
1182 kvm_release_page_clean(vcpu->arch.time_page);
1183 vcpu->arch.time_page = NULL;
1184 }
1185
c8076604 1186 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1187 break;
1188 }
890ca9ae
HY		 1189 case MSR_IA32_MCG_CTL:
1190 case MSR_IA32_MCG_STATUS:
1191 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1192 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1193
1194 /* Performance counters are not protected by a CPUID bit,
1195 * so we should check all of them in the generic path for the sake of
1196 * cross vendor migration.
1197 * Writing a zero into the event select MSRs disables them,
1198 * which we perfectly emulate ;-). Any other value should be at least
1199 * reported, some guests depend on them.
1200 */
1201 case MSR_P6_EVNTSEL0:
1202 case MSR_P6_EVNTSEL1:
1203 case MSR_K7_EVNTSEL0:
1204 case MSR_K7_EVNTSEL1:
1205 case MSR_K7_EVNTSEL2:
1206 case MSR_K7_EVNTSEL3:
1207 if (data != 0)
1208 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1209 "0x%x data 0x%llx\n", msr, data);
1210 break;
1211 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1212 * so we ignore writes to make it happy.
1213 */
1214 case MSR_P6_PERFCTR0:
1215 case MSR_P6_PERFCTR1:
1216 case MSR_K7_PERFCTR0:
1217 case MSR_K7_PERFCTR1:
1218 case MSR_K7_PERFCTR2:
1219 case MSR_K7_PERFCTR3:
1220 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1221 "0x%x data 0x%llx\n", msr, data);
1222 break;
55cd8e5a
GN		 1223 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1224 if (kvm_hv_msr_partition_wide(msr)) {
1225 int r;
1226 mutex_lock(&vcpu->kvm->lock);
1227 r = set_msr_hyperv_pw(vcpu, msr, data);
1228 mutex_unlock(&vcpu->kvm->lock);
1229 return r;
1230 } else
1231 return set_msr_hyperv(vcpu, msr, data);
1232 break;
15c4a640 1233 default:
ffde22ac
ES		 1234 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1235 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1236 if (!ignore_msrs) {
1237 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1238 msr, data);
1239 return 1;
1240 } else {
1241 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1242 msr, data);
1243 break;
1244 }
15c4a640
CO		 1245 }
1246 return 0;
1247}
1248EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1249
1250
1251/*
1252 * Reads an msr value (of 'msr_index') into 'pdata'.
1253 * Returns 0 on success, non-0 otherwise.
1254 * Assumes vcpu_load() was already called.
1255 */
1256int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1257{
1258 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1259}
1260
9ba075a6
AK		 1261static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1262{
0bed3b56
SY		 1263 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1264
9ba075a6
AK		 1265 if (!msr_mtrr_valid(msr))
1266 return 1;
1267
0bed3b56
SY		 1268 if (msr == MSR_MTRRdefType)
1269 *pdata = vcpu->arch.mtrr_state.def_type +
1270 (vcpu->arch.mtrr_state.enabled << 10);
1271 else if (msr == MSR_MTRRfix64K_00000)
1272 *pdata = p[0];
1273 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1274 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1275 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1276 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1277 else if (msr == MSR_IA32_CR_PAT)
1278 *pdata = vcpu->arch.pat;
1279 else { /* Variable MTRRs */
1280 int idx, is_mtrr_mask;
1281 u64 *pt;
1282
1283 idx = (msr - 0x200) / 2;
1284 is_mtrr_mask = msr - 0x200 - 2 * idx;
1285 if (!is_mtrr_mask)
1286 pt =
1287 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1288 else
1289 pt =
1290 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1291 *pdata = *pt;
1292 }
1293
9ba075a6
AK		 1294 return 0;
1295}
1296
890ca9ae 1297static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1298{
1299 u64 data;
890ca9ae
HY		 1300 u64 mcg_cap = vcpu->arch.mcg_cap;
1301 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1302
1303 switch (msr) {
15c4a640
CO		 1304 case MSR_IA32_P5_MC_ADDR:
1305 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1306 data = 0;
1307 break;
15c4a640 1308 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1309 data = vcpu->arch.mcg_cap;
1310 break;
c7ac679c 1311 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1312 if (!(mcg_cap & MCG_CTL_P))
1313 return 1;
1314 data = vcpu->arch.mcg_ctl;
1315 break;
1316 case MSR_IA32_MCG_STATUS:
1317 data = vcpu->arch.mcg_status;
1318 break;
1319 default:
1320 if (msr >= MSR_IA32_MC0_CTL &&
1321 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1322 u32 offset = msr - MSR_IA32_MC0_CTL;
1323 data = vcpu->arch.mce_banks[offset];
1324 break;
1325 }
1326 return 1;
1327 }
1328 *pdata = data;
1329 return 0;
1330}
1331
55cd8e5a
GN		 1332static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1333{
1334 u64 data = 0;
1335 struct kvm *kvm = vcpu->kvm;
1336
1337 switch (msr) {
1338 case HV_X64_MSR_GUEST_OS_ID:
1339 data = kvm->arch.hv_guest_os_id;
1340 break;
1341 case HV_X64_MSR_HYPERCALL:
1342 data = kvm->arch.hv_hypercall;
1343 break;
1344 default:
1345 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1346 return 1;
1347 }
1348
1349 *pdata = data;
1350 return 0;
1351}
1352
1353static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1354{
1355 u64 data = 0;
1356
1357 switch (msr) {
1358 case HV_X64_MSR_VP_INDEX: {
1359 int r;
1360 struct kvm_vcpu *v;
1361 kvm_for_each_vcpu(r, v, vcpu->kvm)
1362 if (v == vcpu)
1363 data = r;
1364 break;
1365 }
10388a07
GN		 1366 case HV_X64_MSR_EOI:
1367 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1368 case HV_X64_MSR_ICR:
1369 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1370 case HV_X64_MSR_TPR:
1371 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1372 default:
1373 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1374 return 1;
1375 }
1376 *pdata = data;
1377 return 0;
1378}
1379
890ca9ae
HY		 1380int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1381{
1382 u64 data;
1383
1384 switch (msr) {
890ca9ae 1385 case MSR_IA32_PLATFORM_ID:
15c4a640 1386 case MSR_IA32_UCODE_REV:
15c4a640 1387 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1388 case MSR_IA32_DEBUGCTLMSR:
1389 case MSR_IA32_LASTBRANCHFROMIP:
1390 case MSR_IA32_LASTBRANCHTOIP:
1391 case MSR_IA32_LASTINTFROMIP:
1392 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1393 case MSR_K8_SYSCFG:
1394 case MSR_K7_HWCR:
61a6bd67 1395 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1396 case MSR_P6_PERFCTR0:
1397 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1398 case MSR_P6_EVNTSEL0:
1399 case MSR_P6_EVNTSEL1:
9e699624 1400 case MSR_K7_EVNTSEL0:
1f3ee616 1401 case MSR_K7_PERFCTR0:
1fdbd48c 1402 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1403 case MSR_AMD64_NB_CFG:
f7c6d140 1404 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1405 data = 0;
1406 break;
9ba075a6
AK		 1407 case MSR_MTRRcap:
1408 data = 0x500 | KVM_NR_VAR_MTRR;
1409 break;
1410 case 0x200 ... 0x2ff:
1411 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1412 case 0xcd: /* fsb frequency */
1413 data = 3;
1414 break;
1415 case MSR_IA32_APICBASE:
1416 data = kvm_get_apic_base(vcpu);
1417 break;
0105d1a5
GN		 1418 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1419 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1420 break;
15c4a640 1421 case MSR_IA32_MISC_ENABLE:
ad312c7c 1422 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1423 break;
847f0ad8
AG		 1424 case MSR_IA32_PERF_STATUS:
1425 /* TSC increment by tick */
1426 data = 1000ULL;
1427 /* CPU multiplier */
1428 data |= (((uint64_t)4ULL) << 40);
1429 break;
15c4a640 1430 case MSR_EFER:
f6801dff 1431 data = vcpu->arch.efer;
15c4a640 1432 break;
18068523
GOC		 1433 case MSR_KVM_WALL_CLOCK:
1434 data = vcpu->kvm->arch.wall_clock;
1435 break;
1436 case MSR_KVM_SYSTEM_TIME:
1437 data = vcpu->arch.time;
1438 break;
890ca9ae
HY		 1439 case MSR_IA32_P5_MC_ADDR:
1440 case MSR_IA32_P5_MC_TYPE:
1441 case MSR_IA32_MCG_CAP:
1442 case MSR_IA32_MCG_CTL:
1443 case MSR_IA32_MCG_STATUS:
1444 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1445 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1446 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1447 if (kvm_hv_msr_partition_wide(msr)) {
1448 int r;
1449 mutex_lock(&vcpu->kvm->lock);
1450 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1451 mutex_unlock(&vcpu->kvm->lock);
1452 return r;
1453 } else
1454 return get_msr_hyperv(vcpu, msr, pdata);
1455 break;
15c4a640 1456 default:
ed85c068
AP		 1457 if (!ignore_msrs) {
1458 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1459 return 1;
1460 } else {
1461 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1462 data = 0;
1463 }
1464 break;
15c4a640
CO		 1465 }
1466 *pdata = data;
1467 return 0;
1468}
1469EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1470
313a3dc7
CO		 1471/*
1472 * Read or write a bunch of msrs. All parameters are kernel addresses.
1473 *
1474 * @return number of msrs set successfully.
1475 */
1476static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1477 struct kvm_msr_entry *entries,
1478 int (*do_msr)(struct kvm_vcpu *vcpu,
1479 unsigned index, u64 *data))
1480{
f656ce01 1481 int i, idx;
313a3dc7
CO		 1482
1483 vcpu_load(vcpu);
1484
f656ce01 1485 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1486 for (i = 0; i < msrs->nmsrs; ++i)
1487 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1488 break;
f656ce01 1489 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1490
1491 vcpu_put(vcpu);
1492
1493 return i;
1494}
1495
1496/*
1497 * Read or write a bunch of msrs. Parameters are user addresses.
1498 *
1499 * @return number of msrs set successfully.
1500 */
1501static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1502 int (*do_msr)(struct kvm_vcpu *vcpu,
1503 unsigned index, u64 *data),
1504 int writeback)
1505{
1506 struct kvm_msrs msrs;
1507 struct kvm_msr_entry *entries;
1508 int r, n;
1509 unsigned size;
1510
1511 r = -EFAULT;
1512 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1513 goto out;
1514
1515 r = -E2BIG;
1516 if (msrs.nmsrs >= MAX_IO_MSRS)
1517 goto out;
1518
1519 r = -ENOMEM;
1520 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1521 entries = vmalloc(size);
1522 if (!entries)
1523 goto out;
1524
1525 r = -EFAULT;
1526 if (copy_from_user(entries, user_msrs->entries, size))
1527 goto out_free;
1528
1529 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1530 if (r < 0)
1531 goto out_free;
1532
1533 r = -EFAULT;
1534 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1535 goto out_free;
1536
1537 r = n;
1538
1539out_free:
1540 vfree(entries);
1541out:
1542 return r;
1543}
1544
018d00d2
ZX		 1545int kvm_dev_ioctl_check_extension(long ext)
1546{
1547 int r;
1548
1549 switch (ext) {
1550 case KVM_CAP_IRQCHIP:
1551 case KVM_CAP_HLT:
1552 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1553 case KVM_CAP_SET_TSS_ADDR:
07716717 1554 case KVM_CAP_EXT_CPUID:
c8076604 1555 case KVM_CAP_CLOCKSOURCE:
7837699f 1556 case KVM_CAP_PIT:
a28e4f5a 1557 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1558 case KVM_CAP_MP_STATE:
ed848624 1559 case KVM_CAP_SYNC_MMU:
52d939a0 1560 case KVM_CAP_REINJECT_CONTROL:
4925663a 1561 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1562 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1563 case KVM_CAP_IRQFD:
d34e6b17 1564 case KVM_CAP_IOEVENTFD:
c5ff41ce 1565 case KVM_CAP_PIT2:
e9f42757 1566 case KVM_CAP_PIT_STATE2:
b927a3ce 1567 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1568 case KVM_CAP_XEN_HVM:
afbcf7ab 1569 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1570 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1571 case KVM_CAP_HYPERV:
10388a07 1572 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1573 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1574 case KVM_CAP_PCI_SEGMENT:
d2be1651 1575 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1576 r = 1;
1577 break;
542472b5
LV		 1578 case KVM_CAP_COALESCED_MMIO:
1579 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1580 break;
774ead3a
AK		 1581 case KVM_CAP_VAPIC:
1582 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1583 break;
f725230a
AK		 1584 case KVM_CAP_NR_VCPUS:
1585 r = KVM_MAX_VCPUS;
1586 break;
a988b910
AK		 1587 case KVM_CAP_NR_MEMSLOTS:
1588 r = KVM_MEMORY_SLOTS;
1589 break;
a68a6a72
MT		 1590 case KVM_CAP_PV_MMU: /* obsolete */
1591 r = 0;
2f333bcb 1592 break;
62c476c7 1593 case KVM_CAP_IOMMU:
19de40a8 1594 r = iommu_found();
62c476c7 1595 break;
890ca9ae
HY		 1596 case KVM_CAP_MCE:
1597 r = KVM_MAX_MCE_BANKS;
1598 break;
018d00d2
ZX		 1599 default:
1600 r = 0;
1601 break;
1602 }
1603 return r;
1604
1605}
1606
043405e1
CO		 1607long kvm_arch_dev_ioctl(struct file *filp,
1608 unsigned int ioctl, unsigned long arg)
1609{
1610 void __user *argp = (void __user *)arg;
1611 long r;
1612
1613 switch (ioctl) {
1614 case KVM_GET_MSR_INDEX_LIST: {
1615 struct kvm_msr_list __user *user_msr_list = argp;
1616 struct kvm_msr_list msr_list;
1617 unsigned n;
1618
1619 r = -EFAULT;
1620 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1621 goto out;
1622 n = msr_list.nmsrs;
1623 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1624 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1625 goto out;
1626 r = -E2BIG;
e125e7b6 1627 if (n < msr_list.nmsrs)
043405e1
CO		 1628 goto out;
1629 r = -EFAULT;
1630 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1631 num_msrs_to_save * sizeof(u32)))
1632 goto out;
e125e7b6 1633 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1634 &emulated_msrs,
1635 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1636 goto out;
1637 r = 0;
1638 break;
1639 }
674eea0f
AK		 1640 case KVM_GET_SUPPORTED_CPUID: {
1641 struct kvm_cpuid2 __user *cpuid_arg = argp;
1642 struct kvm_cpuid2 cpuid;
1643
1644 r = -EFAULT;
1645 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1646 goto out;
1647 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1648 cpuid_arg->entries);
674eea0f
AK		 1649 if (r)
1650 goto out;
1651
1652 r = -EFAULT;
1653 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1654 goto out;
1655 r = 0;
1656 break;
1657 }
890ca9ae
HY		 1658 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1659 u64 mce_cap;
1660
1661 mce_cap = KVM_MCE_CAP_SUPPORTED;
1662 r = -EFAULT;
1663 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1664 goto out;
1665 r = 0;
1666 break;
1667 }
043405e1
CO		 1668 default:
1669 r = -EINVAL;
1670 }
1671out:
1672 return r;
1673}
1674
313a3dc7
CO		 1675void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1676{
1677 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1678 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1679 unsigned long khz = cpufreq_quick_get(cpu);
1680 if (!khz)
1681 khz = tsc_khz;
1682 per_cpu(cpu_tsc_khz, cpu) = khz;
1683 }
c8076604 1684 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1685}
1686
1687void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1688{
9327fd11 1689 kvm_put_guest_fpu(vcpu);
02daab21 1690 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1691}
1692
07716717 1693static int is_efer_nx(void)
313a3dc7 1694{
e286e86e 1695 unsigned long long efer = 0;
313a3dc7 1696
e286e86e 1697 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1698 return efer & EFER_NX;
1699}
1700
1701static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1702{
1703 int i;
1704 struct kvm_cpuid_entry2 *e, *entry;
1705
313a3dc7 1706 entry = NULL;
ad312c7c
ZX		 1707 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1708 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1709 if (e->function == 0x80000001) {
1710 entry = e;
1711 break;
1712 }
1713 }
07716717 1714 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1715 entry->edx &= ~(1 << 20);
1716 printk(KERN_INFO "kvm: guest NX capability removed\n");
1717 }
1718}
1719
07716717 1720/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1721static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1722 struct kvm_cpuid *cpuid,
1723 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1724{
1725 int r, i;
1726 struct kvm_cpuid_entry *cpuid_entries;
1727
1728 r = -E2BIG;
1729 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1730 goto out;
1731 r = -ENOMEM;
1732 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1733 if (!cpuid_entries)
1734 goto out;
1735 r = -EFAULT;
1736 if (copy_from_user(cpuid_entries, entries,
1737 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1738 goto out_free;
1739 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1740 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1741 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1742 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1743 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1744 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1745 vcpu->arch.cpuid_entries[i].index = 0;
1746 vcpu->arch.cpuid_entries[i].flags = 0;
1747 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1748 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1749 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1750 }
1751 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1752 cpuid_fix_nx_cap(vcpu);
1753 r = 0;
fc61b800 1754 kvm_apic_set_version(vcpu);
0e851880 1755 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1756
1757out_free:
1758 vfree(cpuid_entries);
1759out:
1760 return r;
1761}
1762
1763static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1764 struct kvm_cpuid2 *cpuid,
1765 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1766{
1767 int r;
1768
1769 r = -E2BIG;
1770 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1771 goto out;
1772 r = -EFAULT;
ad312c7c 1773 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1774 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1775 goto out;
ad312c7c 1776 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1777 kvm_apic_set_version(vcpu);
0e851880 1778 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1779 return 0;
1780
1781out:
1782 return r;
1783}
1784
07716717 1785static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1786 struct kvm_cpuid2 *cpuid,
1787 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1788{
1789 int r;
1790
1791 r = -E2BIG;
ad312c7c 1792 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1793 goto out;
1794 r = -EFAULT;
ad312c7c 1795 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1796 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1797 goto out;
1798 return 0;
1799
1800out:
ad312c7c 1801 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1802 return r;
1803}
1804
07716717 1805static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1806 u32 index)
07716717
DK		 1807{
1808 entry->function = function;
1809 entry->index = index;
1810 cpuid_count(entry->function, entry->index,
19355475 1811 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1812 entry->flags = 0;
1813}
1814
7faa4ee1
AK		 1815#define F(x) bit(X86_FEATURE_##x)
1816
07716717
DK		 1817static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1818 u32 index, int *nent, int maxnent)
1819{
7faa4ee1 1820 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1821#ifdef CONFIG_X86_64
17cc3935
SY		 1822 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1823 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1824 unsigned f_lm = F(LM);
1825#else
17cc3935 1826 unsigned f_gbpages = 0;
7faa4ee1 1827 unsigned f_lm = 0;
07716717 1828#endif
4e47c7a6 1829 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1830
1831 /* cpuid 1.edx */
1832 const u32 kvm_supported_word0_x86_features =
1833 F(FPU) | F(VME) | F(DE) | F(PSE) |
1834 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1835 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1836 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1837 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1838 0 /* Reserved, DS, ACPI */ | F(MMX) |
1839 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1840 0 /* HTT, TM, Reserved, PBE */;
1841 /* cpuid 0x80000001.edx */
1842 const u32 kvm_supported_word1_x86_features =
1843 F(FPU) | F(VME) | F(DE) | F(PSE) |
1844 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1845 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1846 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1847 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1848 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1849 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1850 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1851 /* cpuid 1.ecx */
1852 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1853 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1854 0 /* DS-CPL, VMX, SMX, EST */ |
1855 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1856 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1857 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1858 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1859 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1860 /* cpuid 0x80000001.ecx */
07716717 1861 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1862 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1863 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1864 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1865 0 /* SKINIT */ | 0 /* WDT */;
07716717 1866
19355475 1867 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1868 get_cpu();
1869 do_cpuid_1_ent(entry, function, index);
1870 ++*nent;
1871
1872 switch (function) {
1873 case 0:
1874 entry->eax = min(entry->eax, (u32)0xb);
1875 break;
1876 case 1:
1877 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1878 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1879 /* we support x2apic emulation even if host does not support
1880 * it since we emulate x2apic in software */
1881 entry->ecx |= F(X2APIC);
07716717
DK		 1882 break;
1883 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1884 * may return different values. This forces us to get_cpu() before
1885 * issuing the first command, and also to emulate this annoying behavior
1886 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1887 case 2: {
1888 int t, times = entry->eax & 0xff;
1889
1890 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1891 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1892 for (t = 1; t < times && *nent < maxnent; ++t) {
1893 do_cpuid_1_ent(&entry[t], function, 0);
1894 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1895 ++*nent;
1896 }
1897 break;
1898 }
1899 /* function 4 and 0xb have additional index. */
1900 case 4: {
14af3f3c 1901 int i, cache_type;
07716717
DK		 1902
1903 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1904 /* read more entries until cache_type is zero */
14af3f3c
HH		 1905 for (i = 1; *nent < maxnent; ++i) {
1906 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1907 if (!cache_type)
1908 break;
14af3f3c
HH		 1909 do_cpuid_1_ent(&entry[i], function, i);
1910 entry[i].flags |=
07716717
DK		 1911 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1912 ++*nent;
1913 }
1914 break;
1915 }
1916 case 0xb: {
14af3f3c 1917 int i, level_type;
07716717
DK		 1918
1919 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1920 /* read more entries until level_type is zero */
14af3f3c 1921 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1922 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1923 if (!level_type)
1924 break;
14af3f3c
HH		 1925 do_cpuid_1_ent(&entry[i], function, i);
1926 entry[i].flags |=
07716717
DK		 1927 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1928 ++*nent;
1929 }
1930 break;
1931 }
1932 case 0x80000000:
1933 entry->eax = min(entry->eax, 0x8000001a);
1934 break;
1935 case 0x80000001:
1936 entry->edx &= kvm_supported_word1_x86_features;
1937 entry->ecx &= kvm_supported_word6_x86_features;
1938 break;
1939 }
1940 put_cpu();
1941}
1942
7faa4ee1
AK		 1943#undef F
1944
674eea0f 1945static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1946 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1947{
1948 struct kvm_cpuid_entry2 *cpuid_entries;
1949 int limit, nent = 0, r = -E2BIG;
1950 u32 func;
1951
1952 if (cpuid->nent < 1)
1953 goto out;
6a544355
AK		 1954 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1955 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1956 r = -ENOMEM;
1957 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1958 if (!cpuid_entries)
1959 goto out;
1960
1961 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1962 limit = cpuid_entries[0].eax;
1963 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1964 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1965 &nent, cpuid->nent);
07716717
DK		 1966 r = -E2BIG;
1967 if (nent >= cpuid->nent)
1968 goto out_free;
1969
1970 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1971 limit = cpuid_entries[nent - 1].eax;
1972 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1973 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1974 &nent, cpuid->nent);
cb007648
MM		 1975 r = -E2BIG;
1976 if (nent >= cpuid->nent)
1977 goto out_free;
1978
07716717
DK		 1979 r = -EFAULT;
1980 if (copy_to_user(entries, cpuid_entries,
19355475 1981 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1982 goto out_free;
1983 cpuid->nent = nent;
1984 r = 0;
1985
1986out_free:
1987 vfree(cpuid_entries);
1988out:
1989 return r;
1990}
1991
313a3dc7
CO		 1992static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1993 struct kvm_lapic_state *s)
1994{
1995 vcpu_load(vcpu);
ad312c7c 1996 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1997 vcpu_put(vcpu);
1998
1999 return 0;
2000}
2001
2002static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2003 struct kvm_lapic_state *s)
2004{
2005 vcpu_load(vcpu);
ad312c7c 2006 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2007 kvm_apic_post_state_restore(vcpu);
cb142eb7 2008 update_cr8_intercept(vcpu);
313a3dc7
CO		 2009 vcpu_put(vcpu);
2010
2011 return 0;
2012}
2013
f77bc6a4
ZX		 2014static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2015 struct kvm_interrupt *irq)
2016{
2017 if (irq->irq < 0 || irq->irq >= 256)
2018 return -EINVAL;
2019 if (irqchip_in_kernel(vcpu->kvm))
2020 return -ENXIO;
2021 vcpu_load(vcpu);
2022
66fd3f7f 2023 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2024
2025 vcpu_put(vcpu);
2026
2027 return 0;
2028}
2029
c4abb7c9
JK		 2030static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2031{
2032 vcpu_load(vcpu);
2033 kvm_inject_nmi(vcpu);
2034 vcpu_put(vcpu);
2035
2036 return 0;
2037}
2038
b209749f
AK		 2039static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2040 struct kvm_tpr_access_ctl *tac)
2041{
2042 if (tac->flags)
2043 return -EINVAL;
2044 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2045 return 0;
2046}
2047
890ca9ae
HY		 2048static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2049 u64 mcg_cap)
2050{
2051 int r;
2052 unsigned bank_num = mcg_cap & 0xff, bank;
2053
2054 r = -EINVAL;
a9e38c3e 2055 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2056 goto out;
2057 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2058 goto out;
2059 r = 0;
2060 vcpu->arch.mcg_cap = mcg_cap;
2061 /* Init IA32_MCG_CTL to all 1s */
2062 if (mcg_cap & MCG_CTL_P)
2063 vcpu->arch.mcg_ctl = ~(u64)0;
2064 /* Init IA32_MCi_CTL to all 1s */
2065 for (bank = 0; bank < bank_num; bank++)
2066 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2067out:
2068 return r;
2069}
2070
2071static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2072 struct kvm_x86_mce *mce)
2073{
2074 u64 mcg_cap = vcpu->arch.mcg_cap;
2075 unsigned bank_num = mcg_cap & 0xff;
2076 u64 *banks = vcpu->arch.mce_banks;
2077
2078 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2079 return -EINVAL;
2080 /*
2081 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2082 * reporting is disabled
2083 */
2084 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2085 vcpu->arch.mcg_ctl != ~(u64)0)
2086 return 0;
2087 banks += 4 * mce->bank;
2088 /*
2089 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2090 * reporting is disabled for the bank
2091 */
2092 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2093 return 0;
2094 if (mce->status & MCI_STATUS_UC) {
2095 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2096 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2097 printk(KERN_DEBUG "kvm: set_mce: "
2098 "injects mce exception while "
2099 "previous one is in progress!\n");
2100 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2101 return 0;
2102 }
2103 if (banks[1] & MCI_STATUS_VAL)
2104 mce->status |= MCI_STATUS_OVER;
2105 banks[2] = mce->addr;
2106 banks[3] = mce->misc;
2107 vcpu->arch.mcg_status = mce->mcg_status;
2108 banks[1] = mce->status;
2109 kvm_queue_exception(vcpu, MC_VECTOR);
2110 } else if (!(banks[1] & MCI_STATUS_VAL)
2111 || !(banks[1] & MCI_STATUS_UC)) {
2112 if (banks[1] & MCI_STATUS_VAL)
2113 mce->status |= MCI_STATUS_OVER;
2114 banks[2] = mce->addr;
2115 banks[3] = mce->misc;
2116 banks[1] = mce->status;
2117 } else
2118 banks[1] |= MCI_STATUS_OVER;
2119 return 0;
2120}
2121
3cfc3092
JK		 2122static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2123 struct kvm_vcpu_events *events)
2124{
2125 vcpu_load(vcpu);
2126
2127 events->exception.injected = vcpu->arch.exception.pending;
2128 events->exception.nr = vcpu->arch.exception.nr;
2129 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2130 events->exception.error_code = vcpu->arch.exception.error_code;
2131
2132 events->interrupt.injected = vcpu->arch.interrupt.pending;
2133 events->interrupt.nr = vcpu->arch.interrupt.nr;
2134 events->interrupt.soft = vcpu->arch.interrupt.soft;
2135
2136 events->nmi.injected = vcpu->arch.nmi_injected;
2137 events->nmi.pending = vcpu->arch.nmi_pending;
2138 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2139
2140 events->sipi_vector = vcpu->arch.sipi_vector;
2141
dab4b911
JK		 2142 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2143 | KVM_VCPUEVENT_VALID_SIPI_VECTOR);
3cfc3092
JK		 2144
2145 vcpu_put(vcpu);
2146}
2147
2148static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2149 struct kvm_vcpu_events *events)
2150{
dab4b911
JK		 2151 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2152 | KVM_VCPUEVENT_VALID_SIPI_VECTOR))
3cfc3092
JK		 2153 return -EINVAL;
2154
2155 vcpu_load(vcpu);
2156
2157 vcpu->arch.exception.pending = events->exception.injected;
2158 vcpu->arch.exception.nr = events->exception.nr;
2159 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2160 vcpu->arch.exception.error_code = events->exception.error_code;
2161
2162 vcpu->arch.interrupt.pending = events->interrupt.injected;
2163 vcpu->arch.interrupt.nr = events->interrupt.nr;
2164 vcpu->arch.interrupt.soft = events->interrupt.soft;
2165 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2166 kvm_pic_clear_isr_ack(vcpu->kvm);
2167
2168 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2169 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2170 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2171 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2172
dab4b911
JK		 2173 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2174 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2175
2176 vcpu_put(vcpu);
2177
2178 return 0;
2179}
2180
313a3dc7
CO		 2181long kvm_arch_vcpu_ioctl(struct file *filp,
2182 unsigned int ioctl, unsigned long arg)
2183{
2184 struct kvm_vcpu *vcpu = filp->private_data;
2185 void __user *argp = (void __user *)arg;
2186 int r;
b772ff36 2187 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2188
2189 switch (ioctl) {
2190 case KVM_GET_LAPIC: {
2204ae3c
MT		 2191 r = -EINVAL;
2192 if (!vcpu->arch.apic)
2193 goto out;
b772ff36 2194 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2195
b772ff36
DH		 2196 r = -ENOMEM;
2197 if (!lapic)
2198 goto out;
2199 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2200 if (r)
2201 goto out;
2202 r = -EFAULT;
b772ff36 2203 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2204 goto out;
2205 r = 0;
2206 break;
2207 }
2208 case KVM_SET_LAPIC: {
2204ae3c
MT		 2209 r = -EINVAL;
2210 if (!vcpu->arch.apic)
2211 goto out;
b772ff36
DH		 2212 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2213 r = -ENOMEM;
2214 if (!lapic)
2215 goto out;
313a3dc7 2216 r = -EFAULT;
b772ff36 2217 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2218 goto out;
b772ff36 2219 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2220 if (r)
2221 goto out;
2222 r = 0;
2223 break;
2224 }
f77bc6a4
ZX		 2225 case KVM_INTERRUPT: {
2226 struct kvm_interrupt irq;
2227
2228 r = -EFAULT;
2229 if (copy_from_user(&irq, argp, sizeof irq))
2230 goto out;
2231 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2232 if (r)
2233 goto out;
2234 r = 0;
2235 break;
2236 }
c4abb7c9
JK		 2237 case KVM_NMI: {
2238 r = kvm_vcpu_ioctl_nmi(vcpu);
2239 if (r)
2240 goto out;
2241 r = 0;
2242 break;
2243 }
313a3dc7
CO		 2244 case KVM_SET_CPUID: {
2245 struct kvm_cpuid __user *cpuid_arg = argp;
2246 struct kvm_cpuid cpuid;
2247
2248 r = -EFAULT;
2249 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2250 goto out;
2251 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2252 if (r)
2253 goto out;
2254 break;
2255 }
07716717
DK		 2256 case KVM_SET_CPUID2: {
2257 struct kvm_cpuid2 __user *cpuid_arg = argp;
2258 struct kvm_cpuid2 cpuid;
2259
2260 r = -EFAULT;
2261 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2262 goto out;
2263 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2264 cpuid_arg->entries);
07716717
DK		 2265 if (r)
2266 goto out;
2267 break;
2268 }
2269 case KVM_GET_CPUID2: {
2270 struct kvm_cpuid2 __user *cpuid_arg = argp;
2271 struct kvm_cpuid2 cpuid;
2272
2273 r = -EFAULT;
2274 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2275 goto out;
2276 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2277 cpuid_arg->entries);
07716717
DK		 2278 if (r)
2279 goto out;
2280 r = -EFAULT;
2281 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2282 goto out;
2283 r = 0;
2284 break;
2285 }
313a3dc7
CO		 2286 case KVM_GET_MSRS:
2287 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2288 break;
2289 case KVM_SET_MSRS:
2290 r = msr_io(vcpu, argp, do_set_msr, 0);
2291 break;
b209749f
AK		 2292 case KVM_TPR_ACCESS_REPORTING: {
2293 struct kvm_tpr_access_ctl tac;
2294
2295 r = -EFAULT;
2296 if (copy_from_user(&tac, argp, sizeof tac))
2297 goto out;
2298 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2299 if (r)
2300 goto out;
2301 r = -EFAULT;
2302 if (copy_to_user(argp, &tac, sizeof tac))
2303 goto out;
2304 r = 0;
2305 break;
2306 };
b93463aa
AK		 2307 case KVM_SET_VAPIC_ADDR: {
2308 struct kvm_vapic_addr va;
2309
2310 r = -EINVAL;
2311 if (!irqchip_in_kernel(vcpu->kvm))
2312 goto out;
2313 r = -EFAULT;
2314 if (copy_from_user(&va, argp, sizeof va))
2315 goto out;
2316 r = 0;
2317 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2318 break;
2319 }
890ca9ae
HY		 2320 case KVM_X86_SETUP_MCE: {
2321 u64 mcg_cap;
2322
2323 r = -EFAULT;
2324 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2325 goto out;
2326 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2327 break;
2328 }
2329 case KVM_X86_SET_MCE: {
2330 struct kvm_x86_mce mce;
2331
2332 r = -EFAULT;
2333 if (copy_from_user(&mce, argp, sizeof mce))
2334 goto out;
2335 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2336 break;
2337 }
3cfc3092
JK		 2338 case KVM_GET_VCPU_EVENTS: {
2339 struct kvm_vcpu_events events;
2340
2341 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2342
2343 r = -EFAULT;
2344 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2345 break;
2346 r = 0;
2347 break;
2348 }
2349 case KVM_SET_VCPU_EVENTS: {
2350 struct kvm_vcpu_events events;
2351
2352 r = -EFAULT;
2353 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2354 break;
2355
2356 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2357 break;
2358 }
313a3dc7
CO		 2359 default:
2360 r = -EINVAL;
2361 }
2362out:
7a6ce84c 2363 kfree(lapic);
313a3dc7
CO		 2364 return r;
2365}
2366
1fe779f8
CO		 2367static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2368{
2369 int ret;
2370
2371 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2372 return -1;
2373 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2374 return ret;
2375}
2376
b927a3ce
SY		 2377static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2378 u64 ident_addr)
2379{
2380 kvm->arch.ept_identity_map_addr = ident_addr;
2381 return 0;
2382}
2383
1fe779f8
CO		 2384static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2385 u32 kvm_nr_mmu_pages)
2386{
2387 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2388 return -EINVAL;
2389
79fac95e 2390 mutex_lock(&kvm->slots_lock);
7c8a83b7 2391 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2392
2393 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2394 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2395
7c8a83b7 2396 spin_unlock(&kvm->mmu_lock);
79fac95e 2397 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2398 return 0;
2399}
2400
2401static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2402{
f05e70ac 2403 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2404}
2405
a983fb23
MT		 2406gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2407{
2408 int i;
2409 struct kvm_mem_alias *alias;
2410 struct kvm_mem_aliases *aliases;
2411
2412 aliases = rcu_dereference(kvm->arch.aliases);
2413
2414 for (i = 0; i < aliases->naliases; ++i) {
2415 alias = &aliases->aliases[i];
2416 if (alias->flags & KVM_ALIAS_INVALID)
2417 continue;
2418 if (gfn >= alias->base_gfn
2419 && gfn < alias->base_gfn + alias->npages)
2420 return alias->target_gfn + gfn - alias->base_gfn;
2421 }
2422 return gfn;
2423}
2424
e9f85cde
ZX		 2425gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2426{
2427 int i;
2428 struct kvm_mem_alias *alias;
a983fb23
MT		 2429 struct kvm_mem_aliases *aliases;
2430
2431 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2432
fef9cce0
MT		 2433 for (i = 0; i < aliases->naliases; ++i) {
2434 alias = &aliases->aliases[i];
e9f85cde
ZX		 2435 if (gfn >= alias->base_gfn
2436 && gfn < alias->base_gfn + alias->npages)
2437 return alias->target_gfn + gfn - alias->base_gfn;
2438 }
2439 return gfn;
2440}
2441
1fe779f8
CO		 2442/*
2443 * Set a new alias region. Aliases map a portion of physical memory into
2444 * another portion. This is useful for memory windows, for example the PC
2445 * VGA region.
2446 */
2447static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2448 struct kvm_memory_alias *alias)
2449{
2450 int r, n;
2451 struct kvm_mem_alias *p;
a983fb23 2452 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2453
2454 r = -EINVAL;
2455 /* General sanity checks */
2456 if (alias->memory_size & (PAGE_SIZE - 1))
2457 goto out;
2458 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2459 goto out;
2460 if (alias->slot >= KVM_ALIAS_SLOTS)
2461 goto out;
2462 if (alias->guest_phys_addr + alias->memory_size
2463 < alias->guest_phys_addr)
2464 goto out;
2465 if (alias->target_phys_addr + alias->memory_size
2466 < alias->target_phys_addr)
2467 goto out;
2468
a983fb23
MT		 2469 r = -ENOMEM;
2470 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2471 if (!aliases)
2472 goto out;
2473
79fac95e 2474 mutex_lock(&kvm->slots_lock);
1fe779f8 2475
a983fb23
MT		 2476 /* invalidate any gfn reference in case of deletion/shrinking */
2477 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2478 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2479 old_aliases = kvm->arch.aliases;
2480 rcu_assign_pointer(kvm->arch.aliases, aliases);
2481 synchronize_srcu_expedited(&kvm->srcu);
2482 kvm_mmu_zap_all(kvm);
2483 kfree(old_aliases);
2484
2485 r = -ENOMEM;
2486 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2487 if (!aliases)
2488 goto out_unlock;
2489
2490 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2491
2492 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2493 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2494 p->npages = alias->memory_size >> PAGE_SHIFT;
2495 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2496 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2497
2498 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2499 if (aliases->aliases[n - 1].npages)
1fe779f8 2500 break;
fef9cce0 2501 aliases->naliases = n;
1fe779f8 2502
a983fb23
MT		 2503 old_aliases = kvm->arch.aliases;
2504 rcu_assign_pointer(kvm->arch.aliases, aliases);
2505 synchronize_srcu_expedited(&kvm->srcu);
2506 kfree(old_aliases);
2507 r = 0;
1fe779f8 2508
a983fb23 2509out_unlock:
79fac95e 2510 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2511out:
2512 return r;
2513}
2514
2515static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2516{
2517 int r;
2518
2519 r = 0;
2520 switch (chip->chip_id) {
2521 case KVM_IRQCHIP_PIC_MASTER:
2522 memcpy(&chip->chip.pic,
2523 &pic_irqchip(kvm)->pics[0],
2524 sizeof(struct kvm_pic_state));
2525 break;
2526 case KVM_IRQCHIP_PIC_SLAVE:
2527 memcpy(&chip->chip.pic,
2528 &pic_irqchip(kvm)->pics[1],
2529 sizeof(struct kvm_pic_state));
2530 break;
2531 case KVM_IRQCHIP_IOAPIC:
eba0226b 2532 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2533 break;
2534 default:
2535 r = -EINVAL;
2536 break;
2537 }
2538 return r;
2539}
2540
2541static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2542{
2543 int r;
2544
2545 r = 0;
2546 switch (chip->chip_id) {
2547 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2548 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2549 memcpy(&pic_irqchip(kvm)->pics[0],
2550 &chip->chip.pic,
2551 sizeof(struct kvm_pic_state));
fa8273e9 2552 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2553 break;
2554 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2555 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2556 memcpy(&pic_irqchip(kvm)->pics[1],
2557 &chip->chip.pic,
2558 sizeof(struct kvm_pic_state));
fa8273e9 2559 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2560 break;
2561 case KVM_IRQCHIP_IOAPIC:
eba0226b 2562 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2563 break;
2564 default:
2565 r = -EINVAL;
2566 break;
2567 }
2568 kvm_pic_update_irq(pic_irqchip(kvm));
2569 return r;
2570}
2571
e0f63cb9
SY		 2572static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2573{
2574 int r = 0;
2575
894a9c55 2576 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2577 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2578 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2579 return r;
2580}
2581
2582static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2583{
2584 int r = 0;
2585
894a9c55 2586 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2587 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2588 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2589 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2590 return r;
2591}
2592
2593static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2594{
2595 int r = 0;
2596
2597 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2598 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2599 sizeof(ps->channels));
2600 ps->flags = kvm->arch.vpit->pit_state.flags;
2601 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2602 return r;
2603}
2604
2605static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2606{
2607 int r = 0, start = 0;
2608 u32 prev_legacy, cur_legacy;
2609 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2610 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2611 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2612 if (!prev_legacy && cur_legacy)
2613 start = 1;
2614 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2615 sizeof(kvm->arch.vpit->pit_state.channels));
2616 kvm->arch.vpit->pit_state.flags = ps->flags;
2617 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2618 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2619 return r;
2620}
2621
52d939a0
MT		 2622static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2623 struct kvm_reinject_control *control)
2624{
2625 if (!kvm->arch.vpit)
2626 return -ENXIO;
894a9c55 2627 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2628 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2629 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2630 return 0;
2631}
2632
5bb064dc
ZX		 2633/*
2634 * Get (and clear) the dirty memory log for a memory slot.
2635 */
2636int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2637 struct kvm_dirty_log *log)
2638{
b050b015 2639 int r, n, i;
5bb064dc 2640 struct kvm_memory_slot *memslot;
b050b015
MT		 2641 unsigned long is_dirty = 0;
2642 unsigned long *dirty_bitmap = NULL;
5bb064dc 2643
79fac95e 2644 mutex_lock(&kvm->slots_lock);
5bb064dc 2645
b050b015
MT		 2646 r = -EINVAL;
2647 if (log->slot >= KVM_MEMORY_SLOTS)
2648 goto out;
2649
2650 memslot = &kvm->memslots->memslots[log->slot];
2651 r = -ENOENT;
2652 if (!memslot->dirty_bitmap)
2653 goto out;
2654
2655 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2656
2657 r = -ENOMEM;
2658 dirty_bitmap = vmalloc(n);
2659 if (!dirty_bitmap)
5bb064dc 2660 goto out;
b050b015
MT		 2661 memset(dirty_bitmap, 0, n);
2662
2663 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2664 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2665
2666 /* If nothing is dirty, don't bother messing with page tables. */
2667 if (is_dirty) {
b050b015
MT		 2668 struct kvm_memslots *slots, *old_slots;
2669
7c8a83b7 2670 spin_lock(&kvm->mmu_lock);
5bb064dc 2671 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2672 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2673
2674 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2675 if (!slots)
2676 goto out_free;
2677
2678 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2679 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2680
2681 old_slots = kvm->memslots;
2682 rcu_assign_pointer(kvm->memslots, slots);
2683 synchronize_srcu_expedited(&kvm->srcu);
2684 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2685 kfree(old_slots);
5bb064dc 2686 }
b050b015 2687
5bb064dc 2688 r = 0;
b050b015
MT		 2689 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2690 r = -EFAULT;
2691out_free:
2692 vfree(dirty_bitmap);
5bb064dc 2693out:
79fac95e 2694 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2695 return r;
2696}
2697
1fe779f8
CO		 2698long kvm_arch_vm_ioctl(struct file *filp,
2699 unsigned int ioctl, unsigned long arg)
2700{
2701 struct kvm *kvm = filp->private_data;
2702 void __user *argp = (void __user *)arg;
367e1319 2703 int r = -ENOTTY;
f0d66275
DH		 2704 /*
2705 * This union makes it completely explicit to gcc-3.x
2706 * that these two variables' stack usage should be
2707 * combined, not added together.
2708 */
2709 union {
2710 struct kvm_pit_state ps;
e9f42757 2711 struct kvm_pit_state2 ps2;
f0d66275 2712 struct kvm_memory_alias alias;
c5ff41ce 2713 struct kvm_pit_config pit_config;
f0d66275 2714 } u;
1fe779f8
CO		 2715
2716 switch (ioctl) {
2717 case KVM_SET_TSS_ADDR:
2718 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2719 if (r < 0)
2720 goto out;
2721 break;
b927a3ce
SY		 2722 case KVM_SET_IDENTITY_MAP_ADDR: {
2723 u64 ident_addr;
2724
2725 r = -EFAULT;
2726 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2727 goto out;
2728 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2729 if (r < 0)
2730 goto out;
2731 break;
2732 }
1fe779f8
CO		 2733 case KVM_SET_MEMORY_REGION: {
2734 struct kvm_memory_region kvm_mem;
2735 struct kvm_userspace_memory_region kvm_userspace_mem;
2736
2737 r = -EFAULT;
2738 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2739 goto out;
2740 kvm_userspace_mem.slot = kvm_mem.slot;
2741 kvm_userspace_mem.flags = kvm_mem.flags;
2742 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2743 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2744 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2745 if (r)
2746 goto out;
2747 break;
2748 }
2749 case KVM_SET_NR_MMU_PAGES:
2750 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2751 if (r)
2752 goto out;
2753 break;
2754 case KVM_GET_NR_MMU_PAGES:
2755 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2756 break;
f0d66275 2757 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2758 r = -EFAULT;
f0d66275 2759 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2760 goto out;
f0d66275 2761 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2762 if (r)
2763 goto out;
2764 break;
3ddea128
MT		 2765 case KVM_CREATE_IRQCHIP: {
2766 struct kvm_pic *vpic;
2767
2768 mutex_lock(&kvm->lock);
2769 r = -EEXIST;
2770 if (kvm->arch.vpic)
2771 goto create_irqchip_unlock;
1fe779f8 2772 r = -ENOMEM;
3ddea128
MT		 2773 vpic = kvm_create_pic(kvm);
2774 if (vpic) {
1fe779f8
CO		 2775 r = kvm_ioapic_init(kvm);
2776 if (r) {
72bb2fcd
WY		 2777 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2778 &vpic->dev);
3ddea128
MT		 2779 kfree(vpic);
2780 goto create_irqchip_unlock;
1fe779f8
CO		 2781 }
2782 } else
3ddea128
MT		 2783 goto create_irqchip_unlock;
2784 smp_wmb();
2785 kvm->arch.vpic = vpic;
2786 smp_wmb();
399ec807
AK		 2787 r = kvm_setup_default_irq_routing(kvm);
2788 if (r) {
3ddea128 2789 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2790 kvm_ioapic_destroy(kvm);
2791 kvm_destroy_pic(kvm);
3ddea128 2792 mutex_unlock(&kvm->irq_lock);
399ec807 2793 }
3ddea128
MT		 2794 create_irqchip_unlock:
2795 mutex_unlock(&kvm->lock);
1fe779f8 2796 break;
3ddea128 2797 }
7837699f 2798 case KVM_CREATE_PIT:
c5ff41ce
JK		 2799 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2800 goto create_pit;
2801 case KVM_CREATE_PIT2:
2802 r = -EFAULT;
2803 if (copy_from_user(&u.pit_config, argp,
2804 sizeof(struct kvm_pit_config)))
2805 goto out;
2806 create_pit:
79fac95e 2807 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2808 r = -EEXIST;
2809 if (kvm->arch.vpit)
2810 goto create_pit_unlock;
7837699f 2811 r = -ENOMEM;
c5ff41ce 2812 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2813 if (kvm->arch.vpit)
2814 r = 0;
269e05e4 2815 create_pit_unlock:
79fac95e 2816 mutex_unlock(&kvm->slots_lock);
7837699f 2817 break;
4925663a 2818 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2819 case KVM_IRQ_LINE: {
2820 struct kvm_irq_level irq_event;
2821
2822 r = -EFAULT;
2823 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2824 goto out;
2825 if (irqchip_in_kernel(kvm)) {
4925663a 2826 __s32 status;
4925663a
GN		 2827 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2828 irq_event.irq, irq_event.level);
4925663a
GN		 2829 if (ioctl == KVM_IRQ_LINE_STATUS) {
2830 irq_event.status = status;
2831 if (copy_to_user(argp, &irq_event,
2832 sizeof irq_event))
2833 goto out;
2834 }
1fe779f8
CO		 2835 r = 0;
2836 }
2837 break;
2838 }
2839 case KVM_GET_IRQCHIP: {
2840 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2841 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2842
f0d66275
DH		 2843 r = -ENOMEM;
2844 if (!chip)
1fe779f8 2845 goto out;
f0d66275
DH		 2846 r = -EFAULT;
2847 if (copy_from_user(chip, argp, sizeof *chip))
2848 goto get_irqchip_out;
1fe779f8
CO		 2849 r = -ENXIO;
2850 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2851 goto get_irqchip_out;
2852 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2853 if (r)
f0d66275 2854 goto get_irqchip_out;
1fe779f8 2855 r = -EFAULT;
f0d66275
DH		 2856 if (copy_to_user(argp, chip, sizeof *chip))
2857 goto get_irqchip_out;
1fe779f8 2858 r = 0;
f0d66275
DH		 2859 get_irqchip_out:
2860 kfree(chip);
2861 if (r)
2862 goto out;
1fe779f8
CO		 2863 break;
2864 }
2865 case KVM_SET_IRQCHIP: {
2866 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2867 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2868
f0d66275
DH		 2869 r = -ENOMEM;
2870 if (!chip)
1fe779f8 2871 goto out;
f0d66275
DH		 2872 r = -EFAULT;
2873 if (copy_from_user(chip, argp, sizeof *chip))
2874 goto set_irqchip_out;
1fe779f8
CO		 2875 r = -ENXIO;
2876 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2877 goto set_irqchip_out;
2878 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2879 if (r)
f0d66275 2880 goto set_irqchip_out;
1fe779f8 2881 r = 0;
f0d66275
DH		 2882 set_irqchip_out:
2883 kfree(chip);
2884 if (r)
2885 goto out;
1fe779f8
CO		 2886 break;
2887 }
e0f63cb9 2888 case KVM_GET_PIT: {
e0f63cb9 2889 r = -EFAULT;
f0d66275 2890 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2891 goto out;
2892 r = -ENXIO;
2893 if (!kvm->arch.vpit)
2894 goto out;
f0d66275 2895 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2896 if (r)
2897 goto out;
2898 r = -EFAULT;
f0d66275 2899 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2900 goto out;
2901 r = 0;
2902 break;
2903 }
2904 case KVM_SET_PIT: {
e0f63cb9 2905 r = -EFAULT;
f0d66275 2906 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2907 goto out;
2908 r = -ENXIO;
2909 if (!kvm->arch.vpit)
2910 goto out;
f0d66275 2911 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2912 if (r)
2913 goto out;
2914 r = 0;
2915 break;
2916 }
e9f42757
BK		 2917 case KVM_GET_PIT2: {
2918 r = -ENXIO;
2919 if (!kvm->arch.vpit)
2920 goto out;
2921 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2922 if (r)
2923 goto out;
2924 r = -EFAULT;
2925 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2926 goto out;
2927 r = 0;
2928 break;
2929 }
2930 case KVM_SET_PIT2: {
2931 r = -EFAULT;
2932 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2933 goto out;
2934 r = -ENXIO;
2935 if (!kvm->arch.vpit)
2936 goto out;
2937 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2938 if (r)
2939 goto out;
2940 r = 0;
2941 break;
2942 }
52d939a0
MT		 2943 case KVM_REINJECT_CONTROL: {
2944 struct kvm_reinject_control control;
2945 r = -EFAULT;
2946 if (copy_from_user(&control, argp, sizeof(control)))
2947 goto out;
2948 r = kvm_vm_ioctl_reinject(kvm, &control);
2949 if (r)
2950 goto out;
2951 r = 0;
2952 break;
2953 }
ffde22ac
ES		 2954 case KVM_XEN_HVM_CONFIG: {
2955 r = -EFAULT;
2956 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
2957 sizeof(struct kvm_xen_hvm_config)))
2958 goto out;
2959 r = -EINVAL;
2960 if (kvm->arch.xen_hvm_config.flags)
2961 goto out;
2962 r = 0;
2963 break;
2964 }
afbcf7ab
GC		 2965 case KVM_SET_CLOCK: {
2966 struct timespec now;
2967 struct kvm_clock_data user_ns;
2968 u64 now_ns;
2969 s64 delta;
2970
2971 r = -EFAULT;
2972 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
2973 goto out;
2974
2975 r = -EINVAL;
2976 if (user_ns.flags)
2977 goto out;
2978
2979 r = 0;
2980 ktime_get_ts(&now);
2981 now_ns = timespec_to_ns(&now);
2982 delta = user_ns.clock - now_ns;
2983 kvm->arch.kvmclock_offset = delta;
2984 break;
2985 }
2986 case KVM_GET_CLOCK: {
2987 struct timespec now;
2988 struct kvm_clock_data user_ns;
2989 u64 now_ns;
2990
2991 ktime_get_ts(&now);
2992 now_ns = timespec_to_ns(&now);
2993 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
2994 user_ns.flags = 0;
2995
2996 r = -EFAULT;
2997 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
2998 goto out;
2999 r = 0;
3000 break;
3001 }
3002
1fe779f8
CO		 3003 default:
3004 ;
3005 }
3006out:
3007 return r;
3008}
3009
a16b043c 3010static void kvm_init_msr_list(void)
043405e1
CO		 3011{
3012 u32 dummy[2];
3013 unsigned i, j;
3014
e3267cbb
GC		 3015 /* skip the first msrs in the list. KVM-specific */
3016 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3017 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3018 continue;
3019 if (j < i)
3020 msrs_to_save[j] = msrs_to_save[i];
3021 j++;
3022 }
3023 num_msrs_to_save = j;
3024}
3025
bda9020e
MT		 3026static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3027 const void *v)
bbd9b64e 3028{
bda9020e
MT		 3029 if (vcpu->arch.apic &&
3030 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3031 return 0;
bbd9b64e 3032
e93f8a0f 3033 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3034}
3035
bda9020e 3036static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3037{
bda9020e
MT		 3038 if (vcpu->arch.apic &&
3039 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3040 return 0;
bbd9b64e 3041
e93f8a0f 3042 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3043}
3044
1871c602
GN		 3045gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3046{
3047 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3048 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3049}
3050
3051 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3052{
3053 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3054 access |= PFERR_FETCH_MASK;
3055 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3056}
3057
3058gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3059{
3060 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3061 access |= PFERR_WRITE_MASK;
3062 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3063}
3064
3065/* uses this to access any guest's mapped memory without checking CPL */
3066gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3067{
3068 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3069}
3070
3071static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3072 struct kvm_vcpu *vcpu, u32 access,
3073 u32 *error)
bbd9b64e
CO		 3074{
3075 void *data = val;
10589a46 3076 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3077
3078 while (bytes) {
1871c602 3079 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3080 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3081 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3082 int ret;
3083
10589a46
MT		 3084 if (gpa == UNMAPPED_GVA) {
3085 r = X86EMUL_PROPAGATE_FAULT;
3086 goto out;
3087 }
77c2002e 3088 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3089 if (ret < 0) {
3090 r = X86EMUL_UNHANDLEABLE;
3091 goto out;
3092 }
bbd9b64e 3093
77c2002e
IE		 3094 bytes -= toread;
3095 data += toread;
3096 addr += toread;
bbd9b64e 3097 }
10589a46 3098out:
10589a46 3099 return r;
bbd9b64e 3100}
77c2002e 3101
1871c602
GN		 3102/* used for instruction fetching */
3103static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3104 struct kvm_vcpu *vcpu, u32 *error)
3105{
3106 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3107 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3108 access | PFERR_FETCH_MASK, error);
3109}
3110
3111static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3112 struct kvm_vcpu *vcpu, u32 *error)
3113{
3114 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3115 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3116 error);
3117}
3118
3119static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3120 struct kvm_vcpu *vcpu, u32 *error)
3121{
3122 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3123}
3124
cded19f3 3125static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3126 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3127{
3128 void *data = val;
3129 int r = X86EMUL_CONTINUE;
3130
3131 while (bytes) {
1871c602 3132 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3133 unsigned offset = addr & (PAGE_SIZE-1);
3134 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3135 int ret;
3136
3137 if (gpa == UNMAPPED_GVA) {
3138 r = X86EMUL_PROPAGATE_FAULT;
3139 goto out;
3140 }
3141 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3142 if (ret < 0) {
3143 r = X86EMUL_UNHANDLEABLE;
3144 goto out;
3145 }
3146
3147 bytes -= towrite;
3148 data += towrite;
3149 addr += towrite;
3150 }
3151out:
3152 return r;
3153}
3154
bbd9b64e 3155
bbd9b64e
CO		 3156static int emulator_read_emulated(unsigned long addr,
3157 void *val,
3158 unsigned int bytes,
3159 struct kvm_vcpu *vcpu)
3160{
bbd9b64e 3161 gpa_t gpa;
1871c602 3162 u32 error_code;
bbd9b64e
CO		 3163
3164 if (vcpu->mmio_read_completed) {
3165 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3166 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3167 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3168 vcpu->mmio_read_completed = 0;
3169 return X86EMUL_CONTINUE;
3170 }
3171
1871c602
GN		 3172 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3173
3174 if (gpa == UNMAPPED_GVA) {
3175 kvm_inject_page_fault(vcpu, addr, error_code);
3176 return X86EMUL_PROPAGATE_FAULT;
3177 }
bbd9b64e
CO		 3178
3179 /* For APIC access vmexit */
3180 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3181 goto mmio;
3182
1871c602 3183 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3184 == X86EMUL_CONTINUE)
bbd9b64e 3185 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3186
3187mmio:
3188 /*
3189 * Is this MMIO handled locally?
3190 */
aec51dc4
AK		 3191 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3192 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3193 return X86EMUL_CONTINUE;
3194 }
aec51dc4
AK		 3195
3196 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3197
3198 vcpu->mmio_needed = 1;
3199 vcpu->mmio_phys_addr = gpa;
3200 vcpu->mmio_size = bytes;
3201 vcpu->mmio_is_write = 0;
3202
3203 return X86EMUL_UNHANDLEABLE;
3204}
3205
3200f405 3206int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3207 const void *val, int bytes)
bbd9b64e
CO		 3208{
3209 int ret;
3210
3211 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3212 if (ret < 0)
bbd9b64e 3213 return 0;
ad218f85 3214 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3215 return 1;
3216}
3217
3218static int emulator_write_emulated_onepage(unsigned long addr,
3219 const void *val,
3220 unsigned int bytes,
3221 struct kvm_vcpu *vcpu)
3222{
10589a46 3223 gpa_t gpa;
1871c602 3224 u32 error_code;
10589a46 3225
1871c602 3226 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3227
3228 if (gpa == UNMAPPED_GVA) {
1871c602 3229 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3230 return X86EMUL_PROPAGATE_FAULT;
3231 }
3232
3233 /* For APIC access vmexit */
3234 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3235 goto mmio;
3236
3237 if (emulator_write_phys(vcpu, gpa, val, bytes))
3238 return X86EMUL_CONTINUE;
3239
3240mmio:
aec51dc4 3241 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3242 /*
3243 * Is this MMIO handled locally?
3244 */
bda9020e 3245 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3246 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3247
3248 vcpu->mmio_needed = 1;
3249 vcpu->mmio_phys_addr = gpa;
3250 vcpu->mmio_size = bytes;
3251 vcpu->mmio_is_write = 1;
3252 memcpy(vcpu->mmio_data, val, bytes);
3253
3254 return X86EMUL_CONTINUE;
3255}
3256
3257int emulator_write_emulated(unsigned long addr,
3258 const void *val,
3259 unsigned int bytes,
3260 struct kvm_vcpu *vcpu)
3261{
3262 /* Crossing a page boundary? */
3263 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3264 int rc, now;
3265
3266 now = -addr & ~PAGE_MASK;
3267 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3268 if (rc != X86EMUL_CONTINUE)
3269 return rc;
3270 addr += now;
3271 val += now;
3272 bytes -= now;
3273 }
3274 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3275}
3276EXPORT_SYMBOL_GPL(emulator_write_emulated);
3277
3278static int emulator_cmpxchg_emulated(unsigned long addr,
3279 const void *old,
3280 const void *new,
3281 unsigned int bytes,
3282 struct kvm_vcpu *vcpu)
3283{
9f51e24e 3284 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3285#ifndef CONFIG_X86_64
3286 /* guests cmpxchg8b have to be emulated atomically */
3287 if (bytes == 8) {
10589a46 3288 gpa_t gpa;
2bacc55c 3289 struct page *page;
c0b49b0d 3290 char *kaddr;
2bacc55c
MT		 3291 u64 val;
3292
1871c602 3293 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3294
2bacc55c
MT		 3295 if (gpa == UNMAPPED_GVA ||
3296 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3297 goto emul_write;
3298
3299 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3300 goto emul_write;
3301
3302 val = *(u64 *)new;
72dc67a6 3303
2bacc55c 3304 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3305
c0b49b0d
AM		 3306 kaddr = kmap_atomic(page, KM_USER0);
3307 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3308 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3309 kvm_release_page_dirty(page);
3310 }
3200f405 3311emul_write:
2bacc55c
MT		 3312#endif
3313
bbd9b64e
CO		 3314 return emulator_write_emulated(addr, new, bytes, vcpu);
3315}
3316
3317static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3318{
3319 return kvm_x86_ops->get_segment_base(vcpu, seg);
3320}
3321
3322int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3323{
a7052897 3324 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3325 return X86EMUL_CONTINUE;
3326}
3327
3328int emulate_clts(struct kvm_vcpu *vcpu)
3329{
4d4ec087 3330 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3331 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3332 return X86EMUL_CONTINUE;
3333}
3334
3335int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3336{
c76de350 3337 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3338}
3339
3340int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3341{
3342 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3343
c76de350 3344 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3345}
3346
3347void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3348{
bbd9b64e 3349 u8 opcodes[4];
5fdbf976 3350 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3351 unsigned long rip_linear;
3352
f76c710d 3353 if (!printk_ratelimit())
bbd9b64e
CO		 3354 return;
3355
25be4608
GC		 3356 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3357
1871c602 3358 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3359
3360 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3361 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3362}
3363EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3364
14af3f3c 3365static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3366 .read_std = kvm_read_guest_virt_system,
3367 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3368 .read_emulated = emulator_read_emulated,
3369 .write_emulated = emulator_write_emulated,
3370 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3371};
3372
5fdbf976
MT		 3373static void cache_all_regs(struct kvm_vcpu *vcpu)
3374{
3375 kvm_register_read(vcpu, VCPU_REGS_RAX);
3376 kvm_register_read(vcpu, VCPU_REGS_RSP);
3377 kvm_register_read(vcpu, VCPU_REGS_RIP);
3378 vcpu->arch.regs_dirty = ~0;
3379}
3380
bbd9b64e 3381int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3382 unsigned long cr2,
3383 u16 error_code,
571008da 3384 int emulation_type)
bbd9b64e 3385{
310b5d30 3386 int r, shadow_mask;
571008da 3387 struct decode_cache *c;
851ba692 3388 struct kvm_run *run = vcpu->run;
bbd9b64e 3389
26eef70c 3390 kvm_clear_exception_queue(vcpu);
ad312c7c 3391 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3392 /*
56e82318 3393 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3394 * instead of direct ->regs accesses, can save hundred cycles
3395 * on Intel for instructions that don't read/change RSP, for
3396 * for example.
3397 */
3398 cache_all_regs(vcpu);
bbd9b64e
CO		 3399
3400 vcpu->mmio_is_write = 0;
ad312c7c 3401 vcpu->arch.pio.string = 0;
bbd9b64e 3402
571008da 3403 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3404 int cs_db, cs_l;
3405 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3406
ad312c7c 3407 vcpu->arch.emulate_ctxt.vcpu = vcpu;
91586a3b 3408 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
ad312c7c 3409 vcpu->arch.emulate_ctxt.mode =
a0044755 3410 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3411 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3412 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3413 ? X86EMUL_MODE_PROT64 : cs_db
3414 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3415
ad312c7c 3416 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3417
0cb5762e
AP		 3418 /* Only allow emulation of specific instructions on #UD
3419 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3420 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3421 if (emulation_type & EMULTYPE_TRAP_UD) {
3422 if (!c->twobyte)
3423 return EMULATE_FAIL;
3424 switch (c->b) {
3425 case 0x01: /* VMMCALL */
3426 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3427 return EMULATE_FAIL;
3428 break;
3429 case 0x34: /* sysenter */
3430 case 0x35: /* sysexit */
3431 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3432 return EMULATE_FAIL;
3433 break;
3434 case 0x05: /* syscall */
3435 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3436 return EMULATE_FAIL;
3437 break;
3438 default:
3439 return EMULATE_FAIL;
3440 }
3441
3442 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3443 return EMULATE_FAIL;
3444 }
571008da 3445
f2b5756b 3446 ++vcpu->stat.insn_emulation;
bbd9b64e 3447 if (r) {
f2b5756b 3448 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3449 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3450 return EMULATE_DONE;
3451 return EMULATE_FAIL;
3452 }
3453 }
3454
ba8afb6b
GN		 3455 if (emulation_type & EMULTYPE_SKIP) {
3456 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3457 return EMULATE_DONE;
3458 }
3459
ad312c7c 3460 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3461 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3462
3463 if (r == 0)
3464 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3465
ad312c7c 3466 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3467 return EMULATE_DO_MMIO;
3468
3469 if ((r || vcpu->mmio_is_write) && run) {
3470 run->exit_reason = KVM_EXIT_MMIO;
3471 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3472 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3473 run->mmio.len = vcpu->mmio_size;
3474 run->mmio.is_write = vcpu->mmio_is_write;
3475 }
3476
3477 if (r) {
3478 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3479 return EMULATE_DONE;
3480 if (!vcpu->mmio_needed) {
3481 kvm_report_emulation_failure(vcpu, "mmio");
3482 return EMULATE_FAIL;
3483 }
3484 return EMULATE_DO_MMIO;
3485 }
3486
91586a3b 3487 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3488
3489 if (vcpu->mmio_is_write) {
3490 vcpu->mmio_needed = 0;
3491 return EMULATE_DO_MMIO;
3492 }
3493
3494 return EMULATE_DONE;
3495}
3496EXPORT_SYMBOL_GPL(emulate_instruction);
3497
de7d789a
CO		 3498static int pio_copy_data(struct kvm_vcpu *vcpu)
3499{
ad312c7c 3500 void *p = vcpu->arch.pio_data;
0f346074 3501 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3502 unsigned bytes;
0f346074 3503 int ret;
1871c602 3504 u32 error_code;
de7d789a 3505
ad312c7c
ZX		 3506 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3507 if (vcpu->arch.pio.in)
1871c602 3508 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3509 else
1871c602
GN		 3510 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3511
3512 if (ret == X86EMUL_PROPAGATE_FAULT)
3513 kvm_inject_page_fault(vcpu, q, error_code);
3514
0f346074 3515 return ret;
de7d789a
CO		 3516}
3517
3518int complete_pio(struct kvm_vcpu *vcpu)
3519{
ad312c7c 3520 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3521 long delta;
3522 int r;
5fdbf976 3523 unsigned long val;
de7d789a
CO		 3524
3525 if (!io->string) {
5fdbf976
MT		 3526 if (io->in) {
3527 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3528 memcpy(&val, vcpu->arch.pio_data, io->size);
3529 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3530 }
de7d789a
CO		 3531 } else {
3532 if (io->in) {
3533 r = pio_copy_data(vcpu);
5fdbf976 3534 if (r)
1871c602 3535 goto out;
de7d789a
CO		 3536 }
3537
3538 delta = 1;
3539 if (io->rep) {
3540 delta *= io->cur_count;
3541 /*
3542 * The size of the register should really depend on
3543 * current address size.
3544 */
5fdbf976
MT		 3545 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3546 val -= delta;
3547 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3548 }
3549 if (io->down)
3550 delta = -delta;
3551 delta *= io->size;
5fdbf976
MT		 3552 if (io->in) {
3553 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3554 val += delta;
3555 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3556 } else {
3557 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3558 val += delta;
3559 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3560 }
de7d789a 3561 }
1871c602 3562out:
de7d789a
CO		 3563 io->count -= io->cur_count;
3564 io->cur_count = 0;
3565
3566 return 0;
3567}
3568
bda9020e 3569static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3570{
3571 /* TODO: String I/O for in kernel device */
bda9020e 3572 int r;
de7d789a 3573
ad312c7c 3574 if (vcpu->arch.pio.in)
e93f8a0f 3575 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3576 vcpu->arch.pio.size, pd);
de7d789a 3577 else
e93f8a0f
MT		 3578 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3579 vcpu->arch.pio.port, vcpu->arch.pio.size,
3580 pd);
bda9020e 3581 return r;
de7d789a
CO		 3582}
3583
bda9020e 3584static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3585{
ad312c7c
ZX		 3586 struct kvm_pio_request *io = &vcpu->arch.pio;
3587 void *pd = vcpu->arch.pio_data;
bda9020e 3588 int i, r = 0;
de7d789a 3589
de7d789a 3590 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3591 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3592 io->port, io->size, pd)) {
3593 r = -EOPNOTSUPP;
3594 break;
3595 }
de7d789a
CO		 3596 pd += io->size;
3597 }
bda9020e 3598 return r;
de7d789a
CO		 3599}
3600
851ba692 3601int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3602{
5fdbf976 3603 unsigned long val;
de7d789a 3604
f850e2e6
GN		 3605 trace_kvm_pio(!in, port, size, 1);
3606
de7d789a
CO		 3607 vcpu->run->exit_reason = KVM_EXIT_IO;
3608 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3609 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3610 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3611 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3612 vcpu->run->io.port = vcpu->arch.pio.port = port;
3613 vcpu->arch.pio.in = in;
3614 vcpu->arch.pio.string = 0;
3615 vcpu->arch.pio.down = 0;
ad312c7c 3616 vcpu->arch.pio.rep = 0;
de7d789a 3617
1976d2d2
TY		 3618 if (!vcpu->arch.pio.in) {
3619 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3620 memcpy(vcpu->arch.pio_data, &val, 4);
3621 }
de7d789a 3622
bda9020e 3623 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3624 complete_pio(vcpu);
3625 return 1;
3626 }
3627 return 0;
3628}
3629EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3630
851ba692 3631int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3632 int size, unsigned long count, int down,
3633 gva_t address, int rep, unsigned port)
3634{
3635 unsigned now, in_page;
0f346074 3636 int ret = 0;
de7d789a 3637
f850e2e6
GN		 3638 trace_kvm_pio(!in, port, size, count);
3639
de7d789a
CO		 3640 vcpu->run->exit_reason = KVM_EXIT_IO;
3641 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3642 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3643 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3644 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3645 vcpu->run->io.port = vcpu->arch.pio.port = port;
3646 vcpu->arch.pio.in = in;
3647 vcpu->arch.pio.string = 1;
3648 vcpu->arch.pio.down = down;
ad312c7c 3649 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3650
3651 if (!count) {
3652 kvm_x86_ops->skip_emulated_instruction(vcpu);
3653 return 1;
3654 }
3655
3656 if (!down)
3657 in_page = PAGE_SIZE - offset_in_page(address);
3658 else
3659 in_page = offset_in_page(address) + size;
3660 now = min(count, (unsigned long)in_page / size);
0f346074 3661 if (!now)
de7d789a 3662 now = 1;
de7d789a
CO		 3663 if (down) {
3664 /*
3665 * String I/O in reverse. Yuck. Kill the guest, fix later.
3666 */
3667 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3668 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3669 return 1;
3670 }
3671 vcpu->run->io.count = now;
ad312c7c 3672 vcpu->arch.pio.cur_count = now;
de7d789a 3673
ad312c7c 3674 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3675 kvm_x86_ops->skip_emulated_instruction(vcpu);
3676
0f346074 3677 vcpu->arch.pio.guest_gva = address;
de7d789a 3678
ad312c7c 3679 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3680 /* string PIO write */
3681 ret = pio_copy_data(vcpu);
1871c602 3682 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3683 return 1;
bda9020e 3684 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3685 complete_pio(vcpu);
ad312c7c 3686 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3687 ret = 1;
3688 }
bda9020e
MT		 3689 }
3690 /* no string PIO read support yet */
de7d789a
CO		 3691
3692 return ret;
3693}
3694EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3695
c8076604
GH		 3696static void bounce_off(void *info)
3697{
3698 /* nothing */
3699}
3700
c8076604
GH		 3701static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3702 void *data)
3703{
3704 struct cpufreq_freqs *freq = data;
3705 struct kvm *kvm;
3706 struct kvm_vcpu *vcpu;
3707 int i, send_ipi = 0;
3708
c8076604
GH		 3709 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3710 return 0;
3711 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3712 return 0;
0cca7907 3713 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3714
3715 spin_lock(&kvm_lock);
3716 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3717 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3718 if (vcpu->cpu != freq->cpu)
3719 continue;
3720 if (!kvm_request_guest_time_update(vcpu))
3721 continue;
3722 if (vcpu->cpu != smp_processor_id())
3723 send_ipi++;
3724 }
3725 }
3726 spin_unlock(&kvm_lock);
3727
3728 if (freq->old < freq->new && send_ipi) {
3729 /*
3730 * We upscale the frequency. Must make the guest
3731 * doesn't see old kvmclock values while running with
3732 * the new frequency, otherwise we risk the guest sees
3733 * time go backwards.
3734 *
3735 * In case we update the frequency for another cpu
3736 * (which might be in guest context) send an interrupt
3737 * to kick the cpu out of guest context. Next time
3738 * guest context is entered kvmclock will be updated,
3739 * so the guest will not see stale values.
3740 */
3741 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3742 }
3743 return 0;
3744}
3745
3746static struct notifier_block kvmclock_cpufreq_notifier_block = {
3747 .notifier_call = kvmclock_cpufreq_notifier
3748};
3749
b820cc0c
ZA		 3750static void kvm_timer_init(void)
3751{
3752 int cpu;
3753
b820cc0c 3754 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3755 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3756 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3757 for_each_online_cpu(cpu) {
3758 unsigned long khz = cpufreq_get(cpu);
3759 if (!khz)
3760 khz = tsc_khz;
3761 per_cpu(cpu_tsc_khz, cpu) = khz;
3762 }
0cca7907
ZA		 3763 } else {
3764 for_each_possible_cpu(cpu)
3765 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3766 }
3767}
3768
ff9d07a0
ZY		 3769static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
3770
3771static int kvm_is_in_guest(void)
3772{
3773 return percpu_read(current_vcpu) != NULL;
3774}
3775
3776static int kvm_is_user_mode(void)
3777{
3778 int user_mode = 3;
dcf46b94 3779
ff9d07a0
ZY		 3780 if (percpu_read(current_vcpu))
3781 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 3782
ff9d07a0
ZY		 3783 return user_mode != 0;
3784}
3785
3786static unsigned long kvm_get_guest_ip(void)
3787{
3788 unsigned long ip = 0;
dcf46b94 3789
ff9d07a0
ZY		 3790 if (percpu_read(current_vcpu))
3791 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 3792
ff9d07a0
ZY		 3793 return ip;
3794}
3795
3796static struct perf_guest_info_callbacks kvm_guest_cbs = {
3797 .is_in_guest = kvm_is_in_guest,
3798 .is_user_mode = kvm_is_user_mode,
3799 .get_guest_ip = kvm_get_guest_ip,
3800};
3801
3802void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
3803{
3804 percpu_write(current_vcpu, vcpu);
3805}
3806EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
3807
3808void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
3809{
3810 percpu_write(current_vcpu, NULL);
3811}
3812EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
3813
f8c16bba 3814int kvm_arch_init(void *opaque)
043405e1 3815{
b820cc0c 3816 int r;
f8c16bba
ZX		 3817 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3818
f8c16bba
ZX		 3819 if (kvm_x86_ops) {
3820 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3821 r = -EEXIST;
3822 goto out;
f8c16bba
ZX		 3823 }
3824
3825 if (!ops->cpu_has_kvm_support()) {
3826 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3827 r = -EOPNOTSUPP;
3828 goto out;
f8c16bba
ZX		 3829 }
3830 if (ops->disabled_by_bios()) {
3831 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3832 r = -EOPNOTSUPP;
3833 goto out;
f8c16bba
ZX		 3834 }
3835
97db56ce
AK		 3836 r = kvm_mmu_module_init();
3837 if (r)
3838 goto out;
3839
3840 kvm_init_msr_list();
3841
f8c16bba 3842 kvm_x86_ops = ops;
56c6d28a 3843 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3844 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3845 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3846 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3847
b820cc0c 3848 kvm_timer_init();
c8076604 3849
ff9d07a0
ZY		 3850 perf_register_guest_info_callbacks(&kvm_guest_cbs);
3851
f8c16bba 3852 return 0;
56c6d28a
ZX		 3853
3854out:
56c6d28a 3855 return r;
043405e1 3856}
8776e519 3857
f8c16bba
ZX		 3858void kvm_arch_exit(void)
3859{
ff9d07a0
ZY		 3860 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
3861
888d256e
JK		 3862 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3863 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3864 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3865 kvm_x86_ops = NULL;
56c6d28a
ZX		 3866 kvm_mmu_module_exit();
3867}
f8c16bba 3868
8776e519
HB		 3869int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3870{
3871 ++vcpu->stat.halt_exits;
3872 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3873 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3874 return 1;
3875 } else {
3876 vcpu->run->exit_reason = KVM_EXIT_HLT;
3877 return 0;
3878 }
3879}
3880EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3881
2f333bcb
MT		 3882static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3883 unsigned long a1)
3884{
3885 if (is_long_mode(vcpu))
3886 return a0;
3887 else
3888 return a0 | ((gpa_t)a1 << 32);
3889}
3890
55cd8e5a
GN		 3891int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3892{
3893 u64 param, ingpa, outgpa, ret;
3894 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3895 bool fast, longmode;
3896 int cs_db, cs_l;
3897
3898 /*
3899 * hypercall generates UD from non zero cpl and real mode
3900 * per HYPER-V spec
3901 */
3eeb3288 3902 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3903 kvm_queue_exception(vcpu, UD_VECTOR);
3904 return 0;
3905 }
3906
3907 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3908 longmode = is_long_mode(vcpu) && cs_l == 1;
3909
3910 if (!longmode) {
ccd46936
GN		 3911 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3912 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3913 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3914 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3915 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3916 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3917 }
3918#ifdef CONFIG_X86_64
3919 else {
3920 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3921 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3922 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3923 }
3924#endif
3925
3926 code = param & 0xffff;
3927 fast = (param >> 16) & 0x1;
3928 rep_cnt = (param >> 32) & 0xfff;
3929 rep_idx = (param >> 48) & 0xfff;
3930
3931 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3932
c25bc163
GN		 3933 switch (code) {
3934 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3935 kvm_vcpu_on_spin(vcpu);
3936 break;
3937 default:
3938 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3939 break;
3940 }
55cd8e5a
GN		 3941
3942 ret = res | (((u64)rep_done & 0xfff) << 32);
3943 if (longmode) {
3944 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3945 } else {
3946 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3947 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3948 }
3949
3950 return 1;
3951}
3952
8776e519
HB		 3953int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3954{
3955 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3956 int r = 1;
8776e519 3957
55cd8e5a
GN		 3958 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3959 return kvm_hv_hypercall(vcpu);
3960
5fdbf976
MT		 3961 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3962 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3963 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3964 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3965 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3966
229456fc 3967 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3968
8776e519
HB		 3969 if (!is_long_mode(vcpu)) {
3970 nr &= 0xFFFFFFFF;
3971 a0 &= 0xFFFFFFFF;
3972 a1 &= 0xFFFFFFFF;
3973 a2 &= 0xFFFFFFFF;
3974 a3 &= 0xFFFFFFFF;
3975 }
3976
07708c4a
JK		 3977 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3978 ret = -KVM_EPERM;
3979 goto out;
3980 }
3981
8776e519 3982 switch (nr) {
b93463aa
AK		 3983 case KVM_HC_VAPIC_POLL_IRQ:
3984 ret = 0;
3985 break;
2f333bcb
MT		 3986 case KVM_HC_MMU_OP:
3987 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3988 break;
8776e519
HB		 3989 default:
3990 ret = -KVM_ENOSYS;
3991 break;
3992 }
07708c4a 3993out:
5fdbf976 3994 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3995 ++vcpu->stat.hypercalls;
2f333bcb 3996 return r;
8776e519
HB		 3997}
3998EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3999
4000int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4001{
4002 char instruction[3];
5fdbf976 4003 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4004
8776e519
HB		 4005 /*
4006 * Blow out the MMU to ensure that no other VCPU has an active mapping
4007 * to ensure that the updated hypercall appears atomically across all
4008 * VCPUs.
4009 */
4010 kvm_mmu_zap_all(vcpu->kvm);
4011
8776e519 4012 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4013
7edcface 4014 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4015}
4016
4017static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4018{
4019 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4020}
4021
4022void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4023{
4024 struct descriptor_table dt = { limit, base };
4025
4026 kvm_x86_ops->set_gdt(vcpu, &dt);
4027}
4028
4029void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4030{
4031 struct descriptor_table dt = { limit, base };
4032
4033 kvm_x86_ops->set_idt(vcpu, &dt);
4034}
4035
4036void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
4037 unsigned long *rflags)
4038{
2d3ad1f4 4039 kvm_lmsw(vcpu, msw);
91586a3b 4040 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4041}
4042
4043unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
4044{
54e445ca
JR		 4045 unsigned long value;
4046
8776e519
HB		 4047 switch (cr) {
4048 case 0:
4d4ec087 4049 value = kvm_read_cr0(vcpu);
54e445ca 4050 break;
8776e519 4051 case 2:
54e445ca
JR		 4052 value = vcpu->arch.cr2;
4053 break;
8776e519 4054 case 3:
54e445ca
JR		 4055 value = vcpu->arch.cr3;
4056 break;
8776e519 4057 case 4:
fc78f519 4058 value = kvm_read_cr4(vcpu);
54e445ca 4059 break;
152ff9be 4060 case 8:
54e445ca
JR		 4061 value = kvm_get_cr8(vcpu);
4062 break;
8776e519 4063 default:
b8688d51 4064 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4065 return 0;
4066 }
54e445ca
JR		 4067
4068 return value;
8776e519
HB		 4069}
4070
4071void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
4072 unsigned long *rflags)
4073{
4074 switch (cr) {
4075 case 0:
4d4ec087 4076 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4077 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4078 break;
4079 case 2:
ad312c7c 4080 vcpu->arch.cr2 = val;
8776e519
HB		 4081 break;
4082 case 3:
2d3ad1f4 4083 kvm_set_cr3(vcpu, val);
8776e519
HB		 4084 break;
4085 case 4:
fc78f519 4086 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4087 break;
152ff9be 4088 case 8:
2d3ad1f4 4089 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4090 break;
8776e519 4091 default:
b8688d51 4092 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4093 }
4094}
4095
07716717
DK		 4096static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4097{
ad312c7c
ZX		 4098 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4099 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4100
4101 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4102 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4103 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4104 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4105 if (ej->function == e->function) {
4106 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4107 return j;
4108 }
4109 }
4110 return 0; /* silence gcc, even though control never reaches here */
4111}
4112
4113/* find an entry with matching function, matching index (if needed), and that
4114 * should be read next (if it's stateful) */
4115static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4116 u32 function, u32 index)
4117{
4118 if (e->function != function)
4119 return 0;
4120 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4121 return 0;
4122 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4123 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4124 return 0;
4125 return 1;
4126}
4127
d8017474
AG		 4128struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4129 u32 function, u32 index)
8776e519
HB		 4130{
4131 int i;
d8017474 4132 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4133
ad312c7c 4134 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4135 struct kvm_cpuid_entry2 *e;
4136
ad312c7c 4137 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4138 if (is_matching_cpuid_entry(e, function, index)) {
4139 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4140 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4141 best = e;
4142 break;
4143 }
4144 /*
4145 * Both basic or both extended?
4146 */
4147 if (((e->function ^ function) & 0x80000000) == 0)
4148 if (!best || e->function > best->function)
4149 best = e;
4150 }
d8017474
AG		 4151 return best;
4152}
0e851880 4153EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4154
82725b20
DE		 4155int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4156{
4157 struct kvm_cpuid_entry2 *best;
4158
4159 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4160 if (best)
4161 return best->eax & 0xff;
4162 return 36;
4163}
4164
d8017474
AG		 4165void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4166{
4167 u32 function, index;
4168 struct kvm_cpuid_entry2 *best;
4169
4170 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4171 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4172 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4173 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4174 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4175 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4176 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4177 if (best) {
5fdbf976
MT		 4178 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4179 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4180 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4181 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4182 }
8776e519 4183 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4184 trace_kvm_cpuid(function,
4185 kvm_register_read(vcpu, VCPU_REGS_RAX),
4186 kvm_register_read(vcpu, VCPU_REGS_RBX),
4187 kvm_register_read(vcpu, VCPU_REGS_RCX),
4188 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4189}
4190EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4191
b6c7a5dc
HB		 4192/*
4193 * Check if userspace requested an interrupt window, and that the
4194 * interrupt window is open.
4195 *
4196 * No need to exit to userspace if we already have an interrupt queued.
4197 */
851ba692 4198static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4199{
8061823a 4200 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4201 vcpu->run->request_interrupt_window &&
5df56646 4202 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4203}
4204
851ba692 4205static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4206{
851ba692
AK		 4207 struct kvm_run *kvm_run = vcpu->run;
4208
91586a3b 4209 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4210 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4211 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4212 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4213 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4214 else
b6c7a5dc 4215 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4216 kvm_arch_interrupt_allowed(vcpu) &&
4217 !kvm_cpu_has_interrupt(vcpu) &&
4218 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4219}
4220
b93463aa
AK		 4221static void vapic_enter(struct kvm_vcpu *vcpu)
4222{
4223 struct kvm_lapic *apic = vcpu->arch.apic;
4224 struct page *page;
4225
4226 if (!apic || !apic->vapic_addr)
4227 return;
4228
4229 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4230
4231 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4232}
4233
4234static void vapic_exit(struct kvm_vcpu *vcpu)
4235{
4236 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4237 int idx;
b93463aa
AK		 4238
4239 if (!apic || !apic->vapic_addr)
4240 return;
4241
f656ce01 4242 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4243 kvm_release_page_dirty(apic->vapic_page);
4244 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4245 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4246}
4247
95ba8273
GN		 4248static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4249{
4250 int max_irr, tpr;
4251
4252 if (!kvm_x86_ops->update_cr8_intercept)
4253 return;
4254
88c808fd
AK		 4255 if (!vcpu->arch.apic)
4256 return;
4257
8db3baa2
GN		 4258 if (!vcpu->arch.apic->vapic_addr)
4259 max_irr = kvm_lapic_find_highest_irr(vcpu);
4260 else
4261 max_irr = -1;
95ba8273
GN		 4262
4263 if (max_irr != -1)
4264 max_irr >>= 4;
4265
4266 tpr = kvm_lapic_get_cr8(vcpu);
4267
4268 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4269}
4270
851ba692 4271static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4272{
4273 /* try to reinject previous events if any */
b59bb7bd
GN		 4274 if (vcpu->arch.exception.pending) {
4275 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4276 vcpu->arch.exception.has_error_code,
4277 vcpu->arch.exception.error_code);
4278 return;
4279 }
4280
95ba8273
GN		 4281 if (vcpu->arch.nmi_injected) {
4282 kvm_x86_ops->set_nmi(vcpu);
4283 return;
4284 }
4285
4286 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4287 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4288 return;
4289 }
4290
4291 /* try to inject new event if pending */
4292 if (vcpu->arch.nmi_pending) {
4293 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4294 vcpu->arch.nmi_pending = false;
4295 vcpu->arch.nmi_injected = true;
4296 kvm_x86_ops->set_nmi(vcpu);
4297 }
4298 } else if (kvm_cpu_has_interrupt(vcpu)) {
4299 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4300 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4301 false);
4302 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4303 }
4304 }
4305}
4306
851ba692 4307static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4308{
4309 int r;
6a8b1d13 4310 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4311 vcpu->run->request_interrupt_window;
b6c7a5dc 4312
2e53d63a
MT		 4313 if (vcpu->requests)
4314 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4315 kvm_mmu_unload(vcpu);
4316
b6c7a5dc
HB		 4317 r = kvm_mmu_reload(vcpu);
4318 if (unlikely(r))
4319 goto out;
4320
2f52d58c
AK		 4321 if (vcpu->requests) {
4322 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4323 __kvm_migrate_timers(vcpu);
c8076604
GH		 4324 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4325 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4326 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4327 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4328 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4329 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4330 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4331 &vcpu->requests)) {
851ba692 4332 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4333 r = 0;
4334 goto out;
4335 }
71c4dfaf 4336 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4337 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4338 r = 0;
4339 goto out;
4340 }
02daab21
AK		 4341 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4342 vcpu->fpu_active = 0;
4343 kvm_x86_ops->fpu_deactivate(vcpu);
4344 }
2f52d58c 4345 }
b93463aa 4346
b6c7a5dc
HB		 4347 preempt_disable();
4348
4349 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4350 if (vcpu->fpu_active)
4351 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4352
4353 local_irq_disable();
4354
32f88400
MT		 4355 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4356 smp_mb__after_clear_bit();
4357
d7690175 4358 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4359 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4360 local_irq_enable();
4361 preempt_enable();
4362 r = 1;
4363 goto out;
4364 }
4365
851ba692 4366 inject_pending_event(vcpu);
b6c7a5dc 4367
6a8b1d13
GN		 4368 /* enable NMI/IRQ window open exits if needed */
4369 if (vcpu->arch.nmi_pending)
4370 kvm_x86_ops->enable_nmi_window(vcpu);
4371 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4372 kvm_x86_ops->enable_irq_window(vcpu);
4373
95ba8273 4374 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4375 update_cr8_intercept(vcpu);
4376 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4377 }
b93463aa 4378
f656ce01 4379 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4380
b6c7a5dc
HB		 4381 kvm_guest_enter();
4382
42dbaa5a 4383 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4384 set_debugreg(0, 7);
4385 set_debugreg(vcpu->arch.eff_db[0], 0);
4386 set_debugreg(vcpu->arch.eff_db[1], 1);
4387 set_debugreg(vcpu->arch.eff_db[2], 2);
4388 set_debugreg(vcpu->arch.eff_db[3], 3);
4389 }
b6c7a5dc 4390
229456fc 4391 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4392 kvm_x86_ops->run(vcpu);
b6c7a5dc 4393
24f1e32c
FW		 4394 /*
4395 * If the guest has used debug registers, at least dr7
4396 * will be disabled while returning to the host.
4397 * If we don't have active breakpoints in the host, we don't
4398 * care about the messed up debug address registers. But if
4399 * we have some of them active, restore the old state.
4400 */
59d8eb53 4401 if (hw_breakpoint_active())
24f1e32c 4402 hw_breakpoint_restore();
42dbaa5a 4403
32f88400 4404 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4405 local_irq_enable();
4406
4407 ++vcpu->stat.exits;
4408
4409 /*
4410 * We must have an instruction between local_irq_enable() and
4411 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4412 * the interrupt shadow. The stat.exits increment will do nicely.
4413 * But we need to prevent reordering, hence this barrier():
4414 */
4415 barrier();
4416
4417 kvm_guest_exit();
4418
4419 preempt_enable();
4420
f656ce01 4421 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4422
b6c7a5dc
HB		 4423 /*
4424 * Profile KVM exit RIPs:
4425 */
4426 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4427 unsigned long rip = kvm_rip_read(vcpu);
4428 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4429 }
4430
298101da 4431
b93463aa
AK		 4432 kvm_lapic_sync_from_vapic(vcpu);
4433
851ba692 4434 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4435out:
4436 return r;
4437}
b6c7a5dc 4438
09cec754 4439
851ba692 4440static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4441{
4442 int r;
f656ce01 4443 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4444
4445 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4446 pr_debug("vcpu %d received sipi with vector # %x\n",
4447 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4448 kvm_lapic_reset(vcpu);
5f179287 4449 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4450 if (r)
4451 return r;
4452 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4453 }
4454
f656ce01 4455 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4456 vapic_enter(vcpu);
4457
4458 r = 1;
4459 while (r > 0) {
af2152f5 4460 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4461 r = vcpu_enter_guest(vcpu);
d7690175 4462 else {
f656ce01 4463 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4464 kvm_vcpu_block(vcpu);
f656ce01 4465 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4466 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4467 {
4468 switch(vcpu->arch.mp_state) {
4469 case KVM_MP_STATE_HALTED:
d7690175 4470 vcpu->arch.mp_state =
09cec754
GN		 4471 KVM_MP_STATE_RUNNABLE;
4472 case KVM_MP_STATE_RUNNABLE:
4473 break;
4474 case KVM_MP_STATE_SIPI_RECEIVED:
4475 default:
4476 r = -EINTR;
4477 break;
4478 }
4479 }
d7690175
MT		 4480 }
4481
09cec754
GN		 4482 if (r <= 0)
4483 break;
4484
4485 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4486 if (kvm_cpu_has_pending_timer(vcpu))
4487 kvm_inject_pending_timer_irqs(vcpu);
4488
851ba692 4489 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4490 r = -EINTR;
851ba692 4491 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4492 ++vcpu->stat.request_irq_exits;
4493 }
4494 if (signal_pending(current)) {
4495 r = -EINTR;
851ba692 4496 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4497 ++vcpu->stat.signal_exits;
4498 }
4499 if (need_resched()) {
f656ce01 4500 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4501 kvm_resched(vcpu);
f656ce01 4502 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4503 }
b6c7a5dc
HB		 4504 }
4505
f656ce01 4506 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4507 post_kvm_run_save(vcpu);
b6c7a5dc 4508
b93463aa
AK		 4509 vapic_exit(vcpu);
4510
b6c7a5dc
HB		 4511 return r;
4512}
4513
4514int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4515{
4516 int r;
4517 sigset_t sigsaved;
4518
4519 vcpu_load(vcpu);
4520
ac9f6dc0
AK		 4521 if (vcpu->sigset_active)
4522 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4523
a4535290 4524 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4525 kvm_vcpu_block(vcpu);
d7690175 4526 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4527 r = -EAGAIN;
4528 goto out;
b6c7a5dc
HB		 4529 }
4530
b6c7a5dc
HB		 4531 /* re-sync apic's tpr */
4532 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4533 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4534
ad312c7c 4535 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 4536 r = complete_pio(vcpu);
4537 if (r)
4538 goto out;
4539 }
b6c7a5dc
HB		 4540 if (vcpu->mmio_needed) {
4541 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4542 vcpu->mmio_read_completed = 1;
4543 vcpu->mmio_needed = 0;
3200f405 4544
f656ce01 4545 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4546 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4547 EMULTYPE_NO_DECODE);
f656ce01 4548 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4549 if (r == EMULATE_DO_MMIO) {
4550 /*
4551 * Read-modify-write. Back to userspace.
4552 */
4553 r = 0;
4554 goto out;
4555 }
4556 }
5fdbf976
MT		 4557 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4558 kvm_register_write(vcpu, VCPU_REGS_RAX,
4559 kvm_run->hypercall.ret);
b6c7a5dc 4560
851ba692 4561 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4562
4563out:
4564 if (vcpu->sigset_active)
4565 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4566
4567 vcpu_put(vcpu);
4568 return r;
4569}
4570
4571int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4572{
4573 vcpu_load(vcpu);
4574
5fdbf976
MT		 4575 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4576 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4577 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4578 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4579 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4580 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4581 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4582 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4583#ifdef CONFIG_X86_64
5fdbf976
MT		 4584 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4585 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4586 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4587 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4588 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4589 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4590 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4591 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4592#endif
4593
5fdbf976 4594 regs->rip = kvm_rip_read(vcpu);
91586a3b 4595 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4596
4597 vcpu_put(vcpu);
4598
4599 return 0;
4600}
4601
4602int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4603{
4604 vcpu_load(vcpu);
4605
5fdbf976
MT		 4606 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4607 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4608 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4609 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4610 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4611 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4612 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4613 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4614#ifdef CONFIG_X86_64
5fdbf976
MT		 4615 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4616 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4617 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4618 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4619 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4620 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4621 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4622 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4623#endif
4624
5fdbf976 4625 kvm_rip_write(vcpu, regs->rip);
91586a3b 4626 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4627
b4f14abd
JK		 4628 vcpu->arch.exception.pending = false;
4629
b6c7a5dc
HB		 4630 vcpu_put(vcpu);
4631
4632 return 0;
4633}
4634
3e6e0aab
GT		 4635void kvm_get_segment(struct kvm_vcpu *vcpu,
4636 struct kvm_segment *var, int seg)
b6c7a5dc 4637{
14af3f3c 4638 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4639}
4640
4641void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4642{
4643 struct kvm_segment cs;
4644
3e6e0aab 4645 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4646 *db = cs.db;
4647 *l = cs.l;
4648}
4649EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4650
4651int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4652 struct kvm_sregs *sregs)
4653{
4654 struct descriptor_table dt;
b6c7a5dc
HB		 4655
4656 vcpu_load(vcpu);
4657
3e6e0aab
GT		 4658 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4659 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4660 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4661 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4662 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4663 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4664
3e6e0aab
GT		 4665 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4666 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4667
4668 kvm_x86_ops->get_idt(vcpu, &dt);
4669 sregs->idt.limit = dt.limit;
4670 sregs->idt.base = dt.base;
4671 kvm_x86_ops->get_gdt(vcpu, &dt);
4672 sregs->gdt.limit = dt.limit;
4673 sregs->gdt.base = dt.base;
4674
4d4ec087 4675 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4676 sregs->cr2 = vcpu->arch.cr2;
4677 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4678 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4679 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4680 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4681 sregs->apic_base = kvm_get_apic_base(vcpu);
4682
923c61bb 4683 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4684
36752c9b 4685 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4686 set_bit(vcpu->arch.interrupt.nr,
4687 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4688
b6c7a5dc
HB		 4689 vcpu_put(vcpu);
4690
4691 return 0;
4692}
4693
62d9f0db
MT		 4694int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4695 struct kvm_mp_state *mp_state)
4696{
4697 vcpu_load(vcpu);
4698 mp_state->mp_state = vcpu->arch.mp_state;
4699 vcpu_put(vcpu);
4700 return 0;
4701}
4702
4703int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4704 struct kvm_mp_state *mp_state)
4705{
4706 vcpu_load(vcpu);
4707 vcpu->arch.mp_state = mp_state->mp_state;
4708 vcpu_put(vcpu);
4709 return 0;
4710}
4711
3e6e0aab 4712static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4713 struct kvm_segment *var, int seg)
4714{
14af3f3c 4715 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4716}
4717
37817f29
IE		 4718static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4719 struct kvm_segment *kvm_desct)
4720{
46a359e7
AM		 4721 kvm_desct->base = get_desc_base(seg_desc);
4722 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4723 if (seg_desc->g) {
4724 kvm_desct->limit <<= 12;
4725 kvm_desct->limit |= 0xfff;
4726 }
37817f29
IE		 4727 kvm_desct->selector = selector;
4728 kvm_desct->type = seg_desc->type;
4729 kvm_desct->present = seg_desc->p;
4730 kvm_desct->dpl = seg_desc->dpl;
4731 kvm_desct->db = seg_desc->d;
4732 kvm_desct->s = seg_desc->s;
4733 kvm_desct->l = seg_desc->l;
4734 kvm_desct->g = seg_desc->g;
4735 kvm_desct->avl = seg_desc->avl;
4736 if (!selector)
4737 kvm_desct->unusable = 1;
4738 else
4739 kvm_desct->unusable = 0;
4740 kvm_desct->padding = 0;
4741}
4742
b8222ad2
AS		 4743static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4744 u16 selector,
4745 struct descriptor_table *dtable)
37817f29
IE		 4746{
4747 if (selector & 1 << 2) {
4748 struct kvm_segment kvm_seg;
4749
3e6e0aab 4750 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4751
4752 if (kvm_seg.unusable)
4753 dtable->limit = 0;
4754 else
4755 dtable->limit = kvm_seg.limit;
4756 dtable->base = kvm_seg.base;
4757 }
4758 else
4759 kvm_x86_ops->get_gdt(vcpu, dtable);
4760}
4761
4762/* allowed just for 8 bytes segments */
4763static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4764 struct desc_struct *seg_desc)
4765{
4766 struct descriptor_table dtable;
4767 u16 index = selector >> 3;
6f550484
TY		 4768 int ret;
4769 u32 err;
4770 gva_t addr;
37817f29 4771
b8222ad2 4772 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4773
4774 if (dtable.limit < index * 8 + 7) {
4775 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4776 return X86EMUL_PROPAGATE_FAULT;
37817f29 4777 }
6f550484
TY		 4778 addr = dtable.base + index * 8;
4779 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4780 vcpu, &err);
4781 if (ret == X86EMUL_PROPAGATE_FAULT)
4782 kvm_inject_page_fault(vcpu, addr, err);
4783
4784 return ret;
37817f29
IE		 4785}
4786
4787/* allowed just for 8 bytes segments */
4788static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4789 struct desc_struct *seg_desc)
4790{
4791 struct descriptor_table dtable;
4792 u16 index = selector >> 3;
4793
b8222ad2 4794 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 4795
4796 if (dtable.limit < index * 8 + 7)
4797 return 1;
1871c602
GN		 4798 return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
4799}
4800
4801static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4802 struct desc_struct *seg_desc)
4803{
4804 u32 base_addr = get_desc_base(seg_desc);
4805
4806 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4807}
4808
1871c602 4809static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4810 struct desc_struct *seg_desc)
4811{
46a359e7 4812 u32 base_addr = get_desc_base(seg_desc);
37817f29 4813
1871c602 4814 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4815}
4816
37817f29
IE		 4817static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4818{
4819 struct kvm_segment kvm_seg;
4820
3e6e0aab 4821 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4822 return kvm_seg.selector;
4823}
4824
2259e3a7 4825static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4826{
4827 struct kvm_segment segvar = {
4828 .base = selector << 4,
4829 .limit = 0xffff,
4830 .selector = selector,
4831 .type = 3,
4832 .present = 1,
4833 .dpl = 3,
4834 .db = 0,
4835 .s = 1,
4836 .l = 0,
4837 .g = 0,
4838 .avl = 0,
4839 .unusable = 0,
4840 };
4841 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4842 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4843}
4844
c0c7c04b
AL		 4845static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4846{
4847 return (seg != VCPU_SREG_LDTR) &&
4848 (seg != VCPU_SREG_TR) &&
91586a3b 4849 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4850}
4851
c697518a 4852int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4853{
4854 struct kvm_segment kvm_seg;
e01c2426 4855 struct desc_struct seg_desc;
c697518a
GN		 4856 u8 dpl, rpl, cpl;
4857 unsigned err_vec = GP_VECTOR;
4858 u32 err_code = 0;
4859 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4860 int ret;
37817f29 4861
3eeb3288 4862 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4863 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4864
c697518a
GN		 4865 /* NULL selector is not valid for TR, CS and SS */
4866 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4867 && null_selector)
4868 goto exception;
4869
4870 /* TR should be in GDT only */
4871 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4872 goto exception;
4873
4874 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4875 if (ret)
4876 return ret;
4877
e01c2426 4878 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4879
c697518a
GN		 4880 if (null_selector) { /* for NULL selector skip all following checks */
4881 kvm_seg.unusable = 1;
4882 goto load;
4883 }
37817f29 4884
c697518a
GN		 4885 err_code = selector & 0xfffc;
4886 err_vec = GP_VECTOR;
37817f29 4887
c697518a
GN		 4888 /* can't load system descriptor into segment selecor */
4889 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4890 goto exception;
4891
4892 if (!kvm_seg.present) {
4893 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4894 goto exception;
4895 }
4896
4897 rpl = selector & 3;
4898 dpl = kvm_seg.dpl;
4899 cpl = kvm_x86_ops->get_cpl(vcpu);
4900
4901 switch (seg) {
4902 case VCPU_SREG_SS:
4903 /*
4904 * segment is not a writable data segment or segment
4905 * selector's RPL != CPL or segment selector's RPL != CPL
4906 */
4907 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4908 goto exception;
4909 break;
4910 case VCPU_SREG_CS:
4911 if (!(kvm_seg.type & 8))
4912 goto exception;
4913
4914 if (kvm_seg.type & 4) {
4915 /* conforming */
4916 if (dpl > cpl)
4917 goto exception;
4918 } else {
4919 /* nonconforming */
4920 if (rpl > cpl || dpl != cpl)
4921 goto exception;
4922 }
4923 /* CS(RPL) <- CPL */
4924 selector = (selector & 0xfffc) | cpl;
4925 break;
4926 case VCPU_SREG_TR:
4927 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4928 goto exception;
4929 break;
4930 case VCPU_SREG_LDTR:
4931 if (kvm_seg.s || kvm_seg.type != 2)
4932 goto exception;
4933 break;
4934 default: /* DS, ES, FS, or GS */
4935 /*
4936 * segment is not a data or readable code segment or
4937 * ((segment is a data or nonconforming code segment)
4938 * and (both RPL and CPL > DPL))
4939 */
4940 if ((kvm_seg.type & 0xa) == 0x8 ||
4941 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4942 goto exception;
4943 break;
4944 }
4945
4946 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4947 /* mark segment as accessed */
c697518a 4948 kvm_seg.type |= 1;
e01c2426
GN		 4949 seg_desc.type |= 1;
4950 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4951 }
c697518a
GN		 4952load:
4953 kvm_set_segment(vcpu, &kvm_seg, seg);
4954 return X86EMUL_CONTINUE;
4955exception:
4956 kvm_queue_exception_e(vcpu, err_vec, err_code);
4957 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4958}
4959
4960static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4961 struct tss_segment_32 *tss)
4962{
4963 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4964 tss->eip = kvm_rip_read(vcpu);
91586a3b 4965 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4966 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4967 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4968 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4969 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4970 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4971 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4972 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4973 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4974 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4975 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4976 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4977 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4978 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4979 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4980 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4981}
4982
c697518a
GN		 4983static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4984{
4985 struct kvm_segment kvm_seg;
4986 kvm_get_segment(vcpu, &kvm_seg, seg);
4987 kvm_seg.selector = sel;
4988 kvm_set_segment(vcpu, &kvm_seg, seg);
4989}
4990
37817f29
IE		 4991static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4992 struct tss_segment_32 *tss)
4993{
4994 kvm_set_cr3(vcpu, tss->cr3);
4995
5fdbf976 4996 kvm_rip_write(vcpu, tss->eip);
91586a3b 4997 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4998
5fdbf976
MT		 4999 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
5000 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
5001 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
5002 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
5003 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
5004 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
5005 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
5006 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 5007
c697518a
GN		 5008 /*
5009 * SDM says that segment selectors are loaded before segment
5010 * descriptors
5011 */
5012 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
5013 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5014 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5015 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5016 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5017 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
5018 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
5019
5020 /*
5021 * Now load segment descriptors. If fault happenes at this stage
5022 * it is handled in a context of new task
5023 */
5024 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 5025 return 1;
5026
c697518a 5027 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5028 return 1;
5029
c697518a 5030 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5031 return 1;
5032
c697518a 5033 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5034 return 1;
5035
c697518a 5036 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5037 return 1;
5038
c697518a 5039 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 5040 return 1;
5041
c697518a 5042 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 5043 return 1;
5044 return 0;
5045}
5046
5047static void save_state_to_tss16(struct kvm_vcpu *vcpu,
5048 struct tss_segment_16 *tss)
5049{
5fdbf976 5050 tss->ip = kvm_rip_read(vcpu);
91586a3b 5051 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 5052 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5053 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5054 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5055 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5056 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5057 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5058 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
5059 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 5060
5061 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
5062 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
5063 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
5064 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
5065 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 5066}
5067
5068static int load_state_from_tss16(struct kvm_vcpu *vcpu,
5069 struct tss_segment_16 *tss)
5070{
5fdbf976 5071 kvm_rip_write(vcpu, tss->ip);
91586a3b 5072 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5073 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5074 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5075 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5076 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5077 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5078 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5079 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5080 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5081
c697518a
GN		 5082 /*
5083 * SDM says that segment selectors are loaded before segment
5084 * descriptors
5085 */
5086 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5087 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5088 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5089 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5090 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5091
5092 /*
5093 * Now load segment descriptors. If fault happenes at this stage
5094 * it is handled in a context of new task
5095 */
5096 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5097 return 1;
5098
c697518a 5099 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5100 return 1;
5101
c697518a 5102 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5103 return 1;
5104
c697518a 5105 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5106 return 1;
5107
c697518a 5108 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5109 return 1;
5110 return 0;
5111}
5112
8b2cf73c 5113static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5114 u16 old_tss_sel, u32 old_tss_base,
5115 struct desc_struct *nseg_desc)
37817f29
IE		 5116{
5117 struct tss_segment_16 tss_segment_16;
5118 int ret = 0;
5119
34198bf8
MT		 5120 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5121 sizeof tss_segment_16))
37817f29
IE		 5122 goto out;
5123
5124 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5125
34198bf8
MT		 5126 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5127 sizeof tss_segment_16))
37817f29 5128 goto out;
34198bf8 5129
1871c602 5130 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5131 &tss_segment_16, sizeof tss_segment_16))
5132 goto out;
5133
b237ac37
GN		 5134 if (old_tss_sel != 0xffff) {
5135 tss_segment_16.prev_task_link = old_tss_sel;
5136
5137 if (kvm_write_guest(vcpu->kvm,
1871c602 5138 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5139 &tss_segment_16.prev_task_link,
5140 sizeof tss_segment_16.prev_task_link))
5141 goto out;
5142 }
5143
37817f29
IE		 5144 if (load_state_from_tss16(vcpu, &tss_segment_16))
5145 goto out;
5146
5147 ret = 1;
5148out:
5149 return ret;
5150}
5151
8b2cf73c 5152static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5153 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5154 struct desc_struct *nseg_desc)
5155{
5156 struct tss_segment_32 tss_segment_32;
5157 int ret = 0;
5158
34198bf8
MT		 5159 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5160 sizeof tss_segment_32))
37817f29
IE		 5161 goto out;
5162
5163 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5164
34198bf8
MT		 5165 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5166 sizeof tss_segment_32))
5167 goto out;
5168
1871c602 5169 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5170 &tss_segment_32, sizeof tss_segment_32))
37817f29 5171 goto out;
34198bf8 5172
b237ac37
GN		 5173 if (old_tss_sel != 0xffff) {
5174 tss_segment_32.prev_task_link = old_tss_sel;
5175
5176 if (kvm_write_guest(vcpu->kvm,
1871c602 5177 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5178 &tss_segment_32.prev_task_link,
5179 sizeof tss_segment_32.prev_task_link))
5180 goto out;
5181 }
5182
37817f29
IE		 5183 if (load_state_from_tss32(vcpu, &tss_segment_32))
5184 goto out;
5185
5186 ret = 1;
5187out:
5188 return ret;
5189}
5190
5191int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5192{
5193 struct kvm_segment tr_seg;
5194 struct desc_struct cseg_desc;
5195 struct desc_struct nseg_desc;
5196 int ret = 0;
34198bf8
MT		 5197 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5198 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 5199
1871c602 5200 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5201
34198bf8
MT		 5202 /* FIXME: Handle errors. Failure to read either TSS or their
5203 * descriptors should generate a pagefault.
5204 */
37817f29
IE		 5205 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5206 goto out;
5207
34198bf8 5208 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5209 goto out;
5210
37817f29
IE		 5211 if (reason != TASK_SWITCH_IRET) {
5212 int cpl;
5213
5214 cpl = kvm_x86_ops->get_cpl(vcpu);
5215 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5216 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5217 return 1;
5218 }
5219 }
5220
46a359e7 5221 if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
37817f29
IE		 5222 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5223 return 1;
5224 }
5225
5226 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5227 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5228 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5229 }
5230
5231 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5232 u32 eflags = kvm_get_rflags(vcpu);
5233 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5234 }
5235
b237ac37
GN		 5236 /* set back link to prev task only if NT bit is set in eflags
5237 note that old_tss_sel is not used afetr this point */
5238 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5239 old_tss_sel = 0xffff;
5240
37817f29 5241 if (nseg_desc.type & 8)
b237ac37
GN		 5242 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5243 old_tss_base, &nseg_desc);
37817f29 5244 else
b237ac37
GN		 5245 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5246 old_tss_base, &nseg_desc);
37817f29
IE		 5247
5248 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5249 u32 eflags = kvm_get_rflags(vcpu);
5250 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5251 }
5252
5253 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5254 nseg_desc.type |= (1 << 1);
37817f29
IE		 5255 save_guest_segment_descriptor(vcpu, tss_selector,
5256 &nseg_desc);
5257 }
5258
4d4ec087 5259 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5260 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5261 tr_seg.type = 11;
3e6e0aab 5262 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5263out:
37817f29
IE		 5264 return ret;
5265}
5266EXPORT_SYMBOL_GPL(kvm_task_switch);
5267
b6c7a5dc
HB		 5268int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5269 struct kvm_sregs *sregs)
5270{
5271 int mmu_reset_needed = 0;
923c61bb 5272 int pending_vec, max_bits;
b6c7a5dc
HB		 5273 struct descriptor_table dt;
5274
5275 vcpu_load(vcpu);
5276
5277 dt.limit = sregs->idt.limit;
5278 dt.base = sregs->idt.base;
5279 kvm_x86_ops->set_idt(vcpu, &dt);
5280 dt.limit = sregs->gdt.limit;
5281 dt.base = sregs->gdt.base;
5282 kvm_x86_ops->set_gdt(vcpu, &dt);
5283
ad312c7c
ZX		 5284 vcpu->arch.cr2 = sregs->cr2;
5285 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5286 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5287
2d3ad1f4 5288 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5289
f6801dff 5290 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5291 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5292 kvm_set_apic_base(vcpu, sregs->apic_base);
5293
4d4ec087 5294 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5295 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5296 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5297
fc78f519 5298 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5299 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5300 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5301 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5302 mmu_reset_needed = 1;
5303 }
b6c7a5dc
HB		 5304
5305 if (mmu_reset_needed)
5306 kvm_mmu_reset_context(vcpu);
5307
923c61bb
GN		 5308 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5309 pending_vec = find_first_bit(
5310 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5311 if (pending_vec < max_bits) {
66fd3f7f 5312 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5313 pr_debug("Set back pending irq %d\n", pending_vec);
5314 if (irqchip_in_kernel(vcpu->kvm))
5315 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5316 }
5317
3e6e0aab
GT		 5318 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5319 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5320 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5321 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5322 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5323 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5324
3e6e0aab
GT		 5325 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5326 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5327
5f0269f5
ME		 5328 update_cr8_intercept(vcpu);
5329
9c3e4aab 5330 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5331 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5332 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5333 !is_protmode(vcpu))
9c3e4aab
MT		 5334 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5335
b6c7a5dc
HB		 5336 vcpu_put(vcpu);
5337
5338 return 0;
5339}
5340
d0bfb940
JK		 5341int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5342 struct kvm_guest_debug *dbg)
b6c7a5dc 5343{
355be0b9 5344 unsigned long rflags;
ae675ef0 5345 int i, r;
b6c7a5dc
HB		 5346
5347 vcpu_load(vcpu);
5348
4f926bf2
JK		 5349 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5350 r = -EBUSY;
5351 if (vcpu->arch.exception.pending)
5352 goto unlock_out;
5353 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5354 kvm_queue_exception(vcpu, DB_VECTOR);
5355 else
5356 kvm_queue_exception(vcpu, BP_VECTOR);
5357 }
5358
91586a3b
JK		 5359 /*
5360 * Read rflags as long as potentially injected trace flags are still
5361 * filtered out.
5362 */
5363 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5364
5365 vcpu->guest_debug = dbg->control;
5366 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5367 vcpu->guest_debug = 0;
5368
5369 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5370 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5371 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5372 vcpu->arch.switch_db_regs =
5373 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5374 } else {
5375 for (i = 0; i < KVM_NR_DB_REGS; i++)
5376 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5377 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5378 }
5379
94fe45da
JK		 5380 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5381 vcpu->arch.singlestep_cs =
5382 get_segment_selector(vcpu, VCPU_SREG_CS);
5383 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu);
5384 }
5385
91586a3b
JK		 5386 /*
5387 * Trigger an rflags update that will inject or remove the trace
5388 * flags.
5389 */
5390 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5391
355be0b9 5392 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5393
4f926bf2 5394 r = 0;
d0bfb940 5395
4f926bf2 5396unlock_out:
b6c7a5dc
HB		 5397 vcpu_put(vcpu);
5398
5399 return r;
5400}
5401
d0752060
HB		 5402/*
5403 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5404 * we have asm/x86/processor.h
5405 */
5406struct fxsave {
5407 u16 cwd;
5408 u16 swd;
5409 u16 twd;
5410 u16 fop;
5411 u64 rip;
5412 u64 rdp;
5413 u32 mxcsr;
5414 u32 mxcsr_mask;
5415 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5416#ifdef CONFIG_X86_64
5417 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5418#else
5419 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5420#endif
5421};
5422
8b006791
ZX		 5423/*
5424 * Translate a guest virtual address to a guest physical address.
5425 */
5426int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5427 struct kvm_translation *tr)
5428{
5429 unsigned long vaddr = tr->linear_address;
5430 gpa_t gpa;
f656ce01 5431 int idx;
8b006791
ZX		 5432
5433 vcpu_load(vcpu);
f656ce01 5434 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5435 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5436 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5437 tr->physical_address = gpa;
5438 tr->valid = gpa != UNMAPPED_GVA;
5439 tr->writeable = 1;
5440 tr->usermode = 0;
8b006791
ZX		 5441 vcpu_put(vcpu);
5442
5443 return 0;
5444}
5445
d0752060
HB		 5446int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5447{
ad312c7c 5448 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5449
5450 vcpu_load(vcpu);
5451
5452 memcpy(fpu->fpr, fxsave->st_space, 128);
5453 fpu->fcw = fxsave->cwd;
5454 fpu->fsw = fxsave->swd;
5455 fpu->ftwx = fxsave->twd;
5456 fpu->last_opcode = fxsave->fop;
5457 fpu->last_ip = fxsave->rip;
5458 fpu->last_dp = fxsave->rdp;
5459 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5460
5461 vcpu_put(vcpu);
5462
5463 return 0;
5464}
5465
5466int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5467{
ad312c7c 5468 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5469
5470 vcpu_load(vcpu);
5471
5472 memcpy(fxsave->st_space, fpu->fpr, 128);
5473 fxsave->cwd = fpu->fcw;
5474 fxsave->swd = fpu->fsw;
5475 fxsave->twd = fpu->ftwx;
5476 fxsave->fop = fpu->last_opcode;
5477 fxsave->rip = fpu->last_ip;
5478 fxsave->rdp = fpu->last_dp;
5479 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5480
5481 vcpu_put(vcpu);
5482
5483 return 0;
5484}
5485
5486void fx_init(struct kvm_vcpu *vcpu)
5487{
5488 unsigned after_mxcsr_mask;
5489
bc1a34f1
AA		 5490 /*
5491 * Touch the fpu the first time in non atomic context as if
5492 * this is the first fpu instruction the exception handler
5493 * will fire before the instruction returns and it'll have to
5494 * allocate ram with GFP_KERNEL.
5495 */
5496 if (!used_math())
d6e88aec 5497 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5498
d0752060
HB		 5499 /* Initialize guest FPU by resetting ours and saving into guest's */
5500 preempt_disable();
d6e88aec
AK		 5501 kvm_fx_save(&vcpu->arch.host_fx_image);
5502 kvm_fx_finit();
5503 kvm_fx_save(&vcpu->arch.guest_fx_image);
5504 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5505 preempt_enable();
5506
ad312c7c 5507 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5508 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5509 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5510 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5511 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5512}
5513EXPORT_SYMBOL_GPL(fx_init);
5514
5515void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5516{
2608d7a1 5517 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5518 return;
5519
5520 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5521 kvm_fx_save(&vcpu->arch.host_fx_image);
5522 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5523 trace_kvm_fpu(1);
d0752060 5524}
d0752060
HB		 5525
5526void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5527{
5528 if (!vcpu->guest_fpu_loaded)
5529 return;
5530
5531 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5532 kvm_fx_save(&vcpu->arch.guest_fx_image);
5533 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5534 ++vcpu->stat.fpu_reload;
02daab21 5535 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5536 trace_kvm_fpu(0);
d0752060 5537}
e9b11c17
ZX		 5538
5539void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5540{
7f1ea208
JR		 5541 if (vcpu->arch.time_page) {
5542 kvm_release_page_dirty(vcpu->arch.time_page);
5543 vcpu->arch.time_page = NULL;
5544 }
5545
e9b11c17
ZX		 5546 kvm_x86_ops->vcpu_free(vcpu);
5547}
5548
5549struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5550 unsigned int id)
5551{
26e5215f
AK		 5552 return kvm_x86_ops->vcpu_create(kvm, id);
5553}
e9b11c17 5554
26e5215f
AK		 5555int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5556{
5557 int r;
e9b11c17
ZX		 5558
5559 /* We do fxsave: this must be aligned. */
ad312c7c 5560 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5561
0bed3b56 5562 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5563 vcpu_load(vcpu);
5564 r = kvm_arch_vcpu_reset(vcpu);
5565 if (r == 0)
5566 r = kvm_mmu_setup(vcpu);
5567 vcpu_put(vcpu);
5568 if (r < 0)
5569 goto free_vcpu;
5570
26e5215f 5571 return 0;
e9b11c17
ZX		 5572free_vcpu:
5573 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5574 return r;
e9b11c17
ZX		 5575}
5576
d40ccc62 5577void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5578{
5579 vcpu_load(vcpu);
5580 kvm_mmu_unload(vcpu);
5581 vcpu_put(vcpu);
5582
5583 kvm_x86_ops->vcpu_free(vcpu);
5584}
5585
5586int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5587{
448fa4a9
JK		 5588 vcpu->arch.nmi_pending = false;
5589 vcpu->arch.nmi_injected = false;
5590
42dbaa5a
JK		 5591 vcpu->arch.switch_db_regs = 0;
5592 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5593 vcpu->arch.dr6 = DR6_FIXED_1;
5594 vcpu->arch.dr7 = DR7_FIXED_1;
5595
e9b11c17
ZX		 5596 return kvm_x86_ops->vcpu_reset(vcpu);
5597}
5598
10474ae8 5599int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5600{
0cca7907
ZA		 5601 /*
5602 * Since this may be called from a hotplug notifcation,
5603 * we can't get the CPU frequency directly.
5604 */
5605 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5606 int cpu = raw_smp_processor_id();
5607 per_cpu(cpu_tsc_khz, cpu) = 0;
5608 }
18863bdd
AK		 5609
5610 kvm_shared_msr_cpu_online();
5611
10474ae8 5612 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5613}
5614
5615void kvm_arch_hardware_disable(void *garbage)
5616{
5617 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5618 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5619}
5620
5621int kvm_arch_hardware_setup(void)
5622{
5623 return kvm_x86_ops->hardware_setup();
5624}
5625
5626void kvm_arch_hardware_unsetup(void)
5627{
5628 kvm_x86_ops->hardware_unsetup();
5629}
5630
5631void kvm_arch_check_processor_compat(void *rtn)
5632{
5633 kvm_x86_ops->check_processor_compatibility(rtn);
5634}
5635
5636int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5637{
5638 struct page *page;
5639 struct kvm *kvm;
5640 int r;
5641
5642 BUG_ON(vcpu->kvm == NULL);
5643 kvm = vcpu->kvm;
5644
ad312c7c 5645 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5646 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5647 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5648 else
a4535290 5649 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5650
5651 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5652 if (!page) {
5653 r = -ENOMEM;
5654 goto fail;
5655 }
ad312c7c 5656 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5657
5658 r = kvm_mmu_create(vcpu);
5659 if (r < 0)
5660 goto fail_free_pio_data;
5661
5662 if (irqchip_in_kernel(kvm)) {
5663 r = kvm_create_lapic(vcpu);
5664 if (r < 0)
5665 goto fail_mmu_destroy;
5666 }
5667
890ca9ae
HY		 5668 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5669 GFP_KERNEL);
5670 if (!vcpu->arch.mce_banks) {
5671 r = -ENOMEM;
443c39bc 5672 goto fail_free_lapic;
890ca9ae
HY		 5673 }
5674 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5675
e9b11c17 5676 return 0;
443c39bc
WY		 5677fail_free_lapic:
5678 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5679fail_mmu_destroy:
5680 kvm_mmu_destroy(vcpu);
5681fail_free_pio_data:
ad312c7c 5682 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5683fail:
5684 return r;
5685}
5686
5687void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5688{
f656ce01
MT		 5689 int idx;
5690
36cb93fd 5691 kfree(vcpu->arch.mce_banks);
e9b11c17 5692 kvm_free_lapic(vcpu);
f656ce01 5693 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5694 kvm_mmu_destroy(vcpu);
f656ce01 5695 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5696 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5697}
d19a9cd2
ZX		 5698
5699struct kvm *kvm_arch_create_vm(void)
5700{
5701 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5702
5703 if (!kvm)
5704 return ERR_PTR(-ENOMEM);
5705
fef9cce0
MT		 5706 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5707 if (!kvm->arch.aliases) {
5708 kfree(kvm);
5709 return ERR_PTR(-ENOMEM);
5710 }
5711
f05e70ac 5712 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5713 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5714
5550af4d
SY		 5715 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5716 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5717
53f658b3
MT		 5718 rdtscll(kvm->arch.vm_init_tsc);
5719
d19a9cd2
ZX		 5720 return kvm;
5721}
5722
5723static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5724{
5725 vcpu_load(vcpu);
5726 kvm_mmu_unload(vcpu);
5727 vcpu_put(vcpu);
5728}
5729
5730static void kvm_free_vcpus(struct kvm *kvm)
5731{
5732 unsigned int i;
988a2cae 5733 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5734
5735 /*
5736 * Unpin any mmu pages first.
5737 */
988a2cae
GN		 5738 kvm_for_each_vcpu(i, vcpu, kvm)
5739 kvm_unload_vcpu_mmu(vcpu);
5740 kvm_for_each_vcpu(i, vcpu, kvm)
5741 kvm_arch_vcpu_free(vcpu);
5742
5743 mutex_lock(&kvm->lock);
5744 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5745 kvm->vcpus[i] = NULL;
d19a9cd2 5746
988a2cae
GN		 5747 atomic_set(&kvm->online_vcpus, 0);
5748 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5749}
5750
ad8ba2cd
SY		 5751void kvm_arch_sync_events(struct kvm *kvm)
5752{
ba4cef31 5753 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5754}
5755
d19a9cd2
ZX		 5756void kvm_arch_destroy_vm(struct kvm *kvm)
5757{
6eb55818 5758 kvm_iommu_unmap_guest(kvm);
7837699f 5759 kvm_free_pit(kvm);
d7deeeb0
ZX		 5760 kfree(kvm->arch.vpic);
5761 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5762 kvm_free_vcpus(kvm);
5763 kvm_free_physmem(kvm);
3d45830c
AK		 5764 if (kvm->arch.apic_access_page)
5765 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5766 if (kvm->arch.ept_identity_pagetable)
5767 put_page(kvm->arch.ept_identity_pagetable);
64749204 5768 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5769 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5770 kfree(kvm);
5771}
0de10343 5772
f7784b8e
MT		 5773int kvm_arch_prepare_memory_region(struct kvm *kvm,
5774 struct kvm_memory_slot *memslot,
0de10343 5775 struct kvm_memory_slot old,
f7784b8e 5776 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5777 int user_alloc)
5778{
f7784b8e 5779 int npages = memslot->npages;
0de10343
ZX		 5780
5781 /*To keep backward compatibility with older userspace,
5782 *x86 needs to hanlde !user_alloc case.
5783 */
5784 if (!user_alloc) {
5785 if (npages && !old.rmap) {
604b38ac
AA		 5786 unsigned long userspace_addr;
5787
72dc67a6 5788 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5789 userspace_addr = do_mmap(NULL, 0,
5790 npages * PAGE_SIZE,
5791 PROT_READ | PROT_WRITE,
acee3c04 5792 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5793 0);
72dc67a6 5794 up_write(&current->mm->mmap_sem);
0de10343 5795
604b38ac
AA		 5796 if (IS_ERR((void *)userspace_addr))
5797 return PTR_ERR((void *)userspace_addr);
5798
604b38ac 5799 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5800 }
5801 }
5802
f7784b8e
MT		 5803
5804 return 0;
5805}
5806
5807void kvm_arch_commit_memory_region(struct kvm *kvm,
5808 struct kvm_userspace_memory_region *mem,
5809 struct kvm_memory_slot old,
5810 int user_alloc)
5811{
5812
5813 int npages = mem->memory_size >> PAGE_SHIFT;
5814
5815 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5816 int ret;
5817
5818 down_write(&current->mm->mmap_sem);
5819 ret = do_munmap(current->mm, old.userspace_addr,
5820 old.npages * PAGE_SIZE);
5821 up_write(&current->mm->mmap_sem);
5822 if (ret < 0)
5823 printk(KERN_WARNING
5824 "kvm_vm_ioctl_set_memory_region: "
5825 "failed to munmap memory\n");
5826 }
5827
7c8a83b7 5828 spin_lock(&kvm->mmu_lock);
f05e70ac 5829 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5830 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5831 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5832 }
5833
5834 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5835 spin_unlock(&kvm->mmu_lock);
0de10343 5836}
1d737c8a 5837
34d4cb8f
MT		 5838void kvm_arch_flush_shadow(struct kvm *kvm)
5839{
5840 kvm_mmu_zap_all(kvm);
8986ecc0 5841 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5842}
5843
1d737c8a
ZX		 5844int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5845{
a4535290 5846 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5847 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5848 || vcpu->arch.nmi_pending ||
5849 (kvm_arch_interrupt_allowed(vcpu) &&
5850 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5851}
5736199a 5852
5736199a
ZX		 5853void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5854{
32f88400
MT		 5855 int me;
5856 int cpu = vcpu->cpu;
5736199a
ZX		 5857
5858 if (waitqueue_active(&vcpu->wq)) {
5859 wake_up_interruptible(&vcpu->wq);
5860 ++vcpu->stat.halt_wakeup;
5861 }
32f88400
MT		 5862
5863 me = get_cpu();
5864 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5865 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5866 smp_send_reschedule(cpu);
e9571ed5 5867 put_cpu();
5736199a 5868}
78646121
GN		 5869
5870int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5871{
5872 return kvm_x86_ops->interrupt_allowed(vcpu);
5873}
229456fc 5874
94fe45da
JK		 5875unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5876{
5877 unsigned long rflags;
5878
5879 rflags = kvm_x86_ops->get_rflags(vcpu);
5880 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5881 rflags &= ~(unsigned long)(X86_EFLAGS_TF | X86_EFLAGS_RF);
5882 return rflags;
5883}
5884EXPORT_SYMBOL_GPL(kvm_get_rflags);
5885
5886void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5887{
5888 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
5889 vcpu->arch.singlestep_cs ==
5890 get_segment_selector(vcpu, VCPU_SREG_CS) &&
5891 vcpu->arch.singlestep_rip == kvm_rip_read(vcpu))
5892 rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
5893 kvm_x86_ops->set_rflags(vcpu, rflags);
5894}
5895EXPORT_SYMBOL_GPL(kvm_set_rflags);
5896
229456fc
MT		 5897EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5898EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5899EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5900EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5901EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5902EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5903EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5904EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5905EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5906EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5907EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
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