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KVM: SVM: Ignore write of hwcr.ignne
[net-next-2.6.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
18863bdd 40#include <linux/user-return-notifier.h>
a983fb23 41#include <linux/srcu.h>
5a0e3ad6 42#include <linux/slab.h>
aec51dc4
AK		 43#include <trace/events/kvm.h>
44#undef TRACE_INCLUDE_FILE
229456fc
MT		 45#define CREATE_TRACE_POINTS
46#include "trace.h"
043405e1 47
24f1e32c 48#include <asm/debugreg.h>
043405e1 49#include <asm/uaccess.h>
d825ed0a 50#include <asm/msr.h>
a5f61300 51#include <asm/desc.h>
0bed3b56 52#include <asm/mtrr.h>
890ca9ae 53#include <asm/mce.h>
043405e1 54
313a3dc7 55#define MAX_IO_MSRS 256
a03490ed
CO		 56#define CR0_RESERVED_BITS \
57 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
58 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
59 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
60#define CR4_RESERVED_BITS \
61 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
62 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
63 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
64 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
65
66#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 67
68#define KVM_MAX_MCE_BANKS 32
69#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
76static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
77#else
78static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
79#endif
313a3dc7 80
ba1389b7
AK		 81#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
82#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 83
cb142eb7 84static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 85static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
86 struct kvm_cpuid_entry2 __user *entries);
87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
ed85c068
AP		 91int ignore_msrs = 0;
92module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
93
18863bdd
AK		 94#define KVM_NR_SHARED_MSRS 16
95
96struct kvm_shared_msrs_global {
97 int nr;
2bf78fa7 98 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 99};
100
101struct kvm_shared_msrs {
102 struct user_return_notifier urn;
103 bool registered;
2bf78fa7
SY		 104 struct kvm_shared_msr_values {
105 u64 host;
106 u64 curr;
107 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
111static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
112
417bc304 113struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 114 { "pf_fixed", VCPU_STAT(pf_fixed) },
115 { "pf_guest", VCPU_STAT(pf_guest) },
116 { "tlb_flush", VCPU_STAT(tlb_flush) },
117 { "invlpg", VCPU_STAT(invlpg) },
118 { "exits", VCPU_STAT(exits) },
119 { "io_exits", VCPU_STAT(io_exits) },
120 { "mmio_exits", VCPU_STAT(mmio_exits) },
121 { "signal_exits", VCPU_STAT(signal_exits) },
122 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 123 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 124 { "halt_exits", VCPU_STAT(halt_exits) },
125 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 126 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 127 { "request_irq", VCPU_STAT(request_irq_exits) },
128 { "irq_exits", VCPU_STAT(irq_exits) },
129 { "host_state_reload", VCPU_STAT(host_state_reload) },
130 { "efer_reload", VCPU_STAT(efer_reload) },
131 { "fpu_reload", VCPU_STAT(fpu_reload) },
132 { "insn_emulation", VCPU_STAT(insn_emulation) },
133 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 134 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 135 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 136 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
137 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
138 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
139 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
140 { "mmu_flooded", VM_STAT(mmu_flooded) },
141 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 142 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 143 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 144 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 145 { "largepages", VM_STAT(lpages) },
417bc304
HB		 146 { NULL }
147};
148
18863bdd
AK		 149static void kvm_on_user_return(struct user_return_notifier *urn)
150{
151 unsigned slot;
18863bdd
AK		 152 struct kvm_shared_msrs *locals
153 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 154 struct kvm_shared_msr_values *values;
18863bdd
AK		 155
156 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 157 values = &locals->values[slot];
158 if (values->host != values->curr) {
159 wrmsrl(shared_msrs_global.msrs[slot], values->host);
160 values->curr = values->host;
18863bdd
AK		 161 }
162 }
163 locals->registered = false;
164 user_return_notifier_unregister(urn);
165}
166
2bf78fa7 167static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 168{
2bf78fa7 169 struct kvm_shared_msrs *smsr;
18863bdd
AK		 170 u64 value;
171
2bf78fa7
SY		 172 smsr = &__get_cpu_var(shared_msrs);
173 /* only read, and nobody should modify it at this time,
174 * so don't need lock */
175 if (slot >= shared_msrs_global.nr) {
176 printk(KERN_ERR "kvm: invalid MSR slot!");
177 return;
178 }
179 rdmsrl_safe(msr, &value);
180 smsr->values[slot].host = value;
181 smsr->values[slot].curr = value;
182}
183
184void kvm_define_shared_msr(unsigned slot, u32 msr)
185{
18863bdd
AK		 186 if (slot >= shared_msrs_global.nr)
187 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 188 shared_msrs_global.msrs[slot] = msr;
189 /* we need ensured the shared_msr_global have been updated */
190 smp_wmb();
18863bdd
AK		 191}
192EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
193
194static void kvm_shared_msr_cpu_online(void)
195{
196 unsigned i;
18863bdd
AK		 197
198 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 199 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 200}
201
d5696725 202void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 203{
204 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
205
2bf78fa7 206 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 207 return;
2bf78fa7
SY		 208 smsr->values[slot].curr = value;
209 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 210 if (!smsr->registered) {
211 smsr->urn.on_user_return = kvm_on_user_return;
212 user_return_notifier_register(&smsr->urn);
213 smsr->registered = true;
214 }
215}
216EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
217
3548bab5
AK		 218static void drop_user_return_notifiers(void *ignore)
219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
222 if (smsr->registered)
223 kvm_on_user_return(&smsr->urn);
224}
225
5fb76f9b
CO		 226unsigned long segment_base(u16 selector)
227{
89a27f4d 228 struct desc_ptr gdt;
a5f61300 229 struct desc_struct *d;
5fb76f9b
CO		 230 unsigned long table_base;
231 unsigned long v;
232
233 if (selector == 0)
234 return 0;
235
b792c344 236 kvm_get_gdt(&gdt);
89a27f4d 237 table_base = gdt.address;
5fb76f9b
CO		 238
239 if (selector & 4) { /* from ldt */
b792c344 240 u16 ldt_selector = kvm_read_ldt();
5fb76f9b 241
5fb76f9b
CO		 242 table_base = segment_base(ldt_selector);
243 }
a5f61300 244 d = (struct desc_struct *)(table_base + (selector & ~7));
46a359e7 245 v = get_desc_base(d);
5fb76f9b 246#ifdef CONFIG_X86_64
a5f61300
AK		 247 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
248 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 249#endif
250 return v;
251}
252EXPORT_SYMBOL_GPL(segment_base);
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
256 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 257 return vcpu->arch.apic_base;
6866b83e 258 else
ad312c7c 259 return vcpu->arch.apic_base;
6866b83e
CO		 260}
261EXPORT_SYMBOL_GPL(kvm_get_apic_base);
262
263void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
264{
265 /* TODO: reserve bits check */
266 if (irqchip_in_kernel(vcpu->kvm))
267 kvm_lapic_set_base(vcpu, data);
268 else
ad312c7c 269 vcpu->arch.apic_base = data;
6866b83e
CO		 270}
271EXPORT_SYMBOL_GPL(kvm_set_apic_base);
272
3fd28fce
ED		 273#define EXCPT_BENIGN 0
274#define EXCPT_CONTRIBUTORY 1
275#define EXCPT_PF 2
276
277static int exception_class(int vector)
278{
279 switch (vector) {
280 case PF_VECTOR:
281 return EXCPT_PF;
282 case DE_VECTOR:
283 case TS_VECTOR:
284 case NP_VECTOR:
285 case SS_VECTOR:
286 case GP_VECTOR:
287 return EXCPT_CONTRIBUTORY;
288 default:
289 break;
290 }
291 return EXCPT_BENIGN;
292}
293
294static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
295 unsigned nr, bool has_error, u32 error_code)
296{
297 u32 prev_nr;
298 int class1, class2;
299
300 if (!vcpu->arch.exception.pending) {
301 queue:
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = has_error;
304 vcpu->arch.exception.nr = nr;
305 vcpu->arch.exception.error_code = error_code;
306 return;
307 }
308
309 /* to check exception */
310 prev_nr = vcpu->arch.exception.nr;
311 if (prev_nr == DF_VECTOR) {
312 /* triple fault -> shutdown */
313 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
314 return;
315 }
316 class1 = exception_class(prev_nr);
317 class2 = exception_class(nr);
318 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
319 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
320 /* generate double fault per SDM Table 5-5 */
321 vcpu->arch.exception.pending = true;
322 vcpu->arch.exception.has_error_code = true;
323 vcpu->arch.exception.nr = DF_VECTOR;
324 vcpu->arch.exception.error_code = 0;
325 } else
326 /* replace previous exception with a new one in a hope
327 that instruction re-execution will regenerate lost
328 exception */
329 goto queue;
330}
331
298101da
AK		 332void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
333{
3fd28fce 334 kvm_multiple_exception(vcpu, nr, false, 0);
298101da
AK		 335}
336EXPORT_SYMBOL_GPL(kvm_queue_exception);
337
c3c91fee
AK		 338void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
339 u32 error_code)
340{
341 ++vcpu->stat.pf_guest;
ad312c7c 342 vcpu->arch.cr2 = addr;
c3c91fee
AK		 343 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
344}
345
3419ffc8
SY		 346void kvm_inject_nmi(struct kvm_vcpu *vcpu)
347{
348 vcpu->arch.nmi_pending = 1;
349}
350EXPORT_SYMBOL_GPL(kvm_inject_nmi);
351
298101da
AK		 352void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
353{
3fd28fce 354 kvm_multiple_exception(vcpu, nr, true, error_code);
298101da
AK		 355}
356EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
357
0a79b009
AK		 358/*
359 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
360 * a #GP and return false.
361 */
362bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 363{
0a79b009
AK		 364 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
365 return true;
366 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
367 return false;
298101da 368}
0a79b009 369EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 370
a03490ed
CO		 371/*
372 * Load the pae pdptrs. Return true is they are all valid.
373 */
374int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
375{
376 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
377 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
378 int i;
379 int ret;
ad312c7c 380 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 381
a03490ed
CO		 382 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
383 offset * sizeof(u64), sizeof(pdpte));
384 if (ret < 0) {
385 ret = 0;
386 goto out;
387 }
388 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 389 if (is_present_gpte(pdpte[i]) &&
20c466b5 390 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 391 ret = 0;
392 goto out;
393 }
394 }
395 ret = 1;
396
ad312c7c 397 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 398 __set_bit(VCPU_EXREG_PDPTR,
399 (unsigned long *)&vcpu->arch.regs_avail);
400 __set_bit(VCPU_EXREG_PDPTR,
401 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 402out:
a03490ed
CO		 403
404 return ret;
405}
cc4b6871 406EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 407
d835dfec
AK		 408static bool pdptrs_changed(struct kvm_vcpu *vcpu)
409{
ad312c7c 410 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 411 bool changed = true;
412 int r;
413
414 if (is_long_mode(vcpu) || !is_pae(vcpu))
415 return false;
416
6de4f3ad
AK		 417 if (!test_bit(VCPU_EXREG_PDPTR,
418 (unsigned long *)&vcpu->arch.regs_avail))
419 return true;
420
ad312c7c 421 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 422 if (r < 0)
423 goto out;
ad312c7c 424 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 425out:
d835dfec
AK		 426
427 return changed;
428}
429
2d3ad1f4 430void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 431{
f9a48e6a
AK		 432 cr0 |= X86_CR0_ET;
433
ab344828
GN		 434#ifdef CONFIG_X86_64
435 if (cr0 & 0xffffffff00000000UL) {
c1a5d4f9 436 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 437 return;
438 }
ab344828
GN		 439#endif
440
441 cr0 &= ~CR0_RESERVED_BITS;
a03490ed
CO		 442
443 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
c1a5d4f9 444 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 445 return;
446 }
447
448 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
c1a5d4f9 449 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 450 return;
451 }
452
453 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
454#ifdef CONFIG_X86_64
f6801dff 455 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 456 int cs_db, cs_l;
457
458 if (!is_pae(vcpu)) {
c1a5d4f9 459 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 460 return;
461 }
462 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
463 if (cs_l) {
c1a5d4f9 464 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 465 return;
466
467 }
468 } else
469#endif
ad312c7c 470 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 471 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 472 return;
473 }
474
475 }
476
477 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 478 vcpu->arch.cr0 = cr0;
a03490ed 479
a03490ed 480 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 481 return;
482}
2d3ad1f4 483EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 484
2d3ad1f4 485void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 486{
4d4ec087 487 kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0ful) | (msw & 0x0f));
a03490ed 488}
2d3ad1f4 489EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 490
2d3ad1f4 491void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 492{
fc78f519 493 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 494 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
495
a03490ed 496 if (cr4 & CR4_RESERVED_BITS) {
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 498 return;
499 }
500
501 if (is_long_mode(vcpu)) {
502 if (!(cr4 & X86_CR4_PAE)) {
c1a5d4f9 503 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 504 return;
505 }
a2edf57f
AK		 506 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
507 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 508 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
c1a5d4f9 509 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 510 return;
511 }
512
513 if (cr4 & X86_CR4_VMXE) {
c1a5d4f9 514 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 515 return;
516 }
517 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 518 vcpu->arch.cr4 = cr4;
5a41accd 519 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 520 kvm_mmu_reset_context(vcpu);
a03490ed 521}
2d3ad1f4 522EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 523
2d3ad1f4 524void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 525{
ad312c7c 526 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 527 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 528 kvm_mmu_flush_tlb(vcpu);
529 return;
530 }
531
a03490ed
CO		 532 if (is_long_mode(vcpu)) {
533 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
c1a5d4f9 534 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 535 return;
536 }
537 } else {
538 if (is_pae(vcpu)) {
539 if (cr3 & CR3_PAE_RESERVED_BITS) {
c1a5d4f9 540 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 541 return;
542 }
543 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
c1a5d4f9 544 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 545 return;
546 }
547 }
548 /*
549 * We don't check reserved bits in nonpae mode, because
550 * this isn't enforced, and VMware depends on this.
551 */
552 }
553
a03490ed
CO		 554 /*
555 * Does the new cr3 value map to physical memory? (Note, we
556 * catch an invalid cr3 even in real-mode, because it would
557 * cause trouble later on when we turn on paging anyway.)
558 *
559 * A real CPU would silently accept an invalid cr3 and would
560 * attempt to use it - with largely undefined (and often hard
561 * to debug) behavior on the guest side.
562 */
563 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 564 kvm_inject_gp(vcpu, 0);
a03490ed 565 else {
ad312c7c
ZX		 566 vcpu->arch.cr3 = cr3;
567 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 568 }
a03490ed 569}
2d3ad1f4 570EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 571
2d3ad1f4 572void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 573{
574 if (cr8 & CR8_RESERVED_BITS) {
c1a5d4f9 575 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 576 return;
577 }
578 if (irqchip_in_kernel(vcpu->kvm))
579 kvm_lapic_set_tpr(vcpu, cr8);
580 else
ad312c7c 581 vcpu->arch.cr8 = cr8;
a03490ed 582}
2d3ad1f4 583EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 584
2d3ad1f4 585unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 586{
587 if (irqchip_in_kernel(vcpu->kvm))
588 return kvm_lapic_get_cr8(vcpu);
589 else
ad312c7c 590 return vcpu->arch.cr8;
a03490ed 591}
2d3ad1f4 592EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 593
d8017474
AG		 594static inline u32 bit(int bitno)
595{
596 return 1 << (bitno & 31);
597}
598
043405e1
CO		 599/*
600 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
601 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
602 *
603 * This list is modified at module load time to reflect the
e3267cbb
GC		 604 * capabilities of the host cpu. This capabilities test skips MSRs that are
605 * kvm-specific. Those are put in the beginning of the list.
043405e1 606 */
e3267cbb 607
10388a07 608#define KVM_SAVE_MSRS_BEGIN 5
043405e1 609static u32 msrs_to_save[] = {
e3267cbb 610 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
55cd8e5a 611 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
10388a07 612 HV_X64_MSR_APIC_ASSIST_PAGE,
043405e1
CO		 613 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
614 MSR_K6_STAR,
615#ifdef CONFIG_X86_64
616 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
617#endif
e3267cbb 618 MSR_IA32_TSC, MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 619};
620
621static unsigned num_msrs_to_save;
622
623static u32 emulated_msrs[] = {
624 MSR_IA32_MISC_ENABLE,
625};
626
15c4a640
CO		 627static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
628{
f2b4b7dd 629 if (efer & efer_reserved_bits) {
c1a5d4f9 630 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 631 return;
632 }
633
634 if (is_paging(vcpu)
f6801dff 635 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME)) {
c1a5d4f9 636 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 637 return;
638 }
639
1b2fd70c
AG		 640 if (efer & EFER_FFXSR) {
641 struct kvm_cpuid_entry2 *feat;
642
643 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
644 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
1b2fd70c
AG		 645 kvm_inject_gp(vcpu, 0);
646 return;
647 }
648 }
649
d8017474
AG		 650 if (efer & EFER_SVME) {
651 struct kvm_cpuid_entry2 *feat;
652
653 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
654 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
d8017474
AG		 655 kvm_inject_gp(vcpu, 0);
656 return;
657 }
658 }
659
15c4a640
CO		 660 kvm_x86_ops->set_efer(vcpu, efer);
661
662 efer &= ~EFER_LMA;
f6801dff 663 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 664
f6801dff 665 vcpu->arch.efer = efer;
9645bb56
AK		 666
667 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
668 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 669}
670
f2b4b7dd
JR		 671void kvm_enable_efer_bits(u64 mask)
672{
673 efer_reserved_bits &= ~mask;
674}
675EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
676
677
15c4a640
CO		 678/*
679 * Writes msr value into into the appropriate "register".
680 * Returns 0 on success, non-0 otherwise.
681 * Assumes vcpu_load() was already called.
682 */
683int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
684{
685 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
686}
687
313a3dc7
CO		 688/*
689 * Adapt set_msr() to msr_io()'s calling convention
690 */
691static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
692{
693 return kvm_set_msr(vcpu, index, *data);
694}
695
18068523
GOC		 696static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
697{
698 static int version;
50d0a0f9 699 struct pvclock_wall_clock wc;
923de3cf 700 struct timespec boot;
18068523
GOC		 701
702 if (!wall_clock)
703 return;
704
705 version++;
706
18068523
GOC		 707 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
708
50d0a0f9
GH		 709 /*
710 * The guest calculates current wall clock time by adding
711 * system time (updated by kvm_write_guest_time below) to the
712 * wall clock specified here. guest system time equals host
713 * system time for us, thus we must fill in host boot time here.
714 */
923de3cf 715 getboottime(&boot);
50d0a0f9
GH		 716
717 wc.sec = boot.tv_sec;
718 wc.nsec = boot.tv_nsec;
719 wc.version = version;
18068523
GOC		 720
721 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
722
723 version++;
724 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 725}
726
50d0a0f9
GH		 727static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
728{
729 uint32_t quotient, remainder;
730
731 /* Don't try to replace with do_div(), this one calculates
732 * "(dividend << 32) / divisor" */
733 __asm__ ( "divl %4"
734 : "=a" (quotient), "=d" (remainder)
735 : "0" (0), "1" (dividend), "r" (divisor) );
736 return quotient;
737}
738
739static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
740{
741 uint64_t nsecs = 1000000000LL;
742 int32_t shift = 0;
743 uint64_t tps64;
744 uint32_t tps32;
745
746 tps64 = tsc_khz * 1000LL;
747 while (tps64 > nsecs*2) {
748 tps64 >>= 1;
749 shift--;
750 }
751
752 tps32 = (uint32_t)tps64;
753 while (tps32 <= (uint32_t)nsecs) {
754 tps32 <<= 1;
755 shift++;
756 }
757
758 hv_clock->tsc_shift = shift;
759 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
760
761 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 762 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 763 hv_clock->tsc_to_system_mul);
764}
765
c8076604
GH		 766static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
767
18068523
GOC		 768static void kvm_write_guest_time(struct kvm_vcpu *v)
769{
770 struct timespec ts;
771 unsigned long flags;
772 struct kvm_vcpu_arch *vcpu = &v->arch;
773 void *shared_kaddr;
463656c0 774 unsigned long this_tsc_khz;
18068523
GOC		 775
776 if ((!vcpu->time_page))
777 return;
778
463656c0
AK		 779 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
780 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
781 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
782 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 783 }
463656c0 784 put_cpu_var(cpu_tsc_khz);
50d0a0f9 785
18068523
GOC		 786 /* Keep irq disabled to prevent changes to the clock */
787 local_irq_save(flags);
af24a4e4 788 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523 789 ktime_get_ts(&ts);
923de3cf 790 monotonic_to_bootbased(&ts);
18068523
GOC		 791 local_irq_restore(flags);
792
793 /* With all the info we got, fill in the values */
794
795 vcpu->hv_clock.system_time = ts.tv_nsec +
afbcf7ab
GC		 796 (NSEC_PER_SEC * (u64)ts.tv_sec) + v->kvm->arch.kvmclock_offset;
797
18068523
GOC		 798 /*
799 * The interface expects us to write an even number signaling that the
800 * update is finished. Since the guest won't see the intermediate
50d0a0f9 801 * state, we just increase by 2 at the end.
18068523 802 */
50d0a0f9 803 vcpu->hv_clock.version += 2;
18068523
GOC		 804
805 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
806
807 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 808 sizeof(vcpu->hv_clock));
18068523
GOC		 809
810 kunmap_atomic(shared_kaddr, KM_USER0);
811
812 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
813}
814
c8076604
GH		 815static int kvm_request_guest_time_update(struct kvm_vcpu *v)
816{
817 struct kvm_vcpu_arch *vcpu = &v->arch;
818
819 if (!vcpu->time_page)
820 return 0;
821 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
822 return 1;
823}
824
9ba075a6
AK		 825static bool msr_mtrr_valid(unsigned msr)
826{
827 switch (msr) {
828 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
829 case MSR_MTRRfix64K_00000:
830 case MSR_MTRRfix16K_80000:
831 case MSR_MTRRfix16K_A0000:
832 case MSR_MTRRfix4K_C0000:
833 case MSR_MTRRfix4K_C8000:
834 case MSR_MTRRfix4K_D0000:
835 case MSR_MTRRfix4K_D8000:
836 case MSR_MTRRfix4K_E0000:
837 case MSR_MTRRfix4K_E8000:
838 case MSR_MTRRfix4K_F0000:
839 case MSR_MTRRfix4K_F8000:
840 case MSR_MTRRdefType:
841 case MSR_IA32_CR_PAT:
842 return true;
843 case 0x2f8:
844 return true;
845 }
846 return false;
847}
848
d6289b93
MT		 849static bool valid_pat_type(unsigned t)
850{
851 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
852}
853
854static bool valid_mtrr_type(unsigned t)
855{
856 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
857}
858
859static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
860{
861 int i;
862
863 if (!msr_mtrr_valid(msr))
864 return false;
865
866 if (msr == MSR_IA32_CR_PAT) {
867 for (i = 0; i < 8; i++)
868 if (!valid_pat_type((data >> (i * 8)) & 0xff))
869 return false;
870 return true;
871 } else if (msr == MSR_MTRRdefType) {
872 if (data & ~0xcff)
873 return false;
874 return valid_mtrr_type(data & 0xff);
875 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
876 for (i = 0; i < 8 ; i++)
877 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
878 return false;
879 return true;
880 }
881
882 /* variable MTRRs */
883 return valid_mtrr_type(data & 0xff);
884}
885
9ba075a6
AK		 886static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
887{
0bed3b56
SY		 888 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
889
d6289b93 890 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 891 return 1;
892
0bed3b56
SY		 893 if (msr == MSR_MTRRdefType) {
894 vcpu->arch.mtrr_state.def_type = data;
895 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
896 } else if (msr == MSR_MTRRfix64K_00000)
897 p[0] = data;
898 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
899 p[1 + msr - MSR_MTRRfix16K_80000] = data;
900 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
901 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
902 else if (msr == MSR_IA32_CR_PAT)
903 vcpu->arch.pat = data;
904 else { /* Variable MTRRs */
905 int idx, is_mtrr_mask;
906 u64 *pt;
907
908 idx = (msr - 0x200) / 2;
909 is_mtrr_mask = msr - 0x200 - 2 * idx;
910 if (!is_mtrr_mask)
911 pt =
912 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
913 else
914 pt =
915 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
916 *pt = data;
917 }
918
919 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 920 return 0;
921}
15c4a640 922
890ca9ae 923static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 924{
890ca9ae
HY		 925 u64 mcg_cap = vcpu->arch.mcg_cap;
926 unsigned bank_num = mcg_cap & 0xff;
927
15c4a640 928 switch (msr) {
15c4a640 929 case MSR_IA32_MCG_STATUS:
890ca9ae 930 vcpu->arch.mcg_status = data;
15c4a640 931 break;
c7ac679c 932 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 933 if (!(mcg_cap & MCG_CTL_P))
934 return 1;
935 if (data != 0 && data != ~(u64)0)
936 return -1;
937 vcpu->arch.mcg_ctl = data;
938 break;
939 default:
940 if (msr >= MSR_IA32_MC0_CTL &&
941 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
942 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 943 /* only 0 or all 1s can be written to IA32_MCi_CTL
944 * some Linux kernels though clear bit 10 in bank 4 to
945 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
946 * this to avoid an uncatched #GP in the guest
947 */
890ca9ae 948 if ((offset & 0x3) == 0 &&
114be429 949 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 950 return -1;
951 vcpu->arch.mce_banks[offset] = data;
952 break;
953 }
954 return 1;
955 }
956 return 0;
957}
958
ffde22ac
ES		 959static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
960{
961 struct kvm *kvm = vcpu->kvm;
962 int lm = is_long_mode(vcpu);
963 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
964 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
965 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
966 : kvm->arch.xen_hvm_config.blob_size_32;
967 u32 page_num = data & ~PAGE_MASK;
968 u64 page_addr = data & PAGE_MASK;
969 u8 *page;
970 int r;
971
972 r = -E2BIG;
973 if (page_num >= blob_size)
974 goto out;
975 r = -ENOMEM;
976 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
977 if (!page)
978 goto out;
979 r = -EFAULT;
980 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
981 goto out_free;
982 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
983 goto out_free;
984 r = 0;
985out_free:
986 kfree(page);
987out:
988 return r;
989}
990
55cd8e5a
GN		 991static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
992{
993 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
994}
995
996static bool kvm_hv_msr_partition_wide(u32 msr)
997{
998 bool r = false;
999 switch (msr) {
1000 case HV_X64_MSR_GUEST_OS_ID:
1001 case HV_X64_MSR_HYPERCALL:
1002 r = true;
1003 break;
1004 }
1005
1006 return r;
1007}
1008
1009static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1010{
1011 struct kvm *kvm = vcpu->kvm;
1012
1013 switch (msr) {
1014 case HV_X64_MSR_GUEST_OS_ID:
1015 kvm->arch.hv_guest_os_id = data;
1016 /* setting guest os id to zero disables hypercall page */
1017 if (!kvm->arch.hv_guest_os_id)
1018 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1019 break;
1020 case HV_X64_MSR_HYPERCALL: {
1021 u64 gfn;
1022 unsigned long addr;
1023 u8 instructions[4];
1024
1025 /* if guest os id is not set hypercall should remain disabled */
1026 if (!kvm->arch.hv_guest_os_id)
1027 break;
1028 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1029 kvm->arch.hv_hypercall = data;
1030 break;
1031 }
1032 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1033 addr = gfn_to_hva(kvm, gfn);
1034 if (kvm_is_error_hva(addr))
1035 return 1;
1036 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1037 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1038 if (copy_to_user((void __user *)addr, instructions, 4))
1039 return 1;
1040 kvm->arch.hv_hypercall = data;
1041 break;
1042 }
1043 default:
1044 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1045 "data 0x%llx\n", msr, data);
1046 return 1;
1047 }
1048 return 0;
1049}
1050
1051static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1052{
10388a07
GN		 1053 switch (msr) {
1054 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1055 unsigned long addr;
55cd8e5a 1056
10388a07
GN		 1057 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1058 vcpu->arch.hv_vapic = data;
1059 break;
1060 }
1061 addr = gfn_to_hva(vcpu->kvm, data >>
1062 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1063 if (kvm_is_error_hva(addr))
1064 return 1;
1065 if (clear_user((void __user *)addr, PAGE_SIZE))
1066 return 1;
1067 vcpu->arch.hv_vapic = data;
1068 break;
1069 }
1070 case HV_X64_MSR_EOI:
1071 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1072 case HV_X64_MSR_ICR:
1073 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1074 case HV_X64_MSR_TPR:
1075 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1076 default:
1077 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1078 "data 0x%llx\n", msr, data);
1079 return 1;
1080 }
1081
1082 return 0;
55cd8e5a
GN		 1083}
1084
15c4a640
CO		 1085int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1086{
1087 switch (msr) {
15c4a640
CO		 1088 case MSR_EFER:
1089 set_efer(vcpu, data);
1090 break;
8f1589d9
AP		 1091 case MSR_K7_HWCR:
1092 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1093 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1094 if (data != 0) {
1095 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1096 data);
1097 return 1;
1098 }
15c4a640 1099 break;
f7c6d140
AP		 1100 case MSR_FAM10H_MMIO_CONF_BASE:
1101 if (data != 0) {
1102 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1103 "0x%llx\n", data);
1104 return 1;
1105 }
15c4a640 1106 break;
c323c0e5 1107 case MSR_AMD64_NB_CFG:
c7ac679c 1108 break;
b5e2fec0
AG		 1109 case MSR_IA32_DEBUGCTLMSR:
1110 if (!data) {
1111 /* We support the non-activated case already */
1112 break;
1113 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1114 /* Values other than LBR and BTF are vendor-specific,
1115 thus reserved and should throw a #GP */
1116 return 1;
1117 }
1118 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1119 __func__, data);
1120 break;
15c4a640
CO		 1121 case MSR_IA32_UCODE_REV:
1122 case MSR_IA32_UCODE_WRITE:
61a6bd67 1123 case MSR_VM_HSAVE_PA:
6098ca93 1124 case MSR_AMD64_PATCH_LOADER:
15c4a640 1125 break;
9ba075a6
AK		 1126 case 0x200 ... 0x2ff:
1127 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1128 case MSR_IA32_APICBASE:
1129 kvm_set_apic_base(vcpu, data);
1130 break;
0105d1a5
GN		 1131 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1132 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1133 case MSR_IA32_MISC_ENABLE:
ad312c7c 1134 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1135 break;
18068523
GOC		 1136 case MSR_KVM_WALL_CLOCK:
1137 vcpu->kvm->arch.wall_clock = data;
1138 kvm_write_wall_clock(vcpu->kvm, data);
1139 break;
1140 case MSR_KVM_SYSTEM_TIME: {
1141 if (vcpu->arch.time_page) {
1142 kvm_release_page_dirty(vcpu->arch.time_page);
1143 vcpu->arch.time_page = NULL;
1144 }
1145
1146 vcpu->arch.time = data;
1147
1148 /* we verify if the enable bit is set... */
1149 if (!(data & 1))
1150 break;
1151
1152 /* ...but clean it before doing the actual write */
1153 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1154
18068523
GOC		 1155 vcpu->arch.time_page =
1156 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1157
1158 if (is_error_page(vcpu->arch.time_page)) {
1159 kvm_release_page_clean(vcpu->arch.time_page);
1160 vcpu->arch.time_page = NULL;
1161 }
1162
c8076604 1163 kvm_request_guest_time_update(vcpu);
18068523
GOC		 1164 break;
1165 }
890ca9ae
HY		 1166 case MSR_IA32_MCG_CTL:
1167 case MSR_IA32_MCG_STATUS:
1168 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1169 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1170
1171 /* Performance counters are not protected by a CPUID bit,
1172 * so we should check all of them in the generic path for the sake of
1173 * cross vendor migration.
1174 * Writing a zero into the event select MSRs disables them,
1175 * which we perfectly emulate ;-). Any other value should be at least
1176 * reported, some guests depend on them.
1177 */
1178 case MSR_P6_EVNTSEL0:
1179 case MSR_P6_EVNTSEL1:
1180 case MSR_K7_EVNTSEL0:
1181 case MSR_K7_EVNTSEL1:
1182 case MSR_K7_EVNTSEL2:
1183 case MSR_K7_EVNTSEL3:
1184 if (data != 0)
1185 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1186 "0x%x data 0x%llx\n", msr, data);
1187 break;
1188 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1189 * so we ignore writes to make it happy.
1190 */
1191 case MSR_P6_PERFCTR0:
1192 case MSR_P6_PERFCTR1:
1193 case MSR_K7_PERFCTR0:
1194 case MSR_K7_PERFCTR1:
1195 case MSR_K7_PERFCTR2:
1196 case MSR_K7_PERFCTR3:
1197 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1198 "0x%x data 0x%llx\n", msr, data);
1199 break;
55cd8e5a
GN		 1200 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1201 if (kvm_hv_msr_partition_wide(msr)) {
1202 int r;
1203 mutex_lock(&vcpu->kvm->lock);
1204 r = set_msr_hyperv_pw(vcpu, msr, data);
1205 mutex_unlock(&vcpu->kvm->lock);
1206 return r;
1207 } else
1208 return set_msr_hyperv(vcpu, msr, data);
1209 break;
15c4a640 1210 default:
ffde22ac
ES		 1211 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1212 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1213 if (!ignore_msrs) {
1214 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1215 msr, data);
1216 return 1;
1217 } else {
1218 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1219 msr, data);
1220 break;
1221 }
15c4a640
CO		 1222 }
1223 return 0;
1224}
1225EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1226
1227
1228/*
1229 * Reads an msr value (of 'msr_index') into 'pdata'.
1230 * Returns 0 on success, non-0 otherwise.
1231 * Assumes vcpu_load() was already called.
1232 */
1233int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1234{
1235 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1236}
1237
9ba075a6
AK		 1238static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1239{
0bed3b56
SY		 1240 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1241
9ba075a6
AK		 1242 if (!msr_mtrr_valid(msr))
1243 return 1;
1244
0bed3b56
SY		 1245 if (msr == MSR_MTRRdefType)
1246 *pdata = vcpu->arch.mtrr_state.def_type +
1247 (vcpu->arch.mtrr_state.enabled << 10);
1248 else if (msr == MSR_MTRRfix64K_00000)
1249 *pdata = p[0];
1250 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1251 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1252 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1253 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1254 else if (msr == MSR_IA32_CR_PAT)
1255 *pdata = vcpu->arch.pat;
1256 else { /* Variable MTRRs */
1257 int idx, is_mtrr_mask;
1258 u64 *pt;
1259
1260 idx = (msr - 0x200) / 2;
1261 is_mtrr_mask = msr - 0x200 - 2 * idx;
1262 if (!is_mtrr_mask)
1263 pt =
1264 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1265 else
1266 pt =
1267 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1268 *pdata = *pt;
1269 }
1270
9ba075a6
AK		 1271 return 0;
1272}
1273
890ca9ae 1274static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1275{
1276 u64 data;
890ca9ae
HY		 1277 u64 mcg_cap = vcpu->arch.mcg_cap;
1278 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1279
1280 switch (msr) {
15c4a640
CO		 1281 case MSR_IA32_P5_MC_ADDR:
1282 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1283 data = 0;
1284 break;
15c4a640 1285 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1286 data = vcpu->arch.mcg_cap;
1287 break;
c7ac679c 1288 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1289 if (!(mcg_cap & MCG_CTL_P))
1290 return 1;
1291 data = vcpu->arch.mcg_ctl;
1292 break;
1293 case MSR_IA32_MCG_STATUS:
1294 data = vcpu->arch.mcg_status;
1295 break;
1296 default:
1297 if (msr >= MSR_IA32_MC0_CTL &&
1298 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1299 u32 offset = msr - MSR_IA32_MC0_CTL;
1300 data = vcpu->arch.mce_banks[offset];
1301 break;
1302 }
1303 return 1;
1304 }
1305 *pdata = data;
1306 return 0;
1307}
1308
55cd8e5a
GN		 1309static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1310{
1311 u64 data = 0;
1312 struct kvm *kvm = vcpu->kvm;
1313
1314 switch (msr) {
1315 case HV_X64_MSR_GUEST_OS_ID:
1316 data = kvm->arch.hv_guest_os_id;
1317 break;
1318 case HV_X64_MSR_HYPERCALL:
1319 data = kvm->arch.hv_hypercall;
1320 break;
1321 default:
1322 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1323 return 1;
1324 }
1325
1326 *pdata = data;
1327 return 0;
1328}
1329
1330static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1331{
1332 u64 data = 0;
1333
1334 switch (msr) {
1335 case HV_X64_MSR_VP_INDEX: {
1336 int r;
1337 struct kvm_vcpu *v;
1338 kvm_for_each_vcpu(r, v, vcpu->kvm)
1339 if (v == vcpu)
1340 data = r;
1341 break;
1342 }
10388a07
GN		 1343 case HV_X64_MSR_EOI:
1344 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1345 case HV_X64_MSR_ICR:
1346 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1347 case HV_X64_MSR_TPR:
1348 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1349 default:
1350 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1351 return 1;
1352 }
1353 *pdata = data;
1354 return 0;
1355}
1356
890ca9ae
HY		 1357int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1358{
1359 u64 data;
1360
1361 switch (msr) {
890ca9ae 1362 case MSR_IA32_PLATFORM_ID:
15c4a640 1363 case MSR_IA32_UCODE_REV:
15c4a640 1364 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1365 case MSR_IA32_DEBUGCTLMSR:
1366 case MSR_IA32_LASTBRANCHFROMIP:
1367 case MSR_IA32_LASTBRANCHTOIP:
1368 case MSR_IA32_LASTINTFROMIP:
1369 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1370 case MSR_K8_SYSCFG:
1371 case MSR_K7_HWCR:
61a6bd67 1372 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1373 case MSR_P6_PERFCTR0:
1374 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1375 case MSR_P6_EVNTSEL0:
1376 case MSR_P6_EVNTSEL1:
9e699624 1377 case MSR_K7_EVNTSEL0:
1f3ee616 1378 case MSR_K7_PERFCTR0:
1fdbd48c 1379 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1380 case MSR_AMD64_NB_CFG:
f7c6d140 1381 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1382 data = 0;
1383 break;
9ba075a6
AK		 1384 case MSR_MTRRcap:
1385 data = 0x500 | KVM_NR_VAR_MTRR;
1386 break;
1387 case 0x200 ... 0x2ff:
1388 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1389 case 0xcd: /* fsb frequency */
1390 data = 3;
1391 break;
1392 case MSR_IA32_APICBASE:
1393 data = kvm_get_apic_base(vcpu);
1394 break;
0105d1a5
GN		 1395 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1396 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1397 break;
15c4a640 1398 case MSR_IA32_MISC_ENABLE:
ad312c7c 1399 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1400 break;
847f0ad8
AG		 1401 case MSR_IA32_PERF_STATUS:
1402 /* TSC increment by tick */
1403 data = 1000ULL;
1404 /* CPU multiplier */
1405 data |= (((uint64_t)4ULL) << 40);
1406 break;
15c4a640 1407 case MSR_EFER:
f6801dff 1408 data = vcpu->arch.efer;
15c4a640 1409 break;
18068523
GOC		 1410 case MSR_KVM_WALL_CLOCK:
1411 data = vcpu->kvm->arch.wall_clock;
1412 break;
1413 case MSR_KVM_SYSTEM_TIME:
1414 data = vcpu->arch.time;
1415 break;
890ca9ae
HY		 1416 case MSR_IA32_P5_MC_ADDR:
1417 case MSR_IA32_P5_MC_TYPE:
1418 case MSR_IA32_MCG_CAP:
1419 case MSR_IA32_MCG_CTL:
1420 case MSR_IA32_MCG_STATUS:
1421 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1422 return get_msr_mce(vcpu, msr, pdata);
55cd8e5a
GN		 1423 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1424 if (kvm_hv_msr_partition_wide(msr)) {
1425 int r;
1426 mutex_lock(&vcpu->kvm->lock);
1427 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1428 mutex_unlock(&vcpu->kvm->lock);
1429 return r;
1430 } else
1431 return get_msr_hyperv(vcpu, msr, pdata);
1432 break;
15c4a640 1433 default:
ed85c068
AP		 1434 if (!ignore_msrs) {
1435 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1436 return 1;
1437 } else {
1438 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1439 data = 0;
1440 }
1441 break;
15c4a640
CO		 1442 }
1443 *pdata = data;
1444 return 0;
1445}
1446EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1447
313a3dc7
CO		 1448/*
1449 * Read or write a bunch of msrs. All parameters are kernel addresses.
1450 *
1451 * @return number of msrs set successfully.
1452 */
1453static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1454 struct kvm_msr_entry *entries,
1455 int (*do_msr)(struct kvm_vcpu *vcpu,
1456 unsigned index, u64 *data))
1457{
f656ce01 1458 int i, idx;
313a3dc7
CO		 1459
1460 vcpu_load(vcpu);
1461
f656ce01 1462 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1463 for (i = 0; i < msrs->nmsrs; ++i)
1464 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1465 break;
f656ce01 1466 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7
CO		 1467
1468 vcpu_put(vcpu);
1469
1470 return i;
1471}
1472
1473/*
1474 * Read or write a bunch of msrs. Parameters are user addresses.
1475 *
1476 * @return number of msrs set successfully.
1477 */
1478static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1479 int (*do_msr)(struct kvm_vcpu *vcpu,
1480 unsigned index, u64 *data),
1481 int writeback)
1482{
1483 struct kvm_msrs msrs;
1484 struct kvm_msr_entry *entries;
1485 int r, n;
1486 unsigned size;
1487
1488 r = -EFAULT;
1489 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1490 goto out;
1491
1492 r = -E2BIG;
1493 if (msrs.nmsrs >= MAX_IO_MSRS)
1494 goto out;
1495
1496 r = -ENOMEM;
1497 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1498 entries = vmalloc(size);
1499 if (!entries)
1500 goto out;
1501
1502 r = -EFAULT;
1503 if (copy_from_user(entries, user_msrs->entries, size))
1504 goto out_free;
1505
1506 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1507 if (r < 0)
1508 goto out_free;
1509
1510 r = -EFAULT;
1511 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1512 goto out_free;
1513
1514 r = n;
1515
1516out_free:
1517 vfree(entries);
1518out:
1519 return r;
1520}
1521
018d00d2
ZX		 1522int kvm_dev_ioctl_check_extension(long ext)
1523{
1524 int r;
1525
1526 switch (ext) {
1527 case KVM_CAP_IRQCHIP:
1528 case KVM_CAP_HLT:
1529 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1530 case KVM_CAP_SET_TSS_ADDR:
07716717 1531 case KVM_CAP_EXT_CPUID:
c8076604 1532 case KVM_CAP_CLOCKSOURCE:
7837699f 1533 case KVM_CAP_PIT:
a28e4f5a 1534 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1535 case KVM_CAP_MP_STATE:
ed848624 1536 case KVM_CAP_SYNC_MMU:
52d939a0 1537 case KVM_CAP_REINJECT_CONTROL:
4925663a 1538 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1539 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1540 case KVM_CAP_IRQFD:
d34e6b17 1541 case KVM_CAP_IOEVENTFD:
c5ff41ce 1542 case KVM_CAP_PIT2:
e9f42757 1543 case KVM_CAP_PIT_STATE2:
b927a3ce 1544 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1545 case KVM_CAP_XEN_HVM:
afbcf7ab 1546 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1547 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1548 case KVM_CAP_HYPERV:
10388a07 1549 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1550 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1551 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1552 case KVM_CAP_DEBUGREGS:
d2be1651 1553 case KVM_CAP_X86_ROBUST_SINGLESTEP:
018d00d2
ZX		 1554 r = 1;
1555 break;
542472b5
LV		 1556 case KVM_CAP_COALESCED_MMIO:
1557 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1558 break;
774ead3a
AK		 1559 case KVM_CAP_VAPIC:
1560 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1561 break;
f725230a
AK		 1562 case KVM_CAP_NR_VCPUS:
1563 r = KVM_MAX_VCPUS;
1564 break;
a988b910
AK		 1565 case KVM_CAP_NR_MEMSLOTS:
1566 r = KVM_MEMORY_SLOTS;
1567 break;
a68a6a72
MT		 1568 case KVM_CAP_PV_MMU: /* obsolete */
1569 r = 0;
2f333bcb 1570 break;
62c476c7 1571 case KVM_CAP_IOMMU:
19de40a8 1572 r = iommu_found();
62c476c7 1573 break;
890ca9ae
HY		 1574 case KVM_CAP_MCE:
1575 r = KVM_MAX_MCE_BANKS;
1576 break;
018d00d2
ZX		 1577 default:
1578 r = 0;
1579 break;
1580 }
1581 return r;
1582
1583}
1584
043405e1
CO		 1585long kvm_arch_dev_ioctl(struct file *filp,
1586 unsigned int ioctl, unsigned long arg)
1587{
1588 void __user *argp = (void __user *)arg;
1589 long r;
1590
1591 switch (ioctl) {
1592 case KVM_GET_MSR_INDEX_LIST: {
1593 struct kvm_msr_list __user *user_msr_list = argp;
1594 struct kvm_msr_list msr_list;
1595 unsigned n;
1596
1597 r = -EFAULT;
1598 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1599 goto out;
1600 n = msr_list.nmsrs;
1601 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1602 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1603 goto out;
1604 r = -E2BIG;
e125e7b6 1605 if (n < msr_list.nmsrs)
043405e1
CO		 1606 goto out;
1607 r = -EFAULT;
1608 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1609 num_msrs_to_save * sizeof(u32)))
1610 goto out;
e125e7b6 1611 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1612 &emulated_msrs,
1613 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1614 goto out;
1615 r = 0;
1616 break;
1617 }
674eea0f
AK		 1618 case KVM_GET_SUPPORTED_CPUID: {
1619 struct kvm_cpuid2 __user *cpuid_arg = argp;
1620 struct kvm_cpuid2 cpuid;
1621
1622 r = -EFAULT;
1623 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1624 goto out;
1625 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1626 cpuid_arg->entries);
674eea0f
AK		 1627 if (r)
1628 goto out;
1629
1630 r = -EFAULT;
1631 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1632 goto out;
1633 r = 0;
1634 break;
1635 }
890ca9ae
HY		 1636 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1637 u64 mce_cap;
1638
1639 mce_cap = KVM_MCE_CAP_SUPPORTED;
1640 r = -EFAULT;
1641 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1642 goto out;
1643 r = 0;
1644 break;
1645 }
043405e1
CO		 1646 default:
1647 r = -EINVAL;
1648 }
1649out:
1650 return r;
1651}
1652
313a3dc7
CO		 1653void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1654{
1655 kvm_x86_ops->vcpu_load(vcpu, cpu);
6b7d7e76
ZA		 1656 if (unlikely(per_cpu(cpu_tsc_khz, cpu) == 0)) {
1657 unsigned long khz = cpufreq_quick_get(cpu);
1658 if (!khz)
1659 khz = tsc_khz;
1660 per_cpu(cpu_tsc_khz, cpu) = khz;
1661 }
c8076604 1662 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1663}
1664
1665void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1666{
9327fd11 1667 kvm_put_guest_fpu(vcpu);
02daab21 1668 kvm_x86_ops->vcpu_put(vcpu);
313a3dc7
CO		 1669}
1670
07716717 1671static int is_efer_nx(void)
313a3dc7 1672{
e286e86e 1673 unsigned long long efer = 0;
313a3dc7 1674
e286e86e 1675 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1676 return efer & EFER_NX;
1677}
1678
1679static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1680{
1681 int i;
1682 struct kvm_cpuid_entry2 *e, *entry;
1683
313a3dc7 1684 entry = NULL;
ad312c7c
ZX		 1685 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1686 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1687 if (e->function == 0x80000001) {
1688 entry = e;
1689 break;
1690 }
1691 }
07716717 1692 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1693 entry->edx &= ~(1 << 20);
1694 printk(KERN_INFO "kvm: guest NX capability removed\n");
1695 }
1696}
1697
07716717 1698/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1699static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1700 struct kvm_cpuid *cpuid,
1701 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1702{
1703 int r, i;
1704 struct kvm_cpuid_entry *cpuid_entries;
1705
1706 r = -E2BIG;
1707 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1708 goto out;
1709 r = -ENOMEM;
1710 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1711 if (!cpuid_entries)
1712 goto out;
1713 r = -EFAULT;
1714 if (copy_from_user(cpuid_entries, entries,
1715 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1716 goto out_free;
1717 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1718 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1719 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1720 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1721 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1722 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1723 vcpu->arch.cpuid_entries[i].index = 0;
1724 vcpu->arch.cpuid_entries[i].flags = 0;
1725 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1726 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1727 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1728 }
1729 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1730 cpuid_fix_nx_cap(vcpu);
1731 r = 0;
fc61b800 1732 kvm_apic_set_version(vcpu);
0e851880 1733 kvm_x86_ops->cpuid_update(vcpu);
07716717
DK		 1734
1735out_free:
1736 vfree(cpuid_entries);
1737out:
1738 return r;
1739}
1740
1741static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1742 struct kvm_cpuid2 *cpuid,
1743 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1744{
1745 int r;
1746
1747 r = -E2BIG;
1748 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1749 goto out;
1750 r = -EFAULT;
ad312c7c 1751 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1752 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1753 goto out;
ad312c7c 1754 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 1755 kvm_apic_set_version(vcpu);
0e851880 1756 kvm_x86_ops->cpuid_update(vcpu);
313a3dc7
CO		 1757 return 0;
1758
1759out:
1760 return r;
1761}
1762
07716717 1763static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1764 struct kvm_cpuid2 *cpuid,
1765 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1766{
1767 int r;
1768
1769 r = -E2BIG;
ad312c7c 1770 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1771 goto out;
1772 r = -EFAULT;
ad312c7c 1773 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1774 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1775 goto out;
1776 return 0;
1777
1778out:
ad312c7c 1779 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1780 return r;
1781}
1782
07716717 1783static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1784 u32 index)
07716717
DK		 1785{
1786 entry->function = function;
1787 entry->index = index;
1788 cpuid_count(entry->function, entry->index,
19355475 1789 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1790 entry->flags = 0;
1791}
1792
7faa4ee1
AK		 1793#define F(x) bit(X86_FEATURE_##x)
1794
07716717
DK		 1795static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1796 u32 index, int *nent, int maxnent)
1797{
7faa4ee1 1798 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1799#ifdef CONFIG_X86_64
17cc3935
SY		 1800 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
1801 ? F(GBPAGES) : 0;
7faa4ee1
AK		 1802 unsigned f_lm = F(LM);
1803#else
17cc3935 1804 unsigned f_gbpages = 0;
7faa4ee1 1805 unsigned f_lm = 0;
07716717 1806#endif
4e47c7a6 1807 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 1808
1809 /* cpuid 1.edx */
1810 const u32 kvm_supported_word0_x86_features =
1811 F(FPU) | F(VME) | F(DE) | F(PSE) |
1812 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1813 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1814 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1815 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1816 0 /* Reserved, DS, ACPI */ | F(MMX) |
1817 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1818 0 /* HTT, TM, Reserved, PBE */;
1819 /* cpuid 0x80000001.edx */
1820 const u32 kvm_supported_word1_x86_features =
1821 F(FPU) | F(VME) | F(DE) | F(PSE) |
1822 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1823 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1824 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1825 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1826 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 1827 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 1828 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1829 /* cpuid 1.ecx */
1830 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1831 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1832 0 /* DS-CPL, VMX, SMX, EST */ |
1833 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1834 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1835 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 1836 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
d149c731 1837 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1838 /* cpuid 0x80000001.ecx */
07716717 1839 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1840 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1841 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1842 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1843 0 /* SKINIT */ | 0 /* WDT */;
07716717 1844
19355475 1845 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1846 get_cpu();
1847 do_cpuid_1_ent(entry, function, index);
1848 ++*nent;
1849
1850 switch (function) {
1851 case 0:
1852 entry->eax = min(entry->eax, (u32)0xb);
1853 break;
1854 case 1:
1855 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1856 entry->ecx &= kvm_supported_word4_x86_features;
0d1de2d9
GN		 1857 /* we support x2apic emulation even if host does not support
1858 * it since we emulate x2apic in software */
1859 entry->ecx |= F(X2APIC);
07716717
DK		 1860 break;
1861 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1862 * may return different values. This forces us to get_cpu() before
1863 * issuing the first command, and also to emulate this annoying behavior
1864 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1865 case 2: {
1866 int t, times = entry->eax & 0xff;
1867
1868 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1869 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1870 for (t = 1; t < times && *nent < maxnent; ++t) {
1871 do_cpuid_1_ent(&entry[t], function, 0);
1872 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1873 ++*nent;
1874 }
1875 break;
1876 }
1877 /* function 4 and 0xb have additional index. */
1878 case 4: {
14af3f3c 1879 int i, cache_type;
07716717
DK		 1880
1881 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1882 /* read more entries until cache_type is zero */
14af3f3c
HH		 1883 for (i = 1; *nent < maxnent; ++i) {
1884 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1885 if (!cache_type)
1886 break;
14af3f3c
HH		 1887 do_cpuid_1_ent(&entry[i], function, i);
1888 entry[i].flags |=
07716717
DK		 1889 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1890 ++*nent;
1891 }
1892 break;
1893 }
1894 case 0xb: {
14af3f3c 1895 int i, level_type;
07716717
DK		 1896
1897 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1898 /* read more entries until level_type is zero */
14af3f3c 1899 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1900 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1901 if (!level_type)
1902 break;
14af3f3c
HH		 1903 do_cpuid_1_ent(&entry[i], function, i);
1904 entry[i].flags |=
07716717
DK		 1905 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1906 ++*nent;
1907 }
1908 break;
1909 }
1910 case 0x80000000:
1911 entry->eax = min(entry->eax, 0x8000001a);
1912 break;
1913 case 0x80000001:
1914 entry->edx &= kvm_supported_word1_x86_features;
1915 entry->ecx &= kvm_supported_word6_x86_features;
1916 break;
1917 }
1918 put_cpu();
1919}
1920
7faa4ee1
AK		 1921#undef F
1922
674eea0f 1923static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1924 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1925{
1926 struct kvm_cpuid_entry2 *cpuid_entries;
1927 int limit, nent = 0, r = -E2BIG;
1928 u32 func;
1929
1930 if (cpuid->nent < 1)
1931 goto out;
6a544355
AK		 1932 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1933 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 1934 r = -ENOMEM;
1935 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1936 if (!cpuid_entries)
1937 goto out;
1938
1939 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1940 limit = cpuid_entries[0].eax;
1941 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1942 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1943 &nent, cpuid->nent);
07716717
DK		 1944 r = -E2BIG;
1945 if (nent >= cpuid->nent)
1946 goto out_free;
1947
1948 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1949 limit = cpuid_entries[nent - 1].eax;
1950 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1951 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1952 &nent, cpuid->nent);
cb007648
MM		 1953 r = -E2BIG;
1954 if (nent >= cpuid->nent)
1955 goto out_free;
1956
07716717
DK		 1957 r = -EFAULT;
1958 if (copy_to_user(entries, cpuid_entries,
19355475 1959 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1960 goto out_free;
1961 cpuid->nent = nent;
1962 r = 0;
1963
1964out_free:
1965 vfree(cpuid_entries);
1966out:
1967 return r;
1968}
1969
313a3dc7
CO		 1970static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1971 struct kvm_lapic_state *s)
1972{
1973 vcpu_load(vcpu);
ad312c7c 1974 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1975 vcpu_put(vcpu);
1976
1977 return 0;
1978}
1979
1980static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1981 struct kvm_lapic_state *s)
1982{
1983 vcpu_load(vcpu);
ad312c7c 1984 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 1985 kvm_apic_post_state_restore(vcpu);
cb142eb7 1986 update_cr8_intercept(vcpu);
313a3dc7
CO		 1987 vcpu_put(vcpu);
1988
1989 return 0;
1990}
1991
f77bc6a4
ZX		 1992static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1993 struct kvm_interrupt *irq)
1994{
1995 if (irq->irq < 0 || irq->irq >= 256)
1996 return -EINVAL;
1997 if (irqchip_in_kernel(vcpu->kvm))
1998 return -ENXIO;
1999 vcpu_load(vcpu);
2000
66fd3f7f 2001 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 2002
2003 vcpu_put(vcpu);
2004
2005 return 0;
2006}
2007
c4abb7c9
JK		 2008static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2009{
2010 vcpu_load(vcpu);
2011 kvm_inject_nmi(vcpu);
2012 vcpu_put(vcpu);
2013
2014 return 0;
2015}
2016
b209749f
AK		 2017static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2018 struct kvm_tpr_access_ctl *tac)
2019{
2020 if (tac->flags)
2021 return -EINVAL;
2022 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2023 return 0;
2024}
2025
890ca9ae
HY		 2026static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2027 u64 mcg_cap)
2028{
2029 int r;
2030 unsigned bank_num = mcg_cap & 0xff, bank;
2031
2032 r = -EINVAL;
a9e38c3e 2033 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2034 goto out;
2035 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2036 goto out;
2037 r = 0;
2038 vcpu->arch.mcg_cap = mcg_cap;
2039 /* Init IA32_MCG_CTL to all 1s */
2040 if (mcg_cap & MCG_CTL_P)
2041 vcpu->arch.mcg_ctl = ~(u64)0;
2042 /* Init IA32_MCi_CTL to all 1s */
2043 for (bank = 0; bank < bank_num; bank++)
2044 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2045out:
2046 return r;
2047}
2048
2049static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2050 struct kvm_x86_mce *mce)
2051{
2052 u64 mcg_cap = vcpu->arch.mcg_cap;
2053 unsigned bank_num = mcg_cap & 0xff;
2054 u64 *banks = vcpu->arch.mce_banks;
2055
2056 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2057 return -EINVAL;
2058 /*
2059 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2060 * reporting is disabled
2061 */
2062 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2063 vcpu->arch.mcg_ctl != ~(u64)0)
2064 return 0;
2065 banks += 4 * mce->bank;
2066 /*
2067 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2068 * reporting is disabled for the bank
2069 */
2070 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2071 return 0;
2072 if (mce->status & MCI_STATUS_UC) {
2073 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2074 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
890ca9ae
HY		 2075 printk(KERN_DEBUG "kvm: set_mce: "
2076 "injects mce exception while "
2077 "previous one is in progress!\n");
2078 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2079 return 0;
2080 }
2081 if (banks[1] & MCI_STATUS_VAL)
2082 mce->status |= MCI_STATUS_OVER;
2083 banks[2] = mce->addr;
2084 banks[3] = mce->misc;
2085 vcpu->arch.mcg_status = mce->mcg_status;
2086 banks[1] = mce->status;
2087 kvm_queue_exception(vcpu, MC_VECTOR);
2088 } else if (!(banks[1] & MCI_STATUS_VAL)
2089 || !(banks[1] & MCI_STATUS_UC)) {
2090 if (banks[1] & MCI_STATUS_VAL)
2091 mce->status |= MCI_STATUS_OVER;
2092 banks[2] = mce->addr;
2093 banks[3] = mce->misc;
2094 banks[1] = mce->status;
2095 } else
2096 banks[1] |= MCI_STATUS_OVER;
2097 return 0;
2098}
2099
3cfc3092
JK		 2100static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2101 struct kvm_vcpu_events *events)
2102{
2103 vcpu_load(vcpu);
2104
03b82a30
JK		 2105 events->exception.injected =
2106 vcpu->arch.exception.pending &&
2107 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2108 events->exception.nr = vcpu->arch.exception.nr;
2109 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2110 events->exception.error_code = vcpu->arch.exception.error_code;
2111
03b82a30
JK		 2112 events->interrupt.injected =
2113 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2114 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2115 events->interrupt.soft = 0;
48005f64
JK		 2116 events->interrupt.shadow =
2117 kvm_x86_ops->get_interrupt_shadow(vcpu,
2118 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2119
2120 events->nmi.injected = vcpu->arch.nmi_injected;
2121 events->nmi.pending = vcpu->arch.nmi_pending;
2122 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2123
2124 events->sipi_vector = vcpu->arch.sipi_vector;
2125
dab4b911 2126 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2127 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2128 | KVM_VCPUEVENT_VALID_SHADOW);
3cfc3092
JK		 2129
2130 vcpu_put(vcpu);
2131}
2132
2133static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2134 struct kvm_vcpu_events *events)
2135{
dab4b911 2136 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2137 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2138 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2139 return -EINVAL;
2140
2141 vcpu_load(vcpu);
2142
2143 vcpu->arch.exception.pending = events->exception.injected;
2144 vcpu->arch.exception.nr = events->exception.nr;
2145 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2146 vcpu->arch.exception.error_code = events->exception.error_code;
2147
2148 vcpu->arch.interrupt.pending = events->interrupt.injected;
2149 vcpu->arch.interrupt.nr = events->interrupt.nr;
2150 vcpu->arch.interrupt.soft = events->interrupt.soft;
2151 if (vcpu->arch.interrupt.pending && irqchip_in_kernel(vcpu->kvm))
2152 kvm_pic_clear_isr_ack(vcpu->kvm);
48005f64
JK		 2153 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2154 kvm_x86_ops->set_interrupt_shadow(vcpu,
2155 events->interrupt.shadow);
3cfc3092
JK		 2156
2157 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2158 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2159 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2160 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2161
dab4b911
JK		 2162 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2163 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092
JK		 2164
2165 vcpu_put(vcpu);
2166
2167 return 0;
2168}
2169
a1efbe77
JK		 2170static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2171 struct kvm_debugregs *dbgregs)
2172{
2173 vcpu_load(vcpu);
2174
2175 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2176 dbgregs->dr6 = vcpu->arch.dr6;
2177 dbgregs->dr7 = vcpu->arch.dr7;
2178 dbgregs->flags = 0;
2179
2180 vcpu_put(vcpu);
2181}
2182
2183static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2184 struct kvm_debugregs *dbgregs)
2185{
2186 if (dbgregs->flags)
2187 return -EINVAL;
2188
2189 vcpu_load(vcpu);
2190
2191 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2192 vcpu->arch.dr6 = dbgregs->dr6;
2193 vcpu->arch.dr7 = dbgregs->dr7;
2194
2195 vcpu_put(vcpu);
2196
2197 return 0;
2198}
2199
313a3dc7
CO		 2200long kvm_arch_vcpu_ioctl(struct file *filp,
2201 unsigned int ioctl, unsigned long arg)
2202{
2203 struct kvm_vcpu *vcpu = filp->private_data;
2204 void __user *argp = (void __user *)arg;
2205 int r;
b772ff36 2206 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 2207
2208 switch (ioctl) {
2209 case KVM_GET_LAPIC: {
2204ae3c
MT		 2210 r = -EINVAL;
2211 if (!vcpu->arch.apic)
2212 goto out;
b772ff36 2213 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2214
b772ff36
DH		 2215 r = -ENOMEM;
2216 if (!lapic)
2217 goto out;
2218 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 2219 if (r)
2220 goto out;
2221 r = -EFAULT;
b772ff36 2222 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2223 goto out;
2224 r = 0;
2225 break;
2226 }
2227 case KVM_SET_LAPIC: {
2204ae3c
MT		 2228 r = -EINVAL;
2229 if (!vcpu->arch.apic)
2230 goto out;
b772ff36
DH		 2231 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
2232 r = -ENOMEM;
2233 if (!lapic)
2234 goto out;
313a3dc7 2235 r = -EFAULT;
b772ff36 2236 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2237 goto out;
b772ff36 2238 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 2239 if (r)
2240 goto out;
2241 r = 0;
2242 break;
2243 }
f77bc6a4
ZX		 2244 case KVM_INTERRUPT: {
2245 struct kvm_interrupt irq;
2246
2247 r = -EFAULT;
2248 if (copy_from_user(&irq, argp, sizeof irq))
2249 goto out;
2250 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2251 if (r)
2252 goto out;
2253 r = 0;
2254 break;
2255 }
c4abb7c9
JK		 2256 case KVM_NMI: {
2257 r = kvm_vcpu_ioctl_nmi(vcpu);
2258 if (r)
2259 goto out;
2260 r = 0;
2261 break;
2262 }
313a3dc7
CO		 2263 case KVM_SET_CPUID: {
2264 struct kvm_cpuid __user *cpuid_arg = argp;
2265 struct kvm_cpuid cpuid;
2266
2267 r = -EFAULT;
2268 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2269 goto out;
2270 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2271 if (r)
2272 goto out;
2273 break;
2274 }
07716717
DK		 2275 case KVM_SET_CPUID2: {
2276 struct kvm_cpuid2 __user *cpuid_arg = argp;
2277 struct kvm_cpuid2 cpuid;
2278
2279 r = -EFAULT;
2280 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2281 goto out;
2282 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2283 cpuid_arg->entries);
07716717
DK		 2284 if (r)
2285 goto out;
2286 break;
2287 }
2288 case KVM_GET_CPUID2: {
2289 struct kvm_cpuid2 __user *cpuid_arg = argp;
2290 struct kvm_cpuid2 cpuid;
2291
2292 r = -EFAULT;
2293 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2294 goto out;
2295 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2296 cpuid_arg->entries);
07716717
DK		 2297 if (r)
2298 goto out;
2299 r = -EFAULT;
2300 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2301 goto out;
2302 r = 0;
2303 break;
2304 }
313a3dc7
CO		 2305 case KVM_GET_MSRS:
2306 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2307 break;
2308 case KVM_SET_MSRS:
2309 r = msr_io(vcpu, argp, do_set_msr, 0);
2310 break;
b209749f
AK		 2311 case KVM_TPR_ACCESS_REPORTING: {
2312 struct kvm_tpr_access_ctl tac;
2313
2314 r = -EFAULT;
2315 if (copy_from_user(&tac, argp, sizeof tac))
2316 goto out;
2317 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2318 if (r)
2319 goto out;
2320 r = -EFAULT;
2321 if (copy_to_user(argp, &tac, sizeof tac))
2322 goto out;
2323 r = 0;
2324 break;
2325 };
b93463aa
AK		 2326 case KVM_SET_VAPIC_ADDR: {
2327 struct kvm_vapic_addr va;
2328
2329 r = -EINVAL;
2330 if (!irqchip_in_kernel(vcpu->kvm))
2331 goto out;
2332 r = -EFAULT;
2333 if (copy_from_user(&va, argp, sizeof va))
2334 goto out;
2335 r = 0;
2336 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2337 break;
2338 }
890ca9ae
HY		 2339 case KVM_X86_SETUP_MCE: {
2340 u64 mcg_cap;
2341
2342 r = -EFAULT;
2343 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2344 goto out;
2345 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2346 break;
2347 }
2348 case KVM_X86_SET_MCE: {
2349 struct kvm_x86_mce mce;
2350
2351 r = -EFAULT;
2352 if (copy_from_user(&mce, argp, sizeof mce))
2353 goto out;
2354 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2355 break;
2356 }
3cfc3092
JK		 2357 case KVM_GET_VCPU_EVENTS: {
2358 struct kvm_vcpu_events events;
2359
2360 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2361
2362 r = -EFAULT;
2363 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2364 break;
2365 r = 0;
2366 break;
2367 }
2368 case KVM_SET_VCPU_EVENTS: {
2369 struct kvm_vcpu_events events;
2370
2371 r = -EFAULT;
2372 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2373 break;
2374
2375 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2376 break;
2377 }
a1efbe77
JK		 2378 case KVM_GET_DEBUGREGS: {
2379 struct kvm_debugregs dbgregs;
2380
2381 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2382
2383 r = -EFAULT;
2384 if (copy_to_user(argp, &dbgregs,
2385 sizeof(struct kvm_debugregs)))
2386 break;
2387 r = 0;
2388 break;
2389 }
2390 case KVM_SET_DEBUGREGS: {
2391 struct kvm_debugregs dbgregs;
2392
2393 r = -EFAULT;
2394 if (copy_from_user(&dbgregs, argp,
2395 sizeof(struct kvm_debugregs)))
2396 break;
2397
2398 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2399 break;
2400 }
313a3dc7
CO		 2401 default:
2402 r = -EINVAL;
2403 }
2404out:
7a6ce84c 2405 kfree(lapic);
313a3dc7
CO		 2406 return r;
2407}
2408
1fe779f8
CO		 2409static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2410{
2411 int ret;
2412
2413 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2414 return -1;
2415 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2416 return ret;
2417}
2418
b927a3ce
SY		 2419static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2420 u64 ident_addr)
2421{
2422 kvm->arch.ept_identity_map_addr = ident_addr;
2423 return 0;
2424}
2425
1fe779f8
CO		 2426static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2427 u32 kvm_nr_mmu_pages)
2428{
2429 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2430 return -EINVAL;
2431
79fac95e 2432 mutex_lock(&kvm->slots_lock);
7c8a83b7 2433 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2434
2435 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2436 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2437
7c8a83b7 2438 spin_unlock(&kvm->mmu_lock);
79fac95e 2439 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2440 return 0;
2441}
2442
2443static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2444{
f05e70ac 2445 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 2446}
2447
a983fb23
MT		 2448gfn_t unalias_gfn_instantiation(struct kvm *kvm, gfn_t gfn)
2449{
2450 int i;
2451 struct kvm_mem_alias *alias;
2452 struct kvm_mem_aliases *aliases;
2453
2454 aliases = rcu_dereference(kvm->arch.aliases);
2455
2456 for (i = 0; i < aliases->naliases; ++i) {
2457 alias = &aliases->aliases[i];
2458 if (alias->flags & KVM_ALIAS_INVALID)
2459 continue;
2460 if (gfn >= alias->base_gfn
2461 && gfn < alias->base_gfn + alias->npages)
2462 return alias->target_gfn + gfn - alias->base_gfn;
2463 }
2464 return gfn;
2465}
2466
e9f85cde
ZX		 2467gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
2468{
2469 int i;
2470 struct kvm_mem_alias *alias;
a983fb23
MT		 2471 struct kvm_mem_aliases *aliases;
2472
2473 aliases = rcu_dereference(kvm->arch.aliases);
e9f85cde 2474
fef9cce0
MT		 2475 for (i = 0; i < aliases->naliases; ++i) {
2476 alias = &aliases->aliases[i];
e9f85cde
ZX		 2477 if (gfn >= alias->base_gfn
2478 && gfn < alias->base_gfn + alias->npages)
2479 return alias->target_gfn + gfn - alias->base_gfn;
2480 }
2481 return gfn;
2482}
2483
1fe779f8
CO		 2484/*
2485 * Set a new alias region. Aliases map a portion of physical memory into
2486 * another portion. This is useful for memory windows, for example the PC
2487 * VGA region.
2488 */
2489static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
2490 struct kvm_memory_alias *alias)
2491{
2492 int r, n;
2493 struct kvm_mem_alias *p;
a983fb23 2494 struct kvm_mem_aliases *aliases, *old_aliases;
1fe779f8
CO		 2495
2496 r = -EINVAL;
2497 /* General sanity checks */
2498 if (alias->memory_size & (PAGE_SIZE - 1))
2499 goto out;
2500 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
2501 goto out;
2502 if (alias->slot >= KVM_ALIAS_SLOTS)
2503 goto out;
2504 if (alias->guest_phys_addr + alias->memory_size
2505 < alias->guest_phys_addr)
2506 goto out;
2507 if (alias->target_phys_addr + alias->memory_size
2508 < alias->target_phys_addr)
2509 goto out;
2510
a983fb23
MT		 2511 r = -ENOMEM;
2512 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2513 if (!aliases)
2514 goto out;
2515
79fac95e 2516 mutex_lock(&kvm->slots_lock);
1fe779f8 2517
a983fb23
MT		 2518 /* invalidate any gfn reference in case of deletion/shrinking */
2519 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
2520 aliases->aliases[alias->slot].flags |= KVM_ALIAS_INVALID;
2521 old_aliases = kvm->arch.aliases;
2522 rcu_assign_pointer(kvm->arch.aliases, aliases);
2523 synchronize_srcu_expedited(&kvm->srcu);
2524 kvm_mmu_zap_all(kvm);
2525 kfree(old_aliases);
2526
2527 r = -ENOMEM;
2528 aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
2529 if (!aliases)
2530 goto out_unlock;
2531
2532 memcpy(aliases, kvm->arch.aliases, sizeof(struct kvm_mem_aliases));
fef9cce0
MT		 2533
2534 p = &aliases->aliases[alias->slot];
1fe779f8
CO		 2535 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
2536 p->npages = alias->memory_size >> PAGE_SHIFT;
2537 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
a983fb23 2538 p->flags &= ~(KVM_ALIAS_INVALID);
1fe779f8
CO		 2539
2540 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
fef9cce0 2541 if (aliases->aliases[n - 1].npages)
1fe779f8 2542 break;
fef9cce0 2543 aliases->naliases = n;
1fe779f8 2544
a983fb23
MT		 2545 old_aliases = kvm->arch.aliases;
2546 rcu_assign_pointer(kvm->arch.aliases, aliases);
2547 synchronize_srcu_expedited(&kvm->srcu);
2548 kfree(old_aliases);
2549 r = 0;
1fe779f8 2550
a983fb23 2551out_unlock:
79fac95e 2552 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2553out:
2554 return r;
2555}
2556
2557static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2558{
2559 int r;
2560
2561 r = 0;
2562 switch (chip->chip_id) {
2563 case KVM_IRQCHIP_PIC_MASTER:
2564 memcpy(&chip->chip.pic,
2565 &pic_irqchip(kvm)->pics[0],
2566 sizeof(struct kvm_pic_state));
2567 break;
2568 case KVM_IRQCHIP_PIC_SLAVE:
2569 memcpy(&chip->chip.pic,
2570 &pic_irqchip(kvm)->pics[1],
2571 sizeof(struct kvm_pic_state));
2572 break;
2573 case KVM_IRQCHIP_IOAPIC:
eba0226b 2574 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2575 break;
2576 default:
2577 r = -EINVAL;
2578 break;
2579 }
2580 return r;
2581}
2582
2583static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2584{
2585 int r;
2586
2587 r = 0;
2588 switch (chip->chip_id) {
2589 case KVM_IRQCHIP_PIC_MASTER:
fa8273e9 2590 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2591 memcpy(&pic_irqchip(kvm)->pics[0],
2592 &chip->chip.pic,
2593 sizeof(struct kvm_pic_state));
fa8273e9 2594 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2595 break;
2596 case KVM_IRQCHIP_PIC_SLAVE:
fa8273e9 2597 raw_spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2598 memcpy(&pic_irqchip(kvm)->pics[1],
2599 &chip->chip.pic,
2600 sizeof(struct kvm_pic_state));
fa8273e9 2601 raw_spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2602 break;
2603 case KVM_IRQCHIP_IOAPIC:
eba0226b 2604 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2605 break;
2606 default:
2607 r = -EINVAL;
2608 break;
2609 }
2610 kvm_pic_update_irq(pic_irqchip(kvm));
2611 return r;
2612}
2613
e0f63cb9
SY		 2614static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2615{
2616 int r = 0;
2617
894a9c55 2618 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2619 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2620 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2621 return r;
2622}
2623
2624static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2625{
2626 int r = 0;
2627
894a9c55 2628 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2629 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2630 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2631 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2632 return r;
2633}
2634
2635static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2636{
2637 int r = 0;
2638
2639 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2640 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2641 sizeof(ps->channels));
2642 ps->flags = kvm->arch.vpit->pit_state.flags;
2643 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2644 return r;
2645}
2646
2647static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2648{
2649 int r = 0, start = 0;
2650 u32 prev_legacy, cur_legacy;
2651 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2652 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2653 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2654 if (!prev_legacy && cur_legacy)
2655 start = 1;
2656 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2657 sizeof(kvm->arch.vpit->pit_state.channels));
2658 kvm->arch.vpit->pit_state.flags = ps->flags;
2659 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2660 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2661 return r;
2662}
2663
52d939a0
MT		 2664static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2665 struct kvm_reinject_control *control)
2666{
2667 if (!kvm->arch.vpit)
2668 return -ENXIO;
894a9c55 2669 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2670 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2671 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2672 return 0;
2673}
2674
5bb064dc
ZX		 2675/*
2676 * Get (and clear) the dirty memory log for a memory slot.
2677 */
2678int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2679 struct kvm_dirty_log *log)
2680{
87bf6e7d 2681 int r, i;
5bb064dc 2682 struct kvm_memory_slot *memslot;
87bf6e7d 2683 unsigned long n;
b050b015
MT		 2684 unsigned long is_dirty = 0;
2685 unsigned long *dirty_bitmap = NULL;
5bb064dc 2686
79fac95e 2687 mutex_lock(&kvm->slots_lock);
5bb064dc 2688
b050b015
MT		 2689 r = -EINVAL;
2690 if (log->slot >= KVM_MEMORY_SLOTS)
2691 goto out;
2692
2693 memslot = &kvm->memslots->memslots[log->slot];
2694 r = -ENOENT;
2695 if (!memslot->dirty_bitmap)
2696 goto out;
2697
87bf6e7d 2698 n = kvm_dirty_bitmap_bytes(memslot);
b050b015
MT		 2699
2700 r = -ENOMEM;
2701 dirty_bitmap = vmalloc(n);
2702 if (!dirty_bitmap)
5bb064dc 2703 goto out;
b050b015
MT		 2704 memset(dirty_bitmap, 0, n);
2705
2706 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
2707 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 2708
2709 /* If nothing is dirty, don't bother messing with page tables. */
2710 if (is_dirty) {
b050b015
MT		 2711 struct kvm_memslots *slots, *old_slots;
2712
7c8a83b7 2713 spin_lock(&kvm->mmu_lock);
5bb064dc 2714 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2715 spin_unlock(&kvm->mmu_lock);
b050b015
MT		 2716
2717 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
2718 if (!slots)
2719 goto out_free;
2720
2721 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
2722 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
2723
2724 old_slots = kvm->memslots;
2725 rcu_assign_pointer(kvm->memslots, slots);
2726 synchronize_srcu_expedited(&kvm->srcu);
2727 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
2728 kfree(old_slots);
5bb064dc 2729 }
b050b015 2730
5bb064dc 2731 r = 0;
b050b015
MT		 2732 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
2733 r = -EFAULT;
2734out_free:
2735 vfree(dirty_bitmap);
5bb064dc 2736out:
79fac95e 2737 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 2738 return r;
2739}
2740
1fe779f8
CO		 2741long kvm_arch_vm_ioctl(struct file *filp,
2742 unsigned int ioctl, unsigned long arg)
2743{
2744 struct kvm *kvm = filp->private_data;
2745 void __user *argp = (void __user *)arg;
367e1319 2746 int r = -ENOTTY;
f0d66275
DH		 2747 /*
2748 * This union makes it completely explicit to gcc-3.x
2749 * that these two variables' stack usage should be
2750 * combined, not added together.
2751 */
2752 union {
2753 struct kvm_pit_state ps;
e9f42757 2754 struct kvm_pit_state2 ps2;
f0d66275 2755 struct kvm_memory_alias alias;
c5ff41ce 2756 struct kvm_pit_config pit_config;
f0d66275 2757 } u;
1fe779f8
CO		 2758
2759 switch (ioctl) {
2760 case KVM_SET_TSS_ADDR:
2761 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2762 if (r < 0)
2763 goto out;
2764 break;
b927a3ce
SY		 2765 case KVM_SET_IDENTITY_MAP_ADDR: {
2766 u64 ident_addr;
2767
2768 r = -EFAULT;
2769 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
2770 goto out;
2771 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
2772 if (r < 0)
2773 goto out;
2774 break;
2775 }
1fe779f8
CO		 2776 case KVM_SET_MEMORY_REGION: {
2777 struct kvm_memory_region kvm_mem;
2778 struct kvm_userspace_memory_region kvm_userspace_mem;
2779
2780 r = -EFAULT;
2781 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2782 goto out;
2783 kvm_userspace_mem.slot = kvm_mem.slot;
2784 kvm_userspace_mem.flags = kvm_mem.flags;
2785 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2786 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2787 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2788 if (r)
2789 goto out;
2790 break;
2791 }
2792 case KVM_SET_NR_MMU_PAGES:
2793 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2794 if (r)
2795 goto out;
2796 break;
2797 case KVM_GET_NR_MMU_PAGES:
2798 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2799 break;
f0d66275 2800 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2801 r = -EFAULT;
f0d66275 2802 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2803 goto out;
f0d66275 2804 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2805 if (r)
2806 goto out;
2807 break;
3ddea128
MT		 2808 case KVM_CREATE_IRQCHIP: {
2809 struct kvm_pic *vpic;
2810
2811 mutex_lock(&kvm->lock);
2812 r = -EEXIST;
2813 if (kvm->arch.vpic)
2814 goto create_irqchip_unlock;
1fe779f8 2815 r = -ENOMEM;
3ddea128
MT		 2816 vpic = kvm_create_pic(kvm);
2817 if (vpic) {
1fe779f8
CO		 2818 r = kvm_ioapic_init(kvm);
2819 if (r) {
72bb2fcd
WY		 2820 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
2821 &vpic->dev);
3ddea128
MT		 2822 kfree(vpic);
2823 goto create_irqchip_unlock;
1fe779f8
CO		 2824 }
2825 } else
3ddea128
MT		 2826 goto create_irqchip_unlock;
2827 smp_wmb();
2828 kvm->arch.vpic = vpic;
2829 smp_wmb();
399ec807
AK		 2830 r = kvm_setup_default_irq_routing(kvm);
2831 if (r) {
3ddea128 2832 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 2833 kvm_ioapic_destroy(kvm);
2834 kvm_destroy_pic(kvm);
3ddea128 2835 mutex_unlock(&kvm->irq_lock);
399ec807 2836 }
3ddea128
MT		 2837 create_irqchip_unlock:
2838 mutex_unlock(&kvm->lock);
1fe779f8 2839 break;
3ddea128 2840 }
7837699f 2841 case KVM_CREATE_PIT:
c5ff41ce
JK		 2842 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2843 goto create_pit;
2844 case KVM_CREATE_PIT2:
2845 r = -EFAULT;
2846 if (copy_from_user(&u.pit_config, argp,
2847 sizeof(struct kvm_pit_config)))
2848 goto out;
2849 create_pit:
79fac95e 2850 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 2851 r = -EEXIST;
2852 if (kvm->arch.vpit)
2853 goto create_pit_unlock;
7837699f 2854 r = -ENOMEM;
c5ff41ce 2855 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2856 if (kvm->arch.vpit)
2857 r = 0;
269e05e4 2858 create_pit_unlock:
79fac95e 2859 mutex_unlock(&kvm->slots_lock);
7837699f 2860 break;
4925663a 2861 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2862 case KVM_IRQ_LINE: {
2863 struct kvm_irq_level irq_event;
2864
2865 r = -EFAULT;
2866 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2867 goto out;
2868 if (irqchip_in_kernel(kvm)) {
4925663a 2869 __s32 status;
4925663a
GN		 2870 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2871 irq_event.irq, irq_event.level);
4925663a
GN		 2872 if (ioctl == KVM_IRQ_LINE_STATUS) {
2873 irq_event.status = status;
2874 if (copy_to_user(argp, &irq_event,
2875 sizeof irq_event))
2876 goto out;
2877 }
1fe779f8
CO		 2878 r = 0;
2879 }
2880 break;
2881 }
2882 case KVM_GET_IRQCHIP: {
2883 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2884 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2885
f0d66275
DH		 2886 r = -ENOMEM;
2887 if (!chip)
1fe779f8 2888 goto out;
f0d66275
DH		 2889 r = -EFAULT;
2890 if (copy_from_user(chip, argp, sizeof *chip))
2891 goto get_irqchip_out;
1fe779f8
CO		 2892 r = -ENXIO;
2893 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2894 goto get_irqchip_out;
2895 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2896 if (r)
f0d66275 2897 goto get_irqchip_out;
1fe779f8 2898 r = -EFAULT;
f0d66275
DH		 2899 if (copy_to_user(argp, chip, sizeof *chip))
2900 goto get_irqchip_out;
1fe779f8 2901 r = 0;
f0d66275
DH		 2902 get_irqchip_out:
2903 kfree(chip);
2904 if (r)
2905 goto out;
1fe779f8
CO		 2906 break;
2907 }
2908 case KVM_SET_IRQCHIP: {
2909 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2910 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2911
f0d66275
DH		 2912 r = -ENOMEM;
2913 if (!chip)
1fe779f8 2914 goto out;
f0d66275
DH		 2915 r = -EFAULT;
2916 if (copy_from_user(chip, argp, sizeof *chip))
2917 goto set_irqchip_out;
1fe779f8
CO		 2918 r = -ENXIO;
2919 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2920 goto set_irqchip_out;
2921 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2922 if (r)
f0d66275 2923 goto set_irqchip_out;
1fe779f8 2924 r = 0;
f0d66275
DH		 2925 set_irqchip_out:
2926 kfree(chip);
2927 if (r)
2928 goto out;
1fe779f8
CO		 2929 break;
2930 }
e0f63cb9 2931 case KVM_GET_PIT: {
e0f63cb9 2932 r = -EFAULT;
f0d66275 2933 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2934 goto out;
2935 r = -ENXIO;
2936 if (!kvm->arch.vpit)
2937 goto out;
f0d66275 2938 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2939 if (r)
2940 goto out;
2941 r = -EFAULT;
f0d66275 2942 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2943 goto out;
2944 r = 0;
2945 break;
2946 }
2947 case KVM_SET_PIT: {
e0f63cb9 2948 r = -EFAULT;
f0d66275 2949 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2950 goto out;
2951 r = -ENXIO;
2952 if (!kvm->arch.vpit)
2953 goto out;
f0d66275 2954 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2955 if (r)
2956 goto out;
2957 r = 0;
2958 break;
2959 }
e9f42757
BK		 2960 case KVM_GET_PIT2: {
2961 r = -ENXIO;
2962 if (!kvm->arch.vpit)
2963 goto out;
2964 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
2965 if (r)
2966 goto out;
2967 r = -EFAULT;
2968 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
2969 goto out;
2970 r = 0;
2971 break;
2972 }
2973 case KVM_SET_PIT2: {
2974 r = -EFAULT;
2975 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
2976 goto out;
2977 r = -ENXIO;
2978 if (!kvm->arch.vpit)
2979 goto out;
2980 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
2981 if (r)
2982 goto out;
2983 r = 0;
2984 break;
2985 }
52d939a0
MT		 2986 case KVM_REINJECT_CONTROL: {
2987 struct kvm_reinject_control control;
2988 r = -EFAULT;
2989 if (copy_from_user(&control, argp, sizeof(control)))
2990 goto out;
2991 r = kvm_vm_ioctl_reinject(kvm, &control);
2992 if (r)
2993 goto out;
2994 r = 0;
2995 break;
2996 }
ffde22ac
ES		 2997 case KVM_XEN_HVM_CONFIG: {
2998 r = -EFAULT;
2999 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3000 sizeof(struct kvm_xen_hvm_config)))
3001 goto out;
3002 r = -EINVAL;
3003 if (kvm->arch.xen_hvm_config.flags)
3004 goto out;
3005 r = 0;
3006 break;
3007 }
afbcf7ab
GC		 3008 case KVM_SET_CLOCK: {
3009 struct timespec now;
3010 struct kvm_clock_data user_ns;
3011 u64 now_ns;
3012 s64 delta;
3013
3014 r = -EFAULT;
3015 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3016 goto out;
3017
3018 r = -EINVAL;
3019 if (user_ns.flags)
3020 goto out;
3021
3022 r = 0;
3023 ktime_get_ts(&now);
3024 now_ns = timespec_to_ns(&now);
3025 delta = user_ns.clock - now_ns;
3026 kvm->arch.kvmclock_offset = delta;
3027 break;
3028 }
3029 case KVM_GET_CLOCK: {
3030 struct timespec now;
3031 struct kvm_clock_data user_ns;
3032 u64 now_ns;
3033
3034 ktime_get_ts(&now);
3035 now_ns = timespec_to_ns(&now);
3036 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3037 user_ns.flags = 0;
3038
3039 r = -EFAULT;
3040 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3041 goto out;
3042 r = 0;
3043 break;
3044 }
3045
1fe779f8
CO		 3046 default:
3047 ;
3048 }
3049out:
3050 return r;
3051}
3052
a16b043c 3053static void kvm_init_msr_list(void)
043405e1
CO		 3054{
3055 u32 dummy[2];
3056 unsigned i, j;
3057
e3267cbb
GC		 3058 /* skip the first msrs in the list. KVM-specific */
3059 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3060 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3061 continue;
3062 if (j < i)
3063 msrs_to_save[j] = msrs_to_save[i];
3064 j++;
3065 }
3066 num_msrs_to_save = j;
3067}
3068
bda9020e
MT		 3069static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3070 const void *v)
bbd9b64e 3071{
bda9020e
MT		 3072 if (vcpu->arch.apic &&
3073 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
3074 return 0;
bbd9b64e 3075
e93f8a0f 3076 return kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3077}
3078
bda9020e 3079static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3080{
bda9020e
MT		 3081 if (vcpu->arch.apic &&
3082 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
3083 return 0;
bbd9b64e 3084
e93f8a0f 3085 return kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, len, v);
bbd9b64e
CO		 3086}
3087
1871c602
GN		 3088gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3089{
3090 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3091 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3092}
3093
3094 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3095{
3096 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3097 access |= PFERR_FETCH_MASK;
3098 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3099}
3100
3101gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3102{
3103 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3104 access |= PFERR_WRITE_MASK;
3105 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, access, error);
3106}
3107
3108/* uses this to access any guest's mapped memory without checking CPL */
3109gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva, u32 *error)
3110{
3111 return vcpu->arch.mmu.gva_to_gpa(vcpu, gva, 0, error);
3112}
3113
3114static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3115 struct kvm_vcpu *vcpu, u32 access,
3116 u32 *error)
bbd9b64e
CO		 3117{
3118 void *data = val;
10589a46 3119 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3120
3121 while (bytes) {
1871c602 3122 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr, access, error);
bbd9b64e 3123 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3124 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3125 int ret;
3126
10589a46
MT		 3127 if (gpa == UNMAPPED_GVA) {
3128 r = X86EMUL_PROPAGATE_FAULT;
3129 goto out;
3130 }
77c2002e 3131 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 3132 if (ret < 0) {
3133 r = X86EMUL_UNHANDLEABLE;
3134 goto out;
3135 }
bbd9b64e 3136
77c2002e
IE		 3137 bytes -= toread;
3138 data += toread;
3139 addr += toread;
bbd9b64e 3140 }
10589a46 3141out:
10589a46 3142 return r;
bbd9b64e 3143}
77c2002e 3144
1871c602
GN		 3145/* used for instruction fetching */
3146static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
3147 struct kvm_vcpu *vcpu, u32 *error)
3148{
3149 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3150 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3151 access | PFERR_FETCH_MASK, error);
3152}
3153
3154static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
3155 struct kvm_vcpu *vcpu, u32 *error)
3156{
3157 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3158 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
3159 error);
3160}
3161
3162static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
3163 struct kvm_vcpu *vcpu, u32 *error)
3164{
3165 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, error);
3166}
3167
cded19f3 3168static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
1871c602 3169 struct kvm_vcpu *vcpu, u32 *error)
77c2002e
IE		 3170{
3171 void *data = val;
3172 int r = X86EMUL_CONTINUE;
3173
3174 while (bytes) {
1871c602 3175 gpa_t gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, error);
77c2002e
IE		 3176 unsigned offset = addr & (PAGE_SIZE-1);
3177 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3178 int ret;
3179
3180 if (gpa == UNMAPPED_GVA) {
3181 r = X86EMUL_PROPAGATE_FAULT;
3182 goto out;
3183 }
3184 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3185 if (ret < 0) {
3186 r = X86EMUL_UNHANDLEABLE;
3187 goto out;
3188 }
3189
3190 bytes -= towrite;
3191 data += towrite;
3192 addr += towrite;
3193 }
3194out:
3195 return r;
3196}
3197
bbd9b64e 3198
bbd9b64e
CO		 3199static int emulator_read_emulated(unsigned long addr,
3200 void *val,
3201 unsigned int bytes,
3202 struct kvm_vcpu *vcpu)
3203{
bbd9b64e 3204 gpa_t gpa;
1871c602 3205 u32 error_code;
bbd9b64e
CO		 3206
3207 if (vcpu->mmio_read_completed) {
3208 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3209 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3210 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3211 vcpu->mmio_read_completed = 0;
3212 return X86EMUL_CONTINUE;
3213 }
3214
1871c602
GN		 3215 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, &error_code);
3216
3217 if (gpa == UNMAPPED_GVA) {
3218 kvm_inject_page_fault(vcpu, addr, error_code);
3219 return X86EMUL_PROPAGATE_FAULT;
3220 }
bbd9b64e
CO		 3221
3222 /* For APIC access vmexit */
3223 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3224 goto mmio;
3225
1871c602 3226 if (kvm_read_guest_virt(addr, val, bytes, vcpu, NULL)
77c2002e 3227 == X86EMUL_CONTINUE)
bbd9b64e 3228 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3229
3230mmio:
3231 /*
3232 * Is this MMIO handled locally?
3233 */
aec51dc4
AK		 3234 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
3235 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3236 return X86EMUL_CONTINUE;
3237 }
aec51dc4
AK		 3238
3239 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3240
3241 vcpu->mmio_needed = 1;
3242 vcpu->mmio_phys_addr = gpa;
3243 vcpu->mmio_size = bytes;
3244 vcpu->mmio_is_write = 0;
3245
3246 return X86EMUL_UNHANDLEABLE;
3247}
3248
3200f405 3249int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 3250 const void *val, int bytes)
bbd9b64e
CO		 3251{
3252 int ret;
3253
3254 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3255 if (ret < 0)
bbd9b64e 3256 return 0;
ad218f85 3257 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3258 return 1;
3259}
3260
3261static int emulator_write_emulated_onepage(unsigned long addr,
3262 const void *val,
3263 unsigned int bytes,
3264 struct kvm_vcpu *vcpu)
3265{
10589a46 3266 gpa_t gpa;
1871c602 3267 u32 error_code;
10589a46 3268
1871c602 3269 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, &error_code);
bbd9b64e
CO		 3270
3271 if (gpa == UNMAPPED_GVA) {
1871c602 3272 kvm_inject_page_fault(vcpu, addr, error_code);
bbd9b64e
CO		 3273 return X86EMUL_PROPAGATE_FAULT;
3274 }
3275
3276 /* For APIC access vmexit */
3277 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3278 goto mmio;
3279
3280 if (emulator_write_phys(vcpu, gpa, val, bytes))
3281 return X86EMUL_CONTINUE;
3282
3283mmio:
aec51dc4 3284 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3285 /*
3286 * Is this MMIO handled locally?
3287 */
bda9020e 3288 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 3289 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3290
3291 vcpu->mmio_needed = 1;
3292 vcpu->mmio_phys_addr = gpa;
3293 vcpu->mmio_size = bytes;
3294 vcpu->mmio_is_write = 1;
3295 memcpy(vcpu->mmio_data, val, bytes);
3296
3297 return X86EMUL_CONTINUE;
3298}
3299
3300int emulator_write_emulated(unsigned long addr,
3301 const void *val,
3302 unsigned int bytes,
3303 struct kvm_vcpu *vcpu)
3304{
3305 /* Crossing a page boundary? */
3306 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3307 int rc, now;
3308
3309 now = -addr & ~PAGE_MASK;
3310 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
3311 if (rc != X86EMUL_CONTINUE)
3312 return rc;
3313 addr += now;
3314 val += now;
3315 bytes -= now;
3316 }
3317 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
3318}
3319EXPORT_SYMBOL_GPL(emulator_write_emulated);
3320
3321static int emulator_cmpxchg_emulated(unsigned long addr,
3322 const void *old,
3323 const void *new,
3324 unsigned int bytes,
3325 struct kvm_vcpu *vcpu)
3326{
9f51e24e 3327 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c
MT		 3328#ifndef CONFIG_X86_64
3329 /* guests cmpxchg8b have to be emulated atomically */
3330 if (bytes == 8) {
10589a46 3331 gpa_t gpa;
2bacc55c 3332 struct page *page;
c0b49b0d 3333 char *kaddr;
2bacc55c
MT		 3334 u64 val;
3335
1871c602 3336 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
10589a46 3337
2bacc55c
MT		 3338 if (gpa == UNMAPPED_GVA ||
3339 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3340 goto emul_write;
3341
3342 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3343 goto emul_write;
3344
3345 val = *(u64 *)new;
72dc67a6 3346
2bacc55c 3347 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 3348
c0b49b0d
AM		 3349 kaddr = kmap_atomic(page, KM_USER0);
3350 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
3351 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 3352 kvm_release_page_dirty(page);
3353 }
3200f405 3354emul_write:
2bacc55c
MT		 3355#endif
3356
bbd9b64e
CO		 3357 return emulator_write_emulated(addr, new, bytes, vcpu);
3358}
3359
3360static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3361{
3362 return kvm_x86_ops->get_segment_base(vcpu, seg);
3363}
3364
3365int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
3366{
a7052897 3367 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 3368 return X86EMUL_CONTINUE;
3369}
3370
3371int emulate_clts(struct kvm_vcpu *vcpu)
3372{
4d4ec087 3373 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 3374 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 3375 return X86EMUL_CONTINUE;
3376}
3377
3378int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
3379{
c76de350 3380 return kvm_x86_ops->get_dr(ctxt->vcpu, dr, dest);
bbd9b64e
CO		 3381}
3382
3383int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
3384{
3385 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
bbd9b64e 3386
c76de350 3387 return kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask);
bbd9b64e
CO		 3388}
3389
3390void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
3391{
bbd9b64e 3392 u8 opcodes[4];
5fdbf976 3393 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 3394 unsigned long rip_linear;
3395
f76c710d 3396 if (!printk_ratelimit())
bbd9b64e
CO		 3397 return;
3398
25be4608
GC		 3399 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
3400
1871c602 3401 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu, NULL);
bbd9b64e
CO		 3402
3403 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
3404 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 3405}
3406EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
3407
14af3f3c 3408static struct x86_emulate_ops emulate_ops = {
1871c602
GN		 3409 .read_std = kvm_read_guest_virt_system,
3410 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 3411 .read_emulated = emulator_read_emulated,
3412 .write_emulated = emulator_write_emulated,
3413 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3414};
3415
5fdbf976
MT		 3416static void cache_all_regs(struct kvm_vcpu *vcpu)
3417{
3418 kvm_register_read(vcpu, VCPU_REGS_RAX);
3419 kvm_register_read(vcpu, VCPU_REGS_RSP);
3420 kvm_register_read(vcpu, VCPU_REGS_RIP);
3421 vcpu->arch.regs_dirty = ~0;
3422}
3423
bbd9b64e 3424int emulate_instruction(struct kvm_vcpu *vcpu,
bbd9b64e
CO		 3425 unsigned long cr2,
3426 u16 error_code,
571008da 3427 int emulation_type)
bbd9b64e 3428{
310b5d30 3429 int r, shadow_mask;
571008da 3430 struct decode_cache *c;
851ba692 3431 struct kvm_run *run = vcpu->run;
bbd9b64e 3432
26eef70c 3433 kvm_clear_exception_queue(vcpu);
ad312c7c 3434 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 3435 /*
56e82318 3436 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 3437 * instead of direct ->regs accesses, can save hundred cycles
3438 * on Intel for instructions that don't read/change RSP, for
3439 * for example.
3440 */
3441 cache_all_regs(vcpu);
bbd9b64e
CO		 3442
3443 vcpu->mmio_is_write = 0;
ad312c7c 3444 vcpu->arch.pio.string = 0;
bbd9b64e 3445
571008da 3446 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 3447 int cs_db, cs_l;
3448 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3449
ad312c7c 3450 vcpu->arch.emulate_ctxt.vcpu = vcpu;
83bf0002 3451 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
ad312c7c 3452 vcpu->arch.emulate_ctxt.mode =
a0044755 3453 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
ad312c7c 3454 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
a0044755 3455 ? X86EMUL_MODE_VM86 : cs_l
bbd9b64e
CO		 3456 ? X86EMUL_MODE_PROT64 : cs_db
3457 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
3458
ad312c7c 3459 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 3460
0cb5762e
AP		 3461 /* Only allow emulation of specific instructions on #UD
3462 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 3463 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 3464 if (emulation_type & EMULTYPE_TRAP_UD) {
3465 if (!c->twobyte)
3466 return EMULATE_FAIL;
3467 switch (c->b) {
3468 case 0x01: /* VMMCALL */
3469 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3470 return EMULATE_FAIL;
3471 break;
3472 case 0x34: /* sysenter */
3473 case 0x35: /* sysexit */
3474 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3475 return EMULATE_FAIL;
3476 break;
3477 case 0x05: /* syscall */
3478 if (c->modrm_mod != 0 || c->modrm_rm != 0)
3479 return EMULATE_FAIL;
3480 break;
3481 default:
3482 return EMULATE_FAIL;
3483 }
3484
3485 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
3486 return EMULATE_FAIL;
3487 }
571008da 3488
f2b5756b 3489 ++vcpu->stat.insn_emulation;
bbd9b64e 3490 if (r) {
f2b5756b 3491 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 3492 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3493 return EMULATE_DONE;
3494 return EMULATE_FAIL;
3495 }
3496 }
3497
ba8afb6b
GN		 3498 if (emulation_type & EMULTYPE_SKIP) {
3499 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
3500 return EMULATE_DONE;
3501 }
3502
ad312c7c 3503 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 3504 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
3505
3506 if (r == 0)
3507 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 3508
ad312c7c 3509 if (vcpu->arch.pio.string)
bbd9b64e
CO		 3510 return EMULATE_DO_MMIO;
3511
112592da 3512 if (r || vcpu->mmio_is_write) {
bbd9b64e
CO		 3513 run->exit_reason = KVM_EXIT_MMIO;
3514 run->mmio.phys_addr = vcpu->mmio_phys_addr;
3515 memcpy(run->mmio.data, vcpu->mmio_data, 8);
3516 run->mmio.len = vcpu->mmio_size;
3517 run->mmio.is_write = vcpu->mmio_is_write;
3518 }
3519
3520 if (r) {
3521 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
3522 return EMULATE_DONE;
3523 if (!vcpu->mmio_needed) {
3524 kvm_report_emulation_failure(vcpu, "mmio");
3525 return EMULATE_FAIL;
3526 }
3527 return EMULATE_DO_MMIO;
3528 }
3529
83bf0002 3530 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 3531
3532 if (vcpu->mmio_is_write) {
3533 vcpu->mmio_needed = 0;
3534 return EMULATE_DO_MMIO;
3535 }
3536
3537 return EMULATE_DONE;
3538}
3539EXPORT_SYMBOL_GPL(emulate_instruction);
3540
de7d789a
CO		 3541static int pio_copy_data(struct kvm_vcpu *vcpu)
3542{
ad312c7c 3543 void *p = vcpu->arch.pio_data;
0f346074 3544 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 3545 unsigned bytes;
0f346074 3546 int ret;
1871c602 3547 u32 error_code;
de7d789a 3548
ad312c7c
ZX		 3549 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
3550 if (vcpu->arch.pio.in)
1871c602 3551 ret = kvm_write_guest_virt(q, p, bytes, vcpu, &error_code);
de7d789a 3552 else
1871c602
GN		 3553 ret = kvm_read_guest_virt(q, p, bytes, vcpu, &error_code);
3554
3555 if (ret == X86EMUL_PROPAGATE_FAULT)
3556 kvm_inject_page_fault(vcpu, q, error_code);
3557
0f346074 3558 return ret;
de7d789a
CO		 3559}
3560
3561int complete_pio(struct kvm_vcpu *vcpu)
3562{
ad312c7c 3563 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 3564 long delta;
3565 int r;
5fdbf976 3566 unsigned long val;
de7d789a
CO		 3567
3568 if (!io->string) {
5fdbf976
MT		 3569 if (io->in) {
3570 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3571 memcpy(&val, vcpu->arch.pio_data, io->size);
3572 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
3573 }
de7d789a
CO		 3574 } else {
3575 if (io->in) {
3576 r = pio_copy_data(vcpu);
5fdbf976 3577 if (r)
1871c602 3578 goto out;
de7d789a
CO		 3579 }
3580
3581 delta = 1;
3582 if (io->rep) {
3583 delta *= io->cur_count;
3584 /*
3585 * The size of the register should really depend on
3586 * current address size.
3587 */
5fdbf976
MT		 3588 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
3589 val -= delta;
3590 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 3591 }
3592 if (io->down)
3593 delta = -delta;
3594 delta *= io->size;
5fdbf976
MT		 3595 if (io->in) {
3596 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
3597 val += delta;
3598 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
3599 } else {
3600 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
3601 val += delta;
3602 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
3603 }
de7d789a 3604 }
1871c602 3605out:
de7d789a
CO		 3606 io->count -= io->cur_count;
3607 io->cur_count = 0;
3608
3609 return 0;
3610}
3611
bda9020e 3612static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 3613{
3614 /* TODO: String I/O for in kernel device */
bda9020e 3615 int r;
de7d789a 3616
ad312c7c 3617 if (vcpu->arch.pio.in)
e93f8a0f 3618 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
bda9020e 3619 vcpu->arch.pio.size, pd);
de7d789a 3620 else
e93f8a0f
MT		 3621 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3622 vcpu->arch.pio.port, vcpu->arch.pio.size,
3623 pd);
bda9020e 3624 return r;
de7d789a
CO		 3625}
3626
bda9020e 3627static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 3628{
ad312c7c
ZX		 3629 struct kvm_pio_request *io = &vcpu->arch.pio;
3630 void *pd = vcpu->arch.pio_data;
bda9020e 3631 int i, r = 0;
de7d789a 3632
de7d789a 3633 for (i = 0; i < io->cur_count; i++) {
e93f8a0f 3634 if (kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
bda9020e
MT		 3635 io->port, io->size, pd)) {
3636 r = -EOPNOTSUPP;
3637 break;
3638 }
de7d789a
CO		 3639 pd += io->size;
3640 }
bda9020e 3641 return r;
de7d789a
CO		 3642}
3643
851ba692 3644int kvm_emulate_pio(struct kvm_vcpu *vcpu, int in, int size, unsigned port)
de7d789a 3645{
5fdbf976 3646 unsigned long val;
de7d789a 3647
f850e2e6
GN		 3648 trace_kvm_pio(!in, port, size, 1);
3649
de7d789a
CO		 3650 vcpu->run->exit_reason = KVM_EXIT_IO;
3651 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3652 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3653 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3654 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
3655 vcpu->run->io.port = vcpu->arch.pio.port = port;
3656 vcpu->arch.pio.in = in;
3657 vcpu->arch.pio.string = 0;
3658 vcpu->arch.pio.down = 0;
ad312c7c 3659 vcpu->arch.pio.rep = 0;
de7d789a 3660
1976d2d2
TY		 3661 if (!vcpu->arch.pio.in) {
3662 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
3663 memcpy(vcpu->arch.pio_data, &val, 4);
3664 }
de7d789a 3665
bda9020e 3666 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 3667 complete_pio(vcpu);
3668 return 1;
3669 }
3670 return 0;
3671}
3672EXPORT_SYMBOL_GPL(kvm_emulate_pio);
3673
851ba692 3674int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, int in,
de7d789a
CO		 3675 int size, unsigned long count, int down,
3676 gva_t address, int rep, unsigned port)
3677{
3678 unsigned now, in_page;
0f346074 3679 int ret = 0;
de7d789a 3680
f850e2e6
GN		 3681 trace_kvm_pio(!in, port, size, count);
3682
de7d789a
CO		 3683 vcpu->run->exit_reason = KVM_EXIT_IO;
3684 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 3685 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 3686 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 3687 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
3688 vcpu->run->io.port = vcpu->arch.pio.port = port;
3689 vcpu->arch.pio.in = in;
3690 vcpu->arch.pio.string = 1;
3691 vcpu->arch.pio.down = down;
ad312c7c 3692 vcpu->arch.pio.rep = rep;
de7d789a
CO		 3693
3694 if (!count) {
3695 kvm_x86_ops->skip_emulated_instruction(vcpu);
3696 return 1;
3697 }
3698
3699 if (!down)
3700 in_page = PAGE_SIZE - offset_in_page(address);
3701 else
3702 in_page = offset_in_page(address) + size;
3703 now = min(count, (unsigned long)in_page / size);
0f346074 3704 if (!now)
de7d789a 3705 now = 1;
de7d789a
CO		 3706 if (down) {
3707 /*
3708 * String I/O in reverse. Yuck. Kill the guest, fix later.
3709 */
3710 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 3711 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 3712 return 1;
3713 }
3714 vcpu->run->io.count = now;
ad312c7c 3715 vcpu->arch.pio.cur_count = now;
de7d789a 3716
ad312c7c 3717 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 3718 kvm_x86_ops->skip_emulated_instruction(vcpu);
3719
0f346074 3720 vcpu->arch.pio.guest_gva = address;
de7d789a 3721
ad312c7c 3722 if (!vcpu->arch.pio.in) {
de7d789a
CO		 3723 /* string PIO write */
3724 ret = pio_copy_data(vcpu);
1871c602 3725 if (ret == X86EMUL_PROPAGATE_FAULT)
0f346074 3726 return 1;
bda9020e 3727 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 3728 complete_pio(vcpu);
ad312c7c 3729 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 3730 ret = 1;
3731 }
bda9020e
MT		 3732 }
3733 /* no string PIO read support yet */
de7d789a
CO		 3734
3735 return ret;
3736}
3737EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
3738
c8076604
GH		 3739static void bounce_off(void *info)
3740{
3741 /* nothing */
3742}
3743
c8076604
GH		 3744static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
3745 void *data)
3746{
3747 struct cpufreq_freqs *freq = data;
3748 struct kvm *kvm;
3749 struct kvm_vcpu *vcpu;
3750 int i, send_ipi = 0;
3751
c8076604
GH		 3752 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
3753 return 0;
3754 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
3755 return 0;
0cca7907 3756 per_cpu(cpu_tsc_khz, freq->cpu) = freq->new;
c8076604
GH		 3757
3758 spin_lock(&kvm_lock);
3759 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 3760 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 3761 if (vcpu->cpu != freq->cpu)
3762 continue;
3763 if (!kvm_request_guest_time_update(vcpu))
3764 continue;
3765 if (vcpu->cpu != smp_processor_id())
3766 send_ipi++;
3767 }
3768 }
3769 spin_unlock(&kvm_lock);
3770
3771 if (freq->old < freq->new && send_ipi) {
3772 /*
3773 * We upscale the frequency. Must make the guest
3774 * doesn't see old kvmclock values while running with
3775 * the new frequency, otherwise we risk the guest sees
3776 * time go backwards.
3777 *
3778 * In case we update the frequency for another cpu
3779 * (which might be in guest context) send an interrupt
3780 * to kick the cpu out of guest context. Next time
3781 * guest context is entered kvmclock will be updated,
3782 * so the guest will not see stale values.
3783 */
3784 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3785 }
3786 return 0;
3787}
3788
3789static struct notifier_block kvmclock_cpufreq_notifier_block = {
3790 .notifier_call = kvmclock_cpufreq_notifier
3791};
3792
b820cc0c
ZA		 3793static void kvm_timer_init(void)
3794{
3795 int cpu;
3796
b820cc0c 3797 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
b820cc0c
ZA		 3798 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3799 CPUFREQ_TRANSITION_NOTIFIER);
6b7d7e76
ZA		 3800 for_each_online_cpu(cpu) {
3801 unsigned long khz = cpufreq_get(cpu);
3802 if (!khz)
3803 khz = tsc_khz;
3804 per_cpu(cpu_tsc_khz, cpu) = khz;
3805 }
0cca7907
ZA		 3806 } else {
3807 for_each_possible_cpu(cpu)
3808 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
b820cc0c
ZA		 3809 }
3810}
3811
f8c16bba 3812int kvm_arch_init(void *opaque)
043405e1 3813{
b820cc0c 3814 int r;
f8c16bba
ZX		 3815 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3816
f8c16bba
ZX		 3817 if (kvm_x86_ops) {
3818 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3819 r = -EEXIST;
3820 goto out;
f8c16bba
ZX		 3821 }
3822
3823 if (!ops->cpu_has_kvm_support()) {
3824 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3825 r = -EOPNOTSUPP;
3826 goto out;
f8c16bba
ZX		 3827 }
3828 if (ops->disabled_by_bios()) {
3829 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3830 r = -EOPNOTSUPP;
3831 goto out;
f8c16bba
ZX		 3832 }
3833
97db56ce
AK		 3834 r = kvm_mmu_module_init();
3835 if (r)
3836 goto out;
3837
3838 kvm_init_msr_list();
3839
f8c16bba 3840 kvm_x86_ops = ops;
56c6d28a 3841 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3842 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3843 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3844 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 3845
b820cc0c 3846 kvm_timer_init();
c8076604 3847
f8c16bba 3848 return 0;
56c6d28a
ZX		 3849
3850out:
56c6d28a 3851 return r;
043405e1 3852}
8776e519 3853
f8c16bba
ZX		 3854void kvm_arch_exit(void)
3855{
888d256e
JK		 3856 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3857 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3858 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3859 kvm_x86_ops = NULL;
56c6d28a
ZX		 3860 kvm_mmu_module_exit();
3861}
f8c16bba 3862
8776e519
HB		 3863int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3864{
3865 ++vcpu->stat.halt_exits;
3866 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3867 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3868 return 1;
3869 } else {
3870 vcpu->run->exit_reason = KVM_EXIT_HLT;
3871 return 0;
3872 }
3873}
3874EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3875
2f333bcb
MT		 3876static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3877 unsigned long a1)
3878{
3879 if (is_long_mode(vcpu))
3880 return a0;
3881 else
3882 return a0 | ((gpa_t)a1 << 32);
3883}
3884
55cd8e5a
GN		 3885int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
3886{
3887 u64 param, ingpa, outgpa, ret;
3888 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
3889 bool fast, longmode;
3890 int cs_db, cs_l;
3891
3892 /*
3893 * hypercall generates UD from non zero cpl and real mode
3894 * per HYPER-V spec
3895 */
3eeb3288 3896 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 3897 kvm_queue_exception(vcpu, UD_VECTOR);
3898 return 0;
3899 }
3900
3901 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
3902 longmode = is_long_mode(vcpu) && cs_l == 1;
3903
3904 if (!longmode) {
ccd46936
GN		 3905 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
3906 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
3907 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
3908 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
3909 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
3910 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 3911 }
3912#ifdef CONFIG_X86_64
3913 else {
3914 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
3915 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
3916 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
3917 }
3918#endif
3919
3920 code = param & 0xffff;
3921 fast = (param >> 16) & 0x1;
3922 rep_cnt = (param >> 32) & 0xfff;
3923 rep_idx = (param >> 48) & 0xfff;
3924
3925 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
3926
c25bc163
GN		 3927 switch (code) {
3928 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
3929 kvm_vcpu_on_spin(vcpu);
3930 break;
3931 default:
3932 res = HV_STATUS_INVALID_HYPERCALL_CODE;
3933 break;
3934 }
55cd8e5a
GN		 3935
3936 ret = res | (((u64)rep_done & 0xfff) << 32);
3937 if (longmode) {
3938 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
3939 } else {
3940 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
3941 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
3942 }
3943
3944 return 1;
3945}
3946
8776e519
HB		 3947int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3948{
3949 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3950 int r = 1;
8776e519 3951
55cd8e5a
GN		 3952 if (kvm_hv_hypercall_enabled(vcpu->kvm))
3953 return kvm_hv_hypercall(vcpu);
3954
5fdbf976
MT		 3955 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3956 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3957 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3958 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3959 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3960
229456fc 3961 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3962
8776e519
HB		 3963 if (!is_long_mode(vcpu)) {
3964 nr &= 0xFFFFFFFF;
3965 a0 &= 0xFFFFFFFF;
3966 a1 &= 0xFFFFFFFF;
3967 a2 &= 0xFFFFFFFF;
3968 a3 &= 0xFFFFFFFF;
3969 }
3970
07708c4a
JK		 3971 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
3972 ret = -KVM_EPERM;
3973 goto out;
3974 }
3975
8776e519 3976 switch (nr) {
b93463aa
AK		 3977 case KVM_HC_VAPIC_POLL_IRQ:
3978 ret = 0;
3979 break;
2f333bcb
MT		 3980 case KVM_HC_MMU_OP:
3981 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3982 break;
8776e519
HB		 3983 default:
3984 ret = -KVM_ENOSYS;
3985 break;
3986 }
07708c4a 3987out:
5fdbf976 3988 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3989 ++vcpu->stat.hypercalls;
2f333bcb 3990 return r;
8776e519
HB		 3991}
3992EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3993
3994int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3995{
3996 char instruction[3];
5fdbf976 3997 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3998
8776e519
HB		 3999 /*
4000 * Blow out the MMU to ensure that no other VCPU has an active mapping
4001 * to ensure that the updated hypercall appears atomically across all
4002 * VCPUs.
4003 */
4004 kvm_mmu_zap_all(vcpu->kvm);
4005
8776e519 4006 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4007
7edcface 4008 return emulator_write_emulated(rip, instruction, 3, vcpu);
8776e519
HB		 4009}
4010
4011static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4012{
4013 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4014}
4015
4016void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4017{
89a27f4d 4018 struct desc_ptr dt = { limit, base };
8776e519
HB		 4019
4020 kvm_x86_ops->set_gdt(vcpu, &dt);
4021}
4022
4023void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4024{
89a27f4d 4025 struct desc_ptr dt = { limit, base };
8776e519
HB		 4026
4027 kvm_x86_ops->set_idt(vcpu, &dt);
4028}
4029
4030void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
4031 unsigned long *rflags)
4032{
2d3ad1f4 4033 kvm_lmsw(vcpu, msw);
91586a3b 4034 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4035}
4036
4037unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
4038{
54e445ca
JR		 4039 unsigned long value;
4040
8776e519
HB		 4041 switch (cr) {
4042 case 0:
4d4ec087 4043 value = kvm_read_cr0(vcpu);
54e445ca 4044 break;
8776e519 4045 case 2:
54e445ca
JR		 4046 value = vcpu->arch.cr2;
4047 break;
8776e519 4048 case 3:
54e445ca
JR		 4049 value = vcpu->arch.cr3;
4050 break;
8776e519 4051 case 4:
fc78f519 4052 value = kvm_read_cr4(vcpu);
54e445ca 4053 break;
152ff9be 4054 case 8:
54e445ca
JR		 4055 value = kvm_get_cr8(vcpu);
4056 break;
8776e519 4057 default:
b8688d51 4058 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4059 return 0;
4060 }
54e445ca
JR		 4061
4062 return value;
8776e519
HB		 4063}
4064
4065void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
4066 unsigned long *rflags)
4067{
4068 switch (cr) {
4069 case 0:
4d4ec087 4070 kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
91586a3b 4071 *rflags = kvm_get_rflags(vcpu);
8776e519
HB		 4072 break;
4073 case 2:
ad312c7c 4074 vcpu->arch.cr2 = val;
8776e519
HB		 4075 break;
4076 case 3:
2d3ad1f4 4077 kvm_set_cr3(vcpu, val);
8776e519
HB		 4078 break;
4079 case 4:
fc78f519 4080 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8776e519 4081 break;
152ff9be 4082 case 8:
2d3ad1f4 4083 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 4084 break;
8776e519 4085 default:
b8688d51 4086 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 4087 }
4088}
4089
07716717
DK		 4090static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4091{
ad312c7c
ZX		 4092 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4093 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4094
4095 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4096 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4097 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4098 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4099 if (ej->function == e->function) {
4100 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4101 return j;
4102 }
4103 }
4104 return 0; /* silence gcc, even though control never reaches here */
4105}
4106
4107/* find an entry with matching function, matching index (if needed), and that
4108 * should be read next (if it's stateful) */
4109static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4110 u32 function, u32 index)
4111{
4112 if (e->function != function)
4113 return 0;
4114 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4115 return 0;
4116 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4117 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4118 return 0;
4119 return 1;
4120}
4121
d8017474
AG		 4122struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
4123 u32 function, u32 index)
8776e519
HB		 4124{
4125 int i;
d8017474 4126 struct kvm_cpuid_entry2 *best = NULL;
8776e519 4127
ad312c7c 4128 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 4129 struct kvm_cpuid_entry2 *e;
4130
ad312c7c 4131 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 4132 if (is_matching_cpuid_entry(e, function, index)) {
4133 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
4134 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 4135 best = e;
4136 break;
4137 }
4138 /*
4139 * Both basic or both extended?
4140 */
4141 if (((e->function ^ function) & 0x80000000) == 0)
4142 if (!best || e->function > best->function)
4143 best = e;
4144 }
d8017474
AG		 4145 return best;
4146}
0e851880 4147EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 4148
82725b20
DE		 4149int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
4150{
4151 struct kvm_cpuid_entry2 *best;
4152
4153 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
4154 if (best)
4155 return best->eax & 0xff;
4156 return 36;
4157}
4158
d8017474
AG		 4159void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
4160{
4161 u32 function, index;
4162 struct kvm_cpuid_entry2 *best;
4163
4164 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
4165 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4166 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
4167 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
4168 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
4169 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
4170 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 4171 if (best) {
5fdbf976
MT		 4172 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
4173 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
4174 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
4175 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 4176 }
8776e519 4177 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 4178 trace_kvm_cpuid(function,
4179 kvm_register_read(vcpu, VCPU_REGS_RAX),
4180 kvm_register_read(vcpu, VCPU_REGS_RBX),
4181 kvm_register_read(vcpu, VCPU_REGS_RCX),
4182 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 4183}
4184EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 4185
b6c7a5dc
HB		 4186/*
4187 * Check if userspace requested an interrupt window, and that the
4188 * interrupt window is open.
4189 *
4190 * No need to exit to userspace if we already have an interrupt queued.
4191 */
851ba692 4192static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4193{
8061823a 4194 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4195 vcpu->run->request_interrupt_window &&
5df56646 4196 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4197}
4198
851ba692 4199static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4200{
851ba692
AK		 4201 struct kvm_run *kvm_run = vcpu->run;
4202
91586a3b 4203 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4204 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4205 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4206 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4207 kvm_run->ready_for_interrupt_injection = 1;
4531220b 4208 else
b6c7a5dc 4209 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 4210 kvm_arch_interrupt_allowed(vcpu) &&
4211 !kvm_cpu_has_interrupt(vcpu) &&
4212 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 4213}
4214
b93463aa
AK		 4215static void vapic_enter(struct kvm_vcpu *vcpu)
4216{
4217 struct kvm_lapic *apic = vcpu->arch.apic;
4218 struct page *page;
4219
4220 if (!apic || !apic->vapic_addr)
4221 return;
4222
4223 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 4224
4225 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 4226}
4227
4228static void vapic_exit(struct kvm_vcpu *vcpu)
4229{
4230 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 4231 int idx;
b93463aa
AK		 4232
4233 if (!apic || !apic->vapic_addr)
4234 return;
4235
f656ce01 4236 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 4237 kvm_release_page_dirty(apic->vapic_page);
4238 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 4239 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 4240}
4241
95ba8273
GN		 4242static void update_cr8_intercept(struct kvm_vcpu *vcpu)
4243{
4244 int max_irr, tpr;
4245
4246 if (!kvm_x86_ops->update_cr8_intercept)
4247 return;
4248
88c808fd
AK		 4249 if (!vcpu->arch.apic)
4250 return;
4251
8db3baa2
GN		 4252 if (!vcpu->arch.apic->vapic_addr)
4253 max_irr = kvm_lapic_find_highest_irr(vcpu);
4254 else
4255 max_irr = -1;
95ba8273
GN		 4256
4257 if (max_irr != -1)
4258 max_irr >>= 4;
4259
4260 tpr = kvm_lapic_get_cr8(vcpu);
4261
4262 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
4263}
4264
851ba692 4265static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 4266{
4267 /* try to reinject previous events if any */
b59bb7bd
GN		 4268 if (vcpu->arch.exception.pending) {
4269 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
4270 vcpu->arch.exception.has_error_code,
4271 vcpu->arch.exception.error_code);
4272 return;
4273 }
4274
95ba8273
GN		 4275 if (vcpu->arch.nmi_injected) {
4276 kvm_x86_ops->set_nmi(vcpu);
4277 return;
4278 }
4279
4280 if (vcpu->arch.interrupt.pending) {
66fd3f7f 4281 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4282 return;
4283 }
4284
4285 /* try to inject new event if pending */
4286 if (vcpu->arch.nmi_pending) {
4287 if (kvm_x86_ops->nmi_allowed(vcpu)) {
4288 vcpu->arch.nmi_pending = false;
4289 vcpu->arch.nmi_injected = true;
4290 kvm_x86_ops->set_nmi(vcpu);
4291 }
4292 } else if (kvm_cpu_has_interrupt(vcpu)) {
4293 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 4294 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
4295 false);
4296 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 4297 }
4298 }
4299}
4300
851ba692 4301static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 4302{
4303 int r;
6a8b1d13 4304 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 4305 vcpu->run->request_interrupt_window;
b6c7a5dc 4306
2e53d63a
MT		 4307 if (vcpu->requests)
4308 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
4309 kvm_mmu_unload(vcpu);
4310
b6c7a5dc
HB		 4311 r = kvm_mmu_reload(vcpu);
4312 if (unlikely(r))
4313 goto out;
4314
2f52d58c
AK		 4315 if (vcpu->requests) {
4316 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 4317 __kvm_migrate_timers(vcpu);
c8076604
GH		 4318 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
4319 kvm_write_guest_time(vcpu);
4731d4c7
MT		 4320 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
4321 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 4322 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
4323 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 4324 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
4325 &vcpu->requests)) {
851ba692 4326 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 4327 r = 0;
4328 goto out;
4329 }
71c4dfaf 4330 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
851ba692 4331 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 4332 r = 0;
4333 goto out;
4334 }
02daab21
AK		 4335 if (test_and_clear_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests)) {
4336 vcpu->fpu_active = 0;
4337 kvm_x86_ops->fpu_deactivate(vcpu);
4338 }
2f52d58c 4339 }
b93463aa 4340
b6c7a5dc
HB		 4341 preempt_disable();
4342
4343 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 4344 if (vcpu->fpu_active)
4345 kvm_load_guest_fpu(vcpu);
b6c7a5dc
HB		 4346
4347 local_irq_disable();
4348
32f88400
MT		 4349 clear_bit(KVM_REQ_KICK, &vcpu->requests);
4350 smp_mb__after_clear_bit();
4351
d7690175 4352 if (vcpu->requests || need_resched() || signal_pending(current)) {
c7f0f24b 4353 set_bit(KVM_REQ_KICK, &vcpu->requests);
6c142801
AK		 4354 local_irq_enable();
4355 preempt_enable();
4356 r = 1;
4357 goto out;
4358 }
4359
851ba692 4360 inject_pending_event(vcpu);
b6c7a5dc 4361
6a8b1d13
GN		 4362 /* enable NMI/IRQ window open exits if needed */
4363 if (vcpu->arch.nmi_pending)
4364 kvm_x86_ops->enable_nmi_window(vcpu);
4365 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
4366 kvm_x86_ops->enable_irq_window(vcpu);
4367
95ba8273 4368 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 4369 update_cr8_intercept(vcpu);
4370 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 4371 }
b93463aa 4372
f656ce01 4373 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 4374
b6c7a5dc
HB		 4375 kvm_guest_enter();
4376
42dbaa5a 4377 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 4378 set_debugreg(0, 7);
4379 set_debugreg(vcpu->arch.eff_db[0], 0);
4380 set_debugreg(vcpu->arch.eff_db[1], 1);
4381 set_debugreg(vcpu->arch.eff_db[2], 2);
4382 set_debugreg(vcpu->arch.eff_db[3], 3);
4383 }
b6c7a5dc 4384
229456fc 4385 trace_kvm_entry(vcpu->vcpu_id);
851ba692 4386 kvm_x86_ops->run(vcpu);
b6c7a5dc 4387
24f1e32c
FW		 4388 /*
4389 * If the guest has used debug registers, at least dr7
4390 * will be disabled while returning to the host.
4391 * If we don't have active breakpoints in the host, we don't
4392 * care about the messed up debug address registers. But if
4393 * we have some of them active, restore the old state.
4394 */
59d8eb53 4395 if (hw_breakpoint_active())
24f1e32c 4396 hw_breakpoint_restore();
42dbaa5a 4397
32f88400 4398 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 4399 local_irq_enable();
4400
4401 ++vcpu->stat.exits;
4402
4403 /*
4404 * We must have an instruction between local_irq_enable() and
4405 * kvm_guest_exit(), so the timer interrupt isn't delayed by
4406 * the interrupt shadow. The stat.exits increment will do nicely.
4407 * But we need to prevent reordering, hence this barrier():
4408 */
4409 barrier();
4410
4411 kvm_guest_exit();
4412
4413 preempt_enable();
4414
f656ce01 4415 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 4416
b6c7a5dc
HB		 4417 /*
4418 * Profile KVM exit RIPs:
4419 */
4420 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 4421 unsigned long rip = kvm_rip_read(vcpu);
4422 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 4423 }
4424
298101da 4425
b93463aa
AK		 4426 kvm_lapic_sync_from_vapic(vcpu);
4427
851ba692 4428 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 4429out:
4430 return r;
4431}
b6c7a5dc 4432
09cec754 4433
851ba692 4434static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 4435{
4436 int r;
f656ce01 4437 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 4438
4439 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 4440 pr_debug("vcpu %d received sipi with vector # %x\n",
4441 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 4442 kvm_lapic_reset(vcpu);
5f179287 4443 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 4444 if (r)
4445 return r;
4446 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 4447 }
4448
f656ce01 4449 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 4450 vapic_enter(vcpu);
4451
4452 r = 1;
4453 while (r > 0) {
af2152f5 4454 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
851ba692 4455 r = vcpu_enter_guest(vcpu);
d7690175 4456 else {
f656ce01 4457 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 4458 kvm_vcpu_block(vcpu);
f656ce01 4459 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4460 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 4461 {
4462 switch(vcpu->arch.mp_state) {
4463 case KVM_MP_STATE_HALTED:
d7690175 4464 vcpu->arch.mp_state =
09cec754
GN		 4465 KVM_MP_STATE_RUNNABLE;
4466 case KVM_MP_STATE_RUNNABLE:
4467 break;
4468 case KVM_MP_STATE_SIPI_RECEIVED:
4469 default:
4470 r = -EINTR;
4471 break;
4472 }
4473 }
d7690175
MT		 4474 }
4475
09cec754
GN		 4476 if (r <= 0)
4477 break;
4478
4479 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
4480 if (kvm_cpu_has_pending_timer(vcpu))
4481 kvm_inject_pending_timer_irqs(vcpu);
4482
851ba692 4483 if (dm_request_for_irq_injection(vcpu)) {
09cec754 4484 r = -EINTR;
851ba692 4485 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4486 ++vcpu->stat.request_irq_exits;
4487 }
4488 if (signal_pending(current)) {
4489 r = -EINTR;
851ba692 4490 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 4491 ++vcpu->stat.signal_exits;
4492 }
4493 if (need_resched()) {
f656ce01 4494 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 4495 kvm_resched(vcpu);
f656ce01 4496 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 4497 }
b6c7a5dc
HB		 4498 }
4499
f656ce01 4500 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
851ba692 4501 post_kvm_run_save(vcpu);
b6c7a5dc 4502
b93463aa
AK		 4503 vapic_exit(vcpu);
4504
b6c7a5dc
HB		 4505 return r;
4506}
4507
4508int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
4509{
4510 int r;
4511 sigset_t sigsaved;
4512
4513 vcpu_load(vcpu);
4514
ac9f6dc0
AK		 4515 if (vcpu->sigset_active)
4516 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
4517
a4535290 4518 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 4519 kvm_vcpu_block(vcpu);
d7690175 4520 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 4521 r = -EAGAIN;
4522 goto out;
b6c7a5dc
HB		 4523 }
4524
b6c7a5dc
HB		 4525 /* re-sync apic's tpr */
4526 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 4527 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 4528
ad312c7c 4529 if (vcpu->arch.pio.cur_count) {
7567cae1 4530 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
b6c7a5dc 4531 r = complete_pio(vcpu);
7567cae1 4532 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4533 if (r)
4534 goto out;
4535 }
b6c7a5dc
HB		 4536 if (vcpu->mmio_needed) {
4537 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
4538 vcpu->mmio_read_completed = 1;
4539 vcpu->mmio_needed = 0;
3200f405 4540
f656ce01 4541 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
851ba692 4542 r = emulate_instruction(vcpu, vcpu->arch.mmio_fault_cr2, 0,
571008da 4543 EMULTYPE_NO_DECODE);
f656ce01 4544 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 4545 if (r == EMULATE_DO_MMIO) {
4546 /*
4547 * Read-modify-write. Back to userspace.
4548 */
4549 r = 0;
4550 goto out;
4551 }
4552 }
5fdbf976
MT		 4553 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
4554 kvm_register_write(vcpu, VCPU_REGS_RAX,
4555 kvm_run->hypercall.ret);
b6c7a5dc 4556
851ba692 4557 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 4558
4559out:
4560 if (vcpu->sigset_active)
4561 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
4562
4563 vcpu_put(vcpu);
4564 return r;
4565}
4566
4567int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4568{
4569 vcpu_load(vcpu);
4570
5fdbf976
MT		 4571 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4572 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4573 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4574 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4575 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4576 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
4577 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4578 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 4579#ifdef CONFIG_X86_64
5fdbf976
MT		 4580 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
4581 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
4582 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
4583 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
4584 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
4585 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
4586 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
4587 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 4588#endif
4589
5fdbf976 4590 regs->rip = kvm_rip_read(vcpu);
91586a3b 4591 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc
HB		 4592
4593 vcpu_put(vcpu);
4594
4595 return 0;
4596}
4597
4598int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
4599{
4600 vcpu_load(vcpu);
4601
5fdbf976
MT		 4602 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
4603 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
4604 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
4605 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
4606 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
4607 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
4608 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
4609 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 4610#ifdef CONFIG_X86_64
5fdbf976
MT		 4611 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
4612 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
4613 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
4614 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
4615 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
4616 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
4617 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
4618 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 4619#endif
4620
5fdbf976 4621 kvm_rip_write(vcpu, regs->rip);
91586a3b 4622 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 4623
b4f14abd
JK		 4624 vcpu->arch.exception.pending = false;
4625
b6c7a5dc
HB		 4626 vcpu_put(vcpu);
4627
4628 return 0;
4629}
4630
3e6e0aab
GT		 4631void kvm_get_segment(struct kvm_vcpu *vcpu,
4632 struct kvm_segment *var, int seg)
b6c7a5dc 4633{
14af3f3c 4634 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 4635}
4636
4637void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4638{
4639 struct kvm_segment cs;
4640
3e6e0aab 4641 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 4642 *db = cs.db;
4643 *l = cs.l;
4644}
4645EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
4646
4647int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
4648 struct kvm_sregs *sregs)
4649{
89a27f4d 4650 struct desc_ptr dt;
b6c7a5dc
HB		 4651
4652 vcpu_load(vcpu);
4653
3e6e0aab
GT		 4654 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4655 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4656 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4657 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4658 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4659 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4660
3e6e0aab
GT		 4661 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4662 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 4663
4664 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 4665 sregs->idt.limit = dt.size;
4666 sregs->idt.base = dt.address;
b6c7a5dc 4667 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 4668 sregs->gdt.limit = dt.size;
4669 sregs->gdt.base = dt.address;
b6c7a5dc 4670
4d4ec087 4671 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c
ZX		 4672 sregs->cr2 = vcpu->arch.cr2;
4673 sregs->cr3 = vcpu->arch.cr3;
fc78f519 4674 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 4675 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 4676 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 4677 sregs->apic_base = kvm_get_apic_base(vcpu);
4678
923c61bb 4679 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 4680
36752c9b 4681 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 4682 set_bit(vcpu->arch.interrupt.nr,
4683 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 4684
b6c7a5dc
HB		 4685 vcpu_put(vcpu);
4686
4687 return 0;
4688}
4689
62d9f0db
MT		 4690int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
4691 struct kvm_mp_state *mp_state)
4692{
4693 vcpu_load(vcpu);
4694 mp_state->mp_state = vcpu->arch.mp_state;
4695 vcpu_put(vcpu);
4696 return 0;
4697}
4698
4699int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
4700 struct kvm_mp_state *mp_state)
4701{
4702 vcpu_load(vcpu);
4703 vcpu->arch.mp_state = mp_state->mp_state;
4704 vcpu_put(vcpu);
4705 return 0;
4706}
4707
3e6e0aab 4708static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 4709 struct kvm_segment *var, int seg)
4710{
14af3f3c 4711 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 4712}
4713
37817f29
IE		 4714static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
4715 struct kvm_segment *kvm_desct)
4716{
46a359e7
AM		 4717 kvm_desct->base = get_desc_base(seg_desc);
4718 kvm_desct->limit = get_desc_limit(seg_desc);
c93cd3a5
MT		 4719 if (seg_desc->g) {
4720 kvm_desct->limit <<= 12;
4721 kvm_desct->limit |= 0xfff;
4722 }
37817f29
IE		 4723 kvm_desct->selector = selector;
4724 kvm_desct->type = seg_desc->type;
4725 kvm_desct->present = seg_desc->p;
4726 kvm_desct->dpl = seg_desc->dpl;
4727 kvm_desct->db = seg_desc->d;
4728 kvm_desct->s = seg_desc->s;
4729 kvm_desct->l = seg_desc->l;
4730 kvm_desct->g = seg_desc->g;
4731 kvm_desct->avl = seg_desc->avl;
4732 if (!selector)
4733 kvm_desct->unusable = 1;
4734 else
4735 kvm_desct->unusable = 0;
4736 kvm_desct->padding = 0;
4737}
4738
b8222ad2
AS		 4739static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
4740 u16 selector,
89a27f4d 4741 struct desc_ptr *dtable)
37817f29
IE		 4742{
4743 if (selector & 1 << 2) {
4744 struct kvm_segment kvm_seg;
4745
3e6e0aab 4746 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 4747
4748 if (kvm_seg.unusable)
89a27f4d 4749 dtable->size = 0;
37817f29 4750 else
89a27f4d
GN		 4751 dtable->size = kvm_seg.limit;
4752 dtable->address = kvm_seg.base;
37817f29
IE		 4753 }
4754 else
4755 kvm_x86_ops->get_gdt(vcpu, dtable);
4756}
4757
4758/* allowed just for 8 bytes segments */
4759static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4760 struct desc_struct *seg_desc)
4761{
89a27f4d 4762 struct desc_ptr dtable;
37817f29 4763 u16 index = selector >> 3;
6f550484
TY		 4764 int ret;
4765 u32 err;
4766 gva_t addr;
37817f29 4767
b8222ad2 4768 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4769
89a27f4d 4770 if (dtable.size < index * 8 + 7) {
37817f29 4771 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
c125c607 4772 return X86EMUL_PROPAGATE_FAULT;
37817f29 4773 }
6f550484
TY		 4774 addr = dtable.base + index * 8;
4775 ret = kvm_read_guest_virt_system(addr, seg_desc, sizeof(*seg_desc),
4776 vcpu, &err);
4777 if (ret == X86EMUL_PROPAGATE_FAULT)
4778 kvm_inject_page_fault(vcpu, addr, err);
4779
4780 return ret;
37817f29
IE		 4781}
4782
4783/* allowed just for 8 bytes segments */
4784static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4785 struct desc_struct *seg_desc)
4786{
89a27f4d 4787 struct desc_ptr dtable;
37817f29
IE		 4788 u16 index = selector >> 3;
4789
b8222ad2 4790 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29 4791
89a27f4d 4792 if (dtable.size < index * 8 + 7)
37817f29 4793 return 1;
89a27f4d 4794 return kvm_write_guest_virt(dtable.address + index*8, seg_desc, sizeof(*seg_desc), vcpu, NULL);
1871c602
GN		 4795}
4796
4797static gpa_t get_tss_base_addr_write(struct kvm_vcpu *vcpu,
4798 struct desc_struct *seg_desc)
4799{
4800 u32 base_addr = get_desc_base(seg_desc);
4801
4802 return kvm_mmu_gva_to_gpa_write(vcpu, base_addr, NULL);
37817f29
IE		 4803}
4804
1871c602 4805static gpa_t get_tss_base_addr_read(struct kvm_vcpu *vcpu,
37817f29
IE		 4806 struct desc_struct *seg_desc)
4807{
46a359e7 4808 u32 base_addr = get_desc_base(seg_desc);
37817f29 4809
1871c602 4810 return kvm_mmu_gva_to_gpa_read(vcpu, base_addr, NULL);
37817f29
IE		 4811}
4812
37817f29
IE		 4813static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
4814{
4815 struct kvm_segment kvm_seg;
4816
3e6e0aab 4817 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4818 return kvm_seg.selector;
4819}
4820
2259e3a7 4821static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 4822{
4823 struct kvm_segment segvar = {
4824 .base = selector << 4,
4825 .limit = 0xffff,
4826 .selector = selector,
4827 .type = 3,
4828 .present = 1,
4829 .dpl = 3,
4830 .db = 0,
4831 .s = 1,
4832 .l = 0,
4833 .g = 0,
4834 .avl = 0,
4835 .unusable = 0,
4836 };
4837 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
c697518a 4838 return X86EMUL_CONTINUE;
f4bbd9aa
AK		 4839}
4840
c0c7c04b
AL		 4841static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
4842{
4843 return (seg != VCPU_SREG_LDTR) &&
4844 (seg != VCPU_SREG_TR) &&
91586a3b 4845 (kvm_get_rflags(vcpu) & X86_EFLAGS_VM);
c0c7c04b
AL		 4846}
4847
c697518a 4848int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg)
37817f29
IE		 4849{
4850 struct kvm_segment kvm_seg;
e01c2426 4851 struct desc_struct seg_desc;
c697518a
GN		 4852 u8 dpl, rpl, cpl;
4853 unsigned err_vec = GP_VECTOR;
4854 u32 err_code = 0;
4855 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
4856 int ret;
37817f29 4857
3eeb3288 4858 if (is_vm86_segment(vcpu, seg) || !is_protmode(vcpu))
f4bbd9aa 4859 return kvm_load_realmode_segment(vcpu, selector, seg);
e01c2426 4860
c697518a
GN		 4861 /* NULL selector is not valid for TR, CS and SS */
4862 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
4863 && null_selector)
4864 goto exception;
4865
4866 /* TR should be in GDT only */
4867 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
4868 goto exception;
4869
4870 ret = load_guest_segment_descriptor(vcpu, selector, &seg_desc);
4871 if (ret)
4872 return ret;
4873
e01c2426 4874 seg_desct_to_kvm_desct(&seg_desc, selector, &kvm_seg);
cb84b55f 4875
c697518a
GN		 4876 if (null_selector) { /* for NULL selector skip all following checks */
4877 kvm_seg.unusable = 1;
4878 goto load;
4879 }
37817f29 4880
c697518a
GN		 4881 err_code = selector & 0xfffc;
4882 err_vec = GP_VECTOR;
37817f29 4883
c697518a
GN		 4884 /* can't load system descriptor into segment selecor */
4885 if (seg <= VCPU_SREG_GS && !kvm_seg.s)
4886 goto exception;
4887
4888 if (!kvm_seg.present) {
4889 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
4890 goto exception;
4891 }
4892
4893 rpl = selector & 3;
4894 dpl = kvm_seg.dpl;
4895 cpl = kvm_x86_ops->get_cpl(vcpu);
4896
4897 switch (seg) {
4898 case VCPU_SREG_SS:
4899 /*
4900 * segment is not a writable data segment or segment
4901 * selector's RPL != CPL or segment selector's RPL != CPL
4902 */
4903 if (rpl != cpl || (kvm_seg.type & 0xa) != 0x2 || dpl != cpl)
4904 goto exception;
4905 break;
4906 case VCPU_SREG_CS:
4907 if (!(kvm_seg.type & 8))
4908 goto exception;
4909
4910 if (kvm_seg.type & 4) {
4911 /* conforming */
4912 if (dpl > cpl)
4913 goto exception;
4914 } else {
4915 /* nonconforming */
4916 if (rpl > cpl || dpl != cpl)
4917 goto exception;
4918 }
4919 /* CS(RPL) <- CPL */
4920 selector = (selector & 0xfffc) | cpl;
4921 break;
4922 case VCPU_SREG_TR:
4923 if (kvm_seg.s || (kvm_seg.type != 1 && kvm_seg.type != 9))
4924 goto exception;
4925 break;
4926 case VCPU_SREG_LDTR:
4927 if (kvm_seg.s || kvm_seg.type != 2)
4928 goto exception;
4929 break;
4930 default: /* DS, ES, FS, or GS */
4931 /*
4932 * segment is not a data or readable code segment or
4933 * ((segment is a data or nonconforming code segment)
4934 * and (both RPL and CPL > DPL))
4935 */
4936 if ((kvm_seg.type & 0xa) == 0x8 ||
4937 (((kvm_seg.type & 0xc) != 0xc) && (rpl > dpl && cpl > dpl)))
4938 goto exception;
4939 break;
4940 }
4941
4942 if (!kvm_seg.unusable && kvm_seg.s) {
e01c2426 4943 /* mark segment as accessed */
c697518a 4944 kvm_seg.type |= 1;
e01c2426
GN		 4945 seg_desc.type |= 1;
4946 save_guest_segment_descriptor(vcpu, selector, &seg_desc);
4947 }
c697518a
GN		 4948load:
4949 kvm_set_segment(vcpu, &kvm_seg, seg);
4950 return X86EMUL_CONTINUE;
4951exception:
4952 kvm_queue_exception_e(vcpu, err_vec, err_code);
4953 return X86EMUL_PROPAGATE_FAULT;
37817f29
IE		 4954}
4955
4956static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4957 struct tss_segment_32 *tss)
4958{
4959 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4960 tss->eip = kvm_rip_read(vcpu);
91586a3b 4961 tss->eflags = kvm_get_rflags(vcpu);
5fdbf976
MT		 4962 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4963 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4964 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4965 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4966 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4967 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4968 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4969 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4970 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4971 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4972 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4973 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4974 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4975 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4976 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4977}
4978
c697518a
GN		 4979static void kvm_load_segment_selector(struct kvm_vcpu *vcpu, u16 sel, int seg)
4980{
4981 struct kvm_segment kvm_seg;
4982 kvm_get_segment(vcpu, &kvm_seg, seg);
4983 kvm_seg.selector = sel;
4984 kvm_set_segment(vcpu, &kvm_seg, seg);
4985}
4986
37817f29
IE		 4987static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4988 struct tss_segment_32 *tss)
4989{
4990 kvm_set_cr3(vcpu, tss->cr3);
4991
5fdbf976 4992 kvm_rip_write(vcpu, tss->eip);
91586a3b 4993 kvm_set_rflags(vcpu, tss->eflags | 2);
37817f29 4994
5fdbf976
MT		 4995 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4996 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4997 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4998 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4999 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
5000 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
5001 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
5002 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 5003
c697518a
GN		 5004 /*
5005 * SDM says that segment selectors are loaded before segment
5006 * descriptors
5007 */
5008 kvm_load_segment_selector(vcpu, tss->ldt_selector, VCPU_SREG_LDTR);
5009 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5010 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5011 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5012 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5013 kvm_load_segment_selector(vcpu, tss->fs, VCPU_SREG_FS);
5014 kvm_load_segment_selector(vcpu, tss->gs, VCPU_SREG_GS);
5015
5016 /*
5017 * Now load segment descriptors. If fault happenes at this stage
5018 * it is handled in a context of new task
5019 */
5020 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, VCPU_SREG_LDTR))
37817f29
IE		 5021 return 1;
5022
c697518a 5023 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5024 return 1;
5025
c697518a 5026 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5027 return 1;
5028
c697518a 5029 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5030 return 1;
5031
c697518a 5032 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5033 return 1;
5034
c697518a 5035 if (kvm_load_segment_descriptor(vcpu, tss->fs, VCPU_SREG_FS))
37817f29
IE		 5036 return 1;
5037
c697518a 5038 if (kvm_load_segment_descriptor(vcpu, tss->gs, VCPU_SREG_GS))
37817f29
IE		 5039 return 1;
5040 return 0;
5041}
5042
5043static void save_state_to_tss16(struct kvm_vcpu *vcpu,
5044 struct tss_segment_16 *tss)
5045{
5fdbf976 5046 tss->ip = kvm_rip_read(vcpu);
91586a3b 5047 tss->flag = kvm_get_rflags(vcpu);
5fdbf976
MT		 5048 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5049 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5050 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5051 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5052 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5053 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
5054 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
5055 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 5056
5057 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
5058 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
5059 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
5060 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
5061 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 5062}
5063
5064static int load_state_from_tss16(struct kvm_vcpu *vcpu,
5065 struct tss_segment_16 *tss)
5066{
5fdbf976 5067 kvm_rip_write(vcpu, tss->ip);
91586a3b 5068 kvm_set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 5069 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
5070 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
5071 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
5072 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
5073 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
5074 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
5075 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
5076 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 5077
c697518a
GN		 5078 /*
5079 * SDM says that segment selectors are loaded before segment
5080 * descriptors
5081 */
5082 kvm_load_segment_selector(vcpu, tss->ldt, VCPU_SREG_LDTR);
5083 kvm_load_segment_selector(vcpu, tss->es, VCPU_SREG_ES);
5084 kvm_load_segment_selector(vcpu, tss->cs, VCPU_SREG_CS);
5085 kvm_load_segment_selector(vcpu, tss->ss, VCPU_SREG_SS);
5086 kvm_load_segment_selector(vcpu, tss->ds, VCPU_SREG_DS);
5087
5088 /*
5089 * Now load segment descriptors. If fault happenes at this stage
5090 * it is handled in a context of new task
5091 */
5092 if (kvm_load_segment_descriptor(vcpu, tss->ldt, VCPU_SREG_LDTR))
37817f29
IE		 5093 return 1;
5094
c697518a 5095 if (kvm_load_segment_descriptor(vcpu, tss->es, VCPU_SREG_ES))
37817f29
IE		 5096 return 1;
5097
c697518a 5098 if (kvm_load_segment_descriptor(vcpu, tss->cs, VCPU_SREG_CS))
37817f29
IE		 5099 return 1;
5100
c697518a 5101 if (kvm_load_segment_descriptor(vcpu, tss->ss, VCPU_SREG_SS))
37817f29
IE		 5102 return 1;
5103
c697518a 5104 if (kvm_load_segment_descriptor(vcpu, tss->ds, VCPU_SREG_DS))
37817f29
IE		 5105 return 1;
5106 return 0;
5107}
5108
8b2cf73c 5109static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 5110 u16 old_tss_sel, u32 old_tss_base,
5111 struct desc_struct *nseg_desc)
37817f29
IE		 5112{
5113 struct tss_segment_16 tss_segment_16;
5114 int ret = 0;
5115
34198bf8
MT		 5116 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5117 sizeof tss_segment_16))
37817f29
IE		 5118 goto out;
5119
5120 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 5121
34198bf8
MT		 5122 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
5123 sizeof tss_segment_16))
37817f29 5124 goto out;
34198bf8 5125
1871c602 5126 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8
MT		 5127 &tss_segment_16, sizeof tss_segment_16))
5128 goto out;
5129
b237ac37
GN		 5130 if (old_tss_sel != 0xffff) {
5131 tss_segment_16.prev_task_link = old_tss_sel;
5132
5133 if (kvm_write_guest(vcpu->kvm,
1871c602 5134 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5135 &tss_segment_16.prev_task_link,
5136 sizeof tss_segment_16.prev_task_link))
5137 goto out;
5138 }
5139
37817f29
IE		 5140 if (load_state_from_tss16(vcpu, &tss_segment_16))
5141 goto out;
5142
5143 ret = 1;
5144out:
5145 return ret;
5146}
5147
8b2cf73c 5148static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 5149 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 5150 struct desc_struct *nseg_desc)
5151{
5152 struct tss_segment_32 tss_segment_32;
5153 int ret = 0;
5154
34198bf8
MT		 5155 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5156 sizeof tss_segment_32))
37817f29
IE		 5157 goto out;
5158
5159 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 5160
34198bf8
MT		 5161 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
5162 sizeof tss_segment_32))
5163 goto out;
5164
1871c602 5165 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr_read(vcpu, nseg_desc),
34198bf8 5166 &tss_segment_32, sizeof tss_segment_32))
37817f29 5167 goto out;
34198bf8 5168
b237ac37
GN		 5169 if (old_tss_sel != 0xffff) {
5170 tss_segment_32.prev_task_link = old_tss_sel;
5171
5172 if (kvm_write_guest(vcpu->kvm,
1871c602 5173 get_tss_base_addr_write(vcpu, nseg_desc),
b237ac37
GN		 5174 &tss_segment_32.prev_task_link,
5175 sizeof tss_segment_32.prev_task_link))
5176 goto out;
5177 }
5178
37817f29
IE		 5179 if (load_state_from_tss32(vcpu, &tss_segment_32))
5180 goto out;
5181
5182 ret = 1;
5183out:
5184 return ret;
5185}
5186
5187int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
5188{
5189 struct kvm_segment tr_seg;
5190 struct desc_struct cseg_desc;
5191 struct desc_struct nseg_desc;
5192 int ret = 0;
34198bf8
MT		 5193 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
5194 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
e8861cfe 5195 u32 desc_limit;
37817f29 5196
1871c602 5197 old_tss_base = kvm_mmu_gva_to_gpa_write(vcpu, old_tss_base, NULL);
37817f29 5198
34198bf8
MT		 5199 /* FIXME: Handle errors. Failure to read either TSS or their
5200 * descriptors should generate a pagefault.
5201 */
37817f29
IE		 5202 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
5203 goto out;
5204
34198bf8 5205 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 5206 goto out;
5207
37817f29
IE		 5208 if (reason != TASK_SWITCH_IRET) {
5209 int cpl;
5210
5211 cpl = kvm_x86_ops->get_cpl(vcpu);
5212 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
5213 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
5214 return 1;
5215 }
5216 }
5217
e8861cfe
JK		 5218 desc_limit = get_desc_limit(&nseg_desc);
5219 if (!nseg_desc.p ||
5220 ((desc_limit < 0x67 && (nseg_desc.type & 8)) ||
5221 desc_limit < 0x2b)) {
37817f29
IE		 5222 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
5223 return 1;
5224 }
5225
5226 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 5227 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 5228 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 5229 }
5230
5231 if (reason == TASK_SWITCH_IRET) {
91586a3b
JK		 5232 u32 eflags = kvm_get_rflags(vcpu);
5233 kvm_set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
37817f29
IE		 5234 }
5235
b237ac37
GN		 5236 /* set back link to prev task only if NT bit is set in eflags
5237 note that old_tss_sel is not used afetr this point */
5238 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
5239 old_tss_sel = 0xffff;
5240
37817f29 5241 if (nseg_desc.type & 8)
b237ac37
GN		 5242 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
5243 old_tss_base, &nseg_desc);
37817f29 5244 else
b237ac37
GN		 5245 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
5246 old_tss_base, &nseg_desc);
37817f29
IE		 5247
5248 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
91586a3b
JK		 5249 u32 eflags = kvm_get_rflags(vcpu);
5250 kvm_set_rflags(vcpu, eflags | X86_EFLAGS_NT);
37817f29
IE		 5251 }
5252
5253 if (reason != TASK_SWITCH_IRET) {
3fe913e7 5254 nseg_desc.type |= (1 << 1);
37817f29
IE		 5255 save_guest_segment_descriptor(vcpu, tss_selector,
5256 &nseg_desc);
5257 }
5258
4d4ec087 5259 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0(vcpu) | X86_CR0_TS);
37817f29
IE		 5260 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
5261 tr_seg.type = 11;
3e6e0aab 5262 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 5263out:
37817f29
IE		 5264 return ret;
5265}
5266EXPORT_SYMBOL_GPL(kvm_task_switch);
5267
b6c7a5dc
HB		 5268int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5269 struct kvm_sregs *sregs)
5270{
5271 int mmu_reset_needed = 0;
923c61bb 5272 int pending_vec, max_bits;
89a27f4d 5273 struct desc_ptr dt;
b6c7a5dc
HB		 5274
5275 vcpu_load(vcpu);
5276
89a27f4d
GN		 5277 dt.size = sregs->idt.limit;
5278 dt.address = sregs->idt.base;
b6c7a5dc 5279 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5280 dt.size = sregs->gdt.limit;
5281 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5282 kvm_x86_ops->set_gdt(vcpu, &dt);
5283
ad312c7c
ZX		 5284 vcpu->arch.cr2 = sregs->cr2;
5285 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
dc7e795e 5286 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 5287
2d3ad1f4 5288 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5289
f6801dff 5290 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5291 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5292 kvm_set_apic_base(vcpu, sregs->apic_base);
5293
4d4ec087 5294 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5295 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5296 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5297
fc78f519 5298 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5299 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
7c93be44 5300 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
ad312c7c 5301 load_pdptrs(vcpu, vcpu->arch.cr3);
7c93be44
MT		 5302 mmu_reset_needed = 1;
5303 }
b6c7a5dc
HB		 5304
5305 if (mmu_reset_needed)
5306 kvm_mmu_reset_context(vcpu);
5307
923c61bb
GN		 5308 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5309 pending_vec = find_first_bit(
5310 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5311 if (pending_vec < max_bits) {
66fd3f7f 5312 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 5313 pr_debug("Set back pending irq %d\n", pending_vec);
5314 if (irqchip_in_kernel(vcpu->kvm))
5315 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 5316 }
5317
3e6e0aab
GT		 5318 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5319 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5320 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5321 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5322 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5323 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5324
3e6e0aab
GT		 5325 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5326 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5327
5f0269f5
ME		 5328 update_cr8_intercept(vcpu);
5329
9c3e4aab 5330 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5331 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5332 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5333 !is_protmode(vcpu))
9c3e4aab
MT		 5334 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5335
b6c7a5dc
HB		 5336 vcpu_put(vcpu);
5337
5338 return 0;
5339}
5340
d0bfb940
JK		 5341int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5342 struct kvm_guest_debug *dbg)
b6c7a5dc 5343{
355be0b9 5344 unsigned long rflags;
ae675ef0 5345 int i, r;
b6c7a5dc
HB		 5346
5347 vcpu_load(vcpu);
5348
4f926bf2
JK		 5349 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5350 r = -EBUSY;
5351 if (vcpu->arch.exception.pending)
5352 goto unlock_out;
5353 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5354 kvm_queue_exception(vcpu, DB_VECTOR);
5355 else
5356 kvm_queue_exception(vcpu, BP_VECTOR);
5357 }
5358
91586a3b
JK		 5359 /*
5360 * Read rflags as long as potentially injected trace flags are still
5361 * filtered out.
5362 */
5363 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5364
5365 vcpu->guest_debug = dbg->control;
5366 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5367 vcpu->guest_debug = 0;
5368
5369 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5370 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5371 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5372 vcpu->arch.switch_db_regs =
5373 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5374 } else {
5375 for (i = 0; i < KVM_NR_DB_REGS; i++)
5376 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5377 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5378 }
5379
f92653ee
JK		 5380 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5381 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5382 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5383
91586a3b
JK		 5384 /*
5385 * Trigger an rflags update that will inject or remove the trace
5386 * flags.
5387 */
5388 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5389
355be0b9 5390 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5391
4f926bf2 5392 r = 0;
d0bfb940 5393
4f926bf2 5394unlock_out:
b6c7a5dc
HB		 5395 vcpu_put(vcpu);
5396
5397 return r;
5398}
5399
d0752060
HB		 5400/*
5401 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
5402 * we have asm/x86/processor.h
5403 */
5404struct fxsave {
5405 u16 cwd;
5406 u16 swd;
5407 u16 twd;
5408 u16 fop;
5409 u64 rip;
5410 u64 rdp;
5411 u32 mxcsr;
5412 u32 mxcsr_mask;
5413 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
5414#ifdef CONFIG_X86_64
5415 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
5416#else
5417 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
5418#endif
5419};
5420
8b006791
ZX		 5421/*
5422 * Translate a guest virtual address to a guest physical address.
5423 */
5424int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5425 struct kvm_translation *tr)
5426{
5427 unsigned long vaddr = tr->linear_address;
5428 gpa_t gpa;
f656ce01 5429 int idx;
8b006791
ZX		 5430
5431 vcpu_load(vcpu);
f656ce01 5432 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5433 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5434 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5435 tr->physical_address = gpa;
5436 tr->valid = gpa != UNMAPPED_GVA;
5437 tr->writeable = 1;
5438 tr->usermode = 0;
8b006791
ZX		 5439 vcpu_put(vcpu);
5440
5441 return 0;
5442}
5443
d0752060
HB		 5444int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5445{
ad312c7c 5446 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5447
5448 vcpu_load(vcpu);
5449
5450 memcpy(fpu->fpr, fxsave->st_space, 128);
5451 fpu->fcw = fxsave->cwd;
5452 fpu->fsw = fxsave->swd;
5453 fpu->ftwx = fxsave->twd;
5454 fpu->last_opcode = fxsave->fop;
5455 fpu->last_ip = fxsave->rip;
5456 fpu->last_dp = fxsave->rdp;
5457 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5458
5459 vcpu_put(vcpu);
5460
5461 return 0;
5462}
5463
5464int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5465{
ad312c7c 5466 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 5467
5468 vcpu_load(vcpu);
5469
5470 memcpy(fxsave->st_space, fpu->fpr, 128);
5471 fxsave->cwd = fpu->fcw;
5472 fxsave->swd = fpu->fsw;
5473 fxsave->twd = fpu->ftwx;
5474 fxsave->fop = fpu->last_opcode;
5475 fxsave->rip = fpu->last_ip;
5476 fxsave->rdp = fpu->last_dp;
5477 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5478
5479 vcpu_put(vcpu);
5480
5481 return 0;
5482}
5483
5484void fx_init(struct kvm_vcpu *vcpu)
5485{
5486 unsigned after_mxcsr_mask;
5487
bc1a34f1
AA		 5488 /*
5489 * Touch the fpu the first time in non atomic context as if
5490 * this is the first fpu instruction the exception handler
5491 * will fire before the instruction returns and it'll have to
5492 * allocate ram with GFP_KERNEL.
5493 */
5494 if (!used_math())
d6e88aec 5495 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 5496
d0752060
HB		 5497 /* Initialize guest FPU by resetting ours and saving into guest's */
5498 preempt_disable();
d6e88aec
AK		 5499 kvm_fx_save(&vcpu->arch.host_fx_image);
5500 kvm_fx_finit();
5501 kvm_fx_save(&vcpu->arch.guest_fx_image);
5502 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 5503 preempt_enable();
5504
ad312c7c 5505 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 5506 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 5507 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
5508 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 5509 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
5510}
5511EXPORT_SYMBOL_GPL(fx_init);
5512
5513void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5514{
2608d7a1 5515 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5516 return;
5517
5518 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 5519 kvm_fx_save(&vcpu->arch.host_fx_image);
5520 kvm_fx_restore(&vcpu->arch.guest_fx_image);
0c04851c 5521 trace_kvm_fpu(1);
d0752060 5522}
d0752060
HB		 5523
5524void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5525{
5526 if (!vcpu->guest_fpu_loaded)
5527 return;
5528
5529 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 5530 kvm_fx_save(&vcpu->arch.guest_fx_image);
5531 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 5532 ++vcpu->stat.fpu_reload;
02daab21 5533 set_bit(KVM_REQ_DEACTIVATE_FPU, &vcpu->requests);
0c04851c 5534 trace_kvm_fpu(0);
d0752060 5535}
e9b11c17
ZX		 5536
5537void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5538{
7f1ea208
JR		 5539 if (vcpu->arch.time_page) {
5540 kvm_release_page_dirty(vcpu->arch.time_page);
5541 vcpu->arch.time_page = NULL;
5542 }
5543
e9b11c17
ZX		 5544 kvm_x86_ops->vcpu_free(vcpu);
5545}
5546
5547struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5548 unsigned int id)
5549{
26e5215f
AK		 5550 return kvm_x86_ops->vcpu_create(kvm, id);
5551}
e9b11c17 5552
26e5215f
AK		 5553int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5554{
5555 int r;
e9b11c17
ZX		 5556
5557 /* We do fxsave: this must be aligned. */
ad312c7c 5558 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 5559
0bed3b56 5560 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5561 vcpu_load(vcpu);
5562 r = kvm_arch_vcpu_reset(vcpu);
5563 if (r == 0)
5564 r = kvm_mmu_setup(vcpu);
5565 vcpu_put(vcpu);
5566 if (r < 0)
5567 goto free_vcpu;
5568
26e5215f 5569 return 0;
e9b11c17
ZX		 5570free_vcpu:
5571 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5572 return r;
e9b11c17
ZX		 5573}
5574
d40ccc62 5575void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 5576{
5577 vcpu_load(vcpu);
5578 kvm_mmu_unload(vcpu);
5579 vcpu_put(vcpu);
5580
5581 kvm_x86_ops->vcpu_free(vcpu);
5582}
5583
5584int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5585{
448fa4a9
JK		 5586 vcpu->arch.nmi_pending = false;
5587 vcpu->arch.nmi_injected = false;
5588
42dbaa5a
JK		 5589 vcpu->arch.switch_db_regs = 0;
5590 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5591 vcpu->arch.dr6 = DR6_FIXED_1;
5592 vcpu->arch.dr7 = DR7_FIXED_1;
5593
e9b11c17
ZX		 5594 return kvm_x86_ops->vcpu_reset(vcpu);
5595}
5596
10474ae8 5597int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5598{
0cca7907
ZA		 5599 /*
5600 * Since this may be called from a hotplug notifcation,
5601 * we can't get the CPU frequency directly.
5602 */
5603 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5604 int cpu = raw_smp_processor_id();
5605 per_cpu(cpu_tsc_khz, cpu) = 0;
5606 }
18863bdd
AK		 5607
5608 kvm_shared_msr_cpu_online();
5609
10474ae8 5610 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5611}
5612
5613void kvm_arch_hardware_disable(void *garbage)
5614{
5615 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5616 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5617}
5618
5619int kvm_arch_hardware_setup(void)
5620{
5621 return kvm_x86_ops->hardware_setup();
5622}
5623
5624void kvm_arch_hardware_unsetup(void)
5625{
5626 kvm_x86_ops->hardware_unsetup();
5627}
5628
5629void kvm_arch_check_processor_compat(void *rtn)
5630{
5631 kvm_x86_ops->check_processor_compatibility(rtn);
5632}
5633
5634int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5635{
5636 struct page *page;
5637 struct kvm *kvm;
5638 int r;
5639
5640 BUG_ON(vcpu->kvm == NULL);
5641 kvm = vcpu->kvm;
5642
ad312c7c 5643 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 5644 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5645 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5646 else
a4535290 5647 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5648
5649 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5650 if (!page) {
5651 r = -ENOMEM;
5652 goto fail;
5653 }
ad312c7c 5654 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 5655
5656 r = kvm_mmu_create(vcpu);
5657 if (r < 0)
5658 goto fail_free_pio_data;
5659
5660 if (irqchip_in_kernel(kvm)) {
5661 r = kvm_create_lapic(vcpu);
5662 if (r < 0)
5663 goto fail_mmu_destroy;
5664 }
5665
890ca9ae
HY		 5666 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5667 GFP_KERNEL);
5668 if (!vcpu->arch.mce_banks) {
5669 r = -ENOMEM;
443c39bc 5670 goto fail_free_lapic;
890ca9ae
HY		 5671 }
5672 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
5673
e9b11c17 5674 return 0;
443c39bc
WY		 5675fail_free_lapic:
5676 kvm_free_lapic(vcpu);
e9b11c17
ZX		 5677fail_mmu_destroy:
5678 kvm_mmu_destroy(vcpu);
5679fail_free_pio_data:
ad312c7c 5680 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 5681fail:
5682 return r;
5683}
5684
5685void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
5686{
f656ce01
MT		 5687 int idx;
5688
36cb93fd 5689 kfree(vcpu->arch.mce_banks);
e9b11c17 5690 kvm_free_lapic(vcpu);
f656ce01 5691 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 5692 kvm_mmu_destroy(vcpu);
f656ce01 5693 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 5694 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 5695}
d19a9cd2
ZX		 5696
5697struct kvm *kvm_arch_create_vm(void)
5698{
5699 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
5700
5701 if (!kvm)
5702 return ERR_PTR(-ENOMEM);
5703
fef9cce0
MT		 5704 kvm->arch.aliases = kzalloc(sizeof(struct kvm_mem_aliases), GFP_KERNEL);
5705 if (!kvm->arch.aliases) {
5706 kfree(kvm);
5707 return ERR_PTR(-ENOMEM);
5708 }
5709
f05e70ac 5710 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 5711 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 5712
5550af4d
SY		 5713 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
5714 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
5715
53f658b3
MT		 5716 rdtscll(kvm->arch.vm_init_tsc);
5717
d19a9cd2
ZX		 5718 return kvm;
5719}
5720
5721static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
5722{
5723 vcpu_load(vcpu);
5724 kvm_mmu_unload(vcpu);
5725 vcpu_put(vcpu);
5726}
5727
5728static void kvm_free_vcpus(struct kvm *kvm)
5729{
5730 unsigned int i;
988a2cae 5731 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 5732
5733 /*
5734 * Unpin any mmu pages first.
5735 */
988a2cae
GN		 5736 kvm_for_each_vcpu(i, vcpu, kvm)
5737 kvm_unload_vcpu_mmu(vcpu);
5738 kvm_for_each_vcpu(i, vcpu, kvm)
5739 kvm_arch_vcpu_free(vcpu);
5740
5741 mutex_lock(&kvm->lock);
5742 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
5743 kvm->vcpus[i] = NULL;
d19a9cd2 5744
988a2cae
GN		 5745 atomic_set(&kvm->online_vcpus, 0);
5746 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 5747}
5748
ad8ba2cd
SY		 5749void kvm_arch_sync_events(struct kvm *kvm)
5750{
ba4cef31 5751 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 5752}
5753
d19a9cd2
ZX		 5754void kvm_arch_destroy_vm(struct kvm *kvm)
5755{
6eb55818 5756 kvm_iommu_unmap_guest(kvm);
7837699f 5757 kvm_free_pit(kvm);
d7deeeb0
ZX		 5758 kfree(kvm->arch.vpic);
5759 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 5760 kvm_free_vcpus(kvm);
5761 kvm_free_physmem(kvm);
3d45830c
AK		 5762 if (kvm->arch.apic_access_page)
5763 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 5764 if (kvm->arch.ept_identity_pagetable)
5765 put_page(kvm->arch.ept_identity_pagetable);
64749204 5766 cleanup_srcu_struct(&kvm->srcu);
fef9cce0 5767 kfree(kvm->arch.aliases);
d19a9cd2
ZX		 5768 kfree(kvm);
5769}
0de10343 5770
f7784b8e
MT		 5771int kvm_arch_prepare_memory_region(struct kvm *kvm,
5772 struct kvm_memory_slot *memslot,
0de10343 5773 struct kvm_memory_slot old,
f7784b8e 5774 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 5775 int user_alloc)
5776{
f7784b8e 5777 int npages = memslot->npages;
0de10343
ZX		 5778
5779 /*To keep backward compatibility with older userspace,
5780 *x86 needs to hanlde !user_alloc case.
5781 */
5782 if (!user_alloc) {
5783 if (npages && !old.rmap) {
604b38ac
AA		 5784 unsigned long userspace_addr;
5785
72dc67a6 5786 down_write(&current->mm->mmap_sem);
604b38ac
AA		 5787 userspace_addr = do_mmap(NULL, 0,
5788 npages * PAGE_SIZE,
5789 PROT_READ | PROT_WRITE,
acee3c04 5790 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 5791 0);
72dc67a6 5792 up_write(&current->mm->mmap_sem);
0de10343 5793
604b38ac
AA		 5794 if (IS_ERR((void *)userspace_addr))
5795 return PTR_ERR((void *)userspace_addr);
5796
604b38ac 5797 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 5798 }
5799 }
5800
f7784b8e
MT		 5801
5802 return 0;
5803}
5804
5805void kvm_arch_commit_memory_region(struct kvm *kvm,
5806 struct kvm_userspace_memory_region *mem,
5807 struct kvm_memory_slot old,
5808 int user_alloc)
5809{
5810
5811 int npages = mem->memory_size >> PAGE_SHIFT;
5812
5813 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
5814 int ret;
5815
5816 down_write(&current->mm->mmap_sem);
5817 ret = do_munmap(current->mm, old.userspace_addr,
5818 old.npages * PAGE_SIZE);
5819 up_write(&current->mm->mmap_sem);
5820 if (ret < 0)
5821 printk(KERN_WARNING
5822 "kvm_vm_ioctl_set_memory_region: "
5823 "failed to munmap memory\n");
5824 }
5825
7c8a83b7 5826 spin_lock(&kvm->mmu_lock);
f05e70ac 5827 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 5828 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
5829 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
5830 }
5831
5832 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 5833 spin_unlock(&kvm->mmu_lock);
0de10343 5834}
1d737c8a 5835
34d4cb8f
MT		 5836void kvm_arch_flush_shadow(struct kvm *kvm)
5837{
5838 kvm_mmu_zap_all(kvm);
8986ecc0 5839 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 5840}
5841
1d737c8a
ZX		 5842int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
5843{
a4535290 5844 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
a1b37100
GN		 5845 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
5846 || vcpu->arch.nmi_pending ||
5847 (kvm_arch_interrupt_allowed(vcpu) &&
5848 kvm_cpu_has_interrupt(vcpu));
1d737c8a 5849}
5736199a 5850
5736199a
ZX		 5851void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
5852{
32f88400
MT		 5853 int me;
5854 int cpu = vcpu->cpu;
5736199a
ZX		 5855
5856 if (waitqueue_active(&vcpu->wq)) {
5857 wake_up_interruptible(&vcpu->wq);
5858 ++vcpu->stat.halt_wakeup;
5859 }
32f88400
MT		 5860
5861 me = get_cpu();
5862 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
5863 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
5864 smp_send_reschedule(cpu);
e9571ed5 5865 put_cpu();
5736199a 5866}
78646121
GN		 5867
5868int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
5869{
5870 return kvm_x86_ops->interrupt_allowed(vcpu);
5871}
229456fc 5872
f92653ee
JK		 5873bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
5874{
5875 unsigned long current_rip = kvm_rip_read(vcpu) +
5876 get_segment_base(vcpu, VCPU_SREG_CS);
5877
5878 return current_rip == linear_rip;
5879}
5880EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
5881
94fe45da
JK		 5882unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
5883{
5884 unsigned long rflags;
5885
5886 rflags = kvm_x86_ops->get_rflags(vcpu);
5887 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 5888 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 5889 return rflags;
5890}
5891EXPORT_SYMBOL_GPL(kvm_get_rflags);
5892
5893void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
5894{
5895 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 5896 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 5897 rflags |= X86_EFLAGS_TF;
94fe45da
JK		 5898 kvm_x86_ops->set_rflags(vcpu, rflags);
5899}
5900EXPORT_SYMBOL_GPL(kvm_set_rflags);
5901
229456fc
MT		 5902EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
5903EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
5904EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
5905EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
5906EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 5907EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 5908EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 5909EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 5910EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 5911EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 5912EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 5913EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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